diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..ed0a92a --- /dev/null +++ b/.cproject @@ -0,0 +1,240 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.mxproject b/.mxproject new file mode 100644 index 0000000..687b48f --- /dev/null +++ b/.mxproject @@ -0,0 +1,14 @@ +[PreviousGenFiles] +HeaderPath=/home/vladimir/Desktop/STM32Display/Inc +HeaderFiles=FreeRTOSConfig.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_cdc_if.h;stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h; +SourcePath=/home/vladimir/Desktop/STM32Display/Src +SourceFiles=freertos.c;usb_device.c;usbd_conf.c;usbd_desc.c;usbd_cdc_if.c;stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c; + +[PreviousLibFiles] +LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h;Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h;Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h;Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h;Middlewares/Third_Party/FreeRTOS/Source/include/list.h;Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h;Middlewares/Third_Party/FreeRTOS/Source/include/portable.h;Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h;Middlewares/Third_Party/FreeRTOS/Source/include/queue.h;Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h;Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h;Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h;Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/task.h;Middlewares/Third_Party/FreeRTOS/Source/include/timers.h;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h;Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h;Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h;Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h;Middlewares/Third_Party/FreeRTOS/Source/include/list.h;Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h;Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h;Middlewares/Third_Party/FreeRTOS/Source/include/portable.h;Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h;Middlewares/Third_Party/FreeRTOS/Source/include/queue.h;Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h;Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h;Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h;Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h;Middlewares/Third_Party/FreeRTOS/Source/include/task.h;Middlewares/Third_Party/FreeRTOS/Source/include/timers.h;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm7.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Src/main.c;Src/freertos.c;Src/usb_device.c;Src/usbd_conf.c;Src/usbd_desc.c;Src/usbd_cdc_if.c;Src/stm32f1xx_it.c;Src/stm32f1xx_hal_msp.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Src/system_stm32f1xx.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c; +HeaderPath=Drivers/STM32F1xx_HAL_Driver/Inc;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy;Middlewares/Third_Party/FreeRTOS/Source/include;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3;Middlewares/ST/STM32_USB_Device_Library/Core/Inc;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc;Drivers/CMSIS/Device/ST/STM32F1xx/Include;Drivers/CMSIS/Include;Inc; +CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;STM32F103xB; + diff --git a/.project b/.project new file mode 100644 index 0000000..972ae3a --- /dev/null +++ b/.project @@ -0,0 +1,30 @@ + + + STM32Display + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml new file mode 100644 index 0000000..343c349 --- /dev/null +++ b/.settings/language.settings.xml @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..bc7e097 --- /dev/null +++ b/Debug/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,119 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c \ +../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c + +OBJS += \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.o + +C_DEPS += \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d \ +./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/Drivers/ili9341/subdir.mk b/Debug/Drivers/ili9341/subdir.mk new file mode 100644 index 0000000..f06e852 --- /dev/null +++ b/Debug/Drivers/ili9341/subdir.mk @@ -0,0 +1,29 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/ili9341/fonts.c \ +../Drivers/ili9341/ili9341.c \ +../Drivers/ili9341/ili9341_touch.c + +OBJS += \ +./Drivers/ili9341/fonts.o \ +./Drivers/ili9341/ili9341.o \ +./Drivers/ili9341/ili9341_touch.o + +C_DEPS += \ +./Drivers/ili9341/fonts.d \ +./Drivers/ili9341/ili9341.d \ +./Drivers/ili9341/ili9341_touch.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/ili9341/fonts.o: ../Drivers/ili9341/fonts.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -I../Drivers/ili9341 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/ili9341/fonts.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/ili9341/ili9341.o: ../Drivers/ili9341/ili9341.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -I../Drivers/ili9341 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/ili9341/ili9341.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/ili9341/ili9341_touch.o: ../Drivers/ili9341/ili9341_touch.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -I../Drivers/ili9341 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/ili9341/ili9341_touch.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk b/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk new file mode 100644 index 0000000..424cd4e --- /dev/null +++ b/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c + +OBJS += \ +./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o: ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk b/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk new file mode 100644 index 0000000..24b5075 --- /dev/null +++ b/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk @@ -0,0 +1,29 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ +../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c + +OBJS += \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d \ +./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o: ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o: ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o: ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk new file mode 100644 index 0000000..848d2a1 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/subdir.mk new file mode 100644 index 0000000..f5975c2 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk new file mode 100644 index 0000000..435e93f --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk new file mode 100644 index 0000000..075341f --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk @@ -0,0 +1,49 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ +../Middlewares/Third_Party/FreeRTOS/Source/list.c \ +../Middlewares/Third_Party/FreeRTOS/Source/queue.c \ +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \ +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ +../Middlewares/Third_Party/FreeRTOS/Source/timers.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.o \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o \ +./Middlewares/Third_Party/FreeRTOS/Source/list.o \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.o \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.o \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.d \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d \ +./Middlewares/Third_Party/FreeRTOS/Source/list.d \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.d \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.d \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/croutine.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/event_groups.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/list.o: ../Middlewares/Third_Party/FreeRTOS/Source/list.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/list.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/queue.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/queue.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/tasks.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/timers.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/timers.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/STM32Display.list b/Debug/STM32Display.list new file mode 100644 index 0000000..046fe1d --- /dev/null +++ b/Debug/STM32Display.list @@ -0,0 +1,30363 @@ + +STM32Display.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000010c 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000c530 08000110 08000110 00010110 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00002bf0 0800c640 0800c640 0001c640 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 0800f230 0800f230 00020208 2**0 + CONTENTS + 4 .ARM 00000000 0800f230 0800f230 00020208 2**0 + CONTENTS + 5 .preinit_array 00000000 0800f230 0800f230 00020208 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800f230 0800f230 0001f230 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 0800f234 0800f234 0001f234 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 00000208 20000000 0800f238 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 0000203c 20000208 0800f440 00020208 2**2 + ALLOC + 10 ._user_heap_stack 00000604 20002244 0800f440 00022244 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 00020208 2**0 + CONTENTS, READONLY + 12 .debug_info 00023c66 00000000 00000000 00020231 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_abbrev 00004e05 00000000 00000000 00043e97 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_aranges 00001da0 00000000 00000000 00048ca0 2**3 + CONTENTS, READONLY, DEBUGGING + 15 .debug_ranges 00001b88 00000000 00000000 0004aa40 2**3 + CONTENTS, READONLY, DEBUGGING + 16 .debug_macro 0001aea4 00000000 00000000 0004c5c8 2**0 + CONTENTS, READONLY, DEBUGGING + 17 .debug_line 00018337 00000000 00000000 0006746c 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .debug_str 00085fd5 00000000 00000000 0007f7a3 2**0 + CONTENTS, READONLY, DEBUGGING + 19 .comment 0000007b 00000000 00000000 00105778 2**0 + CONTENTS, READONLY + 20 .debug_frame 000084e8 00000000 00000000 001057f4 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +08000110 <__do_global_dtors_aux>: + 8000110: b510 push {r4, lr} + 8000112: 4c05 ldr r4, [pc, #20] ; (8000128 <__do_global_dtors_aux+0x18>) + 8000114: 7823 ldrb r3, [r4, #0] + 8000116: b933 cbnz r3, 8000126 <__do_global_dtors_aux+0x16> + 8000118: 4b04 ldr r3, [pc, #16] ; (800012c <__do_global_dtors_aux+0x1c>) + 800011a: b113 cbz r3, 8000122 <__do_global_dtors_aux+0x12> + 800011c: 4804 ldr r0, [pc, #16] ; (8000130 <__do_global_dtors_aux+0x20>) + 800011e: f3af 8000 nop.w + 8000122: 2301 movs r3, #1 + 8000124: 7023 strb r3, [r4, #0] + 8000126: bd10 pop {r4, pc} + 8000128: 20000208 .word 0x20000208 + 800012c: 00000000 .word 0x00000000 + 8000130: 0800c628 .word 0x0800c628 + +08000134 : + 8000134: b508 push {r3, lr} + 8000136: 4b03 ldr r3, [pc, #12] ; (8000144 ) + 8000138: b11b cbz r3, 8000142 + 800013a: 4903 ldr r1, [pc, #12] ; (8000148 ) + 800013c: 4803 ldr r0, [pc, #12] ; (800014c ) + 800013e: f3af 8000 nop.w + 8000142: bd08 pop {r3, pc} + 8000144: 00000000 .word 0x00000000 + 8000148: 2000020c .word 0x2000020c + 800014c: 0800c628 .word 0x0800c628 + +08000150 <__aeabi_drsub>: + 8000150: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 + 8000154: e002 b.n 800015c <__adddf3> + 8000156: bf00 nop + +08000158 <__aeabi_dsub>: + 8000158: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 + +0800015c <__adddf3>: + 800015c: b530 push {r4, r5, lr} + 800015e: ea4f 0441 mov.w r4, r1, lsl #1 + 8000162: ea4f 0543 mov.w r5, r3, lsl #1 + 8000166: ea94 0f05 teq r4, r5 + 800016a: bf08 it eq + 800016c: ea90 0f02 teqeq r0, r2 + 8000170: bf1f itttt ne + 8000172: ea54 0c00 orrsne.w ip, r4, r0 + 8000176: ea55 0c02 orrsne.w ip, r5, r2 + 800017a: ea7f 5c64 mvnsne.w ip, r4, asr #21 + 800017e: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 8000182: f000 80e2 beq.w 800034a <__adddf3+0x1ee> + 8000186: ea4f 5454 mov.w r4, r4, lsr #21 + 800018a: ebd4 5555 rsbs r5, r4, r5, lsr #21 + 800018e: bfb8 it lt + 8000190: 426d neglt r5, r5 + 8000192: dd0c ble.n 80001ae <__adddf3+0x52> + 8000194: 442c add r4, r5 + 8000196: ea80 0202 eor.w r2, r0, r2 + 800019a: ea81 0303 eor.w r3, r1, r3 + 800019e: ea82 0000 eor.w r0, r2, r0 + 80001a2: ea83 0101 eor.w r1, r3, r1 + 80001a6: ea80 0202 eor.w r2, r0, r2 + 80001aa: ea81 0303 eor.w r3, r1, r3 + 80001ae: 2d36 cmp r5, #54 ; 0x36 + 80001b0: bf88 it hi + 80001b2: bd30 pophi {r4, r5, pc} + 80001b4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 80001b8: ea4f 3101 mov.w r1, r1, lsl #12 + 80001bc: f44f 1c80 mov.w ip, #1048576 ; 0x100000 + 80001c0: ea4c 3111 orr.w r1, ip, r1, lsr #12 + 80001c4: d002 beq.n 80001cc <__adddf3+0x70> + 80001c6: 4240 negs r0, r0 + 80001c8: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 80001cc: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 + 80001d0: ea4f 3303 mov.w r3, r3, lsl #12 + 80001d4: ea4c 3313 orr.w r3, ip, r3, lsr #12 + 80001d8: d002 beq.n 80001e0 <__adddf3+0x84> + 80001da: 4252 negs r2, r2 + 80001dc: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 80001e0: ea94 0f05 teq r4, r5 + 80001e4: f000 80a7 beq.w 8000336 <__adddf3+0x1da> + 80001e8: f1a4 0401 sub.w r4, r4, #1 + 80001ec: f1d5 0e20 rsbs lr, r5, #32 + 80001f0: db0d blt.n 800020e <__adddf3+0xb2> + 80001f2: fa02 fc0e lsl.w ip, r2, lr + 80001f6: fa22 f205 lsr.w r2, r2, r5 + 80001fa: 1880 adds r0, r0, r2 + 80001fc: f141 0100 adc.w r1, r1, #0 + 8000200: fa03 f20e lsl.w r2, r3, lr + 8000204: 1880 adds r0, r0, r2 + 8000206: fa43 f305 asr.w r3, r3, r5 + 800020a: 4159 adcs r1, r3 + 800020c: e00e b.n 800022c <__adddf3+0xd0> + 800020e: f1a5 0520 sub.w r5, r5, #32 + 8000212: f10e 0e20 add.w lr, lr, #32 + 8000216: 2a01 cmp r2, #1 + 8000218: fa03 fc0e lsl.w ip, r3, lr + 800021c: bf28 it cs + 800021e: f04c 0c02 orrcs.w ip, ip, #2 + 8000222: fa43 f305 asr.w r3, r3, r5 + 8000226: 18c0 adds r0, r0, r3 + 8000228: eb51 71e3 adcs.w r1, r1, r3, asr #31 + 800022c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000230: d507 bpl.n 8000242 <__adddf3+0xe6> + 8000232: f04f 0e00 mov.w lr, #0 + 8000236: f1dc 0c00 rsbs ip, ip, #0 + 800023a: eb7e 0000 sbcs.w r0, lr, r0 + 800023e: eb6e 0101 sbc.w r1, lr, r1 + 8000242: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 + 8000246: d31b bcc.n 8000280 <__adddf3+0x124> + 8000248: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 + 800024c: d30c bcc.n 8000268 <__adddf3+0x10c> + 800024e: 0849 lsrs r1, r1, #1 + 8000250: ea5f 0030 movs.w r0, r0, rrx + 8000254: ea4f 0c3c mov.w ip, ip, rrx + 8000258: f104 0401 add.w r4, r4, #1 + 800025c: ea4f 5244 mov.w r2, r4, lsl #21 + 8000260: f512 0f80 cmn.w r2, #4194304 ; 0x400000 + 8000264: f080 809a bcs.w 800039c <__adddf3+0x240> + 8000268: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 + 800026c: bf08 it eq + 800026e: ea5f 0c50 movseq.w ip, r0, lsr #1 + 8000272: f150 0000 adcs.w r0, r0, #0 + 8000276: eb41 5104 adc.w r1, r1, r4, lsl #20 + 800027a: ea41 0105 orr.w r1, r1, r5 + 800027e: bd30 pop {r4, r5, pc} + 8000280: ea5f 0c4c movs.w ip, ip, lsl #1 + 8000284: 4140 adcs r0, r0 + 8000286: eb41 0101 adc.w r1, r1, r1 + 800028a: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 800028e: f1a4 0401 sub.w r4, r4, #1 + 8000292: d1e9 bne.n 8000268 <__adddf3+0x10c> + 8000294: f091 0f00 teq r1, #0 + 8000298: bf04 itt eq + 800029a: 4601 moveq r1, r0 + 800029c: 2000 moveq r0, #0 + 800029e: fab1 f381 clz r3, r1 + 80002a2: bf08 it eq + 80002a4: 3320 addeq r3, #32 + 80002a6: f1a3 030b sub.w r3, r3, #11 + 80002aa: f1b3 0220 subs.w r2, r3, #32 + 80002ae: da0c bge.n 80002ca <__adddf3+0x16e> + 80002b0: 320c adds r2, #12 + 80002b2: dd08 ble.n 80002c6 <__adddf3+0x16a> + 80002b4: f102 0c14 add.w ip, r2, #20 + 80002b8: f1c2 020c rsb r2, r2, #12 + 80002bc: fa01 f00c lsl.w r0, r1, ip + 80002c0: fa21 f102 lsr.w r1, r1, r2 + 80002c4: e00c b.n 80002e0 <__adddf3+0x184> + 80002c6: f102 0214 add.w r2, r2, #20 + 80002ca: bfd8 it le + 80002cc: f1c2 0c20 rsble ip, r2, #32 + 80002d0: fa01 f102 lsl.w r1, r1, r2 + 80002d4: fa20 fc0c lsr.w ip, r0, ip + 80002d8: bfdc itt le + 80002da: ea41 010c orrle.w r1, r1, ip + 80002de: 4090 lslle r0, r2 + 80002e0: 1ae4 subs r4, r4, r3 + 80002e2: bfa2 ittt ge + 80002e4: eb01 5104 addge.w r1, r1, r4, lsl #20 + 80002e8: 4329 orrge r1, r5 + 80002ea: bd30 popge {r4, r5, pc} + 80002ec: ea6f 0404 mvn.w r4, r4 + 80002f0: 3c1f subs r4, #31 + 80002f2: da1c bge.n 800032e <__adddf3+0x1d2> + 80002f4: 340c adds r4, #12 + 80002f6: dc0e bgt.n 8000316 <__adddf3+0x1ba> + 80002f8: f104 0414 add.w r4, r4, #20 + 80002fc: f1c4 0220 rsb r2, r4, #32 + 8000300: fa20 f004 lsr.w r0, r0, r4 + 8000304: fa01 f302 lsl.w r3, r1, r2 + 8000308: ea40 0003 orr.w r0, r0, r3 + 800030c: fa21 f304 lsr.w r3, r1, r4 + 8000310: ea45 0103 orr.w r1, r5, r3 + 8000314: bd30 pop {r4, r5, pc} + 8000316: f1c4 040c rsb r4, r4, #12 + 800031a: f1c4 0220 rsb r2, r4, #32 + 800031e: fa20 f002 lsr.w r0, r0, r2 + 8000322: fa01 f304 lsl.w r3, r1, r4 + 8000326: ea40 0003 orr.w r0, r0, r3 + 800032a: 4629 mov r1, r5 + 800032c: bd30 pop {r4, r5, pc} + 800032e: fa21 f004 lsr.w r0, r1, r4 + 8000332: 4629 mov r1, r5 + 8000334: bd30 pop {r4, r5, pc} + 8000336: f094 0f00 teq r4, #0 + 800033a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 + 800033e: bf06 itte eq + 8000340: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 + 8000344: 3401 addeq r4, #1 + 8000346: 3d01 subne r5, #1 + 8000348: e74e b.n 80001e8 <__adddf3+0x8c> + 800034a: ea7f 5c64 mvns.w ip, r4, asr #21 + 800034e: bf18 it ne + 8000350: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 8000354: d029 beq.n 80003aa <__adddf3+0x24e> + 8000356: ea94 0f05 teq r4, r5 + 800035a: bf08 it eq + 800035c: ea90 0f02 teqeq r0, r2 + 8000360: d005 beq.n 800036e <__adddf3+0x212> + 8000362: ea54 0c00 orrs.w ip, r4, r0 + 8000366: bf04 itt eq + 8000368: 4619 moveq r1, r3 + 800036a: 4610 moveq r0, r2 + 800036c: bd30 pop {r4, r5, pc} + 800036e: ea91 0f03 teq r1, r3 + 8000372: bf1e ittt ne + 8000374: 2100 movne r1, #0 + 8000376: 2000 movne r0, #0 + 8000378: bd30 popne {r4, r5, pc} + 800037a: ea5f 5c54 movs.w ip, r4, lsr #21 + 800037e: d105 bne.n 800038c <__adddf3+0x230> + 8000380: 0040 lsls r0, r0, #1 + 8000382: 4149 adcs r1, r1 + 8000384: bf28 it cs + 8000386: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 + 800038a: bd30 pop {r4, r5, pc} + 800038c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 + 8000390: bf3c itt cc + 8000392: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 + 8000396: bd30 popcc {r4, r5, pc} + 8000398: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 800039c: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 + 80003a0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 80003a4: f04f 0000 mov.w r0, #0 + 80003a8: bd30 pop {r4, r5, pc} + 80003aa: ea7f 5c64 mvns.w ip, r4, asr #21 + 80003ae: bf1a itte ne + 80003b0: 4619 movne r1, r3 + 80003b2: 4610 movne r0, r2 + 80003b4: ea7f 5c65 mvnseq.w ip, r5, asr #21 + 80003b8: bf1c itt ne + 80003ba: 460b movne r3, r1 + 80003bc: 4602 movne r2, r0 + 80003be: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 80003c2: bf06 itte eq + 80003c4: ea52 3503 orrseq.w r5, r2, r3, lsl #12 + 80003c8: ea91 0f03 teqeq r1, r3 + 80003cc: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 + 80003d0: bd30 pop {r4, r5, pc} + 80003d2: bf00 nop + +080003d4 <__aeabi_ui2d>: + 80003d4: f090 0f00 teq r0, #0 + 80003d8: bf04 itt eq + 80003da: 2100 moveq r1, #0 + 80003dc: 4770 bxeq lr + 80003de: b530 push {r4, r5, lr} + 80003e0: f44f 6480 mov.w r4, #1024 ; 0x400 + 80003e4: f104 0432 add.w r4, r4, #50 ; 0x32 + 80003e8: f04f 0500 mov.w r5, #0 + 80003ec: f04f 0100 mov.w r1, #0 + 80003f0: e750 b.n 8000294 <__adddf3+0x138> + 80003f2: bf00 nop + +080003f4 <__aeabi_i2d>: + 80003f4: f090 0f00 teq r0, #0 + 80003f8: bf04 itt eq + 80003fa: 2100 moveq r1, #0 + 80003fc: 4770 bxeq lr + 80003fe: b530 push {r4, r5, lr} + 8000400: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000404: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000408: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 + 800040c: bf48 it mi + 800040e: 4240 negmi r0, r0 + 8000410: f04f 0100 mov.w r1, #0 + 8000414: e73e b.n 8000294 <__adddf3+0x138> + 8000416: bf00 nop + +08000418 <__aeabi_f2d>: + 8000418: 0042 lsls r2, r0, #1 + 800041a: ea4f 01e2 mov.w r1, r2, asr #3 + 800041e: ea4f 0131 mov.w r1, r1, rrx + 8000422: ea4f 7002 mov.w r0, r2, lsl #28 + 8000426: bf1f itttt ne + 8000428: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 + 800042c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 + 8000430: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 + 8000434: 4770 bxne lr + 8000436: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 + 800043a: bf08 it eq + 800043c: 4770 bxeq lr + 800043e: f093 4f7f teq r3, #4278190080 ; 0xff000000 + 8000442: bf04 itt eq + 8000444: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 + 8000448: 4770 bxeq lr + 800044a: b530 push {r4, r5, lr} + 800044c: f44f 7460 mov.w r4, #896 ; 0x380 + 8000450: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000454: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8000458: e71c b.n 8000294 <__adddf3+0x138> + 800045a: bf00 nop + +0800045c <__aeabi_ul2d>: + 800045c: ea50 0201 orrs.w r2, r0, r1 + 8000460: bf08 it eq + 8000462: 4770 bxeq lr + 8000464: b530 push {r4, r5, lr} + 8000466: f04f 0500 mov.w r5, #0 + 800046a: e00a b.n 8000482 <__aeabi_l2d+0x16> + +0800046c <__aeabi_l2d>: + 800046c: ea50 0201 orrs.w r2, r0, r1 + 8000470: bf08 it eq + 8000472: 4770 bxeq lr + 8000474: b530 push {r4, r5, lr} + 8000476: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 + 800047a: d502 bpl.n 8000482 <__aeabi_l2d+0x16> + 800047c: 4240 negs r0, r0 + 800047e: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8000482: f44f 6480 mov.w r4, #1024 ; 0x400 + 8000486: f104 0432 add.w r4, r4, #50 ; 0x32 + 800048a: ea5f 5c91 movs.w ip, r1, lsr #22 + 800048e: f43f aed8 beq.w 8000242 <__adddf3+0xe6> + 8000492: f04f 0203 mov.w r2, #3 + 8000496: ea5f 0cdc movs.w ip, ip, lsr #3 + 800049a: bf18 it ne + 800049c: 3203 addne r2, #3 + 800049e: ea5f 0cdc movs.w ip, ip, lsr #3 + 80004a2: bf18 it ne + 80004a4: 3203 addne r2, #3 + 80004a6: eb02 02dc add.w r2, r2, ip, lsr #3 + 80004aa: f1c2 0320 rsb r3, r2, #32 + 80004ae: fa00 fc03 lsl.w ip, r0, r3 + 80004b2: fa20 f002 lsr.w r0, r0, r2 + 80004b6: fa01 fe03 lsl.w lr, r1, r3 + 80004ba: ea40 000e orr.w r0, r0, lr + 80004be: fa21 f102 lsr.w r1, r1, r2 + 80004c2: 4414 add r4, r2 + 80004c4: e6bd b.n 8000242 <__adddf3+0xe6> + 80004c6: bf00 nop + +080004c8 <__aeabi_dmul>: + 80004c8: b570 push {r4, r5, r6, lr} + 80004ca: f04f 0cff mov.w ip, #255 ; 0xff + 80004ce: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 80004d2: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 80004d6: bf1d ittte ne + 80004d8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 80004dc: ea94 0f0c teqne r4, ip + 80004e0: ea95 0f0c teqne r5, ip + 80004e4: f000 f8de bleq 80006a4 <__aeabi_dmul+0x1dc> + 80004e8: 442c add r4, r5 + 80004ea: ea81 0603 eor.w r6, r1, r3 + 80004ee: ea21 514c bic.w r1, r1, ip, lsl #21 + 80004f2: ea23 534c bic.w r3, r3, ip, lsl #21 + 80004f6: ea50 3501 orrs.w r5, r0, r1, lsl #12 + 80004fa: bf18 it ne + 80004fc: ea52 3503 orrsne.w r5, r2, r3, lsl #12 + 8000500: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000504: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8000508: d038 beq.n 800057c <__aeabi_dmul+0xb4> + 800050a: fba0 ce02 umull ip, lr, r0, r2 + 800050e: f04f 0500 mov.w r5, #0 + 8000512: fbe1 e502 umlal lr, r5, r1, r2 + 8000516: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 + 800051a: fbe0 e503 umlal lr, r5, r0, r3 + 800051e: f04f 0600 mov.w r6, #0 + 8000522: fbe1 5603 umlal r5, r6, r1, r3 + 8000526: f09c 0f00 teq ip, #0 + 800052a: bf18 it ne + 800052c: f04e 0e01 orrne.w lr, lr, #1 + 8000530: f1a4 04ff sub.w r4, r4, #255 ; 0xff + 8000534: f5b6 7f00 cmp.w r6, #512 ; 0x200 + 8000538: f564 7440 sbc.w r4, r4, #768 ; 0x300 + 800053c: d204 bcs.n 8000548 <__aeabi_dmul+0x80> + 800053e: ea5f 0e4e movs.w lr, lr, lsl #1 + 8000542: 416d adcs r5, r5 + 8000544: eb46 0606 adc.w r6, r6, r6 + 8000548: ea42 21c6 orr.w r1, r2, r6, lsl #11 + 800054c: ea41 5155 orr.w r1, r1, r5, lsr #21 + 8000550: ea4f 20c5 mov.w r0, r5, lsl #11 + 8000554: ea40 505e orr.w r0, r0, lr, lsr #21 + 8000558: ea4f 2ece mov.w lr, lr, lsl #11 + 800055c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 8000560: bf88 it hi + 8000562: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 8000566: d81e bhi.n 80005a6 <__aeabi_dmul+0xde> + 8000568: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 + 800056c: bf08 it eq + 800056e: ea5f 0e50 movseq.w lr, r0, lsr #1 + 8000572: f150 0000 adcs.w r0, r0, #0 + 8000576: eb41 5104 adc.w r1, r1, r4, lsl #20 + 800057a: bd70 pop {r4, r5, r6, pc} + 800057c: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 + 8000580: ea46 0101 orr.w r1, r6, r1 + 8000584: ea40 0002 orr.w r0, r0, r2 + 8000588: ea81 0103 eor.w r1, r1, r3 + 800058c: ebb4 045c subs.w r4, r4, ip, lsr #1 + 8000590: bfc2 ittt gt + 8000592: ebd4 050c rsbsgt r5, r4, ip + 8000596: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 800059a: bd70 popgt {r4, r5, r6, pc} + 800059c: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 80005a0: f04f 0e00 mov.w lr, #0 + 80005a4: 3c01 subs r4, #1 + 80005a6: f300 80ab bgt.w 8000700 <__aeabi_dmul+0x238> + 80005aa: f114 0f36 cmn.w r4, #54 ; 0x36 + 80005ae: bfde ittt le + 80005b0: 2000 movle r0, #0 + 80005b2: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 + 80005b6: bd70 pople {r4, r5, r6, pc} + 80005b8: f1c4 0400 rsb r4, r4, #0 + 80005bc: 3c20 subs r4, #32 + 80005be: da35 bge.n 800062c <__aeabi_dmul+0x164> + 80005c0: 340c adds r4, #12 + 80005c2: dc1b bgt.n 80005fc <__aeabi_dmul+0x134> + 80005c4: f104 0414 add.w r4, r4, #20 + 80005c8: f1c4 0520 rsb r5, r4, #32 + 80005cc: fa00 f305 lsl.w r3, r0, r5 + 80005d0: fa20 f004 lsr.w r0, r0, r4 + 80005d4: fa01 f205 lsl.w r2, r1, r5 + 80005d8: ea40 0002 orr.w r0, r0, r2 + 80005dc: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 + 80005e0: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 80005e4: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 80005e8: fa21 f604 lsr.w r6, r1, r4 + 80005ec: eb42 0106 adc.w r1, r2, r6 + 80005f0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 80005f4: bf08 it eq + 80005f6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80005fa: bd70 pop {r4, r5, r6, pc} + 80005fc: f1c4 040c rsb r4, r4, #12 + 8000600: f1c4 0520 rsb r5, r4, #32 + 8000604: fa00 f304 lsl.w r3, r0, r4 + 8000608: fa20 f005 lsr.w r0, r0, r5 + 800060c: fa01 f204 lsl.w r2, r1, r4 + 8000610: ea40 0002 orr.w r0, r0, r2 + 8000614: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000618: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 800061c: f141 0100 adc.w r1, r1, #0 + 8000620: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000624: bf08 it eq + 8000626: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800062a: bd70 pop {r4, r5, r6, pc} + 800062c: f1c4 0520 rsb r5, r4, #32 + 8000630: fa00 f205 lsl.w r2, r0, r5 + 8000634: ea4e 0e02 orr.w lr, lr, r2 + 8000638: fa20 f304 lsr.w r3, r0, r4 + 800063c: fa01 f205 lsl.w r2, r1, r5 + 8000640: ea43 0302 orr.w r3, r3, r2 + 8000644: fa21 f004 lsr.w r0, r1, r4 + 8000648: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 800064c: fa21 f204 lsr.w r2, r1, r4 + 8000650: ea20 0002 bic.w r0, r0, r2 + 8000654: eb00 70d3 add.w r0, r0, r3, lsr #31 + 8000658: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 800065c: bf08 it eq + 800065e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 8000662: bd70 pop {r4, r5, r6, pc} + 8000664: f094 0f00 teq r4, #0 + 8000668: d10f bne.n 800068a <__aeabi_dmul+0x1c2> + 800066a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 + 800066e: 0040 lsls r0, r0, #1 + 8000670: eb41 0101 adc.w r1, r1, r1 + 8000674: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000678: bf08 it eq + 800067a: 3c01 subeq r4, #1 + 800067c: d0f7 beq.n 800066e <__aeabi_dmul+0x1a6> + 800067e: ea41 0106 orr.w r1, r1, r6 + 8000682: f095 0f00 teq r5, #0 + 8000686: bf18 it ne + 8000688: 4770 bxne lr + 800068a: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 + 800068e: 0052 lsls r2, r2, #1 + 8000690: eb43 0303 adc.w r3, r3, r3 + 8000694: f413 1f80 tst.w r3, #1048576 ; 0x100000 + 8000698: bf08 it eq + 800069a: 3d01 subeq r5, #1 + 800069c: d0f7 beq.n 800068e <__aeabi_dmul+0x1c6> + 800069e: ea43 0306 orr.w r3, r3, r6 + 80006a2: 4770 bx lr + 80006a4: ea94 0f0c teq r4, ip + 80006a8: ea0c 5513 and.w r5, ip, r3, lsr #20 + 80006ac: bf18 it ne + 80006ae: ea95 0f0c teqne r5, ip + 80006b2: d00c beq.n 80006ce <__aeabi_dmul+0x206> + 80006b4: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80006b8: bf18 it ne + 80006ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80006be: d1d1 bne.n 8000664 <__aeabi_dmul+0x19c> + 80006c0: ea81 0103 eor.w r1, r1, r3 + 80006c4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 80006c8: f04f 0000 mov.w r0, #0 + 80006cc: bd70 pop {r4, r5, r6, pc} + 80006ce: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80006d2: bf06 itte eq + 80006d4: 4610 moveq r0, r2 + 80006d6: 4619 moveq r1, r3 + 80006d8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80006dc: d019 beq.n 8000712 <__aeabi_dmul+0x24a> + 80006de: ea94 0f0c teq r4, ip + 80006e2: d102 bne.n 80006ea <__aeabi_dmul+0x222> + 80006e4: ea50 3601 orrs.w r6, r0, r1, lsl #12 + 80006e8: d113 bne.n 8000712 <__aeabi_dmul+0x24a> + 80006ea: ea95 0f0c teq r5, ip + 80006ee: d105 bne.n 80006fc <__aeabi_dmul+0x234> + 80006f0: ea52 3603 orrs.w r6, r2, r3, lsl #12 + 80006f4: bf1c itt ne + 80006f6: 4610 movne r0, r2 + 80006f8: 4619 movne r1, r3 + 80006fa: d10a bne.n 8000712 <__aeabi_dmul+0x24a> + 80006fc: ea81 0103 eor.w r1, r1, r3 + 8000700: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000704: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000708: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 800070c: f04f 0000 mov.w r0, #0 + 8000710: bd70 pop {r4, r5, r6, pc} + 8000712: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 8000716: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 + 800071a: bd70 pop {r4, r5, r6, pc} + +0800071c <__aeabi_ddiv>: + 800071c: b570 push {r4, r5, r6, lr} + 800071e: f04f 0cff mov.w ip, #255 ; 0xff + 8000722: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 8000726: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 800072a: bf1d ittte ne + 800072c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 8000730: ea94 0f0c teqne r4, ip + 8000734: ea95 0f0c teqne r5, ip + 8000738: f000 f8a7 bleq 800088a <__aeabi_ddiv+0x16e> + 800073c: eba4 0405 sub.w r4, r4, r5 + 8000740: ea81 0e03 eor.w lr, r1, r3 + 8000744: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 8000748: ea4f 3101 mov.w r1, r1, lsl #12 + 800074c: f000 8088 beq.w 8000860 <__aeabi_ddiv+0x144> + 8000750: ea4f 3303 mov.w r3, r3, lsl #12 + 8000754: f04f 5580 mov.w r5, #268435456 ; 0x10000000 + 8000758: ea45 1313 orr.w r3, r5, r3, lsr #4 + 800075c: ea43 6312 orr.w r3, r3, r2, lsr #24 + 8000760: ea4f 2202 mov.w r2, r2, lsl #8 + 8000764: ea45 1511 orr.w r5, r5, r1, lsr #4 + 8000768: ea45 6510 orr.w r5, r5, r0, lsr #24 + 800076c: ea4f 2600 mov.w r6, r0, lsl #8 + 8000770: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 + 8000774: 429d cmp r5, r3 + 8000776: bf08 it eq + 8000778: 4296 cmpeq r6, r2 + 800077a: f144 04fd adc.w r4, r4, #253 ; 0xfd + 800077e: f504 7440 add.w r4, r4, #768 ; 0x300 + 8000782: d202 bcs.n 800078a <__aeabi_ddiv+0x6e> + 8000784: 085b lsrs r3, r3, #1 + 8000786: ea4f 0232 mov.w r2, r2, rrx + 800078a: 1ab6 subs r6, r6, r2 + 800078c: eb65 0503 sbc.w r5, r5, r3 + 8000790: 085b lsrs r3, r3, #1 + 8000792: ea4f 0232 mov.w r2, r2, rrx + 8000796: f44f 1080 mov.w r0, #1048576 ; 0x100000 + 800079a: f44f 2c00 mov.w ip, #524288 ; 0x80000 + 800079e: ebb6 0e02 subs.w lr, r6, r2 + 80007a2: eb75 0e03 sbcs.w lr, r5, r3 + 80007a6: bf22 ittt cs + 80007a8: 1ab6 subcs r6, r6, r2 + 80007aa: 4675 movcs r5, lr + 80007ac: ea40 000c orrcs.w r0, r0, ip + 80007b0: 085b lsrs r3, r3, #1 + 80007b2: ea4f 0232 mov.w r2, r2, rrx + 80007b6: ebb6 0e02 subs.w lr, r6, r2 + 80007ba: eb75 0e03 sbcs.w lr, r5, r3 + 80007be: bf22 ittt cs + 80007c0: 1ab6 subcs r6, r6, r2 + 80007c2: 4675 movcs r5, lr + 80007c4: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 80007c8: 085b lsrs r3, r3, #1 + 80007ca: ea4f 0232 mov.w r2, r2, rrx + 80007ce: ebb6 0e02 subs.w lr, r6, r2 + 80007d2: eb75 0e03 sbcs.w lr, r5, r3 + 80007d6: bf22 ittt cs + 80007d8: 1ab6 subcs r6, r6, r2 + 80007da: 4675 movcs r5, lr + 80007dc: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 80007e0: 085b lsrs r3, r3, #1 + 80007e2: ea4f 0232 mov.w r2, r2, rrx + 80007e6: ebb6 0e02 subs.w lr, r6, r2 + 80007ea: eb75 0e03 sbcs.w lr, r5, r3 + 80007ee: bf22 ittt cs + 80007f0: 1ab6 subcs r6, r6, r2 + 80007f2: 4675 movcs r5, lr + 80007f4: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 80007f8: ea55 0e06 orrs.w lr, r5, r6 + 80007fc: d018 beq.n 8000830 <__aeabi_ddiv+0x114> + 80007fe: ea4f 1505 mov.w r5, r5, lsl #4 + 8000802: ea45 7516 orr.w r5, r5, r6, lsr #28 + 8000806: ea4f 1606 mov.w r6, r6, lsl #4 + 800080a: ea4f 03c3 mov.w r3, r3, lsl #3 + 800080e: ea43 7352 orr.w r3, r3, r2, lsr #29 + 8000812: ea4f 02c2 mov.w r2, r2, lsl #3 + 8000816: ea5f 1c1c movs.w ip, ip, lsr #4 + 800081a: d1c0 bne.n 800079e <__aeabi_ddiv+0x82> + 800081c: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000820: d10b bne.n 800083a <__aeabi_ddiv+0x11e> + 8000822: ea41 0100 orr.w r1, r1, r0 + 8000826: f04f 0000 mov.w r0, #0 + 800082a: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 + 800082e: e7b6 b.n 800079e <__aeabi_ddiv+0x82> + 8000830: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000834: bf04 itt eq + 8000836: 4301 orreq r1, r0 + 8000838: 2000 moveq r0, #0 + 800083a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 800083e: bf88 it hi + 8000840: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 8000844: f63f aeaf bhi.w 80005a6 <__aeabi_dmul+0xde> + 8000848: ebb5 0c03 subs.w ip, r5, r3 + 800084c: bf04 itt eq + 800084e: ebb6 0c02 subseq.w ip, r6, r2 + 8000852: ea5f 0c50 movseq.w ip, r0, lsr #1 + 8000856: f150 0000 adcs.w r0, r0, #0 + 800085a: eb41 5104 adc.w r1, r1, r4, lsl #20 + 800085e: bd70 pop {r4, r5, r6, pc} + 8000860: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 + 8000864: ea4e 3111 orr.w r1, lr, r1, lsr #12 + 8000868: eb14 045c adds.w r4, r4, ip, lsr #1 + 800086c: bfc2 ittt gt + 800086e: ebd4 050c rsbsgt r5, r4, ip + 8000872: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 8000876: bd70 popgt {r4, r5, r6, pc} + 8000878: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 800087c: f04f 0e00 mov.w lr, #0 + 8000880: 3c01 subs r4, #1 + 8000882: e690 b.n 80005a6 <__aeabi_dmul+0xde> + 8000884: ea45 0e06 orr.w lr, r5, r6 + 8000888: e68d b.n 80005a6 <__aeabi_dmul+0xde> + 800088a: ea0c 5513 and.w r5, ip, r3, lsr #20 + 800088e: ea94 0f0c teq r4, ip + 8000892: bf08 it eq + 8000894: ea95 0f0c teqeq r5, ip + 8000898: f43f af3b beq.w 8000712 <__aeabi_dmul+0x24a> + 800089c: ea94 0f0c teq r4, ip + 80008a0: d10a bne.n 80008b8 <__aeabi_ddiv+0x19c> + 80008a2: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 80008a6: f47f af34 bne.w 8000712 <__aeabi_dmul+0x24a> + 80008aa: ea95 0f0c teq r5, ip + 80008ae: f47f af25 bne.w 80006fc <__aeabi_dmul+0x234> + 80008b2: 4610 mov r0, r2 + 80008b4: 4619 mov r1, r3 + 80008b6: e72c b.n 8000712 <__aeabi_dmul+0x24a> + 80008b8: ea95 0f0c teq r5, ip + 80008bc: d106 bne.n 80008cc <__aeabi_ddiv+0x1b0> + 80008be: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 80008c2: f43f aefd beq.w 80006c0 <__aeabi_dmul+0x1f8> + 80008c6: 4610 mov r0, r2 + 80008c8: 4619 mov r1, r3 + 80008ca: e722 b.n 8000712 <__aeabi_dmul+0x24a> + 80008cc: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 80008d0: bf18 it ne + 80008d2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 80008d6: f47f aec5 bne.w 8000664 <__aeabi_dmul+0x19c> + 80008da: ea50 0441 orrs.w r4, r0, r1, lsl #1 + 80008de: f47f af0d bne.w 80006fc <__aeabi_dmul+0x234> + 80008e2: ea52 0543 orrs.w r5, r2, r3, lsl #1 + 80008e6: f47f aeeb bne.w 80006c0 <__aeabi_dmul+0x1f8> + 80008ea: e712 b.n 8000712 <__aeabi_dmul+0x24a> + +080008ec <__gedf2>: + 80008ec: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff + 80008f0: e006 b.n 8000900 <__cmpdf2+0x4> + 80008f2: bf00 nop + +080008f4 <__ledf2>: + 80008f4: f04f 0c01 mov.w ip, #1 + 80008f8: e002 b.n 8000900 <__cmpdf2+0x4> + 80008fa: bf00 nop + +080008fc <__cmpdf2>: + 80008fc: f04f 0c01 mov.w ip, #1 + 8000900: f84d cd04 str.w ip, [sp, #-4]! + 8000904: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000908: ea7f 5c6c mvns.w ip, ip, asr #21 + 800090c: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000910: bf18 it ne + 8000912: ea7f 5c6c mvnsne.w ip, ip, asr #21 + 8000916: d01b beq.n 8000950 <__cmpdf2+0x54> + 8000918: b001 add sp, #4 + 800091a: ea50 0c41 orrs.w ip, r0, r1, lsl #1 + 800091e: bf0c ite eq + 8000920: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 + 8000924: ea91 0f03 teqne r1, r3 + 8000928: bf02 ittt eq + 800092a: ea90 0f02 teqeq r0, r2 + 800092e: 2000 moveq r0, #0 + 8000930: 4770 bxeq lr + 8000932: f110 0f00 cmn.w r0, #0 + 8000936: ea91 0f03 teq r1, r3 + 800093a: bf58 it pl + 800093c: 4299 cmppl r1, r3 + 800093e: bf08 it eq + 8000940: 4290 cmpeq r0, r2 + 8000942: bf2c ite cs + 8000944: 17d8 asrcs r0, r3, #31 + 8000946: ea6f 70e3 mvncc.w r0, r3, asr #31 + 800094a: f040 0001 orr.w r0, r0, #1 + 800094e: 4770 bx lr + 8000950: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000954: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000958: d102 bne.n 8000960 <__cmpdf2+0x64> + 800095a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 800095e: d107 bne.n 8000970 <__cmpdf2+0x74> + 8000960: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000964: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000968: d1d6 bne.n 8000918 <__cmpdf2+0x1c> + 800096a: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 800096e: d0d3 beq.n 8000918 <__cmpdf2+0x1c> + 8000970: f85d 0b04 ldr.w r0, [sp], #4 + 8000974: 4770 bx lr + 8000976: bf00 nop + +08000978 <__aeabi_cdrcmple>: + 8000978: 4684 mov ip, r0 + 800097a: 4610 mov r0, r2 + 800097c: 4662 mov r2, ip + 800097e: 468c mov ip, r1 + 8000980: 4619 mov r1, r3 + 8000982: 4663 mov r3, ip + 8000984: e000 b.n 8000988 <__aeabi_cdcmpeq> + 8000986: bf00 nop + +08000988 <__aeabi_cdcmpeq>: + 8000988: b501 push {r0, lr} + 800098a: f7ff ffb7 bl 80008fc <__cmpdf2> + 800098e: 2800 cmp r0, #0 + 8000990: bf48 it mi + 8000992: f110 0f00 cmnmi.w r0, #0 + 8000996: bd01 pop {r0, pc} + +08000998 <__aeabi_dcmpeq>: + 8000998: f84d ed08 str.w lr, [sp, #-8]! + 800099c: f7ff fff4 bl 8000988 <__aeabi_cdcmpeq> + 80009a0: bf0c ite eq + 80009a2: 2001 moveq r0, #1 + 80009a4: 2000 movne r0, #0 + 80009a6: f85d fb08 ldr.w pc, [sp], #8 + 80009aa: bf00 nop + +080009ac <__aeabi_dcmplt>: + 80009ac: f84d ed08 str.w lr, [sp, #-8]! + 80009b0: f7ff ffea bl 8000988 <__aeabi_cdcmpeq> + 80009b4: bf34 ite cc + 80009b6: 2001 movcc r0, #1 + 80009b8: 2000 movcs r0, #0 + 80009ba: f85d fb08 ldr.w pc, [sp], #8 + 80009be: bf00 nop + +080009c0 <__aeabi_dcmple>: + 80009c0: f84d ed08 str.w lr, [sp, #-8]! + 80009c4: f7ff ffe0 bl 8000988 <__aeabi_cdcmpeq> + 80009c8: bf94 ite ls + 80009ca: 2001 movls r0, #1 + 80009cc: 2000 movhi r0, #0 + 80009ce: f85d fb08 ldr.w pc, [sp], #8 + 80009d2: bf00 nop + +080009d4 <__aeabi_dcmpge>: + 80009d4: f84d ed08 str.w lr, [sp, #-8]! + 80009d8: f7ff ffce bl 8000978 <__aeabi_cdrcmple> + 80009dc: bf94 ite ls + 80009de: 2001 movls r0, #1 + 80009e0: 2000 movhi r0, #0 + 80009e2: f85d fb08 ldr.w pc, [sp], #8 + 80009e6: bf00 nop + +080009e8 <__aeabi_dcmpgt>: + 80009e8: f84d ed08 str.w lr, [sp, #-8]! + 80009ec: f7ff ffc4 bl 8000978 <__aeabi_cdrcmple> + 80009f0: bf34 ite cc + 80009f2: 2001 movcc r0, #1 + 80009f4: 2000 movcs r0, #0 + 80009f6: f85d fb08 ldr.w pc, [sp], #8 + 80009fa: bf00 nop + +080009fc <__aeabi_d2iz>: + 80009fc: ea4f 0241 mov.w r2, r1, lsl #1 + 8000a00: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000a04: d215 bcs.n 8000a32 <__aeabi_d2iz+0x36> + 8000a06: d511 bpl.n 8000a2c <__aeabi_d2iz+0x30> + 8000a08: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000a0c: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000a10: d912 bls.n 8000a38 <__aeabi_d2iz+0x3c> + 8000a12: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000a16: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000a1a: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000a1e: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000a22: fa23 f002 lsr.w r0, r3, r2 + 8000a26: bf18 it ne + 8000a28: 4240 negne r0, r0 + 8000a2a: 4770 bx lr + 8000a2c: f04f 0000 mov.w r0, #0 + 8000a30: 4770 bx lr + 8000a32: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000a36: d105 bne.n 8000a44 <__aeabi_d2iz+0x48> + 8000a38: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 + 8000a3c: bf08 it eq + 8000a3e: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 + 8000a42: 4770 bx lr + 8000a44: f04f 0000 mov.w r0, #0 + 8000a48: 4770 bx lr + 8000a4a: bf00 nop + +08000a4c <__aeabi_frsub>: + 8000a4c: f080 4000 eor.w r0, r0, #2147483648 ; 0x80000000 + 8000a50: e002 b.n 8000a58 <__addsf3> + 8000a52: bf00 nop + +08000a54 <__aeabi_fsub>: + 8000a54: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 + +08000a58 <__addsf3>: + 8000a58: 0042 lsls r2, r0, #1 + 8000a5a: bf1f itttt ne + 8000a5c: ea5f 0341 movsne.w r3, r1, lsl #1 + 8000a60: ea92 0f03 teqne r2, r3 + 8000a64: ea7f 6c22 mvnsne.w ip, r2, asr #24 + 8000a68: ea7f 6c23 mvnsne.w ip, r3, asr #24 + 8000a6c: d06a beq.n 8000b44 <__addsf3+0xec> + 8000a6e: ea4f 6212 mov.w r2, r2, lsr #24 + 8000a72: ebd2 6313 rsbs r3, r2, r3, lsr #24 + 8000a76: bfc1 itttt gt + 8000a78: 18d2 addgt r2, r2, r3 + 8000a7a: 4041 eorgt r1, r0 + 8000a7c: 4048 eorgt r0, r1 + 8000a7e: 4041 eorgt r1, r0 + 8000a80: bfb8 it lt + 8000a82: 425b neglt r3, r3 + 8000a84: 2b19 cmp r3, #25 + 8000a86: bf88 it hi + 8000a88: 4770 bxhi lr + 8000a8a: f010 4f00 tst.w r0, #2147483648 ; 0x80000000 + 8000a8e: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000a92: f020 407f bic.w r0, r0, #4278190080 ; 0xff000000 + 8000a96: bf18 it ne + 8000a98: 4240 negne r0, r0 + 8000a9a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000a9e: f441 0100 orr.w r1, r1, #8388608 ; 0x800000 + 8000aa2: f021 417f bic.w r1, r1, #4278190080 ; 0xff000000 + 8000aa6: bf18 it ne + 8000aa8: 4249 negne r1, r1 + 8000aaa: ea92 0f03 teq r2, r3 + 8000aae: d03f beq.n 8000b30 <__addsf3+0xd8> + 8000ab0: f1a2 0201 sub.w r2, r2, #1 + 8000ab4: fa41 fc03 asr.w ip, r1, r3 + 8000ab8: eb10 000c adds.w r0, r0, ip + 8000abc: f1c3 0320 rsb r3, r3, #32 + 8000ac0: fa01 f103 lsl.w r1, r1, r3 + 8000ac4: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 + 8000ac8: d502 bpl.n 8000ad0 <__addsf3+0x78> + 8000aca: 4249 negs r1, r1 + 8000acc: eb60 0040 sbc.w r0, r0, r0, lsl #1 + 8000ad0: f5b0 0f00 cmp.w r0, #8388608 ; 0x800000 + 8000ad4: d313 bcc.n 8000afe <__addsf3+0xa6> + 8000ad6: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 + 8000ada: d306 bcc.n 8000aea <__addsf3+0x92> + 8000adc: 0840 lsrs r0, r0, #1 + 8000ade: ea4f 0131 mov.w r1, r1, rrx + 8000ae2: f102 0201 add.w r2, r2, #1 + 8000ae6: 2afe cmp r2, #254 ; 0xfe + 8000ae8: d251 bcs.n 8000b8e <__addsf3+0x136> + 8000aea: f1b1 4f00 cmp.w r1, #2147483648 ; 0x80000000 + 8000aee: eb40 50c2 adc.w r0, r0, r2, lsl #23 + 8000af2: bf08 it eq + 8000af4: f020 0001 biceq.w r0, r0, #1 + 8000af8: ea40 0003 orr.w r0, r0, r3 + 8000afc: 4770 bx lr + 8000afe: 0049 lsls r1, r1, #1 + 8000b00: eb40 0000 adc.w r0, r0, r0 + 8000b04: f410 0f00 tst.w r0, #8388608 ; 0x800000 + 8000b08: f1a2 0201 sub.w r2, r2, #1 + 8000b0c: d1ed bne.n 8000aea <__addsf3+0x92> + 8000b0e: fab0 fc80 clz ip, r0 + 8000b12: f1ac 0c08 sub.w ip, ip, #8 + 8000b16: ebb2 020c subs.w r2, r2, ip + 8000b1a: fa00 f00c lsl.w r0, r0, ip + 8000b1e: bfaa itet ge + 8000b20: eb00 50c2 addge.w r0, r0, r2, lsl #23 + 8000b24: 4252 neglt r2, r2 + 8000b26: 4318 orrge r0, r3 + 8000b28: bfbc itt lt + 8000b2a: 40d0 lsrlt r0, r2 + 8000b2c: 4318 orrlt r0, r3 + 8000b2e: 4770 bx lr + 8000b30: f092 0f00 teq r2, #0 + 8000b34: f481 0100 eor.w r1, r1, #8388608 ; 0x800000 + 8000b38: bf06 itte eq + 8000b3a: f480 0000 eoreq.w r0, r0, #8388608 ; 0x800000 + 8000b3e: 3201 addeq r2, #1 + 8000b40: 3b01 subne r3, #1 + 8000b42: e7b5 b.n 8000ab0 <__addsf3+0x58> + 8000b44: ea4f 0341 mov.w r3, r1, lsl #1 + 8000b48: ea7f 6c22 mvns.w ip, r2, asr #24 + 8000b4c: bf18 it ne + 8000b4e: ea7f 6c23 mvnsne.w ip, r3, asr #24 + 8000b52: d021 beq.n 8000b98 <__addsf3+0x140> + 8000b54: ea92 0f03 teq r2, r3 + 8000b58: d004 beq.n 8000b64 <__addsf3+0x10c> + 8000b5a: f092 0f00 teq r2, #0 + 8000b5e: bf08 it eq + 8000b60: 4608 moveq r0, r1 + 8000b62: 4770 bx lr + 8000b64: ea90 0f01 teq r0, r1 + 8000b68: bf1c itt ne + 8000b6a: 2000 movne r0, #0 + 8000b6c: 4770 bxne lr + 8000b6e: f012 4f7f tst.w r2, #4278190080 ; 0xff000000 + 8000b72: d104 bne.n 8000b7e <__addsf3+0x126> + 8000b74: 0040 lsls r0, r0, #1 + 8000b76: bf28 it cs + 8000b78: f040 4000 orrcs.w r0, r0, #2147483648 ; 0x80000000 + 8000b7c: 4770 bx lr + 8000b7e: f112 7200 adds.w r2, r2, #33554432 ; 0x2000000 + 8000b82: bf3c itt cc + 8000b84: f500 0000 addcc.w r0, r0, #8388608 ; 0x800000 + 8000b88: 4770 bxcc lr + 8000b8a: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 + 8000b8e: f043 40fe orr.w r0, r3, #2130706432 ; 0x7f000000 + 8000b92: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000b96: 4770 bx lr + 8000b98: ea7f 6222 mvns.w r2, r2, asr #24 + 8000b9c: bf16 itet ne + 8000b9e: 4608 movne r0, r1 + 8000ba0: ea7f 6323 mvnseq.w r3, r3, asr #24 + 8000ba4: 4601 movne r1, r0 + 8000ba6: 0242 lsls r2, r0, #9 + 8000ba8: bf06 itte eq + 8000baa: ea5f 2341 movseq.w r3, r1, lsl #9 + 8000bae: ea90 0f01 teqeq r0, r1 + 8000bb2: f440 0080 orrne.w r0, r0, #4194304 ; 0x400000 + 8000bb6: 4770 bx lr + +08000bb8 <__aeabi_ui2f>: + 8000bb8: f04f 0300 mov.w r3, #0 + 8000bbc: e004 b.n 8000bc8 <__aeabi_i2f+0x8> + 8000bbe: bf00 nop + +08000bc0 <__aeabi_i2f>: + 8000bc0: f010 4300 ands.w r3, r0, #2147483648 ; 0x80000000 + 8000bc4: bf48 it mi + 8000bc6: 4240 negmi r0, r0 + 8000bc8: ea5f 0c00 movs.w ip, r0 + 8000bcc: bf08 it eq + 8000bce: 4770 bxeq lr + 8000bd0: f043 4396 orr.w r3, r3, #1258291200 ; 0x4b000000 + 8000bd4: 4601 mov r1, r0 + 8000bd6: f04f 0000 mov.w r0, #0 + 8000bda: e01c b.n 8000c16 <__aeabi_l2f+0x2a> + +08000bdc <__aeabi_ul2f>: + 8000bdc: ea50 0201 orrs.w r2, r0, r1 + 8000be0: bf08 it eq + 8000be2: 4770 bxeq lr + 8000be4: f04f 0300 mov.w r3, #0 + 8000be8: e00a b.n 8000c00 <__aeabi_l2f+0x14> + 8000bea: bf00 nop + +08000bec <__aeabi_l2f>: + 8000bec: ea50 0201 orrs.w r2, r0, r1 + 8000bf0: bf08 it eq + 8000bf2: 4770 bxeq lr + 8000bf4: f011 4300 ands.w r3, r1, #2147483648 ; 0x80000000 + 8000bf8: d502 bpl.n 8000c00 <__aeabi_l2f+0x14> + 8000bfa: 4240 negs r0, r0 + 8000bfc: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8000c00: ea5f 0c01 movs.w ip, r1 + 8000c04: bf02 ittt eq + 8000c06: 4684 moveq ip, r0 + 8000c08: 4601 moveq r1, r0 + 8000c0a: 2000 moveq r0, #0 + 8000c0c: f043 43b6 orr.w r3, r3, #1526726656 ; 0x5b000000 + 8000c10: bf08 it eq + 8000c12: f1a3 5380 subeq.w r3, r3, #268435456 ; 0x10000000 + 8000c16: f5a3 0300 sub.w r3, r3, #8388608 ; 0x800000 + 8000c1a: fabc f28c clz r2, ip + 8000c1e: 3a08 subs r2, #8 + 8000c20: eba3 53c2 sub.w r3, r3, r2, lsl #23 + 8000c24: db10 blt.n 8000c48 <__aeabi_l2f+0x5c> + 8000c26: fa01 fc02 lsl.w ip, r1, r2 + 8000c2a: 4463 add r3, ip + 8000c2c: fa00 fc02 lsl.w ip, r0, r2 + 8000c30: f1c2 0220 rsb r2, r2, #32 + 8000c34: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 + 8000c38: fa20 f202 lsr.w r2, r0, r2 + 8000c3c: eb43 0002 adc.w r0, r3, r2 + 8000c40: bf08 it eq + 8000c42: f020 0001 biceq.w r0, r0, #1 + 8000c46: 4770 bx lr + 8000c48: f102 0220 add.w r2, r2, #32 + 8000c4c: fa01 fc02 lsl.w ip, r1, r2 + 8000c50: f1c2 0220 rsb r2, r2, #32 + 8000c54: ea50 004c orrs.w r0, r0, ip, lsl #1 + 8000c58: fa21 f202 lsr.w r2, r1, r2 + 8000c5c: eb43 0002 adc.w r0, r3, r2 + 8000c60: bf08 it eq + 8000c62: ea20 70dc biceq.w r0, r0, ip, lsr #31 + 8000c66: 4770 bx lr + +08000c68 <__aeabi_fmul>: + 8000c68: f04f 0cff mov.w ip, #255 ; 0xff + 8000c6c: ea1c 52d0 ands.w r2, ip, r0, lsr #23 + 8000c70: bf1e ittt ne + 8000c72: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 + 8000c76: ea92 0f0c teqne r2, ip + 8000c7a: ea93 0f0c teqne r3, ip + 8000c7e: d06f beq.n 8000d60 <__aeabi_fmul+0xf8> + 8000c80: 441a add r2, r3 + 8000c82: ea80 0c01 eor.w ip, r0, r1 + 8000c86: 0240 lsls r0, r0, #9 + 8000c88: bf18 it ne + 8000c8a: ea5f 2141 movsne.w r1, r1, lsl #9 + 8000c8e: d01e beq.n 8000cce <__aeabi_fmul+0x66> + 8000c90: f04f 6300 mov.w r3, #134217728 ; 0x8000000 + 8000c94: ea43 1050 orr.w r0, r3, r0, lsr #5 + 8000c98: ea43 1151 orr.w r1, r3, r1, lsr #5 + 8000c9c: fba0 3101 umull r3, r1, r0, r1 + 8000ca0: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 + 8000ca4: f5b1 0f00 cmp.w r1, #8388608 ; 0x800000 + 8000ca8: bf3e ittt cc + 8000caa: 0049 lslcc r1, r1, #1 + 8000cac: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 + 8000cb0: 005b lslcc r3, r3, #1 + 8000cb2: ea40 0001 orr.w r0, r0, r1 + 8000cb6: f162 027f sbc.w r2, r2, #127 ; 0x7f + 8000cba: 2afd cmp r2, #253 ; 0xfd + 8000cbc: d81d bhi.n 8000cfa <__aeabi_fmul+0x92> + 8000cbe: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 8000cc2: eb40 50c2 adc.w r0, r0, r2, lsl #23 + 8000cc6: bf08 it eq + 8000cc8: f020 0001 biceq.w r0, r0, #1 + 8000ccc: 4770 bx lr + 8000cce: f090 0f00 teq r0, #0 + 8000cd2: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 + 8000cd6: bf08 it eq + 8000cd8: 0249 lsleq r1, r1, #9 + 8000cda: ea4c 2050 orr.w r0, ip, r0, lsr #9 + 8000cde: ea40 2051 orr.w r0, r0, r1, lsr #9 + 8000ce2: 3a7f subs r2, #127 ; 0x7f + 8000ce4: bfc2 ittt gt + 8000ce6: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff + 8000cea: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 + 8000cee: 4770 bxgt lr + 8000cf0: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000cf4: f04f 0300 mov.w r3, #0 + 8000cf8: 3a01 subs r2, #1 + 8000cfa: dc5d bgt.n 8000db8 <__aeabi_fmul+0x150> + 8000cfc: f112 0f19 cmn.w r2, #25 + 8000d00: bfdc itt le + 8000d02: f000 4000 andle.w r0, r0, #2147483648 ; 0x80000000 + 8000d06: 4770 bxle lr + 8000d08: f1c2 0200 rsb r2, r2, #0 + 8000d0c: 0041 lsls r1, r0, #1 + 8000d0e: fa21 f102 lsr.w r1, r1, r2 + 8000d12: f1c2 0220 rsb r2, r2, #32 + 8000d16: fa00 fc02 lsl.w ip, r0, r2 + 8000d1a: ea5f 0031 movs.w r0, r1, rrx + 8000d1e: f140 0000 adc.w r0, r0, #0 + 8000d22: ea53 034c orrs.w r3, r3, ip, lsl #1 + 8000d26: bf08 it eq + 8000d28: ea20 70dc biceq.w r0, r0, ip, lsr #31 + 8000d2c: 4770 bx lr + 8000d2e: f092 0f00 teq r2, #0 + 8000d32: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 + 8000d36: bf02 ittt eq + 8000d38: 0040 lsleq r0, r0, #1 + 8000d3a: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 + 8000d3e: 3a01 subeq r2, #1 + 8000d40: d0f9 beq.n 8000d36 <__aeabi_fmul+0xce> + 8000d42: ea40 000c orr.w r0, r0, ip + 8000d46: f093 0f00 teq r3, #0 + 8000d4a: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 + 8000d4e: bf02 ittt eq + 8000d50: 0049 lsleq r1, r1, #1 + 8000d52: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 + 8000d56: 3b01 subeq r3, #1 + 8000d58: d0f9 beq.n 8000d4e <__aeabi_fmul+0xe6> + 8000d5a: ea41 010c orr.w r1, r1, ip + 8000d5e: e78f b.n 8000c80 <__aeabi_fmul+0x18> + 8000d60: ea0c 53d1 and.w r3, ip, r1, lsr #23 + 8000d64: ea92 0f0c teq r2, ip + 8000d68: bf18 it ne + 8000d6a: ea93 0f0c teqne r3, ip + 8000d6e: d00a beq.n 8000d86 <__aeabi_fmul+0x11e> + 8000d70: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 + 8000d74: bf18 it ne + 8000d76: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 + 8000d7a: d1d8 bne.n 8000d2e <__aeabi_fmul+0xc6> + 8000d7c: ea80 0001 eor.w r0, r0, r1 + 8000d80: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 + 8000d84: 4770 bx lr + 8000d86: f090 0f00 teq r0, #0 + 8000d8a: bf17 itett ne + 8000d8c: f090 4f00 teqne r0, #2147483648 ; 0x80000000 + 8000d90: 4608 moveq r0, r1 + 8000d92: f091 0f00 teqne r1, #0 + 8000d96: f091 4f00 teqne r1, #2147483648 ; 0x80000000 + 8000d9a: d014 beq.n 8000dc6 <__aeabi_fmul+0x15e> + 8000d9c: ea92 0f0c teq r2, ip + 8000da0: d101 bne.n 8000da6 <__aeabi_fmul+0x13e> + 8000da2: 0242 lsls r2, r0, #9 + 8000da4: d10f bne.n 8000dc6 <__aeabi_fmul+0x15e> + 8000da6: ea93 0f0c teq r3, ip + 8000daa: d103 bne.n 8000db4 <__aeabi_fmul+0x14c> + 8000dac: 024b lsls r3, r1, #9 + 8000dae: bf18 it ne + 8000db0: 4608 movne r0, r1 + 8000db2: d108 bne.n 8000dc6 <__aeabi_fmul+0x15e> + 8000db4: ea80 0001 eor.w r0, r0, r1 + 8000db8: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 + 8000dbc: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 + 8000dc0: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000dc4: 4770 bx lr + 8000dc6: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 + 8000dca: f440 0040 orr.w r0, r0, #12582912 ; 0xc00000 + 8000dce: 4770 bx lr + +08000dd0 <__aeabi_fdiv>: + 8000dd0: f04f 0cff mov.w ip, #255 ; 0xff + 8000dd4: ea1c 52d0 ands.w r2, ip, r0, lsr #23 + 8000dd8: bf1e ittt ne + 8000dda: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 + 8000dde: ea92 0f0c teqne r2, ip + 8000de2: ea93 0f0c teqne r3, ip + 8000de6: d069 beq.n 8000ebc <__aeabi_fdiv+0xec> + 8000de8: eba2 0203 sub.w r2, r2, r3 + 8000dec: ea80 0c01 eor.w ip, r0, r1 + 8000df0: 0249 lsls r1, r1, #9 + 8000df2: ea4f 2040 mov.w r0, r0, lsl #9 + 8000df6: d037 beq.n 8000e68 <__aeabi_fdiv+0x98> + 8000df8: f04f 5380 mov.w r3, #268435456 ; 0x10000000 + 8000dfc: ea43 1111 orr.w r1, r3, r1, lsr #4 + 8000e00: ea43 1310 orr.w r3, r3, r0, lsr #4 + 8000e04: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 + 8000e08: 428b cmp r3, r1 + 8000e0a: bf38 it cc + 8000e0c: 005b lslcc r3, r3, #1 + 8000e0e: f142 027d adc.w r2, r2, #125 ; 0x7d + 8000e12: f44f 0c00 mov.w ip, #8388608 ; 0x800000 + 8000e16: 428b cmp r3, r1 + 8000e18: bf24 itt cs + 8000e1a: 1a5b subcs r3, r3, r1 + 8000e1c: ea40 000c orrcs.w r0, r0, ip + 8000e20: ebb3 0f51 cmp.w r3, r1, lsr #1 + 8000e24: bf24 itt cs + 8000e26: eba3 0351 subcs.w r3, r3, r1, lsr #1 + 8000e2a: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 8000e2e: ebb3 0f91 cmp.w r3, r1, lsr #2 + 8000e32: bf24 itt cs + 8000e34: eba3 0391 subcs.w r3, r3, r1, lsr #2 + 8000e38: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 8000e3c: ebb3 0fd1 cmp.w r3, r1, lsr #3 + 8000e40: bf24 itt cs + 8000e42: eba3 03d1 subcs.w r3, r3, r1, lsr #3 + 8000e46: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 8000e4a: 011b lsls r3, r3, #4 + 8000e4c: bf18 it ne + 8000e4e: ea5f 1c1c movsne.w ip, ip, lsr #4 + 8000e52: d1e0 bne.n 8000e16 <__aeabi_fdiv+0x46> + 8000e54: 2afd cmp r2, #253 ; 0xfd + 8000e56: f63f af50 bhi.w 8000cfa <__aeabi_fmul+0x92> + 8000e5a: 428b cmp r3, r1 + 8000e5c: eb40 50c2 adc.w r0, r0, r2, lsl #23 + 8000e60: bf08 it eq + 8000e62: f020 0001 biceq.w r0, r0, #1 + 8000e66: 4770 bx lr + 8000e68: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 + 8000e6c: ea4c 2050 orr.w r0, ip, r0, lsr #9 + 8000e70: 327f adds r2, #127 ; 0x7f + 8000e72: bfc2 ittt gt + 8000e74: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff + 8000e78: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 + 8000e7c: 4770 bxgt lr + 8000e7e: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 + 8000e82: f04f 0300 mov.w r3, #0 + 8000e86: 3a01 subs r2, #1 + 8000e88: e737 b.n 8000cfa <__aeabi_fmul+0x92> + 8000e8a: f092 0f00 teq r2, #0 + 8000e8e: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 + 8000e92: bf02 ittt eq + 8000e94: 0040 lsleq r0, r0, #1 + 8000e96: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 + 8000e9a: 3a01 subeq r2, #1 + 8000e9c: d0f9 beq.n 8000e92 <__aeabi_fdiv+0xc2> + 8000e9e: ea40 000c orr.w r0, r0, ip + 8000ea2: f093 0f00 teq r3, #0 + 8000ea6: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 + 8000eaa: bf02 ittt eq + 8000eac: 0049 lsleq r1, r1, #1 + 8000eae: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 + 8000eb2: 3b01 subeq r3, #1 + 8000eb4: d0f9 beq.n 8000eaa <__aeabi_fdiv+0xda> + 8000eb6: ea41 010c orr.w r1, r1, ip + 8000eba: e795 b.n 8000de8 <__aeabi_fdiv+0x18> + 8000ebc: ea0c 53d1 and.w r3, ip, r1, lsr #23 + 8000ec0: ea92 0f0c teq r2, ip + 8000ec4: d108 bne.n 8000ed8 <__aeabi_fdiv+0x108> + 8000ec6: 0242 lsls r2, r0, #9 + 8000ec8: f47f af7d bne.w 8000dc6 <__aeabi_fmul+0x15e> + 8000ecc: ea93 0f0c teq r3, ip + 8000ed0: f47f af70 bne.w 8000db4 <__aeabi_fmul+0x14c> + 8000ed4: 4608 mov r0, r1 + 8000ed6: e776 b.n 8000dc6 <__aeabi_fmul+0x15e> + 8000ed8: ea93 0f0c teq r3, ip + 8000edc: d104 bne.n 8000ee8 <__aeabi_fdiv+0x118> + 8000ede: 024b lsls r3, r1, #9 + 8000ee0: f43f af4c beq.w 8000d7c <__aeabi_fmul+0x114> + 8000ee4: 4608 mov r0, r1 + 8000ee6: e76e b.n 8000dc6 <__aeabi_fmul+0x15e> + 8000ee8: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 + 8000eec: bf18 it ne + 8000eee: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 + 8000ef2: d1ca bne.n 8000e8a <__aeabi_fdiv+0xba> + 8000ef4: f030 4200 bics.w r2, r0, #2147483648 ; 0x80000000 + 8000ef8: f47f af5c bne.w 8000db4 <__aeabi_fmul+0x14c> + 8000efc: f031 4300 bics.w r3, r1, #2147483648 ; 0x80000000 + 8000f00: f47f af3c bne.w 8000d7c <__aeabi_fmul+0x114> + 8000f04: e75f b.n 8000dc6 <__aeabi_fmul+0x15e> + 8000f06: bf00 nop + +08000f08 <__gesf2>: + 8000f08: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff + 8000f0c: e006 b.n 8000f1c <__cmpsf2+0x4> + 8000f0e: bf00 nop + +08000f10 <__lesf2>: + 8000f10: f04f 0c01 mov.w ip, #1 + 8000f14: e002 b.n 8000f1c <__cmpsf2+0x4> + 8000f16: bf00 nop + +08000f18 <__cmpsf2>: + 8000f18: f04f 0c01 mov.w ip, #1 + 8000f1c: f84d cd04 str.w ip, [sp, #-4]! + 8000f20: ea4f 0240 mov.w r2, r0, lsl #1 + 8000f24: ea4f 0341 mov.w r3, r1, lsl #1 + 8000f28: ea7f 6c22 mvns.w ip, r2, asr #24 + 8000f2c: bf18 it ne + 8000f2e: ea7f 6c23 mvnsne.w ip, r3, asr #24 + 8000f32: d011 beq.n 8000f58 <__cmpsf2+0x40> + 8000f34: b001 add sp, #4 + 8000f36: ea52 0c53 orrs.w ip, r2, r3, lsr #1 + 8000f3a: bf18 it ne + 8000f3c: ea90 0f01 teqne r0, r1 + 8000f40: bf58 it pl + 8000f42: ebb2 0003 subspl.w r0, r2, r3 + 8000f46: bf88 it hi + 8000f48: 17c8 asrhi r0, r1, #31 + 8000f4a: bf38 it cc + 8000f4c: ea6f 70e1 mvncc.w r0, r1, asr #31 + 8000f50: bf18 it ne + 8000f52: f040 0001 orrne.w r0, r0, #1 + 8000f56: 4770 bx lr + 8000f58: ea7f 6c22 mvns.w ip, r2, asr #24 + 8000f5c: d102 bne.n 8000f64 <__cmpsf2+0x4c> + 8000f5e: ea5f 2c40 movs.w ip, r0, lsl #9 + 8000f62: d105 bne.n 8000f70 <__cmpsf2+0x58> + 8000f64: ea7f 6c23 mvns.w ip, r3, asr #24 + 8000f68: d1e4 bne.n 8000f34 <__cmpsf2+0x1c> + 8000f6a: ea5f 2c41 movs.w ip, r1, lsl #9 + 8000f6e: d0e1 beq.n 8000f34 <__cmpsf2+0x1c> + 8000f70: f85d 0b04 ldr.w r0, [sp], #4 + 8000f74: 4770 bx lr + 8000f76: bf00 nop + +08000f78 <__aeabi_cfrcmple>: + 8000f78: 4684 mov ip, r0 + 8000f7a: 4608 mov r0, r1 + 8000f7c: 4661 mov r1, ip + 8000f7e: e7ff b.n 8000f80 <__aeabi_cfcmpeq> + +08000f80 <__aeabi_cfcmpeq>: + 8000f80: b50f push {r0, r1, r2, r3, lr} + 8000f82: f7ff ffc9 bl 8000f18 <__cmpsf2> + 8000f86: 2800 cmp r0, #0 + 8000f88: bf48 it mi + 8000f8a: f110 0f00 cmnmi.w r0, #0 + 8000f8e: bd0f pop {r0, r1, r2, r3, pc} + +08000f90 <__aeabi_fcmpeq>: + 8000f90: f84d ed08 str.w lr, [sp, #-8]! + 8000f94: f7ff fff4 bl 8000f80 <__aeabi_cfcmpeq> + 8000f98: bf0c ite eq + 8000f9a: 2001 moveq r0, #1 + 8000f9c: 2000 movne r0, #0 + 8000f9e: f85d fb08 ldr.w pc, [sp], #8 + 8000fa2: bf00 nop + +08000fa4 <__aeabi_fcmplt>: + 8000fa4: f84d ed08 str.w lr, [sp, #-8]! + 8000fa8: f7ff ffea bl 8000f80 <__aeabi_cfcmpeq> + 8000fac: bf34 ite cc + 8000fae: 2001 movcc r0, #1 + 8000fb0: 2000 movcs r0, #0 + 8000fb2: f85d fb08 ldr.w pc, [sp], #8 + 8000fb6: bf00 nop + +08000fb8 <__aeabi_fcmple>: + 8000fb8: f84d ed08 str.w lr, [sp, #-8]! + 8000fbc: f7ff ffe0 bl 8000f80 <__aeabi_cfcmpeq> + 8000fc0: bf94 ite ls + 8000fc2: 2001 movls r0, #1 + 8000fc4: 2000 movhi r0, #0 + 8000fc6: f85d fb08 ldr.w pc, [sp], #8 + 8000fca: bf00 nop + +08000fcc <__aeabi_fcmpge>: + 8000fcc: f84d ed08 str.w lr, [sp, #-8]! + 8000fd0: f7ff ffd2 bl 8000f78 <__aeabi_cfrcmple> + 8000fd4: bf94 ite ls + 8000fd6: 2001 movls r0, #1 + 8000fd8: 2000 movhi r0, #0 + 8000fda: f85d fb08 ldr.w pc, [sp], #8 + 8000fde: bf00 nop + +08000fe0 <__aeabi_fcmpgt>: + 8000fe0: f84d ed08 str.w lr, [sp, #-8]! + 8000fe4: f7ff ffc8 bl 8000f78 <__aeabi_cfrcmple> + 8000fe8: bf34 ite cc + 8000fea: 2001 movcc r0, #1 + 8000fec: 2000 movcs r0, #0 + 8000fee: f85d fb08 ldr.w pc, [sp], #8 + 8000ff2: bf00 nop + +08000ff4 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000ff4: b580 push {r7, lr} + 8000ff6: af00 add r7, sp, #0 + defined(STM32F102x6) || defined(STM32F102xB) || \ + defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ + defined(STM32F105xC) || defined(STM32F107xC) + + /* Prefetch buffer is not available on value line devices */ + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 8000ff8: 4b08 ldr r3, [pc, #32] ; (800101c ) + 8000ffa: 681b ldr r3, [r3, #0] + 8000ffc: 4a07 ldr r2, [pc, #28] ; (800101c ) + 8000ffe: f043 0310 orr.w r3, r3, #16 + 8001002: 6013 str r3, [r2, #0] +#endif +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8001004: 2003 movs r0, #3 + 8001006: f000 f945 bl 8001294 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 800100a: 200f movs r0, #15 + 800100c: f000 f808 bl 8001020 + + /* Init the low level hardware */ + HAL_MspInit(); + 8001010: f008 ff9c bl 8009f4c + + /* Return function status */ + return HAL_OK; + 8001014: 2300 movs r3, #0 +} + 8001016: 4618 mov r0, r3 + 8001018: bd80 pop {r7, pc} + 800101a: bf00 nop + 800101c: 40022000 .word 0x40022000 + +08001020 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8001020: b580 push {r7, lr} + 8001022: b082 sub sp, #8 + 8001024: af00 add r7, sp, #0 + 8001026: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 8001028: 4b12 ldr r3, [pc, #72] ; (8001074 ) + 800102a: 681a ldr r2, [r3, #0] + 800102c: 4b12 ldr r3, [pc, #72] ; (8001078 ) + 800102e: 781b ldrb r3, [r3, #0] + 8001030: 4619 mov r1, r3 + 8001032: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001036: fbb3 f3f1 udiv r3, r3, r1 + 800103a: fbb2 f3f3 udiv r3, r2, r3 + 800103e: 4618 mov r0, r3 + 8001040: f000 f95d bl 80012fe + 8001044: 4603 mov r3, r0 + 8001046: 2b00 cmp r3, #0 + 8001048: d001 beq.n 800104e + { + return HAL_ERROR; + 800104a: 2301 movs r3, #1 + 800104c: e00e b.n 800106c + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 800104e: 687b ldr r3, [r7, #4] + 8001050: 2b0f cmp r3, #15 + 8001052: d80a bhi.n 800106a + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8001054: 2200 movs r2, #0 + 8001056: 6879 ldr r1, [r7, #4] + 8001058: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800105c: f000 f925 bl 80012aa + uwTickPrio = TickPriority; + 8001060: 4a06 ldr r2, [pc, #24] ; (800107c ) + 8001062: 687b ldr r3, [r7, #4] + 8001064: 6013 str r3, [r2, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 8001066: 2300 movs r3, #0 + 8001068: e000 b.n 800106c + return HAL_ERROR; + 800106a: 2301 movs r3, #1 +} + 800106c: 4618 mov r0, r3 + 800106e: 3708 adds r7, #8 + 8001070: 46bd mov sp, r7 + 8001072: bd80 pop {r7, pc} + 8001074: 20000140 .word 0x20000140 + 8001078: 20000004 .word 0x20000004 + 800107c: 20000000 .word 0x20000000 + +08001080 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8001080: b480 push {r7} + 8001082: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8001084: 4b05 ldr r3, [pc, #20] ; (800109c ) + 8001086: 781b ldrb r3, [r3, #0] + 8001088: 461a mov r2, r3 + 800108a: 4b05 ldr r3, [pc, #20] ; (80010a0 ) + 800108c: 681b ldr r3, [r3, #0] + 800108e: 4413 add r3, r2 + 8001090: 4a03 ldr r2, [pc, #12] ; (80010a0 ) + 8001092: 6013 str r3, [r2, #0] +} + 8001094: bf00 nop + 8001096: 46bd mov sp, r7 + 8001098: bc80 pop {r7} + 800109a: 4770 bx lr + 800109c: 20000004 .word 0x20000004 + 80010a0: 200011f4 .word 0x200011f4 + +080010a4 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 80010a4: b480 push {r7} + 80010a6: af00 add r7, sp, #0 + return uwTick; + 80010a8: 4b02 ldr r3, [pc, #8] ; (80010b4 ) + 80010aa: 681b ldr r3, [r3, #0] +} + 80010ac: 4618 mov r0, r3 + 80010ae: 46bd mov sp, r7 + 80010b0: bc80 pop {r7} + 80010b2: 4770 bx lr + 80010b4: 200011f4 .word 0x200011f4 + +080010b8 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 80010b8: b580 push {r7, lr} + 80010ba: b084 sub sp, #16 + 80010bc: af00 add r7, sp, #0 + 80010be: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 80010c0: f7ff fff0 bl 80010a4 + 80010c4: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 80010c6: 687b ldr r3, [r7, #4] + 80010c8: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 80010ca: 68fb ldr r3, [r7, #12] + 80010cc: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80010d0: d005 beq.n 80010de + { + wait += (uint32_t)(uwTickFreq); + 80010d2: 4b09 ldr r3, [pc, #36] ; (80010f8 ) + 80010d4: 781b ldrb r3, [r3, #0] + 80010d6: 461a mov r2, r3 + 80010d8: 68fb ldr r3, [r7, #12] + 80010da: 4413 add r3, r2 + 80010dc: 60fb str r3, [r7, #12] + } + + while ((HAL_GetTick() - tickstart) < wait) + 80010de: bf00 nop + 80010e0: f7ff ffe0 bl 80010a4 + 80010e4: 4602 mov r2, r0 + 80010e6: 68bb ldr r3, [r7, #8] + 80010e8: 1ad3 subs r3, r2, r3 + 80010ea: 68fa ldr r2, [r7, #12] + 80010ec: 429a cmp r2, r3 + 80010ee: d8f7 bhi.n 80010e0 + { + } +} + 80010f0: bf00 nop + 80010f2: 3710 adds r7, #16 + 80010f4: 46bd mov sp, r7 + 80010f6: bd80 pop {r7, pc} + 80010f8: 20000004 .word 0x20000004 + +080010fc <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80010fc: b480 push {r7} + 80010fe: b085 sub sp, #20 + 8001100: af00 add r7, sp, #0 + 8001102: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001104: 687b ldr r3, [r7, #4] + 8001106: f003 0307 and.w r3, r3, #7 + 800110a: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 800110c: 4b0c ldr r3, [pc, #48] ; (8001140 <__NVIC_SetPriorityGrouping+0x44>) + 800110e: 68db ldr r3, [r3, #12] + 8001110: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8001112: 68ba ldr r2, [r7, #8] + 8001114: f64f 03ff movw r3, #63743 ; 0xf8ff + 8001118: 4013 ands r3, r2 + 800111a: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 800111c: 68fb ldr r3, [r7, #12] + 800111e: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8001120: 68bb ldr r3, [r7, #8] + 8001122: 4313 orrs r3, r2 + reg_value = (reg_value | + 8001124: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 8001128: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 800112c: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 800112e: 4a04 ldr r2, [pc, #16] ; (8001140 <__NVIC_SetPriorityGrouping+0x44>) + 8001130: 68bb ldr r3, [r7, #8] + 8001132: 60d3 str r3, [r2, #12] +} + 8001134: bf00 nop + 8001136: 3714 adds r7, #20 + 8001138: 46bd mov sp, r7 + 800113a: bc80 pop {r7} + 800113c: 4770 bx lr + 800113e: bf00 nop + 8001140: e000ed00 .word 0xe000ed00 + +08001144 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8001144: b480 push {r7} + 8001146: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8001148: 4b04 ldr r3, [pc, #16] ; (800115c <__NVIC_GetPriorityGrouping+0x18>) + 800114a: 68db ldr r3, [r3, #12] + 800114c: 0a1b lsrs r3, r3, #8 + 800114e: f003 0307 and.w r3, r3, #7 +} + 8001152: 4618 mov r0, r3 + 8001154: 46bd mov sp, r7 + 8001156: bc80 pop {r7} + 8001158: 4770 bx lr + 800115a: bf00 nop + 800115c: e000ed00 .word 0xe000ed00 + +08001160 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001160: b480 push {r7} + 8001162: b083 sub sp, #12 + 8001164: af00 add r7, sp, #0 + 8001166: 4603 mov r3, r0 + 8001168: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 800116a: f997 3007 ldrsb.w r3, [r7, #7] + 800116e: 2b00 cmp r3, #0 + 8001170: db0b blt.n 800118a <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8001172: 79fb ldrb r3, [r7, #7] + 8001174: f003 021f and.w r2, r3, #31 + 8001178: 4906 ldr r1, [pc, #24] ; (8001194 <__NVIC_EnableIRQ+0x34>) + 800117a: f997 3007 ldrsb.w r3, [r7, #7] + 800117e: 095b lsrs r3, r3, #5 + 8001180: 2001 movs r0, #1 + 8001182: fa00 f202 lsl.w r2, r0, r2 + 8001186: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 800118a: bf00 nop + 800118c: 370c adds r7, #12 + 800118e: 46bd mov sp, r7 + 8001190: bc80 pop {r7} + 8001192: 4770 bx lr + 8001194: e000e100 .word 0xe000e100 + +08001198 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8001198: b480 push {r7} + 800119a: b083 sub sp, #12 + 800119c: af00 add r7, sp, #0 + 800119e: 4603 mov r3, r0 + 80011a0: 6039 str r1, [r7, #0] + 80011a2: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 80011a4: f997 3007 ldrsb.w r3, [r7, #7] + 80011a8: 2b00 cmp r3, #0 + 80011aa: db0a blt.n 80011c2 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 80011ac: 683b ldr r3, [r7, #0] + 80011ae: b2da uxtb r2, r3 + 80011b0: 490c ldr r1, [pc, #48] ; (80011e4 <__NVIC_SetPriority+0x4c>) + 80011b2: f997 3007 ldrsb.w r3, [r7, #7] + 80011b6: 0112 lsls r2, r2, #4 + 80011b8: b2d2 uxtb r2, r2 + 80011ba: 440b add r3, r1 + 80011bc: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 80011c0: e00a b.n 80011d8 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 80011c2: 683b ldr r3, [r7, #0] + 80011c4: b2da uxtb r2, r3 + 80011c6: 4908 ldr r1, [pc, #32] ; (80011e8 <__NVIC_SetPriority+0x50>) + 80011c8: 79fb ldrb r3, [r7, #7] + 80011ca: f003 030f and.w r3, r3, #15 + 80011ce: 3b04 subs r3, #4 + 80011d0: 0112 lsls r2, r2, #4 + 80011d2: b2d2 uxtb r2, r2 + 80011d4: 440b add r3, r1 + 80011d6: 761a strb r2, [r3, #24] +} + 80011d8: bf00 nop + 80011da: 370c adds r7, #12 + 80011dc: 46bd mov sp, r7 + 80011de: bc80 pop {r7} + 80011e0: 4770 bx lr + 80011e2: bf00 nop + 80011e4: e000e100 .word 0xe000e100 + 80011e8: e000ed00 .word 0xe000ed00 + +080011ec : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80011ec: b480 push {r7} + 80011ee: b089 sub sp, #36 ; 0x24 + 80011f0: af00 add r7, sp, #0 + 80011f2: 60f8 str r0, [r7, #12] + 80011f4: 60b9 str r1, [r7, #8] + 80011f6: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80011f8: 68fb ldr r3, [r7, #12] + 80011fa: f003 0307 and.w r3, r3, #7 + 80011fe: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8001200: 69fb ldr r3, [r7, #28] + 8001202: f1c3 0307 rsb r3, r3, #7 + 8001206: 2b04 cmp r3, #4 + 8001208: bf28 it cs + 800120a: 2304 movcs r3, #4 + 800120c: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 800120e: 69fb ldr r3, [r7, #28] + 8001210: 3304 adds r3, #4 + 8001212: 2b06 cmp r3, #6 + 8001214: d902 bls.n 800121c + 8001216: 69fb ldr r3, [r7, #28] + 8001218: 3b03 subs r3, #3 + 800121a: e000 b.n 800121e + 800121c: 2300 movs r3, #0 + 800121e: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001220: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8001224: 69bb ldr r3, [r7, #24] + 8001226: fa02 f303 lsl.w r3, r2, r3 + 800122a: 43da mvns r2, r3 + 800122c: 68bb ldr r3, [r7, #8] + 800122e: 401a ands r2, r3 + 8001230: 697b ldr r3, [r7, #20] + 8001232: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8001234: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 8001238: 697b ldr r3, [r7, #20] + 800123a: fa01 f303 lsl.w r3, r1, r3 + 800123e: 43d9 mvns r1, r3 + 8001240: 687b ldr r3, [r7, #4] + 8001242: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001244: 4313 orrs r3, r2 + ); +} + 8001246: 4618 mov r0, r3 + 8001248: 3724 adds r7, #36 ; 0x24 + 800124a: 46bd mov sp, r7 + 800124c: bc80 pop {r7} + 800124e: 4770 bx lr + +08001250 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8001250: b580 push {r7, lr} + 8001252: b082 sub sp, #8 + 8001254: af00 add r7, sp, #0 + 8001256: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8001258: 687b ldr r3, [r7, #4] + 800125a: 3b01 subs r3, #1 + 800125c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8001260: d301 bcc.n 8001266 + { + return (1UL); /* Reload value impossible */ + 8001262: 2301 movs r3, #1 + 8001264: e00f b.n 8001286 + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8001266: 4a0a ldr r2, [pc, #40] ; (8001290 ) + 8001268: 687b ldr r3, [r7, #4] + 800126a: 3b01 subs r3, #1 + 800126c: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 800126e: 210f movs r1, #15 + 8001270: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8001274: f7ff ff90 bl 8001198 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8001278: 4b05 ldr r3, [pc, #20] ; (8001290 ) + 800127a: 2200 movs r2, #0 + 800127c: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 800127e: 4b04 ldr r3, [pc, #16] ; (8001290 ) + 8001280: 2207 movs r2, #7 + 8001282: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8001284: 2300 movs r3, #0 +} + 8001286: 4618 mov r0, r3 + 8001288: 3708 adds r7, #8 + 800128a: 46bd mov sp, r7 + 800128c: bd80 pop {r7, pc} + 800128e: bf00 nop + 8001290: e000e010 .word 0xe000e010 + +08001294 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8001294: b580 push {r7, lr} + 8001296: b082 sub sp, #8 + 8001298: af00 add r7, sp, #0 + 800129a: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 800129c: 6878 ldr r0, [r7, #4] + 800129e: f7ff ff2d bl 80010fc <__NVIC_SetPriorityGrouping> +} + 80012a2: bf00 nop + 80012a4: 3708 adds r7, #8 + 80012a6: 46bd mov sp, r7 + 80012a8: bd80 pop {r7, pc} + +080012aa : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80012aa: b580 push {r7, lr} + 80012ac: b086 sub sp, #24 + 80012ae: af00 add r7, sp, #0 + 80012b0: 4603 mov r3, r0 + 80012b2: 60b9 str r1, [r7, #8] + 80012b4: 607a str r2, [r7, #4] + 80012b6: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00U; + 80012b8: 2300 movs r3, #0 + 80012ba: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 80012bc: f7ff ff42 bl 8001144 <__NVIC_GetPriorityGrouping> + 80012c0: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 80012c2: 687a ldr r2, [r7, #4] + 80012c4: 68b9 ldr r1, [r7, #8] + 80012c6: 6978 ldr r0, [r7, #20] + 80012c8: f7ff ff90 bl 80011ec + 80012cc: 4602 mov r2, r0 + 80012ce: f997 300f ldrsb.w r3, [r7, #15] + 80012d2: 4611 mov r1, r2 + 80012d4: 4618 mov r0, r3 + 80012d6: f7ff ff5f bl 8001198 <__NVIC_SetPriority> +} + 80012da: bf00 nop + 80012dc: 3718 adds r7, #24 + 80012de: 46bd mov sp, r7 + 80012e0: bd80 pop {r7, pc} + +080012e2 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80012e2: b580 push {r7, lr} + 80012e4: b082 sub sp, #8 + 80012e6: af00 add r7, sp, #0 + 80012e8: 4603 mov r3, r0 + 80012ea: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 80012ec: f997 3007 ldrsb.w r3, [r7, #7] + 80012f0: 4618 mov r0, r3 + 80012f2: f7ff ff35 bl 8001160 <__NVIC_EnableIRQ> +} + 80012f6: bf00 nop + 80012f8: 3708 adds r7, #8 + 80012fa: 46bd mov sp, r7 + 80012fc: bd80 pop {r7, pc} + +080012fe : + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 80012fe: b580 push {r7, lr} + 8001300: b082 sub sp, #8 + 8001302: af00 add r7, sp, #0 + 8001304: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8001306: 6878 ldr r0, [r7, #4] + 8001308: f7ff ffa2 bl 8001250 + 800130c: 4603 mov r3, r0 +} + 800130e: 4618 mov r0, r3 + 8001310: 3708 adds r7, #8 + 8001312: 46bd mov sp, r7 + 8001314: bd80 pop {r7, pc} + ... + +08001318 : + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8001318: b480 push {r7} + 800131a: b08b sub sp, #44 ; 0x2c + 800131c: af00 add r7, sp, #0 + 800131e: 6078 str r0, [r7, #4] + 8001320: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 8001322: 2300 movs r3, #0 + 8001324: 627b str r3, [r7, #36] ; 0x24 + uint32_t ioposition; + uint32_t iocurrent; + uint32_t temp; + uint32_t config = 0x00u; + 8001326: 2300 movs r3, #0 + 8001328: 623b str r3, [r7, #32] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 800132a: e127 b.n 800157c + { + /* Get the IO position */ + ioposition = (0x01uL << position); + 800132c: 2201 movs r2, #1 + 800132e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001330: fa02 f303 lsl.w r3, r2, r3 + 8001334: 61fb str r3, [r7, #28] + + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 8001336: 683b ldr r3, [r7, #0] + 8001338: 681b ldr r3, [r3, #0] + 800133a: 69fa ldr r2, [r7, #28] + 800133c: 4013 ands r3, r2 + 800133e: 61bb str r3, [r7, #24] + + if (iocurrent == ioposition) + 8001340: 69ba ldr r2, [r7, #24] + 8001342: 69fb ldr r3, [r7, #28] + 8001344: 429a cmp r2, r3 + 8001346: f040 8116 bne.w 8001576 + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + + /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ + switch (GPIO_Init->Mode) + 800134a: 683b ldr r3, [r7, #0] + 800134c: 685b ldr r3, [r3, #4] + 800134e: 2b12 cmp r3, #18 + 8001350: d034 beq.n 80013bc + 8001352: 2b12 cmp r3, #18 + 8001354: d80d bhi.n 8001372 + 8001356: 2b02 cmp r3, #2 + 8001358: d02b beq.n 80013b2 + 800135a: 2b02 cmp r3, #2 + 800135c: d804 bhi.n 8001368 + 800135e: 2b00 cmp r3, #0 + 8001360: d031 beq.n 80013c6 + 8001362: 2b01 cmp r3, #1 + 8001364: d01c beq.n 80013a0 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; + break; + + /* Parameters are checked with assert_param */ + default: + break; + 8001366: e048 b.n 80013fa + switch (GPIO_Init->Mode) + 8001368: 2b03 cmp r3, #3 + 800136a: d043 beq.n 80013f4 + 800136c: 2b11 cmp r3, #17 + 800136e: d01b beq.n 80013a8 + break; + 8001370: e043 b.n 80013fa + switch (GPIO_Init->Mode) + 8001372: 4a89 ldr r2, [pc, #548] ; (8001598 ) + 8001374: 4293 cmp r3, r2 + 8001376: d026 beq.n 80013c6 + 8001378: 4a87 ldr r2, [pc, #540] ; (8001598 ) + 800137a: 4293 cmp r3, r2 + 800137c: d806 bhi.n 800138c + 800137e: 4a87 ldr r2, [pc, #540] ; (800159c ) + 8001380: 4293 cmp r3, r2 + 8001382: d020 beq.n 80013c6 + 8001384: 4a86 ldr r2, [pc, #536] ; (80015a0 ) + 8001386: 4293 cmp r3, r2 + 8001388: d01d beq.n 80013c6 + break; + 800138a: e036 b.n 80013fa + switch (GPIO_Init->Mode) + 800138c: 4a85 ldr r2, [pc, #532] ; (80015a4 ) + 800138e: 4293 cmp r3, r2 + 8001390: d019 beq.n 80013c6 + 8001392: 4a85 ldr r2, [pc, #532] ; (80015a8 ) + 8001394: 4293 cmp r3, r2 + 8001396: d016 beq.n 80013c6 + 8001398: 4a84 ldr r2, [pc, #528] ; (80015ac ) + 800139a: 4293 cmp r3, r2 + 800139c: d013 beq.n 80013c6 + break; + 800139e: e02c b.n 80013fa + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; + 80013a0: 683b ldr r3, [r7, #0] + 80013a2: 68db ldr r3, [r3, #12] + 80013a4: 623b str r3, [r7, #32] + break; + 80013a6: e028 b.n 80013fa + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; + 80013a8: 683b ldr r3, [r7, #0] + 80013aa: 68db ldr r3, [r3, #12] + 80013ac: 3304 adds r3, #4 + 80013ae: 623b str r3, [r7, #32] + break; + 80013b0: e023 b.n 80013fa + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; + 80013b2: 683b ldr r3, [r7, #0] + 80013b4: 68db ldr r3, [r3, #12] + 80013b6: 3308 adds r3, #8 + 80013b8: 623b str r3, [r7, #32] + break; + 80013ba: e01e b.n 80013fa + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; + 80013bc: 683b ldr r3, [r7, #0] + 80013be: 68db ldr r3, [r3, #12] + 80013c0: 330c adds r3, #12 + 80013c2: 623b str r3, [r7, #32] + break; + 80013c4: e019 b.n 80013fa + if (GPIO_Init->Pull == GPIO_NOPULL) + 80013c6: 683b ldr r3, [r7, #0] + 80013c8: 689b ldr r3, [r3, #8] + 80013ca: 2b00 cmp r3, #0 + 80013cc: d102 bne.n 80013d4 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; + 80013ce: 2304 movs r3, #4 + 80013d0: 623b str r3, [r7, #32] + break; + 80013d2: e012 b.n 80013fa + else if (GPIO_Init->Pull == GPIO_PULLUP) + 80013d4: 683b ldr r3, [r7, #0] + 80013d6: 689b ldr r3, [r3, #8] + 80013d8: 2b01 cmp r3, #1 + 80013da: d105 bne.n 80013e8 + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + 80013dc: 2308 movs r3, #8 + 80013de: 623b str r3, [r7, #32] + GPIOx->BSRR = ioposition; + 80013e0: 687b ldr r3, [r7, #4] + 80013e2: 69fa ldr r2, [r7, #28] + 80013e4: 611a str r2, [r3, #16] + break; + 80013e6: e008 b.n 80013fa + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + 80013e8: 2308 movs r3, #8 + 80013ea: 623b str r3, [r7, #32] + GPIOx->BRR = ioposition; + 80013ec: 687b ldr r3, [r7, #4] + 80013ee: 69fa ldr r2, [r7, #28] + 80013f0: 615a str r2, [r3, #20] + break; + 80013f2: e002 b.n 80013fa + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; + 80013f4: 2300 movs r3, #0 + 80013f6: 623b str r3, [r7, #32] + break; + 80013f8: bf00 nop + } + + /* Check if the current bit belongs to first half or last half of the pin count number + in order to address CRH or CRL register*/ + configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; + 80013fa: 69bb ldr r3, [r7, #24] + 80013fc: 2bff cmp r3, #255 ; 0xff + 80013fe: d801 bhi.n 8001404 + 8001400: 687b ldr r3, [r7, #4] + 8001402: e001 b.n 8001408 + 8001404: 687b ldr r3, [r7, #4] + 8001406: 3304 adds r3, #4 + 8001408: 617b str r3, [r7, #20] + registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); + 800140a: 69bb ldr r3, [r7, #24] + 800140c: 2bff cmp r3, #255 ; 0xff + 800140e: d802 bhi.n 8001416 + 8001410: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001412: 009b lsls r3, r3, #2 + 8001414: e002 b.n 800141c + 8001416: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001418: 3b08 subs r3, #8 + 800141a: 009b lsls r3, r3, #2 + 800141c: 613b str r3, [r7, #16] + + /* Apply the new configuration of the pin to the register */ + MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); + 800141e: 697b ldr r3, [r7, #20] + 8001420: 681a ldr r2, [r3, #0] + 8001422: 210f movs r1, #15 + 8001424: 693b ldr r3, [r7, #16] + 8001426: fa01 f303 lsl.w r3, r1, r3 + 800142a: 43db mvns r3, r3 + 800142c: 401a ands r2, r3 + 800142e: 6a39 ldr r1, [r7, #32] + 8001430: 693b ldr r3, [r7, #16] + 8001432: fa01 f303 lsl.w r3, r1, r3 + 8001436: 431a orrs r2, r3 + 8001438: 697b ldr r3, [r7, #20] + 800143a: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 800143c: 683b ldr r3, [r7, #0] + 800143e: 685b ldr r3, [r3, #4] + 8001440: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001444: 2b00 cmp r3, #0 + 8001446: f000 8096 beq.w 8001576 + { + /* Enable AFIO Clock */ + __HAL_RCC_AFIO_CLK_ENABLE(); + 800144a: 4b59 ldr r3, [pc, #356] ; (80015b0 ) + 800144c: 699b ldr r3, [r3, #24] + 800144e: 4a58 ldr r2, [pc, #352] ; (80015b0 ) + 8001450: f043 0301 orr.w r3, r3, #1 + 8001454: 6193 str r3, [r2, #24] + 8001456: 4b56 ldr r3, [pc, #344] ; (80015b0 ) + 8001458: 699b ldr r3, [r3, #24] + 800145a: f003 0301 and.w r3, r3, #1 + 800145e: 60bb str r3, [r7, #8] + 8001460: 68bb ldr r3, [r7, #8] + temp = AFIO->EXTICR[position >> 2u]; + 8001462: 4a54 ldr r2, [pc, #336] ; (80015b4 ) + 8001464: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001466: 089b lsrs r3, r3, #2 + 8001468: 3302 adds r3, #2 + 800146a: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800146e: 60fb str r3, [r7, #12] + CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); + 8001470: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001472: f003 0303 and.w r3, r3, #3 + 8001476: 009b lsls r3, r3, #2 + 8001478: 220f movs r2, #15 + 800147a: fa02 f303 lsl.w r3, r2, r3 + 800147e: 43db mvns r3, r3 + 8001480: 68fa ldr r2, [r7, #12] + 8001482: 4013 ands r3, r2 + 8001484: 60fb str r3, [r7, #12] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); + 8001486: 687b ldr r3, [r7, #4] + 8001488: 4a4b ldr r2, [pc, #300] ; (80015b8 ) + 800148a: 4293 cmp r3, r2 + 800148c: d013 beq.n 80014b6 + 800148e: 687b ldr r3, [r7, #4] + 8001490: 4a4a ldr r2, [pc, #296] ; (80015bc ) + 8001492: 4293 cmp r3, r2 + 8001494: d00d beq.n 80014b2 + 8001496: 687b ldr r3, [r7, #4] + 8001498: 4a49 ldr r2, [pc, #292] ; (80015c0 ) + 800149a: 4293 cmp r3, r2 + 800149c: d007 beq.n 80014ae + 800149e: 687b ldr r3, [r7, #4] + 80014a0: 4a48 ldr r2, [pc, #288] ; (80015c4 ) + 80014a2: 4293 cmp r3, r2 + 80014a4: d101 bne.n 80014aa + 80014a6: 2303 movs r3, #3 + 80014a8: e006 b.n 80014b8 + 80014aa: 2304 movs r3, #4 + 80014ac: e004 b.n 80014b8 + 80014ae: 2302 movs r3, #2 + 80014b0: e002 b.n 80014b8 + 80014b2: 2301 movs r3, #1 + 80014b4: e000 b.n 80014b8 + 80014b6: 2300 movs r3, #0 + 80014b8: 6a7a ldr r2, [r7, #36] ; 0x24 + 80014ba: f002 0203 and.w r2, r2, #3 + 80014be: 0092 lsls r2, r2, #2 + 80014c0: 4093 lsls r3, r2 + 80014c2: 68fa ldr r2, [r7, #12] + 80014c4: 4313 orrs r3, r2 + 80014c6: 60fb str r3, [r7, #12] + AFIO->EXTICR[position >> 2u] = temp; + 80014c8: 493a ldr r1, [pc, #232] ; (80015b4 ) + 80014ca: 6a7b ldr r3, [r7, #36] ; 0x24 + 80014cc: 089b lsrs r3, r3, #2 + 80014ce: 3302 adds r3, #2 + 80014d0: 68fa ldr r2, [r7, #12] + 80014d2: f841 2023 str.w r2, [r1, r3, lsl #2] + + + /* Configure the interrupt mask */ + if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 80014d6: 683b ldr r3, [r7, #0] + 80014d8: 685b ldr r3, [r3, #4] + 80014da: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80014de: 2b00 cmp r3, #0 + 80014e0: d006 beq.n 80014f0 + { + SET_BIT(EXTI->IMR, iocurrent); + 80014e2: 4b39 ldr r3, [pc, #228] ; (80015c8 ) + 80014e4: 681a ldr r2, [r3, #0] + 80014e6: 4938 ldr r1, [pc, #224] ; (80015c8 ) + 80014e8: 69bb ldr r3, [r7, #24] + 80014ea: 4313 orrs r3, r2 + 80014ec: 600b str r3, [r1, #0] + 80014ee: e006 b.n 80014fe + } + else + { + CLEAR_BIT(EXTI->IMR, iocurrent); + 80014f0: 4b35 ldr r3, [pc, #212] ; (80015c8 ) + 80014f2: 681a ldr r2, [r3, #0] + 80014f4: 69bb ldr r3, [r7, #24] + 80014f6: 43db mvns r3, r3 + 80014f8: 4933 ldr r1, [pc, #204] ; (80015c8 ) + 80014fa: 4013 ands r3, r2 + 80014fc: 600b str r3, [r1, #0] + } + + /* Configure the event mask */ + if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 80014fe: 683b ldr r3, [r7, #0] + 8001500: 685b ldr r3, [r3, #4] + 8001502: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001506: 2b00 cmp r3, #0 + 8001508: d006 beq.n 8001518 + { + SET_BIT(EXTI->EMR, iocurrent); + 800150a: 4b2f ldr r3, [pc, #188] ; (80015c8 ) + 800150c: 685a ldr r2, [r3, #4] + 800150e: 492e ldr r1, [pc, #184] ; (80015c8 ) + 8001510: 69bb ldr r3, [r7, #24] + 8001512: 4313 orrs r3, r2 + 8001514: 604b str r3, [r1, #4] + 8001516: e006 b.n 8001526 + } + else + { + CLEAR_BIT(EXTI->EMR, iocurrent); + 8001518: 4b2b ldr r3, [pc, #172] ; (80015c8 ) + 800151a: 685a ldr r2, [r3, #4] + 800151c: 69bb ldr r3, [r7, #24] + 800151e: 43db mvns r3, r3 + 8001520: 4929 ldr r1, [pc, #164] ; (80015c8 ) + 8001522: 4013 ands r3, r2 + 8001524: 604b str r3, [r1, #4] + } + + /* Enable or disable the rising trigger */ + if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 8001526: 683b ldr r3, [r7, #0] + 8001528: 685b ldr r3, [r3, #4] + 800152a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 800152e: 2b00 cmp r3, #0 + 8001530: d006 beq.n 8001540 + { + SET_BIT(EXTI->RTSR, iocurrent); + 8001532: 4b25 ldr r3, [pc, #148] ; (80015c8 ) + 8001534: 689a ldr r2, [r3, #8] + 8001536: 4924 ldr r1, [pc, #144] ; (80015c8 ) + 8001538: 69bb ldr r3, [r7, #24] + 800153a: 4313 orrs r3, r2 + 800153c: 608b str r3, [r1, #8] + 800153e: e006 b.n 800154e + } + else + { + CLEAR_BIT(EXTI->RTSR, iocurrent); + 8001540: 4b21 ldr r3, [pc, #132] ; (80015c8 ) + 8001542: 689a ldr r2, [r3, #8] + 8001544: 69bb ldr r3, [r7, #24] + 8001546: 43db mvns r3, r3 + 8001548: 491f ldr r1, [pc, #124] ; (80015c8 ) + 800154a: 4013 ands r3, r2 + 800154c: 608b str r3, [r1, #8] + } + + /* Enable or disable the falling trigger */ + if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 800154e: 683b ldr r3, [r7, #0] + 8001550: 685b ldr r3, [r3, #4] + 8001552: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8001556: 2b00 cmp r3, #0 + 8001558: d006 beq.n 8001568 + { + SET_BIT(EXTI->FTSR, iocurrent); + 800155a: 4b1b ldr r3, [pc, #108] ; (80015c8 ) + 800155c: 68da ldr r2, [r3, #12] + 800155e: 491a ldr r1, [pc, #104] ; (80015c8 ) + 8001560: 69bb ldr r3, [r7, #24] + 8001562: 4313 orrs r3, r2 + 8001564: 60cb str r3, [r1, #12] + 8001566: e006 b.n 8001576 + } + else + { + CLEAR_BIT(EXTI->FTSR, iocurrent); + 8001568: 4b17 ldr r3, [pc, #92] ; (80015c8 ) + 800156a: 68da ldr r2, [r3, #12] + 800156c: 69bb ldr r3, [r7, #24] + 800156e: 43db mvns r3, r3 + 8001570: 4915 ldr r1, [pc, #84] ; (80015c8 ) + 8001572: 4013 ands r3, r2 + 8001574: 60cb str r3, [r1, #12] + } + } + } + + position++; + 8001576: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001578: 3301 adds r3, #1 + 800157a: 627b str r3, [r7, #36] ; 0x24 + while (((GPIO_Init->Pin) >> position) != 0x00u) + 800157c: 683b ldr r3, [r7, #0] + 800157e: 681a ldr r2, [r3, #0] + 8001580: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001582: fa22 f303 lsr.w r3, r2, r3 + 8001586: 2b00 cmp r3, #0 + 8001588: f47f aed0 bne.w 800132c + } +} + 800158c: bf00 nop + 800158e: 372c adds r7, #44 ; 0x2c + 8001590: 46bd mov sp, r7 + 8001592: bc80 pop {r7} + 8001594: 4770 bx lr + 8001596: bf00 nop + 8001598: 10210000 .word 0x10210000 + 800159c: 10110000 .word 0x10110000 + 80015a0: 10120000 .word 0x10120000 + 80015a4: 10310000 .word 0x10310000 + 80015a8: 10320000 .word 0x10320000 + 80015ac: 10220000 .word 0x10220000 + 80015b0: 40021000 .word 0x40021000 + 80015b4: 40010000 .word 0x40010000 + 80015b8: 40010800 .word 0x40010800 + 80015bc: 40010c00 .word 0x40010c00 + 80015c0: 40011000 .word 0x40011000 + 80015c4: 40011400 .word 0x40011400 + 80015c8: 40010400 .word 0x40010400 + +080015cc : + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + 80015cc: b480 push {r7} + 80015ce: b085 sub sp, #20 + 80015d0: af00 add r7, sp, #0 + 80015d2: 6078 str r0, [r7, #4] + 80015d4: 460b mov r3, r1 + 80015d6: 807b strh r3, [r7, #2] + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + 80015d8: 687b ldr r3, [r7, #4] + 80015da: 689a ldr r2, [r3, #8] + 80015dc: 887b ldrh r3, [r7, #2] + 80015de: 4013 ands r3, r2 + 80015e0: 2b00 cmp r3, #0 + 80015e2: d002 beq.n 80015ea + { + bitstatus = GPIO_PIN_SET; + 80015e4: 2301 movs r3, #1 + 80015e6: 73fb strb r3, [r7, #15] + 80015e8: e001 b.n 80015ee + } + else + { + bitstatus = GPIO_PIN_RESET; + 80015ea: 2300 movs r3, #0 + 80015ec: 73fb strb r3, [r7, #15] + } + return bitstatus; + 80015ee: 7bfb ldrb r3, [r7, #15] +} + 80015f0: 4618 mov r0, r3 + 80015f2: 3714 adds r7, #20 + 80015f4: 46bd mov sp, r7 + 80015f6: bc80 pop {r7} + 80015f8: 4770 bx lr + +080015fa : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80015fa: b480 push {r7} + 80015fc: b083 sub sp, #12 + 80015fe: af00 add r7, sp, #0 + 8001600: 6078 str r0, [r7, #4] + 8001602: 460b mov r3, r1 + 8001604: 807b strh r3, [r7, #2] + 8001606: 4613 mov r3, r2 + 8001608: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 800160a: 787b ldrb r3, [r7, #1] + 800160c: 2b00 cmp r3, #0 + 800160e: d003 beq.n 8001618 + { + GPIOx->BSRR = GPIO_Pin; + 8001610: 887a ldrh r2, [r7, #2] + 8001612: 687b ldr r3, [r7, #4] + 8001614: 611a str r2, [r3, #16] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; + } +} + 8001616: e003 b.n 8001620 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; + 8001618: 887b ldrh r3, [r7, #2] + 800161a: 041a lsls r2, r3, #16 + 800161c: 687b ldr r3, [r7, #4] + 800161e: 611a str r2, [r3, #16] +} + 8001620: bf00 nop + 8001622: 370c adds r7, #12 + 8001624: 46bd mov sp, r7 + 8001626: bc80 pop {r7} + 8001628: 4770 bx lr + ... + +0800162c : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + 800162c: b580 push {r7, lr} + 800162e: b084 sub sp, #16 + 8001630: af00 add r7, sp, #0 + 8001632: 6078 str r0, [r7, #4] + uint32_t freqrange; + uint32_t pclk1; + + /* Check the I2C handle allocation */ + if (hi2c == NULL) + 8001634: 687b ldr r3, [r7, #4] + 8001636: 2b00 cmp r3, #0 + 8001638: d101 bne.n 800163e + { + return HAL_ERROR; + 800163a: 2301 movs r3, #1 + 800163c: e10f b.n 800185e + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + 800163e: 687b ldr r3, [r7, #4] + 8001640: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8001644: b2db uxtb r3, r3 + 8001646: 2b00 cmp r3, #0 + 8001648: d106 bne.n 8001658 + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + 800164a: 687b ldr r3, [r7, #4] + 800164c: 2200 movs r2, #0 + 800164e: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + 8001652: 6878 ldr r0, [r7, #4] + 8001654: f008 fcb2 bl 8009fbc +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + 8001658: 687b ldr r3, [r7, #4] + 800165a: 2224 movs r2, #36 ; 0x24 + 800165c: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8001660: 687b ldr r3, [r7, #4] + 8001662: 681b ldr r3, [r3, #0] + 8001664: 681a ldr r2, [r3, #0] + 8001666: 687b ldr r3, [r7, #4] + 8001668: 681b ldr r3, [r3, #0] + 800166a: f022 0201 bic.w r2, r2, #1 + 800166e: 601a str r2, [r3, #0] + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + 8001670: f001 fbc8 bl 8002e04 + 8001674: 60f8 str r0, [r7, #12] + + /* Check the minimum allowed PCLK1 frequency */ + if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) + 8001676: 687b ldr r3, [r7, #4] + 8001678: 685b ldr r3, [r3, #4] + 800167a: 4a7b ldr r2, [pc, #492] ; (8001868 ) + 800167c: 4293 cmp r3, r2 + 800167e: d807 bhi.n 8001690 + 8001680: 68fb ldr r3, [r7, #12] + 8001682: 4a7a ldr r2, [pc, #488] ; (800186c ) + 8001684: 4293 cmp r3, r2 + 8001686: bf94 ite ls + 8001688: 2301 movls r3, #1 + 800168a: 2300 movhi r3, #0 + 800168c: b2db uxtb r3, r3 + 800168e: e006 b.n 800169e + 8001690: 68fb ldr r3, [r7, #12] + 8001692: 4a77 ldr r2, [pc, #476] ; (8001870 ) + 8001694: 4293 cmp r3, r2 + 8001696: bf94 ite ls + 8001698: 2301 movls r3, #1 + 800169a: 2300 movhi r3, #0 + 800169c: b2db uxtb r3, r3 + 800169e: 2b00 cmp r3, #0 + 80016a0: d001 beq.n 80016a6 + { + return HAL_ERROR; + 80016a2: 2301 movs r3, #1 + 80016a4: e0db b.n 800185e + } + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + 80016a6: 68fb ldr r3, [r7, #12] + 80016a8: 4a72 ldr r2, [pc, #456] ; (8001874 ) + 80016aa: fba2 2303 umull r2, r3, r2, r3 + 80016ae: 0c9b lsrs r3, r3, #18 + 80016b0: 60bb str r3, [r7, #8] + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); + 80016b2: 687b ldr r3, [r7, #4] + 80016b4: 681b ldr r3, [r3, #0] + 80016b6: 685b ldr r3, [r3, #4] + 80016b8: f023 013f bic.w r1, r3, #63 ; 0x3f + 80016bc: 687b ldr r3, [r7, #4] + 80016be: 681b ldr r3, [r3, #0] + 80016c0: 68ba ldr r2, [r7, #8] + 80016c2: 430a orrs r2, r1 + 80016c4: 605a str r2, [r3, #4] + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); + 80016c6: 687b ldr r3, [r7, #4] + 80016c8: 681b ldr r3, [r3, #0] + 80016ca: 6a1b ldr r3, [r3, #32] + 80016cc: f023 013f bic.w r1, r3, #63 ; 0x3f + 80016d0: 687b ldr r3, [r7, #4] + 80016d2: 685b ldr r3, [r3, #4] + 80016d4: 4a64 ldr r2, [pc, #400] ; (8001868 ) + 80016d6: 4293 cmp r3, r2 + 80016d8: d802 bhi.n 80016e0 + 80016da: 68bb ldr r3, [r7, #8] + 80016dc: 3301 adds r3, #1 + 80016de: e009 b.n 80016f4 + 80016e0: 68bb ldr r3, [r7, #8] + 80016e2: f44f 7296 mov.w r2, #300 ; 0x12c + 80016e6: fb02 f303 mul.w r3, r2, r3 + 80016ea: 4a63 ldr r2, [pc, #396] ; (8001878 ) + 80016ec: fba2 2303 umull r2, r3, r2, r3 + 80016f0: 099b lsrs r3, r3, #6 + 80016f2: 3301 adds r3, #1 + 80016f4: 687a ldr r2, [r7, #4] + 80016f6: 6812 ldr r2, [r2, #0] + 80016f8: 430b orrs r3, r1 + 80016fa: 6213 str r3, [r2, #32] + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); + 80016fc: 687b ldr r3, [r7, #4] + 80016fe: 681b ldr r3, [r3, #0] + 8001700: 69db ldr r3, [r3, #28] + 8001702: f423 424f bic.w r2, r3, #52992 ; 0xcf00 + 8001706: f022 02ff bic.w r2, r2, #255 ; 0xff + 800170a: 687b ldr r3, [r7, #4] + 800170c: 685b ldr r3, [r3, #4] + 800170e: 4956 ldr r1, [pc, #344] ; (8001868 ) + 8001710: 428b cmp r3, r1 + 8001712: d80d bhi.n 8001730 + 8001714: 68fb ldr r3, [r7, #12] + 8001716: 1e59 subs r1, r3, #1 + 8001718: 687b ldr r3, [r7, #4] + 800171a: 685b ldr r3, [r3, #4] + 800171c: 005b lsls r3, r3, #1 + 800171e: fbb1 f3f3 udiv r3, r1, r3 + 8001722: 3301 adds r3, #1 + 8001724: f3c3 030b ubfx r3, r3, #0, #12 + 8001728: 2b04 cmp r3, #4 + 800172a: bf38 it cc + 800172c: 2304 movcc r3, #4 + 800172e: e04f b.n 80017d0 + 8001730: 687b ldr r3, [r7, #4] + 8001732: 689b ldr r3, [r3, #8] + 8001734: 2b00 cmp r3, #0 + 8001736: d111 bne.n 800175c + 8001738: 68fb ldr r3, [r7, #12] + 800173a: 1e58 subs r0, r3, #1 + 800173c: 687b ldr r3, [r7, #4] + 800173e: 6859 ldr r1, [r3, #4] + 8001740: 460b mov r3, r1 + 8001742: 005b lsls r3, r3, #1 + 8001744: 440b add r3, r1 + 8001746: fbb0 f3f3 udiv r3, r0, r3 + 800174a: 3301 adds r3, #1 + 800174c: f3c3 030b ubfx r3, r3, #0, #12 + 8001750: 2b00 cmp r3, #0 + 8001752: bf0c ite eq + 8001754: 2301 moveq r3, #1 + 8001756: 2300 movne r3, #0 + 8001758: b2db uxtb r3, r3 + 800175a: e012 b.n 8001782 + 800175c: 68fb ldr r3, [r7, #12] + 800175e: 1e58 subs r0, r3, #1 + 8001760: 687b ldr r3, [r7, #4] + 8001762: 6859 ldr r1, [r3, #4] + 8001764: 460b mov r3, r1 + 8001766: 009b lsls r3, r3, #2 + 8001768: 440b add r3, r1 + 800176a: 0099 lsls r1, r3, #2 + 800176c: 440b add r3, r1 + 800176e: fbb0 f3f3 udiv r3, r0, r3 + 8001772: 3301 adds r3, #1 + 8001774: f3c3 030b ubfx r3, r3, #0, #12 + 8001778: 2b00 cmp r3, #0 + 800177a: bf0c ite eq + 800177c: 2301 moveq r3, #1 + 800177e: 2300 movne r3, #0 + 8001780: b2db uxtb r3, r3 + 8001782: 2b00 cmp r3, #0 + 8001784: d001 beq.n 800178a + 8001786: 2301 movs r3, #1 + 8001788: e022 b.n 80017d0 + 800178a: 687b ldr r3, [r7, #4] + 800178c: 689b ldr r3, [r3, #8] + 800178e: 2b00 cmp r3, #0 + 8001790: d10e bne.n 80017b0 + 8001792: 68fb ldr r3, [r7, #12] + 8001794: 1e58 subs r0, r3, #1 + 8001796: 687b ldr r3, [r7, #4] + 8001798: 6859 ldr r1, [r3, #4] + 800179a: 460b mov r3, r1 + 800179c: 005b lsls r3, r3, #1 + 800179e: 440b add r3, r1 + 80017a0: fbb0 f3f3 udiv r3, r0, r3 + 80017a4: 3301 adds r3, #1 + 80017a6: f3c3 030b ubfx r3, r3, #0, #12 + 80017aa: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80017ae: e00f b.n 80017d0 + 80017b0: 68fb ldr r3, [r7, #12] + 80017b2: 1e58 subs r0, r3, #1 + 80017b4: 687b ldr r3, [r7, #4] + 80017b6: 6859 ldr r1, [r3, #4] + 80017b8: 460b mov r3, r1 + 80017ba: 009b lsls r3, r3, #2 + 80017bc: 440b add r3, r1 + 80017be: 0099 lsls r1, r3, #2 + 80017c0: 440b add r3, r1 + 80017c2: fbb0 f3f3 udiv r3, r0, r3 + 80017c6: 3301 adds r3, #1 + 80017c8: f3c3 030b ubfx r3, r3, #0, #12 + 80017cc: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 80017d0: 6879 ldr r1, [r7, #4] + 80017d2: 6809 ldr r1, [r1, #0] + 80017d4: 4313 orrs r3, r2 + 80017d6: 61cb str r3, [r1, #28] + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); + 80017d8: 687b ldr r3, [r7, #4] + 80017da: 681b ldr r3, [r3, #0] + 80017dc: 681b ldr r3, [r3, #0] + 80017de: f023 01c0 bic.w r1, r3, #192 ; 0xc0 + 80017e2: 687b ldr r3, [r7, #4] + 80017e4: 69da ldr r2, [r3, #28] + 80017e6: 687b ldr r3, [r7, #4] + 80017e8: 6a1b ldr r3, [r3, #32] + 80017ea: 431a orrs r2, r3 + 80017ec: 687b ldr r3, [r7, #4] + 80017ee: 681b ldr r3, [r3, #0] + 80017f0: 430a orrs r2, r1 + 80017f2: 601a str r2, [r3, #0] + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); + 80017f4: 687b ldr r3, [r7, #4] + 80017f6: 681b ldr r3, [r3, #0] + 80017f8: 689b ldr r3, [r3, #8] + 80017fa: f423 4303 bic.w r3, r3, #33536 ; 0x8300 + 80017fe: f023 03ff bic.w r3, r3, #255 ; 0xff + 8001802: 687a ldr r2, [r7, #4] + 8001804: 6911 ldr r1, [r2, #16] + 8001806: 687a ldr r2, [r7, #4] + 8001808: 68d2 ldr r2, [r2, #12] + 800180a: 4311 orrs r1, r2 + 800180c: 687a ldr r2, [r7, #4] + 800180e: 6812 ldr r2, [r2, #0] + 8001810: 430b orrs r3, r1 + 8001812: 6093 str r3, [r2, #8] + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); + 8001814: 687b ldr r3, [r7, #4] + 8001816: 681b ldr r3, [r3, #0] + 8001818: 68db ldr r3, [r3, #12] + 800181a: f023 01ff bic.w r1, r3, #255 ; 0xff + 800181e: 687b ldr r3, [r7, #4] + 8001820: 695a ldr r2, [r3, #20] + 8001822: 687b ldr r3, [r7, #4] + 8001824: 699b ldr r3, [r3, #24] + 8001826: 431a orrs r2, r3 + 8001828: 687b ldr r3, [r7, #4] + 800182a: 681b ldr r3, [r3, #0] + 800182c: 430a orrs r2, r1 + 800182e: 60da str r2, [r3, #12] + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 8001830: 687b ldr r3, [r7, #4] + 8001832: 681b ldr r3, [r3, #0] + 8001834: 681a ldr r2, [r3, #0] + 8001836: 687b ldr r3, [r7, #4] + 8001838: 681b ldr r3, [r3, #0] + 800183a: f042 0201 orr.w r2, r2, #1 + 800183e: 601a str r2, [r3, #0] + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8001840: 687b ldr r3, [r7, #4] + 8001842: 2200 movs r2, #0 + 8001844: 641a str r2, [r3, #64] ; 0x40 + hi2c->State = HAL_I2C_STATE_READY; + 8001846: 687b ldr r3, [r7, #4] + 8001848: 2220 movs r2, #32 + 800184a: f883 203d strb.w r2, [r3, #61] ; 0x3d + hi2c->PreviousState = I2C_STATE_NONE; + 800184e: 687b ldr r3, [r7, #4] + 8001850: 2200 movs r2, #0 + 8001852: 631a str r2, [r3, #48] ; 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8001854: 687b ldr r3, [r7, #4] + 8001856: 2200 movs r2, #0 + 8001858: f883 203e strb.w r2, [r3, #62] ; 0x3e + + return HAL_OK; + 800185c: 2300 movs r3, #0 +} + 800185e: 4618 mov r0, r3 + 8001860: 3710 adds r7, #16 + 8001862: 46bd mov sp, r7 + 8001864: bd80 pop {r7, pc} + 8001866: bf00 nop + 8001868: 000186a0 .word 0x000186a0 + 800186c: 001e847f .word 0x001e847f + 8001870: 003d08ff .word 0x003d08ff + 8001874: 431bde83 .word 0x431bde83 + 8001878: 10624dd3 .word 0x10624dd3 + +0800187c : + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ + 800187c: b5f0 push {r4, r5, r6, r7, lr} + 800187e: b08b sub sp, #44 ; 0x2c + 8001880: af06 add r7, sp, #24 + 8001882: 6078 str r0, [r7, #4] + USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ + uint8_t i; + + /* Check the PCD handle allocation */ + if (hpcd == NULL) + 8001884: 687b ldr r3, [r7, #4] + 8001886: 2b00 cmp r3, #0 + 8001888: d101 bne.n 800188e + { + return HAL_ERROR; + 800188a: 2301 movs r3, #1 + 800188c: e0d3 b.n 8001a36 + +#if defined (USB_OTG_FS) + USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + if (hpcd->State == HAL_PCD_STATE_RESET) + 800188e: 687b ldr r3, [r7, #4] + 8001890: f893 3229 ldrb.w r3, [r3, #553] ; 0x229 + 8001894: b2db uxtb r3, r3 + 8001896: 2b00 cmp r3, #0 + 8001898: d106 bne.n 80018a8 + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + 800189a: 687b ldr r3, [r7, #4] + 800189c: 2200 movs r2, #0 + 800189e: f883 2228 strb.w r2, [r3, #552] ; 0x228 + + /* Init the low level hardware */ + hpcd->MspInitCallback(hpcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + 80018a2: 6878 ldr r0, [r7, #4] + 80018a4: f008 fe0c bl 800a4c0 +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + } + + hpcd->State = HAL_PCD_STATE_BUSY; + 80018a8: 687b ldr r3, [r7, #4] + 80018aa: 2203 movs r2, #3 + 80018ac: f883 2229 strb.w r2, [r3, #553] ; 0x229 + hpcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + + /* Disable the Interrupts */ + __HAL_PCD_DISABLE(hpcd); + 80018b0: 687b ldr r3, [r7, #4] + 80018b2: 681b ldr r3, [r3, #0] + 80018b4: 4618 mov r0, r3 + 80018b6: f002 feb6 bl 8004626 + + /*Init the Core (common init.) */ + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + 80018ba: 687b ldr r3, [r7, #4] + 80018bc: 681b ldr r3, [r3, #0] + 80018be: 603b str r3, [r7, #0] + 80018c0: 687e ldr r6, [r7, #4] + 80018c2: 466d mov r5, sp + 80018c4: f106 0410 add.w r4, r6, #16 + 80018c8: cc0f ldmia r4!, {r0, r1, r2, r3} + 80018ca: c50f stmia r5!, {r0, r1, r2, r3} + 80018cc: 6823 ldr r3, [r4, #0] + 80018ce: 602b str r3, [r5, #0] + 80018d0: 1d33 adds r3, r6, #4 + 80018d2: cb0e ldmia r3, {r1, r2, r3} + 80018d4: 6838 ldr r0, [r7, #0] + 80018d6: f002 fe7f bl 80045d8 + 80018da: 4603 mov r3, r0 + 80018dc: 2b00 cmp r3, #0 + 80018de: d005 beq.n 80018ec + { + hpcd->State = HAL_PCD_STATE_ERROR; + 80018e0: 687b ldr r3, [r7, #4] + 80018e2: 2202 movs r2, #2 + 80018e4: f883 2229 strb.w r2, [r3, #553] ; 0x229 + return HAL_ERROR; + 80018e8: 2301 movs r3, #1 + 80018ea: e0a4 b.n 8001a36 + } + + /* Force Device Mode*/ + (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); + 80018ec: 687b ldr r3, [r7, #4] + 80018ee: 681b ldr r3, [r3, #0] + 80018f0: 2100 movs r1, #0 + 80018f2: 4618 mov r0, r3 + 80018f4: f002 feb3 bl 800465e + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 80018f8: 2300 movs r3, #0 + 80018fa: 73fb strb r3, [r7, #15] + 80018fc: e035 b.n 800196a + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + 80018fe: 7bfb ldrb r3, [r7, #15] + 8001900: 687a ldr r2, [r7, #4] + 8001902: 015b lsls r3, r3, #5 + 8001904: 4413 add r3, r2 + 8001906: 3329 adds r3, #41 ; 0x29 + 8001908: 2201 movs r2, #1 + 800190a: 701a strb r2, [r3, #0] + hpcd->IN_ep[i].num = i; + 800190c: 7bfb ldrb r3, [r7, #15] + 800190e: 687a ldr r2, [r7, #4] + 8001910: 015b lsls r3, r3, #5 + 8001912: 4413 add r3, r2 + 8001914: 3328 adds r3, #40 ; 0x28 + 8001916: 7bfa ldrb r2, [r7, #15] + 8001918: 701a strb r2, [r3, #0] + hpcd->IN_ep[i].tx_fifo_num = i; + 800191a: 7bfb ldrb r3, [r7, #15] + 800191c: 7bfa ldrb r2, [r7, #15] + 800191e: b291 uxth r1, r2 + 8001920: 687a ldr r2, [r7, #4] + 8001922: 015b lsls r3, r3, #5 + 8001924: 4413 add r3, r2 + 8001926: 3336 adds r3, #54 ; 0x36 + 8001928: 460a mov r2, r1 + 800192a: 801a strh r2, [r3, #0] + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + 800192c: 7bfb ldrb r3, [r7, #15] + 800192e: 687a ldr r2, [r7, #4] + 8001930: 015b lsls r3, r3, #5 + 8001932: 4413 add r3, r2 + 8001934: 332b adds r3, #43 ; 0x2b + 8001936: 2200 movs r2, #0 + 8001938: 701a strb r2, [r3, #0] + hpcd->IN_ep[i].maxpacket = 0U; + 800193a: 7bfb ldrb r3, [r7, #15] + 800193c: 687a ldr r2, [r7, #4] + 800193e: 015b lsls r3, r3, #5 + 8001940: 4413 add r3, r2 + 8001942: 3338 adds r3, #56 ; 0x38 + 8001944: 2200 movs r2, #0 + 8001946: 601a str r2, [r3, #0] + hpcd->IN_ep[i].xfer_buff = 0U; + 8001948: 7bfb ldrb r3, [r7, #15] + 800194a: 687a ldr r2, [r7, #4] + 800194c: 015b lsls r3, r3, #5 + 800194e: 4413 add r3, r2 + 8001950: 333c adds r3, #60 ; 0x3c + 8001952: 2200 movs r2, #0 + 8001954: 601a str r2, [r3, #0] + hpcd->IN_ep[i].xfer_len = 0U; + 8001956: 7bfb ldrb r3, [r7, #15] + 8001958: 687a ldr r2, [r7, #4] + 800195a: 3302 adds r3, #2 + 800195c: 015b lsls r3, r3, #5 + 800195e: 4413 add r3, r2 + 8001960: 2200 movs r2, #0 + 8001962: 601a str r2, [r3, #0] + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 8001964: 7bfb ldrb r3, [r7, #15] + 8001966: 3301 adds r3, #1 + 8001968: 73fb strb r3, [r7, #15] + 800196a: 7bfa ldrb r2, [r7, #15] + 800196c: 687b ldr r3, [r7, #4] + 800196e: 685b ldr r3, [r3, #4] + 8001970: 429a cmp r2, r3 + 8001972: d3c4 bcc.n 80018fe + } + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 8001974: 2300 movs r3, #0 + 8001976: 73fb strb r3, [r7, #15] + 8001978: e031 b.n 80019de + { + hpcd->OUT_ep[i].is_in = 0U; + 800197a: 7bfb ldrb r3, [r7, #15] + 800197c: 687a ldr r2, [r7, #4] + 800197e: 015b lsls r3, r3, #5 + 8001980: 4413 add r3, r2 + 8001982: f203 1329 addw r3, r3, #297 ; 0x129 + 8001986: 2200 movs r2, #0 + 8001988: 701a strb r2, [r3, #0] + hpcd->OUT_ep[i].num = i; + 800198a: 7bfb ldrb r3, [r7, #15] + 800198c: 687a ldr r2, [r7, #4] + 800198e: 015b lsls r3, r3, #5 + 8001990: 4413 add r3, r2 + 8001992: f503 7394 add.w r3, r3, #296 ; 0x128 + 8001996: 7bfa ldrb r2, [r7, #15] + 8001998: 701a strb r2, [r3, #0] + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + 800199a: 7bfb ldrb r3, [r7, #15] + 800199c: 687a ldr r2, [r7, #4] + 800199e: 015b lsls r3, r3, #5 + 80019a0: 4413 add r3, r2 + 80019a2: f203 132b addw r3, r3, #299 ; 0x12b + 80019a6: 2200 movs r2, #0 + 80019a8: 701a strb r2, [r3, #0] + hpcd->OUT_ep[i].maxpacket = 0U; + 80019aa: 7bfb ldrb r3, [r7, #15] + 80019ac: 687a ldr r2, [r7, #4] + 80019ae: 015b lsls r3, r3, #5 + 80019b0: 4413 add r3, r2 + 80019b2: f503 739c add.w r3, r3, #312 ; 0x138 + 80019b6: 2200 movs r2, #0 + 80019b8: 601a str r2, [r3, #0] + hpcd->OUT_ep[i].xfer_buff = 0U; + 80019ba: 7bfb ldrb r3, [r7, #15] + 80019bc: 687a ldr r2, [r7, #4] + 80019be: 015b lsls r3, r3, #5 + 80019c0: 4413 add r3, r2 + 80019c2: f503 739e add.w r3, r3, #316 ; 0x13c + 80019c6: 2200 movs r2, #0 + 80019c8: 601a str r2, [r3, #0] + hpcd->OUT_ep[i].xfer_len = 0U; + 80019ca: 7bfb ldrb r3, [r7, #15] + 80019cc: 687a ldr r2, [r7, #4] + 80019ce: 330a adds r3, #10 + 80019d0: 015b lsls r3, r3, #5 + 80019d2: 4413 add r3, r2 + 80019d4: 2200 movs r2, #0 + 80019d6: 601a str r2, [r3, #0] + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 80019d8: 7bfb ldrb r3, [r7, #15] + 80019da: 3301 adds r3, #1 + 80019dc: 73fb strb r3, [r7, #15] + 80019de: 7bfa ldrb r2, [r7, #15] + 80019e0: 687b ldr r3, [r7, #4] + 80019e2: 685b ldr r3, [r3, #4] + 80019e4: 429a cmp r2, r3 + 80019e6: d3c8 bcc.n 800197a + } + + /* Init Device */ + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + 80019e8: 687b ldr r3, [r7, #4] + 80019ea: 681b ldr r3, [r3, #0] + 80019ec: 603b str r3, [r7, #0] + 80019ee: 687e ldr r6, [r7, #4] + 80019f0: 466d mov r5, sp + 80019f2: f106 0410 add.w r4, r6, #16 + 80019f6: cc0f ldmia r4!, {r0, r1, r2, r3} + 80019f8: c50f stmia r5!, {r0, r1, r2, r3} + 80019fa: 6823 ldr r3, [r4, #0] + 80019fc: 602b str r3, [r5, #0] + 80019fe: 1d33 adds r3, r6, #4 + 8001a00: cb0e ldmia r3, {r1, r2, r3} + 8001a02: 6838 ldr r0, [r7, #0] + 8001a04: f002 fe37 bl 8004676 + 8001a08: 4603 mov r3, r0 + 8001a0a: 2b00 cmp r3, #0 + 8001a0c: d005 beq.n 8001a1a + { + hpcd->State = HAL_PCD_STATE_ERROR; + 8001a0e: 687b ldr r3, [r7, #4] + 8001a10: 2202 movs r2, #2 + 8001a12: f883 2229 strb.w r2, [r3, #553] ; 0x229 + return HAL_ERROR; + 8001a16: 2301 movs r3, #1 + 8001a18: e00d b.n 8001a36 + } + + hpcd->USB_Address = 0U; + 8001a1a: 687b ldr r3, [r7, #4] + 8001a1c: 2200 movs r2, #0 + 8001a1e: f883 2024 strb.w r2, [r3, #36] ; 0x24 + hpcd->State = HAL_PCD_STATE_READY; + 8001a22: 687b ldr r3, [r7, #4] + 8001a24: 2201 movs r2, #1 + 8001a26: f883 2229 strb.w r2, [r3, #553] ; 0x229 + (void)USB_DevDisconnect(hpcd->Instance); + 8001a2a: 687b ldr r3, [r7, #4] + 8001a2c: 681b ldr r3, [r3, #0] + 8001a2e: 4618 mov r0, r3 + 8001a30: f003 fe75 bl 800571e + + return HAL_OK; + 8001a34: 2300 movs r3, #0 +} + 8001a36: 4618 mov r0, r3 + 8001a38: 3714 adds r7, #20 + 8001a3a: 46bd mov sp, r7 + 8001a3c: bdf0 pop {r4, r5, r6, r7, pc} + +08001a3e : + * @brief Start the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + 8001a3e: b580 push {r7, lr} + 8001a40: b082 sub sp, #8 + 8001a42: af00 add r7, sp, #0 + 8001a44: 6078 str r0, [r7, #4] + __HAL_LOCK(hpcd); + 8001a46: 687b ldr r3, [r7, #4] + 8001a48: f893 3228 ldrb.w r3, [r3, #552] ; 0x228 + 8001a4c: 2b01 cmp r3, #1 + 8001a4e: d101 bne.n 8001a54 + 8001a50: 2302 movs r3, #2 + 8001a52: e016 b.n 8001a82 + 8001a54: 687b ldr r3, [r7, #4] + 8001a56: 2201 movs r2, #1 + 8001a58: f883 2228 strb.w r2, [r3, #552] ; 0x228 +#if defined (USB) + HAL_PCDEx_SetConnectionState(hpcd, 1U); + 8001a5c: 2101 movs r1, #1 + 8001a5e: 6878 ldr r0, [r7, #4] + 8001a60: f008 ff95 bl 800a98e +#endif /* defined (USB) */ + (void)USB_DevConnect(hpcd->Instance); + 8001a64: 687b ldr r3, [r7, #4] + 8001a66: 681b ldr r3, [r3, #0] + 8001a68: 4618 mov r0, r3 + 8001a6a: f003 fe4e bl 800570a + __HAL_PCD_ENABLE(hpcd); + 8001a6e: 687b ldr r3, [r7, #4] + 8001a70: 681b ldr r3, [r3, #0] + 8001a72: 4618 mov r0, r3 + 8001a74: f002 fdc0 bl 80045f8 + __HAL_UNLOCK(hpcd); + 8001a78: 687b ldr r3, [r7, #4] + 8001a7a: 2200 movs r2, #0 + 8001a7c: f883 2228 strb.w r2, [r3, #552] ; 0x228 + return HAL_OK; + 8001a80: 2300 movs r3, #0 +} + 8001a82: 4618 mov r0, r3 + 8001a84: 3708 adds r7, #8 + 8001a86: 46bd mov sp, r7 + 8001a88: bd80 pop {r7, pc} + +08001a8a : + * @brief This function handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + 8001a8a: b580 push {r7, lr} + 8001a8c: b082 sub sp, #8 + 8001a8e: af00 add r7, sp, #0 + 8001a90: 6078 str r0, [r7, #4] + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR)) + 8001a92: 687b ldr r3, [r7, #4] + 8001a94: 681b ldr r3, [r3, #0] + 8001a96: 4618 mov r0, r3 + 8001a98: f003 fe4b bl 8005732 + 8001a9c: 4603 mov r3, r0 + 8001a9e: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8001aa2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8001aa6: d102 bne.n 8001aae + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + (void)PCD_EP_ISR_Handler(hpcd); + 8001aa8: 6878 ldr r0, [r7, #4] + 8001aaa: f000 faf3 bl 8002094 + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET)) + 8001aae: 687b ldr r3, [r7, #4] + 8001ab0: 681b ldr r3, [r3, #0] + 8001ab2: 4618 mov r0, r3 + 8001ab4: f003 fe3d bl 8005732 + 8001ab8: 4603 mov r3, r0 + 8001aba: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8001abe: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8001ac2: d112 bne.n 8001aea + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + 8001ac4: 687b ldr r3, [r7, #4] + 8001ac6: 681b ldr r3, [r3, #0] + 8001ac8: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8001acc: b29a uxth r2, r3 + 8001ace: 687b ldr r3, [r7, #4] + 8001ad0: 681b ldr r3, [r3, #0] + 8001ad2: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8001ad6: b292 uxth r2, r2 + 8001ad8: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); + 8001adc: 6878 ldr r0, [r7, #4] + 8001ade: f008 fd64 bl 800a5aa +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + (void)HAL_PCD_SetAddress(hpcd, 0U); + 8001ae2: 2100 movs r1, #0 + 8001ae4: 6878 ldr r0, [r7, #4] + 8001ae6: f000 f8de bl 8001ca6 + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR)) + 8001aea: 687b ldr r3, [r7, #4] + 8001aec: 681b ldr r3, [r3, #0] + 8001aee: 4618 mov r0, r3 + 8001af0: f003 fe1f bl 8005732 + 8001af4: 4603 mov r3, r0 + 8001af6: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8001afa: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8001afe: d10b bne.n 8001b18 + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + 8001b00: 687b ldr r3, [r7, #4] + 8001b02: 681b ldr r3, [r3, #0] + 8001b04: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8001b08: b29a uxth r2, r3 + 8001b0a: 687b ldr r3, [r7, #4] + 8001b0c: 681b ldr r3, [r3, #0] + 8001b0e: f422 4280 bic.w r2, r2, #16384 ; 0x4000 + 8001b12: b292 uxth r2, r2 + 8001b14: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR)) + 8001b18: 687b ldr r3, [r7, #4] + 8001b1a: 681b ldr r3, [r3, #0] + 8001b1c: 4618 mov r0, r3 + 8001b1e: f003 fe08 bl 8005732 + 8001b22: 4603 mov r3, r0 + 8001b24: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8001b28: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8001b2c: d10b bne.n 8001b46 + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + 8001b2e: 687b ldr r3, [r7, #4] + 8001b30: 681b ldr r3, [r3, #0] + 8001b32: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8001b36: b29a uxth r2, r3 + 8001b38: 687b ldr r3, [r7, #4] + 8001b3a: 681b ldr r3, [r3, #0] + 8001b3c: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 8001b40: b292 uxth r2, r2 + 8001b42: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP)) + 8001b46: 687b ldr r3, [r7, #4] + 8001b48: 681b ldr r3, [r3, #0] + 8001b4a: 4618 mov r0, r3 + 8001b4c: f003 fdf1 bl 8005732 + 8001b50: 4603 mov r3, r0 + 8001b52: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8001b56: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8001b5a: d126 bne.n 8001baa + { + hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE); + 8001b5c: 687b ldr r3, [r7, #4] + 8001b5e: 681b ldr r3, [r3, #0] + 8001b60: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8001b64: b29a uxth r2, r3 + 8001b66: 687b ldr r3, [r7, #4] + 8001b68: 681b ldr r3, [r3, #0] + 8001b6a: f022 0204 bic.w r2, r2, #4 + 8001b6e: b292 uxth r2, r2 + 8001b70: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); + 8001b74: 687b ldr r3, [r7, #4] + 8001b76: 681b ldr r3, [r3, #0] + 8001b78: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8001b7c: b29a uxth r2, r3 + 8001b7e: 687b ldr r3, [r7, #4] + 8001b80: 681b ldr r3, [r3, #0] + 8001b82: f022 0208 bic.w r2, r2, #8 + 8001b86: b292 uxth r2, r2 + 8001b88: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); + 8001b8c: 6878 ldr r0, [r7, #4] + 8001b8e: f008 fd45 bl 800a61c +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + 8001b92: 687b ldr r3, [r7, #4] + 8001b94: 681b ldr r3, [r3, #0] + 8001b96: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8001b9a: b29a uxth r2, r3 + 8001b9c: 687b ldr r3, [r7, #4] + 8001b9e: 681b ldr r3, [r3, #0] + 8001ba0: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 8001ba4: b292 uxth r2, r2 + 8001ba6: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP)) + 8001baa: 687b ldr r3, [r7, #4] + 8001bac: 681b ldr r3, [r3, #0] + 8001bae: 4618 mov r0, r3 + 8001bb0: f003 fdbf bl 8005732 + 8001bb4: 4603 mov r3, r0 + 8001bb6: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8001bba: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8001bbe: d13d bne.n 8001c3c + { + /* Force low-power mode in the macrocell */ + hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + 8001bc0: 687b ldr r3, [r7, #4] + 8001bc2: 681b ldr r3, [r3, #0] + 8001bc4: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8001bc8: b29a uxth r2, r3 + 8001bca: 687b ldr r3, [r7, #4] + 8001bcc: 681b ldr r3, [r3, #0] + 8001bce: f042 0208 orr.w r2, r2, #8 + 8001bd2: b292 uxth r2, r2 + 8001bd4: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + 8001bd8: 687b ldr r3, [r7, #4] + 8001bda: 681b ldr r3, [r3, #0] + 8001bdc: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8001be0: b29a uxth r2, r3 + 8001be2: 687b ldr r3, [r7, #4] + 8001be4: 681b ldr r3, [r3, #0] + 8001be6: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 8001bea: b292 uxth r2, r2 + 8001bec: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + + hpcd->Instance->CNTR |= USB_CNTR_LP_MODE; + 8001bf0: 687b ldr r3, [r7, #4] + 8001bf2: 681b ldr r3, [r3, #0] + 8001bf4: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8001bf8: b29a uxth r2, r3 + 8001bfa: 687b ldr r3, [r7, #4] + 8001bfc: 681b ldr r3, [r3, #0] + 8001bfe: f042 0204 orr.w r2, r2, #4 + 8001c02: b292 uxth r2, r2 + 8001c04: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + /* WA: Clear Wakeup flag if raised with suspend signal */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP)) + 8001c08: 687b ldr r3, [r7, #4] + 8001c0a: 681b ldr r3, [r3, #0] + 8001c0c: 4618 mov r0, r3 + 8001c0e: f003 fd90 bl 8005732 + 8001c12: 4603 mov r3, r0 + 8001c14: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8001c18: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8001c1c: d10b bne.n 8001c36 + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + 8001c1e: 687b ldr r3, [r7, #4] + 8001c20: 681b ldr r3, [r3, #0] + 8001c22: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8001c26: b29a uxth r2, r3 + 8001c28: 687b ldr r3, [r7, #4] + 8001c2a: 681b ldr r3, [r3, #0] + 8001c2c: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 8001c30: b292 uxth r2, r2 + 8001c32: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); + 8001c36: 6878 ldr r0, [r7, #4] + 8001c38: f008 fcd6 bl 800a5e8 +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF)) + 8001c3c: 687b ldr r3, [r7, #4] + 8001c3e: 681b ldr r3, [r3, #0] + 8001c40: 4618 mov r0, r3 + 8001c42: f003 fd76 bl 8005732 + 8001c46: 4603 mov r3, r0 + 8001c48: f403 7300 and.w r3, r3, #512 ; 0x200 + 8001c4c: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8001c50: d10e bne.n 8001c70 + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + 8001c52: 687b ldr r3, [r7, #4] + 8001c54: 681b ldr r3, [r3, #0] + 8001c56: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8001c5a: b29a uxth r2, r3 + 8001c5c: 687b ldr r3, [r7, #4] + 8001c5e: 681b ldr r3, [r3, #0] + 8001c60: f422 7200 bic.w r2, r2, #512 ; 0x200 + 8001c64: b292 uxth r2, r2 + 8001c66: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); + 8001c6a: 6878 ldr r0, [r7, #4] + 8001c6c: f008 fc8f bl 800a58e +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF)) + 8001c70: 687b ldr r3, [r7, #4] + 8001c72: 681b ldr r3, [r3, #0] + 8001c74: 4618 mov r0, r3 + 8001c76: f003 fd5c bl 8005732 + 8001c7a: 4603 mov r3, r0 + 8001c7c: f403 7380 and.w r3, r3, #256 ; 0x100 + 8001c80: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8001c84: d10b bne.n 8001c9e + { + /* clear ESOF flag in ISTR */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + 8001c86: 687b ldr r3, [r7, #4] + 8001c88: 681b ldr r3, [r3, #0] + 8001c8a: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8001c8e: b29a uxth r2, r3 + 8001c90: 687b ldr r3, [r7, #4] + 8001c92: 681b ldr r3, [r3, #0] + 8001c94: f422 7280 bic.w r2, r2, #256 ; 0x100 + 8001c98: b292 uxth r2, r2 + 8001c9a: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + } +} + 8001c9e: bf00 nop + 8001ca0: 3708 adds r7, #8 + 8001ca2: 46bd mov sp, r7 + 8001ca4: bd80 pop {r7, pc} + +08001ca6 : + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + 8001ca6: b580 push {r7, lr} + 8001ca8: b082 sub sp, #8 + 8001caa: af00 add r7, sp, #0 + 8001cac: 6078 str r0, [r7, #4] + 8001cae: 460b mov r3, r1 + 8001cb0: 70fb strb r3, [r7, #3] + __HAL_LOCK(hpcd); + 8001cb2: 687b ldr r3, [r7, #4] + 8001cb4: f893 3228 ldrb.w r3, [r3, #552] ; 0x228 + 8001cb8: 2b01 cmp r3, #1 + 8001cba: d101 bne.n 8001cc0 + 8001cbc: 2302 movs r3, #2 + 8001cbe: e013 b.n 8001ce8 + 8001cc0: 687b ldr r3, [r7, #4] + 8001cc2: 2201 movs r2, #1 + 8001cc4: f883 2228 strb.w r2, [r3, #552] ; 0x228 + hpcd->USB_Address = address; + 8001cc8: 687b ldr r3, [r7, #4] + 8001cca: 78fa ldrb r2, [r7, #3] + 8001ccc: f883 2024 strb.w r2, [r3, #36] ; 0x24 + (void)USB_SetDevAddress(hpcd->Instance, address); + 8001cd0: 687b ldr r3, [r7, #4] + 8001cd2: 681b ldr r3, [r3, #0] + 8001cd4: 78fa ldrb r2, [r7, #3] + 8001cd6: 4611 mov r1, r2 + 8001cd8: 4618 mov r0, r3 + 8001cda: f003 fd03 bl 80056e4 + __HAL_UNLOCK(hpcd); + 8001cde: 687b ldr r3, [r7, #4] + 8001ce0: 2200 movs r2, #0 + 8001ce2: f883 2228 strb.w r2, [r3, #552] ; 0x228 + return HAL_OK; + 8001ce6: 2300 movs r3, #0 +} + 8001ce8: 4618 mov r0, r3 + 8001cea: 3708 adds r7, #8 + 8001cec: 46bd mov sp, r7 + 8001cee: bd80 pop {r7, pc} + +08001cf0 : + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + 8001cf0: b580 push {r7, lr} + 8001cf2: b084 sub sp, #16 + 8001cf4: af00 add r7, sp, #0 + 8001cf6: 6078 str r0, [r7, #4] + 8001cf8: 4608 mov r0, r1 + 8001cfa: 4611 mov r1, r2 + 8001cfc: 461a mov r2, r3 + 8001cfe: 4603 mov r3, r0 + 8001d00: 70fb strb r3, [r7, #3] + 8001d02: 460b mov r3, r1 + 8001d04: 803b strh r3, [r7, #0] + 8001d06: 4613 mov r3, r2 + 8001d08: 70bb strb r3, [r7, #2] + HAL_StatusTypeDef ret = HAL_OK; + 8001d0a: 2300 movs r3, #0 + 8001d0c: 72fb strb r3, [r7, #11] + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + 8001d0e: f997 3003 ldrsb.w r3, [r7, #3] + 8001d12: 2b00 cmp r3, #0 + 8001d14: da0b bge.n 8001d2e + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + 8001d16: 78fb ldrb r3, [r7, #3] + 8001d18: f003 0307 and.w r3, r3, #7 + 8001d1c: 015b lsls r3, r3, #5 + 8001d1e: 3328 adds r3, #40 ; 0x28 + 8001d20: 687a ldr r2, [r7, #4] + 8001d22: 4413 add r3, r2 + 8001d24: 60fb str r3, [r7, #12] + ep->is_in = 1U; + 8001d26: 68fb ldr r3, [r7, #12] + 8001d28: 2201 movs r2, #1 + 8001d2a: 705a strb r2, [r3, #1] + 8001d2c: e00b b.n 8001d46 + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + 8001d2e: 78fb ldrb r3, [r7, #3] + 8001d30: f003 0307 and.w r3, r3, #7 + 8001d34: 015b lsls r3, r3, #5 + 8001d36: f503 7394 add.w r3, r3, #296 ; 0x128 + 8001d3a: 687a ldr r2, [r7, #4] + 8001d3c: 4413 add r3, r2 + 8001d3e: 60fb str r3, [r7, #12] + ep->is_in = 0U; + 8001d40: 68fb ldr r3, [r7, #12] + 8001d42: 2200 movs r2, #0 + 8001d44: 705a strb r2, [r3, #1] + } + + ep->num = ep_addr & EP_ADDR_MSK; + 8001d46: 78fb ldrb r3, [r7, #3] + 8001d48: f003 0307 and.w r3, r3, #7 + 8001d4c: b2da uxtb r2, r3 + 8001d4e: 68fb ldr r3, [r7, #12] + 8001d50: 701a strb r2, [r3, #0] + ep->maxpacket = ep_mps; + 8001d52: 883a ldrh r2, [r7, #0] + 8001d54: 68fb ldr r3, [r7, #12] + 8001d56: 611a str r2, [r3, #16] + ep->type = ep_type; + 8001d58: 68fb ldr r3, [r7, #12] + 8001d5a: 78ba ldrb r2, [r7, #2] + 8001d5c: 70da strb r2, [r3, #3] + + if (ep->is_in != 0U) + 8001d5e: 68fb ldr r3, [r7, #12] + 8001d60: 785b ldrb r3, [r3, #1] + 8001d62: 2b00 cmp r3, #0 + 8001d64: d004 beq.n 8001d70 + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + 8001d66: 68fb ldr r3, [r7, #12] + 8001d68: 781b ldrb r3, [r3, #0] + 8001d6a: b29a uxth r2, r3 + 8001d6c: 68fb ldr r3, [r7, #12] + 8001d6e: 81da strh r2, [r3, #14] + } + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + 8001d70: 78bb ldrb r3, [r7, #2] + 8001d72: 2b02 cmp r3, #2 + 8001d74: d102 bne.n 8001d7c + { + ep->data_pid_start = 0U; + 8001d76: 68fb ldr r3, [r7, #12] + 8001d78: 2200 movs r2, #0 + 8001d7a: 711a strb r2, [r3, #4] + } + + __HAL_LOCK(hpcd); + 8001d7c: 687b ldr r3, [r7, #4] + 8001d7e: f893 3228 ldrb.w r3, [r3, #552] ; 0x228 + 8001d82: 2b01 cmp r3, #1 + 8001d84: d101 bne.n 8001d8a + 8001d86: 2302 movs r3, #2 + 8001d88: e00e b.n 8001da8 + 8001d8a: 687b ldr r3, [r7, #4] + 8001d8c: 2201 movs r2, #1 + 8001d8e: f883 2228 strb.w r2, [r3, #552] ; 0x228 + (void)USB_ActivateEndpoint(hpcd->Instance, ep); + 8001d92: 687b ldr r3, [r7, #4] + 8001d94: 681b ldr r3, [r3, #0] + 8001d96: 68f9 ldr r1, [r7, #12] + 8001d98: 4618 mov r0, r3 + 8001d9a: f002 fc91 bl 80046c0 + __HAL_UNLOCK(hpcd); + 8001d9e: 687b ldr r3, [r7, #4] + 8001da0: 2200 movs r2, #0 + 8001da2: f883 2228 strb.w r2, [r3, #552] ; 0x228 + + return ret; + 8001da6: 7afb ldrb r3, [r7, #11] +} + 8001da8: 4618 mov r0, r3 + 8001daa: 3710 adds r7, #16 + 8001dac: 46bd mov sp, r7 + 8001dae: bd80 pop {r7, pc} + +08001db0 : + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + 8001db0: b580 push {r7, lr} + 8001db2: b084 sub sp, #16 + 8001db4: af00 add r7, sp, #0 + 8001db6: 6078 str r0, [r7, #4] + 8001db8: 460b mov r3, r1 + 8001dba: 70fb strb r3, [r7, #3] + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + 8001dbc: f997 3003 ldrsb.w r3, [r7, #3] + 8001dc0: 2b00 cmp r3, #0 + 8001dc2: da0b bge.n 8001ddc + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + 8001dc4: 78fb ldrb r3, [r7, #3] + 8001dc6: f003 0307 and.w r3, r3, #7 + 8001dca: 015b lsls r3, r3, #5 + 8001dcc: 3328 adds r3, #40 ; 0x28 + 8001dce: 687a ldr r2, [r7, #4] + 8001dd0: 4413 add r3, r2 + 8001dd2: 60fb str r3, [r7, #12] + ep->is_in = 1U; + 8001dd4: 68fb ldr r3, [r7, #12] + 8001dd6: 2201 movs r2, #1 + 8001dd8: 705a strb r2, [r3, #1] + 8001dda: e00b b.n 8001df4 + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + 8001ddc: 78fb ldrb r3, [r7, #3] + 8001dde: f003 0307 and.w r3, r3, #7 + 8001de2: 015b lsls r3, r3, #5 + 8001de4: f503 7394 add.w r3, r3, #296 ; 0x128 + 8001de8: 687a ldr r2, [r7, #4] + 8001dea: 4413 add r3, r2 + 8001dec: 60fb str r3, [r7, #12] + ep->is_in = 0U; + 8001dee: 68fb ldr r3, [r7, #12] + 8001df0: 2200 movs r2, #0 + 8001df2: 705a strb r2, [r3, #1] + } + ep->num = ep_addr & EP_ADDR_MSK; + 8001df4: 78fb ldrb r3, [r7, #3] + 8001df6: f003 0307 and.w r3, r3, #7 + 8001dfa: b2da uxtb r2, r3 + 8001dfc: 68fb ldr r3, [r7, #12] + 8001dfe: 701a strb r2, [r3, #0] + + __HAL_LOCK(hpcd); + 8001e00: 687b ldr r3, [r7, #4] + 8001e02: f893 3228 ldrb.w r3, [r3, #552] ; 0x228 + 8001e06: 2b01 cmp r3, #1 + 8001e08: d101 bne.n 8001e0e + 8001e0a: 2302 movs r3, #2 + 8001e0c: e00e b.n 8001e2c + 8001e0e: 687b ldr r3, [r7, #4] + 8001e10: 2201 movs r2, #1 + 8001e12: f883 2228 strb.w r2, [r3, #552] ; 0x228 + (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + 8001e16: 687b ldr r3, [r7, #4] + 8001e18: 681b ldr r3, [r3, #0] + 8001e1a: 68f9 ldr r1, [r7, #12] + 8001e1c: 4618 mov r0, r3 + 8001e1e: f002 ff3d bl 8004c9c + __HAL_UNLOCK(hpcd); + 8001e22: 687b ldr r3, [r7, #4] + 8001e24: 2200 movs r2, #0 + 8001e26: f883 2228 strb.w r2, [r3, #552] ; 0x228 + return HAL_OK; + 8001e2a: 2300 movs r3, #0 +} + 8001e2c: 4618 mov r0, r3 + 8001e2e: 3710 adds r7, #16 + 8001e30: 46bd mov sp, r7 + 8001e32: bd80 pop {r7, pc} + +08001e34 : + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + 8001e34: b580 push {r7, lr} + 8001e36: b086 sub sp, #24 + 8001e38: af00 add r7, sp, #0 + 8001e3a: 60f8 str r0, [r7, #12] + 8001e3c: 607a str r2, [r7, #4] + 8001e3e: 603b str r3, [r7, #0] + 8001e40: 460b mov r3, r1 + 8001e42: 72fb strb r3, [r7, #11] + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + 8001e44: 7afb ldrb r3, [r7, #11] + 8001e46: f003 0307 and.w r3, r3, #7 + 8001e4a: 015b lsls r3, r3, #5 + 8001e4c: f503 7394 add.w r3, r3, #296 ; 0x128 + 8001e50: 68fa ldr r2, [r7, #12] + 8001e52: 4413 add r3, r2 + 8001e54: 617b str r3, [r7, #20] + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + 8001e56: 697b ldr r3, [r7, #20] + 8001e58: 687a ldr r2, [r7, #4] + 8001e5a: 615a str r2, [r3, #20] + ep->xfer_len = len; + 8001e5c: 697b ldr r3, [r7, #20] + 8001e5e: 683a ldr r2, [r7, #0] + 8001e60: 619a str r2, [r3, #24] + ep->xfer_count = 0U; + 8001e62: 697b ldr r3, [r7, #20] + 8001e64: 2200 movs r2, #0 + 8001e66: 61da str r2, [r3, #28] + ep->is_in = 0U; + 8001e68: 697b ldr r3, [r7, #20] + 8001e6a: 2200 movs r2, #0 + 8001e6c: 705a strb r2, [r3, #1] + ep->num = ep_addr & EP_ADDR_MSK; + 8001e6e: 7afb ldrb r3, [r7, #11] + 8001e70: f003 0307 and.w r3, r3, #7 + 8001e74: b2da uxtb r2, r3 + 8001e76: 697b ldr r3, [r7, #20] + 8001e78: 701a strb r2, [r3, #0] + + if ((ep_addr & EP_ADDR_MSK) == 0U) + 8001e7a: 7afb ldrb r3, [r7, #11] + 8001e7c: f003 0307 and.w r3, r3, #7 + 8001e80: 2b00 cmp r3, #0 + 8001e82: d106 bne.n 8001e92 + { + (void)USB_EP0StartXfer(hpcd->Instance, ep); + 8001e84: 68fb ldr r3, [r7, #12] + 8001e86: 681b ldr r3, [r3, #0] + 8001e88: 6979 ldr r1, [r7, #20] + 8001e8a: 4618 mov r0, r3 + 8001e8c: f003 f89c bl 8004fc8 + 8001e90: e005 b.n 8001e9e + } + else + { + (void)USB_EPStartXfer(hpcd->Instance, ep); + 8001e92: 68fb ldr r3, [r7, #12] + 8001e94: 681b ldr r3, [r3, #0] + 8001e96: 6979 ldr r1, [r7, #20] + 8001e98: 4618 mov r0, r3 + 8001e9a: f003 f895 bl 8004fc8 + } + + return HAL_OK; + 8001e9e: 2300 movs r3, #0 +} + 8001ea0: 4618 mov r0, r3 + 8001ea2: 3718 adds r7, #24 + 8001ea4: 46bd mov sp, r7 + 8001ea6: bd80 pop {r7, pc} + +08001ea8 : + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + 8001ea8: b480 push {r7} + 8001eaa: b083 sub sp, #12 + 8001eac: af00 add r7, sp, #0 + 8001eae: 6078 str r0, [r7, #4] + 8001eb0: 460b mov r3, r1 + 8001eb2: 70fb strb r3, [r7, #3] + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; + 8001eb4: 78fb ldrb r3, [r7, #3] + 8001eb6: f003 0307 and.w r3, r3, #7 + 8001eba: 687a ldr r2, [r7, #4] + 8001ebc: 330a adds r3, #10 + 8001ebe: 015b lsls r3, r3, #5 + 8001ec0: 4413 add r3, r2 + 8001ec2: 3304 adds r3, #4 + 8001ec4: 681b ldr r3, [r3, #0] +} + 8001ec6: 4618 mov r0, r3 + 8001ec8: 370c adds r7, #12 + 8001eca: 46bd mov sp, r7 + 8001ecc: bc80 pop {r7} + 8001ece: 4770 bx lr + +08001ed0 : + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + 8001ed0: b580 push {r7, lr} + 8001ed2: b086 sub sp, #24 + 8001ed4: af00 add r7, sp, #0 + 8001ed6: 60f8 str r0, [r7, #12] + 8001ed8: 607a str r2, [r7, #4] + 8001eda: 603b str r3, [r7, #0] + 8001edc: 460b mov r3, r1 + 8001ede: 72fb strb r3, [r7, #11] + PCD_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + 8001ee0: 7afb ldrb r3, [r7, #11] + 8001ee2: f003 0307 and.w r3, r3, #7 + 8001ee6: 015b lsls r3, r3, #5 + 8001ee8: 3328 adds r3, #40 ; 0x28 + 8001eea: 68fa ldr r2, [r7, #12] + 8001eec: 4413 add r3, r2 + 8001eee: 617b str r3, [r7, #20] + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + 8001ef0: 697b ldr r3, [r7, #20] + 8001ef2: 687a ldr r2, [r7, #4] + 8001ef4: 615a str r2, [r3, #20] + ep->xfer_len = len; + 8001ef6: 697b ldr r3, [r7, #20] + 8001ef8: 683a ldr r2, [r7, #0] + 8001efa: 619a str r2, [r3, #24] + ep->xfer_count = 0U; + 8001efc: 697b ldr r3, [r7, #20] + 8001efe: 2200 movs r2, #0 + 8001f00: 61da str r2, [r3, #28] + ep->is_in = 1U; + 8001f02: 697b ldr r3, [r7, #20] + 8001f04: 2201 movs r2, #1 + 8001f06: 705a strb r2, [r3, #1] + ep->num = ep_addr & EP_ADDR_MSK; + 8001f08: 7afb ldrb r3, [r7, #11] + 8001f0a: f003 0307 and.w r3, r3, #7 + 8001f0e: b2da uxtb r2, r3 + 8001f10: 697b ldr r3, [r7, #20] + 8001f12: 701a strb r2, [r3, #0] + + if ((ep_addr & EP_ADDR_MSK) == 0U) + 8001f14: 7afb ldrb r3, [r7, #11] + 8001f16: f003 0307 and.w r3, r3, #7 + 8001f1a: 2b00 cmp r3, #0 + 8001f1c: d106 bne.n 8001f2c + { + (void)USB_EP0StartXfer(hpcd->Instance, ep); + 8001f1e: 68fb ldr r3, [r7, #12] + 8001f20: 681b ldr r3, [r3, #0] + 8001f22: 6979 ldr r1, [r7, #20] + 8001f24: 4618 mov r0, r3 + 8001f26: f003 f84f bl 8004fc8 + 8001f2a: e005 b.n 8001f38 + } + else + { + (void)USB_EPStartXfer(hpcd->Instance, ep); + 8001f2c: 68fb ldr r3, [r7, #12] + 8001f2e: 681b ldr r3, [r3, #0] + 8001f30: 6979 ldr r1, [r7, #20] + 8001f32: 4618 mov r0, r3 + 8001f34: f003 f848 bl 8004fc8 + } + + return HAL_OK; + 8001f38: 2300 movs r3, #0 +} + 8001f3a: 4618 mov r0, r3 + 8001f3c: 3718 adds r7, #24 + 8001f3e: 46bd mov sp, r7 + 8001f40: bd80 pop {r7, pc} + +08001f42 : + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + 8001f42: b580 push {r7, lr} + 8001f44: b084 sub sp, #16 + 8001f46: af00 add r7, sp, #0 + 8001f48: 6078 str r0, [r7, #4] + 8001f4a: 460b mov r3, r1 + 8001f4c: 70fb strb r3, [r7, #3] + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) + 8001f4e: 78fb ldrb r3, [r7, #3] + 8001f50: f003 0207 and.w r2, r3, #7 + 8001f54: 687b ldr r3, [r7, #4] + 8001f56: 685b ldr r3, [r3, #4] + 8001f58: 429a cmp r2, r3 + 8001f5a: d901 bls.n 8001f60 + { + return HAL_ERROR; + 8001f5c: 2301 movs r3, #1 + 8001f5e: e046 b.n 8001fee + } + + if ((0x80U & ep_addr) == 0x80U) + 8001f60: f997 3003 ldrsb.w r3, [r7, #3] + 8001f64: 2b00 cmp r3, #0 + 8001f66: da0b bge.n 8001f80 + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + 8001f68: 78fb ldrb r3, [r7, #3] + 8001f6a: f003 0307 and.w r3, r3, #7 + 8001f6e: 015b lsls r3, r3, #5 + 8001f70: 3328 adds r3, #40 ; 0x28 + 8001f72: 687a ldr r2, [r7, #4] + 8001f74: 4413 add r3, r2 + 8001f76: 60fb str r3, [r7, #12] + ep->is_in = 1U; + 8001f78: 68fb ldr r3, [r7, #12] + 8001f7a: 2201 movs r2, #1 + 8001f7c: 705a strb r2, [r3, #1] + 8001f7e: e009 b.n 8001f94 + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + 8001f80: 78fb ldrb r3, [r7, #3] + 8001f82: 015b lsls r3, r3, #5 + 8001f84: f503 7394 add.w r3, r3, #296 ; 0x128 + 8001f88: 687a ldr r2, [r7, #4] + 8001f8a: 4413 add r3, r2 + 8001f8c: 60fb str r3, [r7, #12] + ep->is_in = 0U; + 8001f8e: 68fb ldr r3, [r7, #12] + 8001f90: 2200 movs r2, #0 + 8001f92: 705a strb r2, [r3, #1] + } + + ep->is_stall = 1U; + 8001f94: 68fb ldr r3, [r7, #12] + 8001f96: 2201 movs r2, #1 + 8001f98: 709a strb r2, [r3, #2] + ep->num = ep_addr & EP_ADDR_MSK; + 8001f9a: 78fb ldrb r3, [r7, #3] + 8001f9c: f003 0307 and.w r3, r3, #7 + 8001fa0: b2da uxtb r2, r3 + 8001fa2: 68fb ldr r3, [r7, #12] + 8001fa4: 701a strb r2, [r3, #0] + + __HAL_LOCK(hpcd); + 8001fa6: 687b ldr r3, [r7, #4] + 8001fa8: f893 3228 ldrb.w r3, [r3, #552] ; 0x228 + 8001fac: 2b01 cmp r3, #1 + 8001fae: d101 bne.n 8001fb4 + 8001fb0: 2302 movs r3, #2 + 8001fb2: e01c b.n 8001fee + 8001fb4: 687b ldr r3, [r7, #4] + 8001fb6: 2201 movs r2, #1 + 8001fb8: f883 2228 strb.w r2, [r3, #552] ; 0x228 + + (void)USB_EPSetStall(hpcd->Instance, ep); + 8001fbc: 687b ldr r3, [r7, #4] + 8001fbe: 681b ldr r3, [r3, #0] + 8001fc0: 68f9 ldr r1, [r7, #12] + 8001fc2: 4618 mov r0, r3 + 8001fc4: f003 fab8 bl 8005538 + if ((ep_addr & EP_ADDR_MSK) == 0U) + 8001fc8: 78fb ldrb r3, [r7, #3] + 8001fca: f003 0307 and.w r3, r3, #7 + 8001fce: 2b00 cmp r3, #0 + 8001fd0: d108 bne.n 8001fe4 + { + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); + 8001fd2: 687b ldr r3, [r7, #4] + 8001fd4: 681a ldr r2, [r3, #0] + 8001fd6: 687b ldr r3, [r7, #4] + 8001fd8: f503 730c add.w r3, r3, #560 ; 0x230 + 8001fdc: 4619 mov r1, r3 + 8001fde: 4610 mov r0, r2 + 8001fe0: f003 fbb6 bl 8005750 + } + __HAL_UNLOCK(hpcd); + 8001fe4: 687b ldr r3, [r7, #4] + 8001fe6: 2200 movs r2, #0 + 8001fe8: f883 2228 strb.w r2, [r3, #552] ; 0x228 + + return HAL_OK; + 8001fec: 2300 movs r3, #0 +} + 8001fee: 4618 mov r0, r3 + 8001ff0: 3710 adds r7, #16 + 8001ff2: 46bd mov sp, r7 + 8001ff4: bd80 pop {r7, pc} + +08001ff6 : + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + 8001ff6: b580 push {r7, lr} + 8001ff8: b084 sub sp, #16 + 8001ffa: af00 add r7, sp, #0 + 8001ffc: 6078 str r0, [r7, #4] + 8001ffe: 460b mov r3, r1 + 8002000: 70fb strb r3, [r7, #3] + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + 8002002: 78fb ldrb r3, [r7, #3] + 8002004: f003 020f and.w r2, r3, #15 + 8002008: 687b ldr r3, [r7, #4] + 800200a: 685b ldr r3, [r3, #4] + 800200c: 429a cmp r2, r3 + 800200e: d901 bls.n 8002014 + { + return HAL_ERROR; + 8002010: 2301 movs r3, #1 + 8002012: e03a b.n 800208a + } + + if ((0x80U & ep_addr) == 0x80U) + 8002014: f997 3003 ldrsb.w r3, [r7, #3] + 8002018: 2b00 cmp r3, #0 + 800201a: da0b bge.n 8002034 + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + 800201c: 78fb ldrb r3, [r7, #3] + 800201e: f003 0307 and.w r3, r3, #7 + 8002022: 015b lsls r3, r3, #5 + 8002024: 3328 adds r3, #40 ; 0x28 + 8002026: 687a ldr r2, [r7, #4] + 8002028: 4413 add r3, r2 + 800202a: 60fb str r3, [r7, #12] + ep->is_in = 1U; + 800202c: 68fb ldr r3, [r7, #12] + 800202e: 2201 movs r2, #1 + 8002030: 705a strb r2, [r3, #1] + 8002032: e00b b.n 800204c + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + 8002034: 78fb ldrb r3, [r7, #3] + 8002036: f003 0307 and.w r3, r3, #7 + 800203a: 015b lsls r3, r3, #5 + 800203c: f503 7394 add.w r3, r3, #296 ; 0x128 + 8002040: 687a ldr r2, [r7, #4] + 8002042: 4413 add r3, r2 + 8002044: 60fb str r3, [r7, #12] + ep->is_in = 0U; + 8002046: 68fb ldr r3, [r7, #12] + 8002048: 2200 movs r2, #0 + 800204a: 705a strb r2, [r3, #1] + } + + ep->is_stall = 0U; + 800204c: 68fb ldr r3, [r7, #12] + 800204e: 2200 movs r2, #0 + 8002050: 709a strb r2, [r3, #2] + ep->num = ep_addr & EP_ADDR_MSK; + 8002052: 78fb ldrb r3, [r7, #3] + 8002054: f003 0307 and.w r3, r3, #7 + 8002058: b2da uxtb r2, r3 + 800205a: 68fb ldr r3, [r7, #12] + 800205c: 701a strb r2, [r3, #0] + + __HAL_LOCK(hpcd); + 800205e: 687b ldr r3, [r7, #4] + 8002060: f893 3228 ldrb.w r3, [r3, #552] ; 0x228 + 8002064: 2b01 cmp r3, #1 + 8002066: d101 bne.n 800206c + 8002068: 2302 movs r3, #2 + 800206a: e00e b.n 800208a + 800206c: 687b ldr r3, [r7, #4] + 800206e: 2201 movs r2, #1 + 8002070: f883 2228 strb.w r2, [r3, #552] ; 0x228 + (void)USB_EPClearStall(hpcd->Instance, ep); + 8002074: 687b ldr r3, [r7, #4] + 8002076: 681b ldr r3, [r3, #0] + 8002078: 68f9 ldr r1, [r7, #12] + 800207a: 4618 mov r0, r3 + 800207c: f003 fa9e bl 80055bc + __HAL_UNLOCK(hpcd); + 8002080: 687b ldr r3, [r7, #4] + 8002082: 2200 movs r2, #0 + 8002084: f883 2228 strb.w r2, [r3, #552] ; 0x228 + + return HAL_OK; + 8002088: 2300 movs r3, #0 +} + 800208a: 4618 mov r0, r3 + 800208c: 3710 adds r7, #16 + 800208e: 46bd mov sp, r7 + 8002090: bd80 pop {r7, pc} + ... + +08002094 : + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) +{ + 8002094: b590 push {r4, r7, lr} + 8002096: b089 sub sp, #36 ; 0x24 + 8002098: af00 add r7, sp, #0 + 800209a: 6078 str r0, [r7, #4] + uint16_t wIstr; + uint16_t wEPVal; + uint8_t epindex; + + /* stay in loop while pending interrupts */ + while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) + 800209c: e282 b.n 80025a4 + { + wIstr = hpcd->Instance->ISTR; + 800209e: 687b ldr r3, [r7, #4] + 80020a0: 681b ldr r3, [r3, #0] + 80020a2: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 80020a6: 82fb strh r3, [r7, #22] + /* extract highest priority endpoint number */ + epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + 80020a8: 8afb ldrh r3, [r7, #22] + 80020aa: b2db uxtb r3, r3 + 80020ac: f003 030f and.w r3, r3, #15 + 80020b0: 757b strb r3, [r7, #21] + + if (epindex == 0U) + 80020b2: 7d7b ldrb r3, [r7, #21] + 80020b4: 2b00 cmp r3, #0 + 80020b6: f040 8142 bne.w 800233e + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0U) + 80020ba: 8afb ldrh r3, [r7, #22] + 80020bc: f003 0310 and.w r3, r3, #16 + 80020c0: 2b00 cmp r3, #0 + 80020c2: d151 bne.n 8002168 + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + 80020c4: 687b ldr r3, [r7, #4] + 80020c6: 681b ldr r3, [r3, #0] + 80020c8: 881b ldrh r3, [r3, #0] + 80020ca: b29b uxth r3, r3 + 80020cc: f423 43e1 bic.w r3, r3, #28800 ; 0x7080 + 80020d0: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80020d4: b29c uxth r4, r3 + 80020d6: 687b ldr r3, [r7, #4] + 80020d8: 681a ldr r2, [r3, #0] + 80020da: ea6f 4344 mvn.w r3, r4, lsl #17 + 80020de: ea6f 4353 mvn.w r3, r3, lsr #17 + 80020e2: b29b uxth r3, r3 + 80020e4: 8013 strh r3, [r2, #0] + ep = &hpcd->IN_ep[0]; + 80020e6: 687b ldr r3, [r7, #4] + 80020e8: 3328 adds r3, #40 ; 0x28 + 80020ea: 60fb str r3, [r7, #12] + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + 80020ec: 687b ldr r3, [r7, #4] + 80020ee: 681b ldr r3, [r3, #0] + 80020f0: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80020f4: b29b uxth r3, r3 + 80020f6: 461a mov r2, r3 + 80020f8: 68fb ldr r3, [r7, #12] + 80020fa: 781b ldrb r3, [r3, #0] + 80020fc: 00db lsls r3, r3, #3 + 80020fe: 4413 add r3, r2 + 8002100: 3302 adds r3, #2 + 8002102: 005b lsls r3, r3, #1 + 8002104: 687a ldr r2, [r7, #4] + 8002106: 6812 ldr r2, [r2, #0] + 8002108: 4413 add r3, r2 + 800210a: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800210e: 881b ldrh r3, [r3, #0] + 8002110: f3c3 0209 ubfx r2, r3, #0, #10 + 8002114: 68fb ldr r3, [r7, #12] + 8002116: 61da str r2, [r3, #28] + ep->xfer_buff += ep->xfer_count; + 8002118: 68fb ldr r3, [r7, #12] + 800211a: 695a ldr r2, [r3, #20] + 800211c: 68fb ldr r3, [r7, #12] + 800211e: 69db ldr r3, [r3, #28] + 8002120: 441a add r2, r3 + 8002122: 68fb ldr r3, [r7, #12] + 8002124: 615a str r2, [r3, #20] + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, 0U); +#else + HAL_PCD_DataInStageCallback(hpcd, 0U); + 8002126: 2100 movs r1, #0 + 8002128: 6878 ldr r0, [r7, #4] + 800212a: f008 fa19 bl 800a560 +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) + 800212e: 687b ldr r3, [r7, #4] + 8002130: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 8002134: b2db uxtb r3, r3 + 8002136: 2b00 cmp r3, #0 + 8002138: f000 8234 beq.w 80025a4 + 800213c: 68fb ldr r3, [r7, #12] + 800213e: 699b ldr r3, [r3, #24] + 8002140: 2b00 cmp r3, #0 + 8002142: f040 822f bne.w 80025a4 + { + hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); + 8002146: 687b ldr r3, [r7, #4] + 8002148: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 800214c: b2db uxtb r3, r3 + 800214e: f063 037f orn r3, r3, #127 ; 0x7f + 8002152: b2da uxtb r2, r3 + 8002154: 687b ldr r3, [r7, #4] + 8002156: 681b ldr r3, [r3, #0] + 8002158: b292 uxth r2, r2 + 800215a: f8a3 204c strh.w r2, [r3, #76] ; 0x4c + hpcd->USB_Address = 0U; + 800215e: 687b ldr r3, [r7, #4] + 8002160: 2200 movs r2, #0 + 8002162: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8002166: e21d b.n 80025a4 + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + 8002168: 687b ldr r3, [r7, #4] + 800216a: f503 7394 add.w r3, r3, #296 ; 0x128 + 800216e: 60fb str r3, [r7, #12] + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + 8002170: 687b ldr r3, [r7, #4] + 8002172: 681b ldr r3, [r3, #0] + 8002174: 881b ldrh r3, [r3, #0] + 8002176: 827b strh r3, [r7, #18] + + if ((wEPVal & USB_EP_SETUP) != 0U) + 8002178: 8a7b ldrh r3, [r7, #18] + 800217a: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800217e: 2b00 cmp r3, #0 + 8002180: d033 beq.n 80021ea + { + /* Get SETUP Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + 8002182: 687b ldr r3, [r7, #4] + 8002184: 681b ldr r3, [r3, #0] + 8002186: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800218a: b29b uxth r3, r3 + 800218c: 461a mov r2, r3 + 800218e: 68fb ldr r3, [r7, #12] + 8002190: 781b ldrb r3, [r3, #0] + 8002192: 00db lsls r3, r3, #3 + 8002194: 4413 add r3, r2 + 8002196: 3306 adds r3, #6 + 8002198: 005b lsls r3, r3, #1 + 800219a: 687a ldr r2, [r7, #4] + 800219c: 6812 ldr r2, [r2, #0] + 800219e: 4413 add r3, r2 + 80021a0: f503 6380 add.w r3, r3, #1024 ; 0x400 + 80021a4: 881b ldrh r3, [r3, #0] + 80021a6: f3c3 0209 ubfx r2, r3, #0, #10 + 80021aa: 68fb ldr r3, [r7, #12] + 80021ac: 61da str r2, [r3, #28] + + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, + 80021ae: 687b ldr r3, [r7, #4] + 80021b0: 6818 ldr r0, [r3, #0] + 80021b2: 687b ldr r3, [r7, #4] + 80021b4: f503 710c add.w r1, r3, #560 ; 0x230 + 80021b8: 68fb ldr r3, [r7, #12] + 80021ba: 88da ldrh r2, [r3, #6] + ep->pmaadress, (uint16_t)ep->xfer_count); + 80021bc: 68fb ldr r3, [r7, #12] + 80021be: 69db ldr r3, [r3, #28] + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, + 80021c0: b29b uxth r3, r3 + 80021c2: f003 fb14 bl 80057ee + + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + 80021c6: 687b ldr r3, [r7, #4] + 80021c8: 681b ldr r3, [r3, #0] + 80021ca: 881b ldrh r3, [r3, #0] + 80021cc: b29a uxth r2, r3 + 80021ce: f640 738f movw r3, #3983 ; 0xf8f + 80021d2: 4013 ands r3, r2 + 80021d4: b29c uxth r4, r3 + 80021d6: 687b ldr r3, [r7, #4] + 80021d8: 681b ldr r3, [r3, #0] + 80021da: f044 0280 orr.w r2, r4, #128 ; 0x80 + 80021de: b292 uxth r2, r2 + 80021e0: 801a strh r2, [r3, #0] + + /* Process SETUP Packet*/ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); + 80021e2: 6878 ldr r0, [r7, #4] + 80021e4: f008 f992 bl 800a50c + 80021e8: e1dc b.n 80025a4 +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + else if ((wEPVal & USB_EP_CTR_RX) != 0U) + 80021ea: f9b7 3012 ldrsh.w r3, [r7, #18] + 80021ee: 2b00 cmp r3, #0 + 80021f0: f280 81d8 bge.w 80025a4 + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + 80021f4: 687b ldr r3, [r7, #4] + 80021f6: 681b ldr r3, [r3, #0] + 80021f8: 881b ldrh r3, [r3, #0] + 80021fa: b29a uxth r2, r3 + 80021fc: f640 738f movw r3, #3983 ; 0xf8f + 8002200: 4013 ands r3, r2 + 8002202: b29c uxth r4, r3 + 8002204: 687b ldr r3, [r7, #4] + 8002206: 681b ldr r3, [r3, #0] + 8002208: f044 0280 orr.w r2, r4, #128 ; 0x80 + 800220c: b292 uxth r2, r2 + 800220e: 801a strh r2, [r3, #0] + + /* Get Control Data OUT Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + 8002210: 687b ldr r3, [r7, #4] + 8002212: 681b ldr r3, [r3, #0] + 8002214: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8002218: b29b uxth r3, r3 + 800221a: 461a mov r2, r3 + 800221c: 68fb ldr r3, [r7, #12] + 800221e: 781b ldrb r3, [r3, #0] + 8002220: 00db lsls r3, r3, #3 + 8002222: 4413 add r3, r2 + 8002224: 3306 adds r3, #6 + 8002226: 005b lsls r3, r3, #1 + 8002228: 687a ldr r2, [r7, #4] + 800222a: 6812 ldr r2, [r2, #0] + 800222c: 4413 add r3, r2 + 800222e: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8002232: 881b ldrh r3, [r3, #0] + 8002234: f3c3 0209 ubfx r2, r3, #0, #10 + 8002238: 68fb ldr r3, [r7, #12] + 800223a: 61da str r2, [r3, #28] + + if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + 800223c: 68fb ldr r3, [r7, #12] + 800223e: 69db ldr r3, [r3, #28] + 8002240: 2b00 cmp r3, #0 + 8002242: d019 beq.n 8002278 + 8002244: 68fb ldr r3, [r7, #12] + 8002246: 695b ldr r3, [r3, #20] + 8002248: 2b00 cmp r3, #0 + 800224a: d015 beq.n 8002278 + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + 800224c: 687b ldr r3, [r7, #4] + 800224e: 6818 ldr r0, [r3, #0] + 8002250: 68fb ldr r3, [r7, #12] + 8002252: 6959 ldr r1, [r3, #20] + 8002254: 68fb ldr r3, [r7, #12] + 8002256: 88da ldrh r2, [r3, #6] + ep->pmaadress, (uint16_t)ep->xfer_count); + 8002258: 68fb ldr r3, [r7, #12] + 800225a: 69db ldr r3, [r3, #28] + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + 800225c: b29b uxth r3, r3 + 800225e: f003 fac6 bl 80057ee + + ep->xfer_buff += ep->xfer_count; + 8002262: 68fb ldr r3, [r7, #12] + 8002264: 695a ldr r2, [r3, #20] + 8002266: 68fb ldr r3, [r7, #12] + 8002268: 69db ldr r3, [r3, #28] + 800226a: 441a add r2, r3 + 800226c: 68fb ldr r3, [r7, #12] + 800226e: 615a str r2, [r3, #20] + + /* Process Control Data OUT Packet*/ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, 0U); +#else + HAL_PCD_DataOutStageCallback(hpcd, 0U); + 8002270: 2100 movs r1, #0 + 8002272: 6878 ldr r0, [r7, #4] + 8002274: f008 f95c bl 800a530 +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + 8002278: 687b ldr r3, [r7, #4] + 800227a: 681b ldr r3, [r3, #0] + 800227c: 461c mov r4, r3 + 800227e: 687b ldr r3, [r7, #4] + 8002280: 681b ldr r3, [r3, #0] + 8002282: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8002286: b29b uxth r3, r3 + 8002288: 441c add r4, r3 + 800228a: f204 430c addw r3, r4, #1036 ; 0x40c + 800228e: 461c mov r4, r3 + 8002290: 68fb ldr r3, [r7, #12] + 8002292: 691b ldr r3, [r3, #16] + 8002294: 2b00 cmp r3, #0 + 8002296: d10e bne.n 80022b6 + 8002298: 8823 ldrh r3, [r4, #0] + 800229a: b29b uxth r3, r3 + 800229c: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00 + 80022a0: b29b uxth r3, r3 + 80022a2: 8023 strh r3, [r4, #0] + 80022a4: 8823 ldrh r3, [r4, #0] + 80022a6: b29b uxth r3, r3 + 80022a8: ea6f 4343 mvn.w r3, r3, lsl #17 + 80022ac: ea6f 4353 mvn.w r3, r3, lsr #17 + 80022b0: b29b uxth r3, r3 + 80022b2: 8023 strh r3, [r4, #0] + 80022b4: e02d b.n 8002312 + 80022b6: 68fb ldr r3, [r7, #12] + 80022b8: 691b ldr r3, [r3, #16] + 80022ba: 2b3e cmp r3, #62 ; 0x3e + 80022bc: d812 bhi.n 80022e4 + 80022be: 68fb ldr r3, [r7, #12] + 80022c0: 691b ldr r3, [r3, #16] + 80022c2: 085b lsrs r3, r3, #1 + 80022c4: 61bb str r3, [r7, #24] + 80022c6: 68fb ldr r3, [r7, #12] + 80022c8: 691b ldr r3, [r3, #16] + 80022ca: f003 0301 and.w r3, r3, #1 + 80022ce: 2b00 cmp r3, #0 + 80022d0: d002 beq.n 80022d8 + 80022d2: 69bb ldr r3, [r7, #24] + 80022d4: 3301 adds r3, #1 + 80022d6: 61bb str r3, [r7, #24] + 80022d8: 69bb ldr r3, [r7, #24] + 80022da: b29b uxth r3, r3 + 80022dc: 029b lsls r3, r3, #10 + 80022de: b29b uxth r3, r3 + 80022e0: 8023 strh r3, [r4, #0] + 80022e2: e016 b.n 8002312 + 80022e4: 68fb ldr r3, [r7, #12] + 80022e6: 691b ldr r3, [r3, #16] + 80022e8: 095b lsrs r3, r3, #5 + 80022ea: 61bb str r3, [r7, #24] + 80022ec: 68fb ldr r3, [r7, #12] + 80022ee: 691b ldr r3, [r3, #16] + 80022f0: f003 031f and.w r3, r3, #31 + 80022f4: 2b00 cmp r3, #0 + 80022f6: d102 bne.n 80022fe + 80022f8: 69bb ldr r3, [r7, #24] + 80022fa: 3b01 subs r3, #1 + 80022fc: 61bb str r3, [r7, #24] + 80022fe: 69bb ldr r3, [r7, #24] + 8002300: b29b uxth r3, r3 + 8002302: 029b lsls r3, r3, #10 + 8002304: b29b uxth r3, r3 + 8002306: ea6f 4343 mvn.w r3, r3, lsl #17 + 800230a: ea6f 4353 mvn.w r3, r3, lsr #17 + 800230e: b29b uxth r3, r3 + 8002310: 8023 strh r3, [r4, #0] + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + 8002312: 687b ldr r3, [r7, #4] + 8002314: 681b ldr r3, [r3, #0] + 8002316: 881b ldrh r3, [r3, #0] + 8002318: b29b uxth r3, r3 + 800231a: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800231e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8002322: b29c uxth r4, r3 + 8002324: f484 5380 eor.w r3, r4, #4096 ; 0x1000 + 8002328: b29c uxth r4, r3 + 800232a: f484 5300 eor.w r3, r4, #8192 ; 0x2000 + 800232e: b29c uxth r4, r3 + 8002330: 687b ldr r3, [r7, #4] + 8002332: 681a ldr r2, [r3, #0] + 8002334: 4ba2 ldr r3, [pc, #648] ; (80025c0 ) + 8002336: 4323 orrs r3, r4 + 8002338: b29b uxth r3, r3 + 800233a: 8013 strh r3, [r2, #0] + 800233c: e132 b.n 80025a4 + else + { + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); + 800233e: 687b ldr r3, [r7, #4] + 8002340: 681b ldr r3, [r3, #0] + 8002342: 461a mov r2, r3 + 8002344: 7d7b ldrb r3, [r7, #21] + 8002346: 009b lsls r3, r3, #2 + 8002348: 4413 add r3, r2 + 800234a: 881b ldrh r3, [r3, #0] + 800234c: 827b strh r3, [r7, #18] + if ((wEPVal & USB_EP_CTR_RX) != 0U) + 800234e: f9b7 3012 ldrsh.w r3, [r7, #18] + 8002352: 2b00 cmp r3, #0 + 8002354: f280 80d1 bge.w 80024fa + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); + 8002358: 687b ldr r3, [r7, #4] + 800235a: 681b ldr r3, [r3, #0] + 800235c: 461a mov r2, r3 + 800235e: 7d7b ldrb r3, [r7, #21] + 8002360: 009b lsls r3, r3, #2 + 8002362: 4413 add r3, r2 + 8002364: 881b ldrh r3, [r3, #0] + 8002366: b29a uxth r2, r3 + 8002368: f640 738f movw r3, #3983 ; 0xf8f + 800236c: 4013 ands r3, r2 + 800236e: b29c uxth r4, r3 + 8002370: 687b ldr r3, [r7, #4] + 8002372: 681b ldr r3, [r3, #0] + 8002374: 461a mov r2, r3 + 8002376: 7d7b ldrb r3, [r7, #21] + 8002378: 009b lsls r3, r3, #2 + 800237a: 4413 add r3, r2 + 800237c: f044 0280 orr.w r2, r4, #128 ; 0x80 + 8002380: b292 uxth r2, r2 + 8002382: 801a strh r2, [r3, #0] + ep = &hpcd->OUT_ep[epindex]; + 8002384: 7d7b ldrb r3, [r7, #21] + 8002386: 015b lsls r3, r3, #5 + 8002388: f503 7394 add.w r3, r3, #296 ; 0x128 + 800238c: 687a ldr r2, [r7, #4] + 800238e: 4413 add r3, r2 + 8002390: 60fb str r3, [r7, #12] + + /* OUT double Buffering*/ + if (ep->doublebuffer == 0U) + 8002392: 68fb ldr r3, [r7, #12] + 8002394: 7b1b ldrb r3, [r3, #12] + 8002396: 2b00 cmp r3, #0 + 8002398: d121 bne.n 80023de + { + count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + 800239a: 687b ldr r3, [r7, #4] + 800239c: 681b ldr r3, [r3, #0] + 800239e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80023a2: b29b uxth r3, r3 + 80023a4: 461a mov r2, r3 + 80023a6: 68fb ldr r3, [r7, #12] + 80023a8: 781b ldrb r3, [r3, #0] + 80023aa: 00db lsls r3, r3, #3 + 80023ac: 4413 add r3, r2 + 80023ae: 3306 adds r3, #6 + 80023b0: 005b lsls r3, r3, #1 + 80023b2: 687a ldr r2, [r7, #4] + 80023b4: 6812 ldr r2, [r2, #0] + 80023b6: 4413 add r3, r2 + 80023b8: f503 6380 add.w r3, r3, #1024 ; 0x400 + 80023bc: 881b ldrh r3, [r3, #0] + 80023be: f3c3 0309 ubfx r3, r3, #0, #10 + 80023c2: 83fb strh r3, [r7, #30] + if (count != 0U) + 80023c4: 8bfb ldrh r3, [r7, #30] + 80023c6: 2b00 cmp r3, #0 + 80023c8: d072 beq.n 80024b0 + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + 80023ca: 687b ldr r3, [r7, #4] + 80023cc: 6818 ldr r0, [r3, #0] + 80023ce: 68fb ldr r3, [r7, #12] + 80023d0: 6959 ldr r1, [r3, #20] + 80023d2: 68fb ldr r3, [r7, #12] + 80023d4: 88da ldrh r2, [r3, #6] + 80023d6: 8bfb ldrh r3, [r7, #30] + 80023d8: f003 fa09 bl 80057ee + 80023dc: e068 b.n 80024b0 + } + } + else + { + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) + 80023de: 687b ldr r3, [r7, #4] + 80023e0: 681b ldr r3, [r3, #0] + 80023e2: 461a mov r2, r3 + 80023e4: 68fb ldr r3, [r7, #12] + 80023e6: 781b ldrb r3, [r3, #0] + 80023e8: 009b lsls r3, r3, #2 + 80023ea: 4413 add r3, r2 + 80023ec: 881b ldrh r3, [r3, #0] + 80023ee: b29b uxth r3, r3 + 80023f0: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80023f4: 2b00 cmp r3, #0 + 80023f6: d021 beq.n 800243c + { + /*read from endpoint BUF0Addr buffer*/ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + 80023f8: 687b ldr r3, [r7, #4] + 80023fa: 681b ldr r3, [r3, #0] + 80023fc: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8002400: b29b uxth r3, r3 + 8002402: 461a mov r2, r3 + 8002404: 68fb ldr r3, [r7, #12] + 8002406: 781b ldrb r3, [r3, #0] + 8002408: 00db lsls r3, r3, #3 + 800240a: 4413 add r3, r2 + 800240c: 3302 adds r3, #2 + 800240e: 005b lsls r3, r3, #1 + 8002410: 687a ldr r2, [r7, #4] + 8002412: 6812 ldr r2, [r2, #0] + 8002414: 4413 add r3, r2 + 8002416: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800241a: 881b ldrh r3, [r3, #0] + 800241c: f3c3 0309 ubfx r3, r3, #0, #10 + 8002420: 83fb strh r3, [r7, #30] + if (count != 0U) + 8002422: 8bfb ldrh r3, [r7, #30] + 8002424: 2b00 cmp r3, #0 + 8002426: d02a beq.n 800247e + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + 8002428: 687b ldr r3, [r7, #4] + 800242a: 6818 ldr r0, [r3, #0] + 800242c: 68fb ldr r3, [r7, #12] + 800242e: 6959 ldr r1, [r3, #20] + 8002430: 68fb ldr r3, [r7, #12] + 8002432: 891a ldrh r2, [r3, #8] + 8002434: 8bfb ldrh r3, [r7, #30] + 8002436: f003 f9da bl 80057ee + 800243a: e020 b.n 800247e + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + 800243c: 687b ldr r3, [r7, #4] + 800243e: 681b ldr r3, [r3, #0] + 8002440: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8002444: b29b uxth r3, r3 + 8002446: 461a mov r2, r3 + 8002448: 68fb ldr r3, [r7, #12] + 800244a: 781b ldrb r3, [r3, #0] + 800244c: 00db lsls r3, r3, #3 + 800244e: 4413 add r3, r2 + 8002450: 3306 adds r3, #6 + 8002452: 005b lsls r3, r3, #1 + 8002454: 687a ldr r2, [r7, #4] + 8002456: 6812 ldr r2, [r2, #0] + 8002458: 4413 add r3, r2 + 800245a: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800245e: 881b ldrh r3, [r3, #0] + 8002460: f3c3 0309 ubfx r3, r3, #0, #10 + 8002464: 83fb strh r3, [r7, #30] + if (count != 0U) + 8002466: 8bfb ldrh r3, [r7, #30] + 8002468: 2b00 cmp r3, #0 + 800246a: d008 beq.n 800247e + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + 800246c: 687b ldr r3, [r7, #4] + 800246e: 6818 ldr r0, [r3, #0] + 8002470: 68fb ldr r3, [r7, #12] + 8002472: 6959 ldr r1, [r3, #20] + 8002474: 68fb ldr r3, [r7, #12] + 8002476: 895a ldrh r2, [r3, #10] + 8002478: 8bfb ldrh r3, [r7, #30] + 800247a: f003 f9b8 bl 80057ee + } + } + /* free EP OUT Buffer */ + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); + 800247e: 687b ldr r3, [r7, #4] + 8002480: 681b ldr r3, [r3, #0] + 8002482: 461a mov r2, r3 + 8002484: 68fb ldr r3, [r7, #12] + 8002486: 781b ldrb r3, [r3, #0] + 8002488: 009b lsls r3, r3, #2 + 800248a: 4413 add r3, r2 + 800248c: 881b ldrh r3, [r3, #0] + 800248e: b29b uxth r3, r3 + 8002490: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8002494: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8002498: b29c uxth r4, r3 + 800249a: 687b ldr r3, [r7, #4] + 800249c: 681b ldr r3, [r3, #0] + 800249e: 461a mov r2, r3 + 80024a0: 68fb ldr r3, [r7, #12] + 80024a2: 781b ldrb r3, [r3, #0] + 80024a4: 009b lsls r3, r3, #2 + 80024a6: 441a add r2, r3 + 80024a8: 4b46 ldr r3, [pc, #280] ; (80025c4 ) + 80024aa: 4323 orrs r3, r4 + 80024ac: b29b uxth r3, r3 + 80024ae: 8013 strh r3, [r2, #0] + } + /*multi-packet on the NON control OUT endpoint*/ + ep->xfer_count += count; + 80024b0: 68fb ldr r3, [r7, #12] + 80024b2: 69da ldr r2, [r3, #28] + 80024b4: 8bfb ldrh r3, [r7, #30] + 80024b6: 441a add r2, r3 + 80024b8: 68fb ldr r3, [r7, #12] + 80024ba: 61da str r2, [r3, #28] + ep->xfer_buff += count; + 80024bc: 68fb ldr r3, [r7, #12] + 80024be: 695a ldr r2, [r3, #20] + 80024c0: 8bfb ldrh r3, [r7, #30] + 80024c2: 441a add r2, r3 + 80024c4: 68fb ldr r3, [r7, #12] + 80024c6: 615a str r2, [r3, #20] + + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) + 80024c8: 68fb ldr r3, [r7, #12] + 80024ca: 699b ldr r3, [r3, #24] + 80024cc: 2b00 cmp r3, #0 + 80024ce: d004 beq.n 80024da + 80024d0: 8bfa ldrh r2, [r7, #30] + 80024d2: 68fb ldr r3, [r7, #12] + 80024d4: 691b ldr r3, [r3, #16] + 80024d6: 429a cmp r2, r3 + 80024d8: d206 bcs.n 80024e8 + { + /* RX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataOutStageCallback(hpcd, ep->num); + 80024da: 68fb ldr r3, [r7, #12] + 80024dc: 781b ldrb r3, [r3, #0] + 80024de: 4619 mov r1, r3 + 80024e0: 6878 ldr r0, [r7, #4] + 80024e2: f008 f825 bl 800a530 + 80024e6: e008 b.n 80024fa +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + 80024e8: 68fb ldr r3, [r7, #12] + 80024ea: 7819 ldrb r1, [r3, #0] + 80024ec: 68fb ldr r3, [r7, #12] + 80024ee: 695a ldr r2, [r3, #20] + 80024f0: 68fb ldr r3, [r7, #12] + 80024f2: 699b ldr r3, [r3, #24] + 80024f4: 6878 ldr r0, [r7, #4] + 80024f6: f7ff fc9d bl 8001e34 + } + + } /* if((wEPVal & EP_CTR_RX) */ + + if ((wEPVal & USB_EP_CTR_TX) != 0U) + 80024fa: 8a7b ldrh r3, [r7, #18] + 80024fc: f003 0380 and.w r3, r3, #128 ; 0x80 + 8002500: 2b00 cmp r3, #0 + 8002502: d04f beq.n 80025a4 + { + ep = &hpcd->IN_ep[epindex]; + 8002504: 7d7b ldrb r3, [r7, #21] + 8002506: 015b lsls r3, r3, #5 + 8002508: 3328 adds r3, #40 ; 0x28 + 800250a: 687a ldr r2, [r7, #4] + 800250c: 4413 add r3, r2 + 800250e: 60fb str r3, [r7, #12] + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); + 8002510: 687b ldr r3, [r7, #4] + 8002512: 681b ldr r3, [r3, #0] + 8002514: 461a mov r2, r3 + 8002516: 7d7b ldrb r3, [r7, #21] + 8002518: 009b lsls r3, r3, #2 + 800251a: 4413 add r3, r2 + 800251c: 881b ldrh r3, [r3, #0] + 800251e: b29b uxth r3, r3 + 8002520: f423 43e1 bic.w r3, r3, #28800 ; 0x7080 + 8002524: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8002528: b29c uxth r4, r3 + 800252a: 687b ldr r3, [r7, #4] + 800252c: 681b ldr r3, [r3, #0] + 800252e: 461a mov r2, r3 + 8002530: 7d7b ldrb r3, [r7, #21] + 8002532: 009b lsls r3, r3, #2 + 8002534: 441a add r2, r3 + 8002536: ea6f 4344 mvn.w r3, r4, lsl #17 + 800253a: ea6f 4353 mvn.w r3, r3, lsr #17 + 800253e: b29b uxth r3, r3 + 8002540: 8013 strh r3, [r2, #0] + + /*multi-packet on the NON control IN endpoint*/ + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + 8002542: 687b ldr r3, [r7, #4] + 8002544: 681b ldr r3, [r3, #0] + 8002546: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800254a: b29b uxth r3, r3 + 800254c: 461a mov r2, r3 + 800254e: 68fb ldr r3, [r7, #12] + 8002550: 781b ldrb r3, [r3, #0] + 8002552: 00db lsls r3, r3, #3 + 8002554: 4413 add r3, r2 + 8002556: 3302 adds r3, #2 + 8002558: 005b lsls r3, r3, #1 + 800255a: 687a ldr r2, [r7, #4] + 800255c: 6812 ldr r2, [r2, #0] + 800255e: 4413 add r3, r2 + 8002560: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8002564: 881b ldrh r3, [r3, #0] + 8002566: f3c3 0209 ubfx r2, r3, #0, #10 + 800256a: 68fb ldr r3, [r7, #12] + 800256c: 61da str r2, [r3, #28] + ep->xfer_buff += ep->xfer_count; + 800256e: 68fb ldr r3, [r7, #12] + 8002570: 695a ldr r2, [r3, #20] + 8002572: 68fb ldr r3, [r7, #12] + 8002574: 69db ldr r3, [r3, #28] + 8002576: 441a add r2, r3 + 8002578: 68fb ldr r3, [r7, #12] + 800257a: 615a str r2, [r3, #20] + + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + 800257c: 68fb ldr r3, [r7, #12] + 800257e: 699b ldr r3, [r3, #24] + 8002580: 2b00 cmp r3, #0 + 8002582: d106 bne.n 8002592 + { + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); + 8002584: 68fb ldr r3, [r7, #12] + 8002586: 781b ldrb r3, [r3, #0] + 8002588: 4619 mov r1, r3 + 800258a: 6878 ldr r0, [r7, #4] + 800258c: f007 ffe8 bl 800a560 + 8002590: e008 b.n 80025a4 +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + 8002592: 68fb ldr r3, [r7, #12] + 8002594: 7819 ldrb r1, [r3, #0] + 8002596: 68fb ldr r3, [r7, #12] + 8002598: 695a ldr r2, [r3, #20] + 800259a: 68fb ldr r3, [r7, #12] + 800259c: 699b ldr r3, [r3, #24] + 800259e: 6878 ldr r0, [r7, #4] + 80025a0: f7ff fc96 bl 8001ed0 + while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) + 80025a4: 687b ldr r3, [r7, #4] + 80025a6: 681b ldr r3, [r3, #0] + 80025a8: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 80025ac: b29b uxth r3, r3 + 80025ae: b21b sxth r3, r3 + 80025b0: 2b00 cmp r3, #0 + 80025b2: f6ff ad74 blt.w 800209e + } + } + } + } + return HAL_OK; + 80025b6: 2300 movs r3, #0 +} + 80025b8: 4618 mov r0, r3 + 80025ba: 3724 adds r7, #36 ; 0x24 + 80025bc: 46bd mov sp, r7 + 80025be: bd90 pop {r4, r7, pc} + 80025c0: ffff8080 .word 0xffff8080 + 80025c4: ffff80c0 .word 0xffff80c0 + +080025c8 : + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress) +{ + 80025c8: b480 push {r7} + 80025ca: b087 sub sp, #28 + 80025cc: af00 add r7, sp, #0 + 80025ce: 60f8 str r0, [r7, #12] + 80025d0: 607b str r3, [r7, #4] + 80025d2: 460b mov r3, r1 + 80025d4: 817b strh r3, [r7, #10] + 80025d6: 4613 mov r3, r2 + 80025d8: 813b strh r3, [r7, #8] + PCD_EPTypeDef *ep; + + /* initialize ep structure*/ + if ((0x80U & ep_addr) == 0x80U) + 80025da: 897b ldrh r3, [r7, #10] + 80025dc: f003 0380 and.w r3, r3, #128 ; 0x80 + 80025e0: b29b uxth r3, r3 + 80025e2: 2b00 cmp r3, #0 + 80025e4: d008 beq.n 80025f8 + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + 80025e6: 897b ldrh r3, [r7, #10] + 80025e8: f003 0307 and.w r3, r3, #7 + 80025ec: 015b lsls r3, r3, #5 + 80025ee: 3328 adds r3, #40 ; 0x28 + 80025f0: 68fa ldr r2, [r7, #12] + 80025f2: 4413 add r3, r2 + 80025f4: 617b str r3, [r7, #20] + 80025f6: e006 b.n 8002606 + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + 80025f8: 897b ldrh r3, [r7, #10] + 80025fa: 015b lsls r3, r3, #5 + 80025fc: f503 7394 add.w r3, r3, #296 ; 0x128 + 8002600: 68fa ldr r2, [r7, #12] + 8002602: 4413 add r3, r2 + 8002604: 617b str r3, [r7, #20] + } + + /* Here we check if the endpoint is single or double Buffer*/ + if (ep_kind == PCD_SNG_BUF) + 8002606: 893b ldrh r3, [r7, #8] + 8002608: 2b00 cmp r3, #0 + 800260a: d107 bne.n 800261c + { + /* Single Buffer */ + ep->doublebuffer = 0U; + 800260c: 697b ldr r3, [r7, #20] + 800260e: 2200 movs r2, #0 + 8002610: 731a strb r2, [r3, #12] + /* Configure the PMA */ + ep->pmaadress = (uint16_t)pmaadress; + 8002612: 687b ldr r3, [r7, #4] + 8002614: b29a uxth r2, r3 + 8002616: 697b ldr r3, [r7, #20] + 8002618: 80da strh r2, [r3, #6] + 800261a: e00b b.n 8002634 + } + else /* USB_DBL_BUF */ + { + /* Double Buffer Endpoint */ + ep->doublebuffer = 1U; + 800261c: 697b ldr r3, [r7, #20] + 800261e: 2201 movs r2, #1 + 8002620: 731a strb r2, [r3, #12] + /* Configure the PMA */ + ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); + 8002622: 687b ldr r3, [r7, #4] + 8002624: b29a uxth r2, r3 + 8002626: 697b ldr r3, [r7, #20] + 8002628: 811a strh r2, [r3, #8] + ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); + 800262a: 687b ldr r3, [r7, #4] + 800262c: 0c1b lsrs r3, r3, #16 + 800262e: b29a uxth r2, r3 + 8002630: 697b ldr r3, [r7, #20] + 8002632: 815a strh r2, [r3, #10] + } + + return HAL_OK; + 8002634: 2300 movs r3, #0 +} + 8002636: 4618 mov r0, r3 + 8002638: 371c adds r7, #28 + 800263a: 46bd mov sp, r7 + 800263c: bc80 pop {r7} + 800263e: 4770 bx lr + +08002640 : + * @note If the HSE divided by 128 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + 8002640: b480 push {r7} + 8002642: af00 add r7, sp, #0 + /* Enable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; + 8002644: 4b03 ldr r3, [pc, #12] ; (8002654 ) + 8002646: 2201 movs r2, #1 + 8002648: 601a str r2, [r3, #0] +} + 800264a: bf00 nop + 800264c: 46bd mov sp, r7 + 800264e: bc80 pop {r7} + 8002650: 4770 bx lr + 8002652: bf00 nop + 8002654: 420e0020 .word 0x420e0020 + +08002658 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8002658: b580 push {r7, lr} + 800265a: b086 sub sp, #24 + 800265c: af00 add r7, sp, #0 + 800265e: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t pll_config; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8002660: 687b ldr r3, [r7, #4] + 8002662: 2b00 cmp r3, #0 + 8002664: d101 bne.n 800266a + { + return HAL_ERROR; + 8002666: 2301 movs r3, #1 + 8002668: e26c b.n 8002b44 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 800266a: 687b ldr r3, [r7, #4] + 800266c: 681b ldr r3, [r3, #0] + 800266e: f003 0301 and.w r3, r3, #1 + 8002672: 2b00 cmp r3, #0 + 8002674: f000 8087 beq.w 8002786 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 8002678: 4b92 ldr r3, [pc, #584] ; (80028c4 ) + 800267a: 685b ldr r3, [r3, #4] + 800267c: f003 030c and.w r3, r3, #12 + 8002680: 2b04 cmp r3, #4 + 8002682: d00c beq.n 800269e + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + 8002684: 4b8f ldr r3, [pc, #572] ; (80028c4 ) + 8002686: 685b ldr r3, [r3, #4] + 8002688: f003 030c and.w r3, r3, #12 + 800268c: 2b08 cmp r3, #8 + 800268e: d112 bne.n 80026b6 + 8002690: 4b8c ldr r3, [pc, #560] ; (80028c4 ) + 8002692: 685b ldr r3, [r3, #4] + 8002694: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8002698: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800269c: d10b bne.n 80026b6 + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 800269e: 4b89 ldr r3, [pc, #548] ; (80028c4 ) + 80026a0: 681b ldr r3, [r3, #0] + 80026a2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80026a6: 2b00 cmp r3, #0 + 80026a8: d06c beq.n 8002784 + 80026aa: 687b ldr r3, [r7, #4] + 80026ac: 685b ldr r3, [r3, #4] + 80026ae: 2b00 cmp r3, #0 + 80026b0: d168 bne.n 8002784 + { + return HAL_ERROR; + 80026b2: 2301 movs r3, #1 + 80026b4: e246 b.n 8002b44 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 80026b6: 687b ldr r3, [r7, #4] + 80026b8: 685b ldr r3, [r3, #4] + 80026ba: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80026be: d106 bne.n 80026ce + 80026c0: 4b80 ldr r3, [pc, #512] ; (80028c4 ) + 80026c2: 681b ldr r3, [r3, #0] + 80026c4: 4a7f ldr r2, [pc, #508] ; (80028c4 ) + 80026c6: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80026ca: 6013 str r3, [r2, #0] + 80026cc: e02e b.n 800272c + 80026ce: 687b ldr r3, [r7, #4] + 80026d0: 685b ldr r3, [r3, #4] + 80026d2: 2b00 cmp r3, #0 + 80026d4: d10c bne.n 80026f0 + 80026d6: 4b7b ldr r3, [pc, #492] ; (80028c4 ) + 80026d8: 681b ldr r3, [r3, #0] + 80026da: 4a7a ldr r2, [pc, #488] ; (80028c4 ) + 80026dc: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80026e0: 6013 str r3, [r2, #0] + 80026e2: 4b78 ldr r3, [pc, #480] ; (80028c4 ) + 80026e4: 681b ldr r3, [r3, #0] + 80026e6: 4a77 ldr r2, [pc, #476] ; (80028c4 ) + 80026e8: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80026ec: 6013 str r3, [r2, #0] + 80026ee: e01d b.n 800272c + 80026f0: 687b ldr r3, [r7, #4] + 80026f2: 685b ldr r3, [r3, #4] + 80026f4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 80026f8: d10c bne.n 8002714 + 80026fa: 4b72 ldr r3, [pc, #456] ; (80028c4 ) + 80026fc: 681b ldr r3, [r3, #0] + 80026fe: 4a71 ldr r2, [pc, #452] ; (80028c4 ) + 8002700: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8002704: 6013 str r3, [r2, #0] + 8002706: 4b6f ldr r3, [pc, #444] ; (80028c4 ) + 8002708: 681b ldr r3, [r3, #0] + 800270a: 4a6e ldr r2, [pc, #440] ; (80028c4 ) + 800270c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002710: 6013 str r3, [r2, #0] + 8002712: e00b b.n 800272c + 8002714: 4b6b ldr r3, [pc, #428] ; (80028c4 ) + 8002716: 681b ldr r3, [r3, #0] + 8002718: 4a6a ldr r2, [pc, #424] ; (80028c4 ) + 800271a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 800271e: 6013 str r3, [r2, #0] + 8002720: 4b68 ldr r3, [pc, #416] ; (80028c4 ) + 8002722: 681b ldr r3, [r3, #0] + 8002724: 4a67 ldr r2, [pc, #412] ; (80028c4 ) + 8002726: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 800272a: 6013 str r3, [r2, #0] + + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 800272c: 687b ldr r3, [r7, #4] + 800272e: 685b ldr r3, [r3, #4] + 8002730: 2b00 cmp r3, #0 + 8002732: d013 beq.n 800275c + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002734: f7fe fcb6 bl 80010a4 + 8002738: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 800273a: e008 b.n 800274e + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 800273c: f7fe fcb2 bl 80010a4 + 8002740: 4602 mov r2, r0 + 8002742: 693b ldr r3, [r7, #16] + 8002744: 1ad3 subs r3, r2, r3 + 8002746: 2b64 cmp r3, #100 ; 0x64 + 8002748: d901 bls.n 800274e + { + return HAL_TIMEOUT; + 800274a: 2303 movs r3, #3 + 800274c: e1fa b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 800274e: 4b5d ldr r3, [pc, #372] ; (80028c4 ) + 8002750: 681b ldr r3, [r3, #0] + 8002752: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002756: 2b00 cmp r3, #0 + 8002758: d0f0 beq.n 800273c + 800275a: e014 b.n 8002786 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800275c: f7fe fca2 bl 80010a4 + 8002760: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8002762: e008 b.n 8002776 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8002764: f7fe fc9e bl 80010a4 + 8002768: 4602 mov r2, r0 + 800276a: 693b ldr r3, [r7, #16] + 800276c: 1ad3 subs r3, r2, r3 + 800276e: 2b64 cmp r3, #100 ; 0x64 + 8002770: d901 bls.n 8002776 + { + return HAL_TIMEOUT; + 8002772: 2303 movs r3, #3 + 8002774: e1e6 b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8002776: 4b53 ldr r3, [pc, #332] ; (80028c4 ) + 8002778: 681b ldr r3, [r3, #0] + 800277a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800277e: 2b00 cmp r3, #0 + 8002780: d1f0 bne.n 8002764 + 8002782: e000 b.n 8002786 + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8002784: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8002786: 687b ldr r3, [r7, #4] + 8002788: 681b ldr r3, [r3, #0] + 800278a: f003 0302 and.w r3, r3, #2 + 800278e: 2b00 cmp r3, #0 + 8002790: d063 beq.n 800285a + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 8002792: 4b4c ldr r3, [pc, #304] ; (80028c4 ) + 8002794: 685b ldr r3, [r3, #4] + 8002796: f003 030c and.w r3, r3, #12 + 800279a: 2b00 cmp r3, #0 + 800279c: d00b beq.n 80027b6 + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) + 800279e: 4b49 ldr r3, [pc, #292] ; (80028c4 ) + 80027a0: 685b ldr r3, [r3, #4] + 80027a2: f003 030c and.w r3, r3, #12 + 80027a6: 2b08 cmp r3, #8 + 80027a8: d11c bne.n 80027e4 + 80027aa: 4b46 ldr r3, [pc, #280] ; (80028c4 ) + 80027ac: 685b ldr r3, [r3, #4] + 80027ae: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80027b2: 2b00 cmp r3, #0 + 80027b4: d116 bne.n 80027e4 + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80027b6: 4b43 ldr r3, [pc, #268] ; (80028c4 ) + 80027b8: 681b ldr r3, [r3, #0] + 80027ba: f003 0302 and.w r3, r3, #2 + 80027be: 2b00 cmp r3, #0 + 80027c0: d005 beq.n 80027ce + 80027c2: 687b ldr r3, [r7, #4] + 80027c4: 691b ldr r3, [r3, #16] + 80027c6: 2b01 cmp r3, #1 + 80027c8: d001 beq.n 80027ce + { + return HAL_ERROR; + 80027ca: 2301 movs r3, #1 + 80027cc: e1ba b.n 8002b44 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80027ce: 4b3d ldr r3, [pc, #244] ; (80028c4 ) + 80027d0: 681b ldr r3, [r3, #0] + 80027d2: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 80027d6: 687b ldr r3, [r7, #4] + 80027d8: 695b ldr r3, [r3, #20] + 80027da: 00db lsls r3, r3, #3 + 80027dc: 4939 ldr r1, [pc, #228] ; (80028c4 ) + 80027de: 4313 orrs r3, r2 + 80027e0: 600b str r3, [r1, #0] + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80027e2: e03a b.n 800285a + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 80027e4: 687b ldr r3, [r7, #4] + 80027e6: 691b ldr r3, [r3, #16] + 80027e8: 2b00 cmp r3, #0 + 80027ea: d020 beq.n 800282e + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 80027ec: 4b36 ldr r3, [pc, #216] ; (80028c8 ) + 80027ee: 2201 movs r2, #1 + 80027f0: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80027f2: f7fe fc57 bl 80010a4 + 80027f6: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80027f8: e008 b.n 800280c + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 80027fa: f7fe fc53 bl 80010a4 + 80027fe: 4602 mov r2, r0 + 8002800: 693b ldr r3, [r7, #16] + 8002802: 1ad3 subs r3, r2, r3 + 8002804: 2b02 cmp r3, #2 + 8002806: d901 bls.n 800280c + { + return HAL_TIMEOUT; + 8002808: 2303 movs r3, #3 + 800280a: e19b b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 800280c: 4b2d ldr r3, [pc, #180] ; (80028c4 ) + 800280e: 681b ldr r3, [r3, #0] + 8002810: f003 0302 and.w r3, r3, #2 + 8002814: 2b00 cmp r3, #0 + 8002816: d0f0 beq.n 80027fa + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8002818: 4b2a ldr r3, [pc, #168] ; (80028c4 ) + 800281a: 681b ldr r3, [r3, #0] + 800281c: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8002820: 687b ldr r3, [r7, #4] + 8002822: 695b ldr r3, [r3, #20] + 8002824: 00db lsls r3, r3, #3 + 8002826: 4927 ldr r1, [pc, #156] ; (80028c4 ) + 8002828: 4313 orrs r3, r2 + 800282a: 600b str r3, [r1, #0] + 800282c: e015 b.n 800285a + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 800282e: 4b26 ldr r3, [pc, #152] ; (80028c8 ) + 8002830: 2200 movs r2, #0 + 8002832: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002834: f7fe fc36 bl 80010a4 + 8002838: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 800283a: e008 b.n 800284e + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 800283c: f7fe fc32 bl 80010a4 + 8002840: 4602 mov r2, r0 + 8002842: 693b ldr r3, [r7, #16] + 8002844: 1ad3 subs r3, r2, r3 + 8002846: 2b02 cmp r3, #2 + 8002848: d901 bls.n 800284e + { + return HAL_TIMEOUT; + 800284a: 2303 movs r3, #3 + 800284c: e17a b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 800284e: 4b1d ldr r3, [pc, #116] ; (80028c4 ) + 8002850: 681b ldr r3, [r3, #0] + 8002852: f003 0302 and.w r3, r3, #2 + 8002856: 2b00 cmp r3, #0 + 8002858: d1f0 bne.n 800283c + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 800285a: 687b ldr r3, [r7, #4] + 800285c: 681b ldr r3, [r3, #0] + 800285e: f003 0308 and.w r3, r3, #8 + 8002862: 2b00 cmp r3, #0 + 8002864: d03a beq.n 80028dc + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8002866: 687b ldr r3, [r7, #4] + 8002868: 699b ldr r3, [r3, #24] + 800286a: 2b00 cmp r3, #0 + 800286c: d019 beq.n 80028a2 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800286e: 4b17 ldr r3, [pc, #92] ; (80028cc ) + 8002870: 2201 movs r2, #1 + 8002872: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002874: f7fe fc16 bl 80010a4 + 8002878: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 800287a: e008 b.n 800288e + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 800287c: f7fe fc12 bl 80010a4 + 8002880: 4602 mov r2, r0 + 8002882: 693b ldr r3, [r7, #16] + 8002884: 1ad3 subs r3, r2, r3 + 8002886: 2b02 cmp r3, #2 + 8002888: d901 bls.n 800288e + { + return HAL_TIMEOUT; + 800288a: 2303 movs r3, #3 + 800288c: e15a b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 800288e: 4b0d ldr r3, [pc, #52] ; (80028c4 ) + 8002890: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002892: f003 0302 and.w r3, r3, #2 + 8002896: 2b00 cmp r3, #0 + 8002898: d0f0 beq.n 800287c + } + } + /* To have a fully stabilized clock in the specified range, a software delay of 1ms + should be added.*/ + RCC_Delay(1); + 800289a: 2001 movs r0, #1 + 800289c: f000 fada bl 8002e54 + 80028a0: e01c b.n 80028dc + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 80028a2: 4b0a ldr r3, [pc, #40] ; (80028cc ) + 80028a4: 2200 movs r2, #0 + 80028a6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80028a8: f7fe fbfc bl 80010a4 + 80028ac: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 80028ae: e00f b.n 80028d0 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 80028b0: f7fe fbf8 bl 80010a4 + 80028b4: 4602 mov r2, r0 + 80028b6: 693b ldr r3, [r7, #16] + 80028b8: 1ad3 subs r3, r2, r3 + 80028ba: 2b02 cmp r3, #2 + 80028bc: d908 bls.n 80028d0 + { + return HAL_TIMEOUT; + 80028be: 2303 movs r3, #3 + 80028c0: e140 b.n 8002b44 + 80028c2: bf00 nop + 80028c4: 40021000 .word 0x40021000 + 80028c8: 42420000 .word 0x42420000 + 80028cc: 42420480 .word 0x42420480 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 80028d0: 4b9e ldr r3, [pc, #632] ; (8002b4c ) + 80028d2: 6a5b ldr r3, [r3, #36] ; 0x24 + 80028d4: f003 0302 and.w r3, r3, #2 + 80028d8: 2b00 cmp r3, #0 + 80028da: d1e9 bne.n 80028b0 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 80028dc: 687b ldr r3, [r7, #4] + 80028de: 681b ldr r3, [r3, #0] + 80028e0: f003 0304 and.w r3, r3, #4 + 80028e4: 2b00 cmp r3, #0 + 80028e6: f000 80a6 beq.w 8002a36 + { + FlagStatus pwrclkchanged = RESET; + 80028ea: 2300 movs r3, #0 + 80028ec: 75fb strb r3, [r7, #23] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 80028ee: 4b97 ldr r3, [pc, #604] ; (8002b4c ) + 80028f0: 69db ldr r3, [r3, #28] + 80028f2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80028f6: 2b00 cmp r3, #0 + 80028f8: d10d bne.n 8002916 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 80028fa: 4b94 ldr r3, [pc, #592] ; (8002b4c ) + 80028fc: 69db ldr r3, [r3, #28] + 80028fe: 4a93 ldr r2, [pc, #588] ; (8002b4c ) + 8002900: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002904: 61d3 str r3, [r2, #28] + 8002906: 4b91 ldr r3, [pc, #580] ; (8002b4c ) + 8002908: 69db ldr r3, [r3, #28] + 800290a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800290e: 60bb str r3, [r7, #8] + 8002910: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8002912: 2301 movs r3, #1 + 8002914: 75fb strb r3, [r7, #23] + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002916: 4b8e ldr r3, [pc, #568] ; (8002b50 ) + 8002918: 681b ldr r3, [r3, #0] + 800291a: f403 7380 and.w r3, r3, #256 ; 0x100 + 800291e: 2b00 cmp r3, #0 + 8002920: d118 bne.n 8002954 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8002922: 4b8b ldr r3, [pc, #556] ; (8002b50 ) + 8002924: 681b ldr r3, [r3, #0] + 8002926: 4a8a ldr r2, [pc, #552] ; (8002b50 ) + 8002928: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800292c: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 800292e: f7fe fbb9 bl 80010a4 + 8002932: 6138 str r0, [r7, #16] + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002934: e008 b.n 8002948 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8002936: f7fe fbb5 bl 80010a4 + 800293a: 4602 mov r2, r0 + 800293c: 693b ldr r3, [r7, #16] + 800293e: 1ad3 subs r3, r2, r3 + 8002940: 2b64 cmp r3, #100 ; 0x64 + 8002942: d901 bls.n 8002948 + { + return HAL_TIMEOUT; + 8002944: 2303 movs r3, #3 + 8002946: e0fd b.n 8002b44 + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002948: 4b81 ldr r3, [pc, #516] ; (8002b50 ) + 800294a: 681b ldr r3, [r3, #0] + 800294c: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002950: 2b00 cmp r3, #0 + 8002952: d0f0 beq.n 8002936 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8002954: 687b ldr r3, [r7, #4] + 8002956: 68db ldr r3, [r3, #12] + 8002958: 2b01 cmp r3, #1 + 800295a: d106 bne.n 800296a + 800295c: 4b7b ldr r3, [pc, #492] ; (8002b4c ) + 800295e: 6a1b ldr r3, [r3, #32] + 8002960: 4a7a ldr r2, [pc, #488] ; (8002b4c ) + 8002962: f043 0301 orr.w r3, r3, #1 + 8002966: 6213 str r3, [r2, #32] + 8002968: e02d b.n 80029c6 + 800296a: 687b ldr r3, [r7, #4] + 800296c: 68db ldr r3, [r3, #12] + 800296e: 2b00 cmp r3, #0 + 8002970: d10c bne.n 800298c + 8002972: 4b76 ldr r3, [pc, #472] ; (8002b4c ) + 8002974: 6a1b ldr r3, [r3, #32] + 8002976: 4a75 ldr r2, [pc, #468] ; (8002b4c ) + 8002978: f023 0301 bic.w r3, r3, #1 + 800297c: 6213 str r3, [r2, #32] + 800297e: 4b73 ldr r3, [pc, #460] ; (8002b4c ) + 8002980: 6a1b ldr r3, [r3, #32] + 8002982: 4a72 ldr r2, [pc, #456] ; (8002b4c ) + 8002984: f023 0304 bic.w r3, r3, #4 + 8002988: 6213 str r3, [r2, #32] + 800298a: e01c b.n 80029c6 + 800298c: 687b ldr r3, [r7, #4] + 800298e: 68db ldr r3, [r3, #12] + 8002990: 2b05 cmp r3, #5 + 8002992: d10c bne.n 80029ae + 8002994: 4b6d ldr r3, [pc, #436] ; (8002b4c ) + 8002996: 6a1b ldr r3, [r3, #32] + 8002998: 4a6c ldr r2, [pc, #432] ; (8002b4c ) + 800299a: f043 0304 orr.w r3, r3, #4 + 800299e: 6213 str r3, [r2, #32] + 80029a0: 4b6a ldr r3, [pc, #424] ; (8002b4c ) + 80029a2: 6a1b ldr r3, [r3, #32] + 80029a4: 4a69 ldr r2, [pc, #420] ; (8002b4c ) + 80029a6: f043 0301 orr.w r3, r3, #1 + 80029aa: 6213 str r3, [r2, #32] + 80029ac: e00b b.n 80029c6 + 80029ae: 4b67 ldr r3, [pc, #412] ; (8002b4c ) + 80029b0: 6a1b ldr r3, [r3, #32] + 80029b2: 4a66 ldr r2, [pc, #408] ; (8002b4c ) + 80029b4: f023 0301 bic.w r3, r3, #1 + 80029b8: 6213 str r3, [r2, #32] + 80029ba: 4b64 ldr r3, [pc, #400] ; (8002b4c ) + 80029bc: 6a1b ldr r3, [r3, #32] + 80029be: 4a63 ldr r2, [pc, #396] ; (8002b4c ) + 80029c0: f023 0304 bic.w r3, r3, #4 + 80029c4: 6213 str r3, [r2, #32] + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 80029c6: 687b ldr r3, [r7, #4] + 80029c8: 68db ldr r3, [r3, #12] + 80029ca: 2b00 cmp r3, #0 + 80029cc: d015 beq.n 80029fa + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80029ce: f7fe fb69 bl 80010a4 + 80029d2: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 80029d4: e00a b.n 80029ec + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 80029d6: f7fe fb65 bl 80010a4 + 80029da: 4602 mov r2, r0 + 80029dc: 693b ldr r3, [r7, #16] + 80029de: 1ad3 subs r3, r2, r3 + 80029e0: f241 3288 movw r2, #5000 ; 0x1388 + 80029e4: 4293 cmp r3, r2 + 80029e6: d901 bls.n 80029ec + { + return HAL_TIMEOUT; + 80029e8: 2303 movs r3, #3 + 80029ea: e0ab b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 80029ec: 4b57 ldr r3, [pc, #348] ; (8002b4c ) + 80029ee: 6a1b ldr r3, [r3, #32] + 80029f0: f003 0302 and.w r3, r3, #2 + 80029f4: 2b00 cmp r3, #0 + 80029f6: d0ee beq.n 80029d6 + 80029f8: e014 b.n 8002a24 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80029fa: f7fe fb53 bl 80010a4 + 80029fe: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8002a00: e00a b.n 8002a18 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8002a02: f7fe fb4f bl 80010a4 + 8002a06: 4602 mov r2, r0 + 8002a08: 693b ldr r3, [r7, #16] + 8002a0a: 1ad3 subs r3, r2, r3 + 8002a0c: f241 3288 movw r2, #5000 ; 0x1388 + 8002a10: 4293 cmp r3, r2 + 8002a12: d901 bls.n 8002a18 + { + return HAL_TIMEOUT; + 8002a14: 2303 movs r3, #3 + 8002a16: e095 b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8002a18: 4b4c ldr r3, [pc, #304] ; (8002b4c ) + 8002a1a: 6a1b ldr r3, [r3, #32] + 8002a1c: f003 0302 and.w r3, r3, #2 + 8002a20: 2b00 cmp r3, #0 + 8002a22: d1ee bne.n 8002a02 + } + } + } + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + 8002a24: 7dfb ldrb r3, [r7, #23] + 8002a26: 2b01 cmp r3, #1 + 8002a28: d105 bne.n 8002a36 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8002a2a: 4b48 ldr r3, [pc, #288] ; (8002b4c ) + 8002a2c: 69db ldr r3, [r3, #28] + 8002a2e: 4a47 ldr r2, [pc, #284] ; (8002b4c ) + 8002a30: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8002a34: 61d3 str r3, [r2, #28] + +#endif /* RCC_CR_PLL2ON */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8002a36: 687b ldr r3, [r7, #4] + 8002a38: 69db ldr r3, [r3, #28] + 8002a3a: 2b00 cmp r3, #0 + 8002a3c: f000 8081 beq.w 8002b42 + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8002a40: 4b42 ldr r3, [pc, #264] ; (8002b4c ) + 8002a42: 685b ldr r3, [r3, #4] + 8002a44: f003 030c and.w r3, r3, #12 + 8002a48: 2b08 cmp r3, #8 + 8002a4a: d061 beq.n 8002b10 + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8002a4c: 687b ldr r3, [r7, #4] + 8002a4e: 69db ldr r3, [r3, #28] + 8002a50: 2b02 cmp r3, #2 + 8002a52: d146 bne.n 8002ae2 + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002a54: 4b3f ldr r3, [pc, #252] ; (8002b54 ) + 8002a56: 2200 movs r2, #0 + 8002a58: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002a5a: f7fe fb23 bl 80010a4 + 8002a5e: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002a60: e008 b.n 8002a74 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8002a62: f7fe fb1f bl 80010a4 + 8002a66: 4602 mov r2, r0 + 8002a68: 693b ldr r3, [r7, #16] + 8002a6a: 1ad3 subs r3, r2, r3 + 8002a6c: 2b02 cmp r3, #2 + 8002a6e: d901 bls.n 8002a74 + { + return HAL_TIMEOUT; + 8002a70: 2303 movs r3, #3 + 8002a72: e067 b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002a74: 4b35 ldr r3, [pc, #212] ; (8002b4c ) + 8002a76: 681b ldr r3, [r3, #0] + 8002a78: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002a7c: 2b00 cmp r3, #0 + 8002a7e: d1f0 bne.n 8002a62 + } + } + + /* Configure the HSE prediv factor --------------------------------*/ + /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ + if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) + 8002a80: 687b ldr r3, [r7, #4] + 8002a82: 6a1b ldr r3, [r3, #32] + 8002a84: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8002a88: d108 bne.n 8002a9c + /* Set PREDIV1 source */ + SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); +#endif /* RCC_CFGR2_PREDIV1SRC */ + + /* Set PREDIV1 Value */ + __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); + 8002a8a: 4b30 ldr r3, [pc, #192] ; (8002b4c ) + 8002a8c: 685b ldr r3, [r3, #4] + 8002a8e: f423 3200 bic.w r2, r3, #131072 ; 0x20000 + 8002a92: 687b ldr r3, [r7, #4] + 8002a94: 689b ldr r3, [r3, #8] + 8002a96: 492d ldr r1, [pc, #180] ; (8002b4c ) + 8002a98: 4313 orrs r3, r2 + 8002a9a: 604b str r3, [r1, #4] + } + + /* Configure the main PLL clock source and multiplication factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8002a9c: 4b2b ldr r3, [pc, #172] ; (8002b4c ) + 8002a9e: 685b ldr r3, [r3, #4] + 8002aa0: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 + 8002aa4: 687b ldr r3, [r7, #4] + 8002aa6: 6a19 ldr r1, [r3, #32] + 8002aa8: 687b ldr r3, [r7, #4] + 8002aaa: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002aac: 430b orrs r3, r1 + 8002aae: 4927 ldr r1, [pc, #156] ; (8002b4c ) + 8002ab0: 4313 orrs r3, r2 + 8002ab2: 604b str r3, [r1, #4] + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8002ab4: 4b27 ldr r3, [pc, #156] ; (8002b54 ) + 8002ab6: 2201 movs r2, #1 + 8002ab8: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002aba: f7fe faf3 bl 80010a4 + 8002abe: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002ac0: e008 b.n 8002ad4 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8002ac2: f7fe faef bl 80010a4 + 8002ac6: 4602 mov r2, r0 + 8002ac8: 693b ldr r3, [r7, #16] + 8002aca: 1ad3 subs r3, r2, r3 + 8002acc: 2b02 cmp r3, #2 + 8002ace: d901 bls.n 8002ad4 + { + return HAL_TIMEOUT; + 8002ad0: 2303 movs r3, #3 + 8002ad2: e037 b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002ad4: 4b1d ldr r3, [pc, #116] ; (8002b4c ) + 8002ad6: 681b ldr r3, [r3, #0] + 8002ad8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002adc: 2b00 cmp r3, #0 + 8002ade: d0f0 beq.n 8002ac2 + 8002ae0: e02f b.n 8002b42 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002ae2: 4b1c ldr r3, [pc, #112] ; (8002b54 ) + 8002ae4: 2200 movs r2, #0 + 8002ae6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002ae8: f7fe fadc bl 80010a4 + 8002aec: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002aee: e008 b.n 8002b02 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8002af0: f7fe fad8 bl 80010a4 + 8002af4: 4602 mov r2, r0 + 8002af6: 693b ldr r3, [r7, #16] + 8002af8: 1ad3 subs r3, r2, r3 + 8002afa: 2b02 cmp r3, #2 + 8002afc: d901 bls.n 8002b02 + { + return HAL_TIMEOUT; + 8002afe: 2303 movs r3, #3 + 8002b00: e020 b.n 8002b44 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002b02: 4b12 ldr r3, [pc, #72] ; (8002b4c ) + 8002b04: 681b ldr r3, [r3, #0] + 8002b06: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002b0a: 2b00 cmp r3, #0 + 8002b0c: d1f0 bne.n 8002af0 + 8002b0e: e018 b.n 8002b42 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8002b10: 687b ldr r3, [r7, #4] + 8002b12: 69db ldr r3, [r3, #28] + 8002b14: 2b01 cmp r3, #1 + 8002b16: d101 bne.n 8002b1c + { + return HAL_ERROR; + 8002b18: 2301 movs r3, #1 + 8002b1a: e013 b.n 8002b44 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 8002b1c: 4b0b ldr r3, [pc, #44] ; (8002b4c ) + 8002b1e: 685b ldr r3, [r3, #4] + 8002b20: 60fb str r3, [r7, #12] + if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8002b22: 68fb ldr r3, [r7, #12] + 8002b24: f403 3280 and.w r2, r3, #65536 ; 0x10000 + 8002b28: 687b ldr r3, [r7, #4] + 8002b2a: 6a1b ldr r3, [r3, #32] + 8002b2c: 429a cmp r2, r3 + 8002b2e: d106 bne.n 8002b3e + (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) + 8002b30: 68fb ldr r3, [r7, #12] + 8002b32: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 + 8002b36: 687b ldr r3, [r7, #4] + 8002b38: 6a5b ldr r3, [r3, #36] ; 0x24 + if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8002b3a: 429a cmp r2, r3 + 8002b3c: d001 beq.n 8002b42 + { + return HAL_ERROR; + 8002b3e: 2301 movs r3, #1 + 8002b40: e000 b.n 8002b44 + } + } + } + } + + return HAL_OK; + 8002b42: 2300 movs r3, #0 +} + 8002b44: 4618 mov r0, r3 + 8002b46: 3718 adds r7, #24 + 8002b48: 46bd mov sp, r7 + 8002b4a: bd80 pop {r7, pc} + 8002b4c: 40021000 .word 0x40021000 + 8002b50: 40007000 .word 0x40007000 + 8002b54: 42420060 .word 0x42420060 + +08002b58 : + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8002b58: b580 push {r7, lr} + 8002b5a: b084 sub sp, #16 + 8002b5c: af00 add r7, sp, #0 + 8002b5e: 6078 str r0, [r7, #4] + 8002b60: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 8002b62: 687b ldr r3, [r7, #4] + 8002b64: 2b00 cmp r3, #0 + 8002b66: d101 bne.n 8002b6c + { + return HAL_ERROR; + 8002b68: 2301 movs r3, #1 + 8002b6a: e0d0 b.n 8002d0e + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + +#if defined(FLASH_ACR_LATENCY) + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8002b6c: 4b6a ldr r3, [pc, #424] ; (8002d18 ) + 8002b6e: 681b ldr r3, [r3, #0] + 8002b70: f003 0307 and.w r3, r3, #7 + 8002b74: 683a ldr r2, [r7, #0] + 8002b76: 429a cmp r2, r3 + 8002b78: d910 bls.n 8002b9c + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8002b7a: 4b67 ldr r3, [pc, #412] ; (8002d18 ) + 8002b7c: 681b ldr r3, [r3, #0] + 8002b7e: f023 0207 bic.w r2, r3, #7 + 8002b82: 4965 ldr r1, [pc, #404] ; (8002d18 ) + 8002b84: 683b ldr r3, [r7, #0] + 8002b86: 4313 orrs r3, r2 + 8002b88: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002b8a: 4b63 ldr r3, [pc, #396] ; (8002d18 ) + 8002b8c: 681b ldr r3, [r3, #0] + 8002b8e: f003 0307 and.w r3, r3, #7 + 8002b92: 683a ldr r2, [r7, #0] + 8002b94: 429a cmp r2, r3 + 8002b96: d001 beq.n 8002b9c + { + return HAL_ERROR; + 8002b98: 2301 movs r3, #1 + 8002b9a: e0b8 b.n 8002d0e + } +} + +#endif /* FLASH_ACR_LATENCY */ +/*-------------------------- HCLK Configuration --------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8002b9c: 687b ldr r3, [r7, #4] + 8002b9e: 681b ldr r3, [r3, #0] + 8002ba0: f003 0302 and.w r3, r3, #2 + 8002ba4: 2b00 cmp r3, #0 + 8002ba6: d020 beq.n 8002bea + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002ba8: 687b ldr r3, [r7, #4] + 8002baa: 681b ldr r3, [r3, #0] + 8002bac: f003 0304 and.w r3, r3, #4 + 8002bb0: 2b00 cmp r3, #0 + 8002bb2: d005 beq.n 8002bc0 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 8002bb4: 4b59 ldr r3, [pc, #356] ; (8002d1c ) + 8002bb6: 685b ldr r3, [r3, #4] + 8002bb8: 4a58 ldr r2, [pc, #352] ; (8002d1c ) + 8002bba: f443 63e0 orr.w r3, r3, #1792 ; 0x700 + 8002bbe: 6053 str r3, [r2, #4] + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8002bc0: 687b ldr r3, [r7, #4] + 8002bc2: 681b ldr r3, [r3, #0] + 8002bc4: f003 0308 and.w r3, r3, #8 + 8002bc8: 2b00 cmp r3, #0 + 8002bca: d005 beq.n 8002bd8 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 8002bcc: 4b53 ldr r3, [pc, #332] ; (8002d1c ) + 8002bce: 685b ldr r3, [r3, #4] + 8002bd0: 4a52 ldr r2, [pc, #328] ; (8002d1c ) + 8002bd2: f443 5360 orr.w r3, r3, #14336 ; 0x3800 + 8002bd6: 6053 str r3, [r2, #4] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8002bd8: 4b50 ldr r3, [pc, #320] ; (8002d1c ) + 8002bda: 685b ldr r3, [r3, #4] + 8002bdc: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8002be0: 687b ldr r3, [r7, #4] + 8002be2: 689b ldr r3, [r3, #8] + 8002be4: 494d ldr r1, [pc, #308] ; (8002d1c ) + 8002be6: 4313 orrs r3, r2 + 8002be8: 604b str r3, [r1, #4] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8002bea: 687b ldr r3, [r7, #4] + 8002bec: 681b ldr r3, [r3, #0] + 8002bee: f003 0301 and.w r3, r3, #1 + 8002bf2: 2b00 cmp r3, #0 + 8002bf4: d040 beq.n 8002c78 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8002bf6: 687b ldr r3, [r7, #4] + 8002bf8: 685b ldr r3, [r3, #4] + 8002bfa: 2b01 cmp r3, #1 + 8002bfc: d107 bne.n 8002c0e + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8002bfe: 4b47 ldr r3, [pc, #284] ; (8002d1c ) + 8002c00: 681b ldr r3, [r3, #0] + 8002c02: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002c06: 2b00 cmp r3, #0 + 8002c08: d115 bne.n 8002c36 + { + return HAL_ERROR; + 8002c0a: 2301 movs r3, #1 + 8002c0c: e07f b.n 8002d0e + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8002c0e: 687b ldr r3, [r7, #4] + 8002c10: 685b ldr r3, [r3, #4] + 8002c12: 2b02 cmp r3, #2 + 8002c14: d107 bne.n 8002c26 + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002c16: 4b41 ldr r3, [pc, #260] ; (8002d1c ) + 8002c18: 681b ldr r3, [r3, #0] + 8002c1a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002c1e: 2b00 cmp r3, #0 + 8002c20: d109 bne.n 8002c36 + { + return HAL_ERROR; + 8002c22: 2301 movs r3, #1 + 8002c24: e073 b.n 8002d0e + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8002c26: 4b3d ldr r3, [pc, #244] ; (8002d1c ) + 8002c28: 681b ldr r3, [r3, #0] + 8002c2a: f003 0302 and.w r3, r3, #2 + 8002c2e: 2b00 cmp r3, #0 + 8002c30: d101 bne.n 8002c36 + { + return HAL_ERROR; + 8002c32: 2301 movs r3, #1 + 8002c34: e06b b.n 8002d0e + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8002c36: 4b39 ldr r3, [pc, #228] ; (8002d1c ) + 8002c38: 685b ldr r3, [r3, #4] + 8002c3a: f023 0203 bic.w r2, r3, #3 + 8002c3e: 687b ldr r3, [r7, #4] + 8002c40: 685b ldr r3, [r3, #4] + 8002c42: 4936 ldr r1, [pc, #216] ; (8002d1c ) + 8002c44: 4313 orrs r3, r2 + 8002c46: 604b str r3, [r1, #4] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002c48: f7fe fa2c bl 80010a4 + 8002c4c: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8002c4e: e00a b.n 8002c66 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002c50: f7fe fa28 bl 80010a4 + 8002c54: 4602 mov r2, r0 + 8002c56: 68fb ldr r3, [r7, #12] + 8002c58: 1ad3 subs r3, r2, r3 + 8002c5a: f241 3288 movw r2, #5000 ; 0x1388 + 8002c5e: 4293 cmp r3, r2 + 8002c60: d901 bls.n 8002c66 + { + return HAL_TIMEOUT; + 8002c62: 2303 movs r3, #3 + 8002c64: e053 b.n 8002d0e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8002c66: 4b2d ldr r3, [pc, #180] ; (8002d1c ) + 8002c68: 685b ldr r3, [r3, #4] + 8002c6a: f003 020c and.w r2, r3, #12 + 8002c6e: 687b ldr r3, [r7, #4] + 8002c70: 685b ldr r3, [r3, #4] + 8002c72: 009b lsls r3, r3, #2 + 8002c74: 429a cmp r2, r3 + 8002c76: d1eb bne.n 8002c50 + } + } + +#if defined(FLASH_ACR_LATENCY) + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8002c78: 4b27 ldr r3, [pc, #156] ; (8002d18 ) + 8002c7a: 681b ldr r3, [r3, #0] + 8002c7c: f003 0307 and.w r3, r3, #7 + 8002c80: 683a ldr r2, [r7, #0] + 8002c82: 429a cmp r2, r3 + 8002c84: d210 bcs.n 8002ca8 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8002c86: 4b24 ldr r3, [pc, #144] ; (8002d18 ) + 8002c88: 681b ldr r3, [r3, #0] + 8002c8a: f023 0207 bic.w r2, r3, #7 + 8002c8e: 4922 ldr r1, [pc, #136] ; (8002d18 ) + 8002c90: 683b ldr r3, [r7, #0] + 8002c92: 4313 orrs r3, r2 + 8002c94: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8002c96: 4b20 ldr r3, [pc, #128] ; (8002d18 ) + 8002c98: 681b ldr r3, [r3, #0] + 8002c9a: f003 0307 and.w r3, r3, #7 + 8002c9e: 683a ldr r2, [r7, #0] + 8002ca0: 429a cmp r2, r3 + 8002ca2: d001 beq.n 8002ca8 + { + return HAL_ERROR; + 8002ca4: 2301 movs r3, #1 + 8002ca6: e032 b.n 8002d0e + } +} +#endif /* FLASH_ACR_LATENCY */ + +/*-------------------------- PCLK1 Configuration ---------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002ca8: 687b ldr r3, [r7, #4] + 8002caa: 681b ldr r3, [r3, #0] + 8002cac: f003 0304 and.w r3, r3, #4 + 8002cb0: 2b00 cmp r3, #0 + 8002cb2: d008 beq.n 8002cc6 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8002cb4: 4b19 ldr r3, [pc, #100] ; (8002d1c ) + 8002cb6: 685b ldr r3, [r3, #4] + 8002cb8: f423 62e0 bic.w r2, r3, #1792 ; 0x700 + 8002cbc: 687b ldr r3, [r7, #4] + 8002cbe: 68db ldr r3, [r3, #12] + 8002cc0: 4916 ldr r1, [pc, #88] ; (8002d1c ) + 8002cc2: 4313 orrs r3, r2 + 8002cc4: 604b str r3, [r1, #4] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8002cc6: 687b ldr r3, [r7, #4] + 8002cc8: 681b ldr r3, [r3, #0] + 8002cca: f003 0308 and.w r3, r3, #8 + 8002cce: 2b00 cmp r3, #0 + 8002cd0: d009 beq.n 8002ce6 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 8002cd2: 4b12 ldr r3, [pc, #72] ; (8002d1c ) + 8002cd4: 685b ldr r3, [r3, #4] + 8002cd6: f423 5260 bic.w r2, r3, #14336 ; 0x3800 + 8002cda: 687b ldr r3, [r7, #4] + 8002cdc: 691b ldr r3, [r3, #16] + 8002cde: 00db lsls r3, r3, #3 + 8002ce0: 490e ldr r1, [pc, #56] ; (8002d1c ) + 8002ce2: 4313 orrs r3, r2 + 8002ce4: 604b str r3, [r1, #4] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + 8002ce6: f000 f821 bl 8002d2c + 8002cea: 4601 mov r1, r0 + 8002cec: 4b0b ldr r3, [pc, #44] ; (8002d1c ) + 8002cee: 685b ldr r3, [r3, #4] + 8002cf0: 091b lsrs r3, r3, #4 + 8002cf2: f003 030f and.w r3, r3, #15 + 8002cf6: 4a0a ldr r2, [pc, #40] ; (8002d20 ) + 8002cf8: 5cd3 ldrb r3, [r2, r3] + 8002cfa: fa21 f303 lsr.w r3, r1, r3 + 8002cfe: 4a09 ldr r2, [pc, #36] ; (8002d24 ) + 8002d00: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + 8002d02: 4b09 ldr r3, [pc, #36] ; (8002d28 ) + 8002d04: 681b ldr r3, [r3, #0] + 8002d06: 4618 mov r0, r3 + 8002d08: f7fe f98a bl 8001020 + + return HAL_OK; + 8002d0c: 2300 movs r3, #0 +} + 8002d0e: 4618 mov r0, r3 + 8002d10: 3710 adds r7, #16 + 8002d12: 46bd mov sp, r7 + 8002d14: bd80 pop {r7, pc} + 8002d16: bf00 nop + 8002d18: 40022000 .word 0x40022000 + 8002d1c: 40021000 .word 0x40021000 + 8002d20: 0800f008 .word 0x0800f008 + 8002d24: 20000140 .word 0x20000140 + 8002d28: 20000000 .word 0x20000000 + +08002d2c : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8002d2c: b490 push {r4, r7} + 8002d2e: b08a sub sp, #40 ; 0x28 + 8002d30: af00 add r7, sp, #0 +#if defined(RCC_CFGR2_PREDIV1SRC) + const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; + 8002d32: 4b2a ldr r3, [pc, #168] ; (8002ddc ) + 8002d34: 1d3c adds r4, r7, #4 + 8002d36: cb0f ldmia r3, {r0, r1, r2, r3} + 8002d38: e884 000f stmia.w r4, {r0, r1, r2, r3} +#if defined(RCC_CFGR2_PREDIV1) + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + const uint8_t aPredivFactorTable[2] = {1, 2}; + 8002d3c: 4b28 ldr r3, [pc, #160] ; (8002de0 ) + 8002d3e: 881b ldrh r3, [r3, #0] + 8002d40: 803b strh r3, [r7, #0] +#endif /*RCC_CFGR2_PREDIV1*/ + +#endif + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + 8002d42: 2300 movs r3, #0 + 8002d44: 61fb str r3, [r7, #28] + 8002d46: 2300 movs r3, #0 + 8002d48: 61bb str r3, [r7, #24] + 8002d4a: 2300 movs r3, #0 + 8002d4c: 627b str r3, [r7, #36] ; 0x24 + 8002d4e: 2300 movs r3, #0 + 8002d50: 617b str r3, [r7, #20] + uint32_t sysclockfreq = 0U; + 8002d52: 2300 movs r3, #0 + 8002d54: 623b str r3, [r7, #32] +#if defined(RCC_CFGR2_PREDIV1SRC) + uint32_t prediv2 = 0U, pll2mul = 0U; +#endif /*RCC_CFGR2_PREDIV1SRC*/ + + tmpreg = RCC->CFGR; + 8002d56: 4b23 ldr r3, [pc, #140] ; (8002de4 ) + 8002d58: 685b ldr r3, [r3, #4] + 8002d5a: 61fb str r3, [r7, #28] + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8002d5c: 69fb ldr r3, [r7, #28] + 8002d5e: f003 030c and.w r3, r3, #12 + 8002d62: 2b04 cmp r3, #4 + 8002d64: d002 beq.n 8002d6c + 8002d66: 2b08 cmp r3, #8 + 8002d68: d003 beq.n 8002d72 + 8002d6a: e02d b.n 8002dc8 + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8002d6c: 4b1e ldr r3, [pc, #120] ; (8002de8 ) + 8002d6e: 623b str r3, [r7, #32] + break; + 8002d70: e02d b.n 8002dce + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + 8002d72: 69fb ldr r3, [r7, #28] + 8002d74: 0c9b lsrs r3, r3, #18 + 8002d76: f003 030f and.w r3, r3, #15 + 8002d7a: f107 0228 add.w r2, r7, #40 ; 0x28 + 8002d7e: 4413 add r3, r2 + 8002d80: f813 3c24 ldrb.w r3, [r3, #-36] + 8002d84: 617b str r3, [r7, #20] + if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + 8002d86: 69fb ldr r3, [r7, #28] + 8002d88: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8002d8c: 2b00 cmp r3, #0 + 8002d8e: d013 beq.n 8002db8 + { +#if defined(RCC_CFGR2_PREDIV1) + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; +#else + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; + 8002d90: 4b14 ldr r3, [pc, #80] ; (8002de4 ) + 8002d92: 685b ldr r3, [r3, #4] + 8002d94: 0c5b lsrs r3, r3, #17 + 8002d96: f003 0301 and.w r3, r3, #1 + 8002d9a: f107 0228 add.w r2, r7, #40 ; 0x28 + 8002d9e: 4413 add r3, r2 + 8002da0: f813 3c28 ldrb.w r3, [r3, #-40] + 8002da4: 61bb str r3, [r7, #24] + { + pllclk = pllclk / 2; + } +#else + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); + 8002da6: 697b ldr r3, [r7, #20] + 8002da8: 4a0f ldr r2, [pc, #60] ; (8002de8 ) + 8002daa: fb02 f203 mul.w r2, r2, r3 + 8002dae: 69bb ldr r3, [r7, #24] + 8002db0: fbb2 f3f3 udiv r3, r2, r3 + 8002db4: 627b str r3, [r7, #36] ; 0x24 + 8002db6: e004 b.n 8002dc2 +#endif /*RCC_CFGR2_PREDIV1SRC*/ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + 8002db8: 697b ldr r3, [r7, #20] + 8002dba: 4a0c ldr r2, [pc, #48] ; (8002dec ) + 8002dbc: fb02 f303 mul.w r3, r2, r3 + 8002dc0: 627b str r3, [r7, #36] ; 0x24 + } + sysclockfreq = pllclk; + 8002dc2: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002dc4: 623b str r3, [r7, #32] + break; + 8002dc6: e002 b.n 8002dce + } + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + 8002dc8: 4b07 ldr r3, [pc, #28] ; (8002de8 ) + 8002dca: 623b str r3, [r7, #32] + break; + 8002dcc: bf00 nop + } + } + return sysclockfreq; + 8002dce: 6a3b ldr r3, [r7, #32] +} + 8002dd0: 4618 mov r0, r3 + 8002dd2: 3728 adds r7, #40 ; 0x28 + 8002dd4: 46bd mov sp, r7 + 8002dd6: bc90 pop {r4, r7} + 8002dd8: 4770 bx lr + 8002dda: bf00 nop + 8002ddc: 0800c640 .word 0x0800c640 + 8002de0: 0800c650 .word 0x0800c650 + 8002de4: 40021000 .word 0x40021000 + 8002de8: 007a1200 .word 0x007a1200 + 8002dec: 003d0900 .word 0x003d0900 + +08002df0 : + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8002df0: b480 push {r7} + 8002df2: af00 add r7, sp, #0 + return SystemCoreClock; + 8002df4: 4b02 ldr r3, [pc, #8] ; (8002e00 ) + 8002df6: 681b ldr r3, [r3, #0] +} + 8002df8: 4618 mov r0, r3 + 8002dfa: 46bd mov sp, r7 + 8002dfc: bc80 pop {r7} + 8002dfe: 4770 bx lr + 8002e00: 20000140 .word 0x20000140 + +08002e04 : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 8002e04: b580 push {r7, lr} + 8002e06: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); + 8002e08: f7ff fff2 bl 8002df0 + 8002e0c: 4601 mov r1, r0 + 8002e0e: 4b05 ldr r3, [pc, #20] ; (8002e24 ) + 8002e10: 685b ldr r3, [r3, #4] + 8002e12: 0a1b lsrs r3, r3, #8 + 8002e14: f003 0307 and.w r3, r3, #7 + 8002e18: 4a03 ldr r2, [pc, #12] ; (8002e28 ) + 8002e1a: 5cd3 ldrb r3, [r2, r3] + 8002e1c: fa21 f303 lsr.w r3, r1, r3 +} + 8002e20: 4618 mov r0, r3 + 8002e22: bd80 pop {r7, pc} + 8002e24: 40021000 .word 0x40021000 + 8002e28: 0800f018 .word 0x0800f018 + +08002e2c : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 8002e2c: b580 push {r7, lr} + 8002e2e: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); + 8002e30: f7ff ffde bl 8002df0 + 8002e34: 4601 mov r1, r0 + 8002e36: 4b05 ldr r3, [pc, #20] ; (8002e4c ) + 8002e38: 685b ldr r3, [r3, #4] + 8002e3a: 0adb lsrs r3, r3, #11 + 8002e3c: f003 0307 and.w r3, r3, #7 + 8002e40: 4a03 ldr r2, [pc, #12] ; (8002e50 ) + 8002e42: 5cd3 ldrb r3, [r2, r3] + 8002e44: fa21 f303 lsr.w r3, r1, r3 +} + 8002e48: 4618 mov r0, r3 + 8002e4a: bd80 pop {r7, pc} + 8002e4c: 40021000 .word 0x40021000 + 8002e50: 0800f018 .word 0x0800f018 + +08002e54 : + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay: specifies the delay time length, in milliseconds. + * @retval None + */ +static void RCC_Delay(uint32_t mdelay) +{ + 8002e54: b480 push {r7} + 8002e56: b085 sub sp, #20 + 8002e58: af00 add r7, sp, #0 + 8002e5a: 6078 str r0, [r7, #4] + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + 8002e5c: 4b0a ldr r3, [pc, #40] ; (8002e88 ) + 8002e5e: 681b ldr r3, [r3, #0] + 8002e60: 4a0a ldr r2, [pc, #40] ; (8002e8c ) + 8002e62: fba2 2303 umull r2, r3, r2, r3 + 8002e66: 0a5b lsrs r3, r3, #9 + 8002e68: 687a ldr r2, [r7, #4] + 8002e6a: fb02 f303 mul.w r3, r2, r3 + 8002e6e: 60fb str r3, [r7, #12] + do + { + __NOP(); + 8002e70: bf00 nop + } + while (Delay --); + 8002e72: 68fb ldr r3, [r7, #12] + 8002e74: 1e5a subs r2, r3, #1 + 8002e76: 60fa str r2, [r7, #12] + 8002e78: 2b00 cmp r3, #0 + 8002e7a: d1f9 bne.n 8002e70 +} + 8002e7c: bf00 nop + 8002e7e: 3714 adds r7, #20 + 8002e80: 46bd mov sp, r7 + 8002e82: bc80 pop {r7} + 8002e84: 4770 bx lr + 8002e86: bf00 nop + 8002e88: 20000140 .word 0x20000140 + 8002e8c: 10624dd3 .word 0x10624dd3 + +08002e90 : + * manually disable it. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8002e90: b580 push {r7, lr} + 8002e92: b086 sub sp, #24 + 8002e94: af00 add r7, sp, #0 + 8002e96: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U, temp_reg = 0U; + 8002e98: 2300 movs r3, #0 + 8002e9a: 613b str r3, [r7, #16] + 8002e9c: 2300 movs r3, #0 + 8002e9e: 60fb str r3, [r7, #12] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------------- RTC/LCD Configuration ------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + 8002ea0: 687b ldr r3, [r7, #4] + 8002ea2: 681b ldr r3, [r3, #0] + 8002ea4: f003 0301 and.w r3, r3, #1 + 8002ea8: 2b00 cmp r3, #0 + 8002eaa: d07d beq.n 8002fa8 + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + FlagStatus pwrclkchanged = RESET; + 8002eac: 2300 movs r3, #0 + 8002eae: 75fb strb r3, [r7, #23] + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8002eb0: 4b4f ldr r3, [pc, #316] ; (8002ff0 ) + 8002eb2: 69db ldr r3, [r3, #28] + 8002eb4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002eb8: 2b00 cmp r3, #0 + 8002eba: d10d bne.n 8002ed8 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8002ebc: 4b4c ldr r3, [pc, #304] ; (8002ff0 ) + 8002ebe: 69db ldr r3, [r3, #28] + 8002ec0: 4a4b ldr r2, [pc, #300] ; (8002ff0 ) + 8002ec2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002ec6: 61d3 str r3, [r2, #28] + 8002ec8: 4b49 ldr r3, [pc, #292] ; (8002ff0 ) + 8002eca: 69db ldr r3, [r3, #28] + 8002ecc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002ed0: 60bb str r3, [r7, #8] + 8002ed2: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8002ed4: 2301 movs r3, #1 + 8002ed6: 75fb strb r3, [r7, #23] + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002ed8: 4b46 ldr r3, [pc, #280] ; (8002ff4 ) + 8002eda: 681b ldr r3, [r3, #0] + 8002edc: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002ee0: 2b00 cmp r3, #0 + 8002ee2: d118 bne.n 8002f16 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8002ee4: 4b43 ldr r3, [pc, #268] ; (8002ff4 ) + 8002ee6: 681b ldr r3, [r3, #0] + 8002ee8: 4a42 ldr r2, [pc, #264] ; (8002ff4 ) + 8002eea: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002eee: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8002ef0: f7fe f8d8 bl 80010a4 + 8002ef4: 6138 str r0, [r7, #16] + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002ef6: e008 b.n 8002f0a + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8002ef8: f7fe f8d4 bl 80010a4 + 8002efc: 4602 mov r2, r0 + 8002efe: 693b ldr r3, [r7, #16] + 8002f00: 1ad3 subs r3, r2, r3 + 8002f02: 2b64 cmp r3, #100 ; 0x64 + 8002f04: d901 bls.n 8002f0a + { + return HAL_TIMEOUT; + 8002f06: 2303 movs r3, #3 + 8002f08: e06d b.n 8002fe6 + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8002f0a: 4b3a ldr r3, [pc, #232] ; (8002ff4 ) + 8002f0c: 681b ldr r3, [r3, #0] + 8002f0e: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002f12: 2b00 cmp r3, #0 + 8002f14: d0f0 beq.n 8002ef8 + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + 8002f16: 4b36 ldr r3, [pc, #216] ; (8002ff0 ) + 8002f18: 6a1b ldr r3, [r3, #32] + 8002f1a: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002f1e: 60fb str r3, [r7, #12] + if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 8002f20: 68fb ldr r3, [r7, #12] + 8002f22: 2b00 cmp r3, #0 + 8002f24: d02e beq.n 8002f84 + 8002f26: 687b ldr r3, [r7, #4] + 8002f28: 685b ldr r3, [r3, #4] + 8002f2a: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002f2e: 68fa ldr r2, [r7, #12] + 8002f30: 429a cmp r2, r3 + 8002f32: d027 beq.n 8002f84 + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 8002f34: 4b2e ldr r3, [pc, #184] ; (8002ff0 ) + 8002f36: 6a1b ldr r3, [r3, #32] + 8002f38: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8002f3c: 60fb str r3, [r7, #12] + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 8002f3e: 4b2e ldr r3, [pc, #184] ; (8002ff8 ) + 8002f40: 2201 movs r2, #1 + 8002f42: 601a str r2, [r3, #0] + __HAL_RCC_BACKUPRESET_RELEASE(); + 8002f44: 4b2c ldr r3, [pc, #176] ; (8002ff8 ) + 8002f46: 2200 movs r2, #0 + 8002f48: 601a str r2, [r3, #0] + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + 8002f4a: 4a29 ldr r2, [pc, #164] ; (8002ff0 ) + 8002f4c: 68fb ldr r3, [r7, #12] + 8002f4e: 6213 str r3, [r2, #32] + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + 8002f50: 68fb ldr r3, [r7, #12] + 8002f52: f003 0301 and.w r3, r3, #1 + 8002f56: 2b00 cmp r3, #0 + 8002f58: d014 beq.n 8002f84 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002f5a: f7fe f8a3 bl 80010a4 + 8002f5e: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002f60: e00a b.n 8002f78 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8002f62: f7fe f89f bl 80010a4 + 8002f66: 4602 mov r2, r0 + 8002f68: 693b ldr r3, [r7, #16] + 8002f6a: 1ad3 subs r3, r2, r3 + 8002f6c: f241 3288 movw r2, #5000 ; 0x1388 + 8002f70: 4293 cmp r3, r2 + 8002f72: d901 bls.n 8002f78 + { + return HAL_TIMEOUT; + 8002f74: 2303 movs r3, #3 + 8002f76: e036 b.n 8002fe6 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002f78: 4b1d ldr r3, [pc, #116] ; (8002ff0 ) + 8002f7a: 6a1b ldr r3, [r3, #32] + 8002f7c: f003 0302 and.w r3, r3, #2 + 8002f80: 2b00 cmp r3, #0 + 8002f82: d0ee beq.n 8002f62 + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8002f84: 4b1a ldr r3, [pc, #104] ; (8002ff0 ) + 8002f86: 6a1b ldr r3, [r3, #32] + 8002f88: f423 7240 bic.w r2, r3, #768 ; 0x300 + 8002f8c: 687b ldr r3, [r7, #4] + 8002f8e: 685b ldr r3, [r3, #4] + 8002f90: 4917 ldr r1, [pc, #92] ; (8002ff0 ) + 8002f92: 4313 orrs r3, r2 + 8002f94: 620b str r3, [r1, #32] + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + 8002f96: 7dfb ldrb r3, [r7, #23] + 8002f98: 2b01 cmp r3, #1 + 8002f9a: d105 bne.n 8002fa8 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8002f9c: 4b14 ldr r3, [pc, #80] ; (8002ff0 ) + 8002f9e: 69db ldr r3, [r3, #28] + 8002fa0: 4a13 ldr r2, [pc, #76] ; (8002ff0 ) + 8002fa2: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8002fa6: 61d3 str r3, [r2, #28] + } + } + + /*------------------------------ ADC clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 8002fa8: 687b ldr r3, [r7, #4] + 8002faa: 681b ldr r3, [r3, #0] + 8002fac: f003 0302 and.w r3, r3, #2 + 8002fb0: 2b00 cmp r3, #0 + 8002fb2: d008 beq.n 8002fc6 + { + /* Check the parameters */ + assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 8002fb4: 4b0e ldr r3, [pc, #56] ; (8002ff0 ) + 8002fb6: 685b ldr r3, [r3, #4] + 8002fb8: f423 4240 bic.w r2, r3, #49152 ; 0xc000 + 8002fbc: 687b ldr r3, [r7, #4] + 8002fbe: 689b ldr r3, [r3, #8] + 8002fc0: 490b ldr r1, [pc, #44] ; (8002ff0 ) + 8002fc2: 4313 orrs r3, r2 + 8002fc4: 604b str r3, [r1, #4] + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + /*------------------------------ USB clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + 8002fc6: 687b ldr r3, [r7, #4] + 8002fc8: 681b ldr r3, [r3, #0] + 8002fca: f003 0310 and.w r3, r3, #16 + 8002fce: 2b00 cmp r3, #0 + 8002fd0: d008 beq.n 8002fe4 + { + /* Check the parameters */ + assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + 8002fd2: 4b07 ldr r3, [pc, #28] ; (8002ff0 ) + 8002fd4: 685b ldr r3, [r3, #4] + 8002fd6: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 + 8002fda: 687b ldr r3, [r7, #4] + 8002fdc: 68db ldr r3, [r3, #12] + 8002fde: 4904 ldr r1, [pc, #16] ; (8002ff0 ) + 8002fe0: 4313 orrs r3, r2 + 8002fe2: 604b str r3, [r1, #4] + } +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + + return HAL_OK; + 8002fe4: 2300 movs r3, #0 +} + 8002fe6: 4618 mov r0, r3 + 8002fe8: 3718 adds r7, #24 + 8002fea: 46bd mov sp, r7 + 8002fec: bd80 pop {r7, pc} + 8002fee: bf00 nop + 8002ff0: 40021000 .word 0x40021000 + 8002ff4: 40007000 .word 0x40007000 + 8002ff8: 42420440 .word 0x42420440 + +08002ffc : + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + 8002ffc: b590 push {r4, r7, lr} + 8002ffe: b08d sub sp, #52 ; 0x34 + 8003000: af00 add r7, sp, #0 + 8003002: 6078 str r0, [r7, #4] + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; + uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; +#endif /* STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ + defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; + 8003004: 4b55 ldr r3, [pc, #340] ; (800315c ) + 8003006: f107 040c add.w r4, r7, #12 + 800300a: cb0f ldmia r3, {r0, r1, r2, r3} + 800300c: e884 000f stmia.w r4, {r0, r1, r2, r3} + const uint8_t aPredivFactorTable[2] = {1, 2}; + 8003010: 4b53 ldr r3, [pc, #332] ; (8003160 ) + 8003012: 881b ldrh r3, [r3, #0] + 8003014: 813b strh r3, [r7, #8] + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; + 8003016: 2300 movs r3, #0 + 8003018: 627b str r3, [r7, #36] ; 0x24 + 800301a: 2300 movs r3, #0 + 800301c: 62fb str r3, [r7, #44] ; 0x2c + 800301e: 2300 movs r3, #0 + 8003020: 623b str r3, [r7, #32] +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + uint32_t temp_reg = 0U, frequency = 0U; + 8003022: 2300 movs r3, #0 + 8003024: 61fb str r3, [r7, #28] + 8003026: 2300 movs r3, #0 + 8003028: 62bb str r3, [r7, #40] ; 0x28 + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + 800302a: 687b ldr r3, [r7, #4] + 800302c: 2b02 cmp r3, #2 + 800302e: d07f beq.n 8003130 + 8003030: 2b10 cmp r3, #16 + 8003032: d002 beq.n 800303a + 8003034: 2b01 cmp r3, #1 + 8003036: d048 beq.n 80030ca + frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); + break; + } + default: + { + break; + 8003038: e08b b.n 8003152 + temp_reg = RCC->CFGR; + 800303a: 4b4a ldr r3, [pc, #296] ; (8003164 ) + 800303c: 685b ldr r3, [r3, #4] + 800303e: 61fb str r3, [r7, #28] + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) + 8003040: 4b48 ldr r3, [pc, #288] ; (8003164 ) + 8003042: 681b ldr r3, [r3, #0] + 8003044: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8003048: 2b00 cmp r3, #0 + 800304a: d07f beq.n 800314c + pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + 800304c: 69fb ldr r3, [r7, #28] + 800304e: 0c9b lsrs r3, r3, #18 + 8003050: f003 030f and.w r3, r3, #15 + 8003054: f107 0230 add.w r2, r7, #48 ; 0x30 + 8003058: 4413 add r3, r2 + 800305a: f813 3c24 ldrb.w r3, [r3, #-36] + 800305e: 623b str r3, [r7, #32] + if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + 8003060: 69fb ldr r3, [r7, #28] + 8003062: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8003066: 2b00 cmp r3, #0 + 8003068: d018 beq.n 800309c + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; + 800306a: 4b3e ldr r3, [pc, #248] ; (8003164 ) + 800306c: 685b ldr r3, [r3, #4] + 800306e: 0c5b lsrs r3, r3, #17 + 8003070: f003 0301 and.w r3, r3, #1 + 8003074: f107 0230 add.w r2, r7, #48 ; 0x30 + 8003078: 4413 add r3, r2 + 800307a: f813 3c28 ldrb.w r3, [r3, #-40] + 800307e: 627b str r3, [r7, #36] ; 0x24 + if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + 8003080: 69fb ldr r3, [r7, #28] + 8003082: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8003086: 2b00 cmp r3, #0 + 8003088: d00d beq.n 80030a6 + pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); + 800308a: 4a37 ldr r2, [pc, #220] ; (8003168 ) + 800308c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800308e: fbb2 f2f3 udiv r2, r2, r3 + 8003092: 6a3b ldr r3, [r7, #32] + 8003094: fb02 f303 mul.w r3, r2, r3 + 8003098: 62fb str r3, [r7, #44] ; 0x2c + 800309a: e004 b.n 80030a6 + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + 800309c: 6a3b ldr r3, [r7, #32] + 800309e: 4a33 ldr r2, [pc, #204] ; (800316c ) + 80030a0: fb02 f303 mul.w r3, r2, r3 + 80030a4: 62fb str r3, [r7, #44] ; 0x2c + if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) + 80030a6: 4b2f ldr r3, [pc, #188] ; (8003164 ) + 80030a8: 685b ldr r3, [r3, #4] + 80030aa: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 80030ae: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 80030b2: d102 bne.n 80030ba + frequency = pllclk; + 80030b4: 6afb ldr r3, [r7, #44] ; 0x2c + 80030b6: 62bb str r3, [r7, #40] ; 0x28 + break; + 80030b8: e048 b.n 800314c + frequency = (pllclk * 2) / 3; + 80030ba: 6afb ldr r3, [r7, #44] ; 0x2c + 80030bc: 005b lsls r3, r3, #1 + 80030be: 4a2c ldr r2, [pc, #176] ; (8003170 ) + 80030c0: fba2 2303 umull r2, r3, r2, r3 + 80030c4: 085b lsrs r3, r3, #1 + 80030c6: 62bb str r3, [r7, #40] ; 0x28 + break; + 80030c8: e040 b.n 800314c + temp_reg = RCC->BDCR; + 80030ca: 4b26 ldr r3, [pc, #152] ; (8003164 ) + 80030cc: 6a1b ldr r3, [r3, #32] + 80030ce: 61fb str r3, [r7, #28] + if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) + 80030d0: 69fb ldr r3, [r7, #28] + 80030d2: f403 7340 and.w r3, r3, #768 ; 0x300 + 80030d6: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 80030da: d108 bne.n 80030ee + 80030dc: 69fb ldr r3, [r7, #28] + 80030de: f003 0302 and.w r3, r3, #2 + 80030e2: 2b00 cmp r3, #0 + 80030e4: d003 beq.n 80030ee + frequency = LSE_VALUE; + 80030e6: f44f 4300 mov.w r3, #32768 ; 0x8000 + 80030ea: 62bb str r3, [r7, #40] ; 0x28 + 80030ec: e01f b.n 800312e + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + 80030ee: 69fb ldr r3, [r7, #28] + 80030f0: f403 7340 and.w r3, r3, #768 ; 0x300 + 80030f4: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 80030f8: d109 bne.n 800310e + 80030fa: 4b1a ldr r3, [pc, #104] ; (8003164 ) + 80030fc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80030fe: f003 0302 and.w r3, r3, #2 + 8003102: 2b00 cmp r3, #0 + 8003104: d003 beq.n 800310e + frequency = LSI_VALUE; + 8003106: f649 4340 movw r3, #40000 ; 0x9c40 + 800310a: 62bb str r3, [r7, #40] ; 0x28 + 800310c: e00f b.n 800312e + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + 800310e: 69fb ldr r3, [r7, #28] + 8003110: f403 7340 and.w r3, r3, #768 ; 0x300 + 8003114: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8003118: d11a bne.n 8003150 + 800311a: 4b12 ldr r3, [pc, #72] ; (8003164 ) + 800311c: 681b ldr r3, [r3, #0] + 800311e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8003122: 2b00 cmp r3, #0 + 8003124: d014 beq.n 8003150 + frequency = HSE_VALUE / 128U; + 8003126: f24f 4324 movw r3, #62500 ; 0xf424 + 800312a: 62bb str r3, [r7, #40] ; 0x28 + break; + 800312c: e010 b.n 8003150 + 800312e: e00f b.n 8003150 + frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); + 8003130: f7ff fe7c bl 8002e2c + 8003134: 4602 mov r2, r0 + 8003136: 4b0b ldr r3, [pc, #44] ; (8003164 ) + 8003138: 685b ldr r3, [r3, #4] + 800313a: 0b9b lsrs r3, r3, #14 + 800313c: f003 0303 and.w r3, r3, #3 + 8003140: 3301 adds r3, #1 + 8003142: 005b lsls r3, r3, #1 + 8003144: fbb2 f3f3 udiv r3, r2, r3 + 8003148: 62bb str r3, [r7, #40] ; 0x28 + break; + 800314a: e002 b.n 8003152 + break; + 800314c: bf00 nop + 800314e: e000 b.n 8003152 + break; + 8003150: bf00 nop + } + } + return (frequency); + 8003152: 6abb ldr r3, [r7, #40] ; 0x28 +} + 8003154: 4618 mov r0, r3 + 8003156: 3734 adds r7, #52 ; 0x34 + 8003158: 46bd mov sp, r7 + 800315a: bd90 pop {r4, r7, pc} + 800315c: 0800c654 .word 0x0800c654 + 8003160: 0800c664 .word 0x0800c664 + 8003164: 40021000 .word 0x40021000 + 8003168: 007a1200 .word 0x007a1200 + 800316c: 003d0900 .word 0x003d0900 + 8003170: aaaaaaab .word 0xaaaaaaab + +08003174 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + 8003174: b580 push {r7, lr} + 8003176: b084 sub sp, #16 + 8003178: af00 add r7, sp, #0 + 800317a: 6078 str r0, [r7, #4] + uint32_t prescaler = 0U; + 800317c: 2300 movs r3, #0 + 800317e: 60fb str r3, [r7, #12] + /* Check input parameters */ + if (hrtc == NULL) + 8003180: 687b ldr r3, [r7, #4] + 8003182: 2b00 cmp r3, #0 + 8003184: d101 bne.n 800318a + { + return HAL_ERROR; + 8003186: 2301 movs r3, #1 + 8003188: e084 b.n 8003294 + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + 800318a: 687b ldr r3, [r7, #4] + 800318c: 7c5b ldrb r3, [r3, #17] + 800318e: b2db uxtb r3, r3 + 8003190: 2b00 cmp r3, #0 + 8003192: d105 bne.n 80031a0 + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + 8003194: 687b ldr r3, [r7, #4] + 8003196: 2200 movs r2, #0 + 8003198: 741a strb r2, [r3, #16] + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + 800319a: 6878 ldr r0, [r7, #4] + 800319c: f006 ff4c bl 800a038 + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + 80031a0: 687b ldr r3, [r7, #4] + 80031a2: 2202 movs r2, #2 + 80031a4: 745a strb r2, [r3, #17] + + /* Waiting for synchro */ + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 80031a6: 6878 ldr r0, [r7, #4] + 80031a8: f000 faa0 bl 80036ec + 80031ac: 4603 mov r3, r0 + 80031ae: 2b00 cmp r3, #0 + 80031b0: d004 beq.n 80031bc + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 80031b2: 687b ldr r3, [r7, #4] + 80031b4: 2204 movs r2, #4 + 80031b6: 745a strb r2, [r3, #17] + + return HAL_ERROR; + 80031b8: 2301 movs r3, #1 + 80031ba: e06b b.n 8003294 + } + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + 80031bc: 6878 ldr r0, [r7, #4] + 80031be: f000 fb59 bl 8003874 + 80031c2: 4603 mov r3, r0 + 80031c4: 2b00 cmp r3, #0 + 80031c6: d004 beq.n 80031d2 + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 80031c8: 687b ldr r3, [r7, #4] + 80031ca: 2204 movs r2, #4 + 80031cc: 745a strb r2, [r3, #17] + + return HAL_ERROR; + 80031ce: 2301 movs r3, #1 + 80031d0: e060 b.n 8003294 + } + else + { + /* Clear Flags Bits */ + CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); + 80031d2: 687b ldr r3, [r7, #4] + 80031d4: 681b ldr r3, [r3, #0] + 80031d6: 685a ldr r2, [r3, #4] + 80031d8: 687b ldr r3, [r7, #4] + 80031da: 681b ldr r3, [r3, #0] + 80031dc: f022 0207 bic.w r2, r2, #7 + 80031e0: 605a str r2, [r3, #4] + + if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) + 80031e2: 687b ldr r3, [r7, #4] + 80031e4: 689b ldr r3, [r3, #8] + 80031e6: 2b00 cmp r3, #0 + 80031e8: d005 beq.n 80031f6 + { + /* Disable the selected Tamper pin */ + CLEAR_BIT(BKP->CR, BKP_CR_TPE); + 80031ea: 4b2c ldr r3, [pc, #176] ; (800329c ) + 80031ec: 6b1b ldr r3, [r3, #48] ; 0x30 + 80031ee: 4a2b ldr r2, [pc, #172] ; (800329c ) + 80031f0: f023 0301 bic.w r3, r3, #1 + 80031f4: 6313 str r3, [r2, #48] ; 0x30 + } + + /* Set the signal which will be routed to RTC Tamper pin*/ + MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); + 80031f6: 4b29 ldr r3, [pc, #164] ; (800329c ) + 80031f8: 6adb ldr r3, [r3, #44] ; 0x2c + 80031fa: f423 7260 bic.w r2, r3, #896 ; 0x380 + 80031fe: 687b ldr r3, [r7, #4] + 8003200: 689b ldr r3, [r3, #8] + 8003202: 4926 ldr r1, [pc, #152] ; (800329c ) + 8003204: 4313 orrs r3, r2 + 8003206: 62cb str r3, [r1, #44] ; 0x2c + + if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) + 8003208: 687b ldr r3, [r7, #4] + 800320a: 685b ldr r3, [r3, #4] + 800320c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8003210: d003 beq.n 800321a + { + /* RTC Prescaler provided directly by end-user*/ + prescaler = hrtc->Init.AsynchPrediv; + 8003212: 687b ldr r3, [r7, #4] + 8003214: 685b ldr r3, [r3, #4] + 8003216: 60fb str r3, [r7, #12] + 8003218: e00e b.n 8003238 + } + else + { + /* RTC Prescaler will be automatically calculated to get 1 second timebase */ + /* Get the RTCCLK frequency */ + prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); + 800321a: 2001 movs r0, #1 + 800321c: f7ff feee bl 8002ffc + 8003220: 60f8 str r0, [r7, #12] + + /* Check that RTC clock is enabled*/ + if (prescaler == 0U) + 8003222: 68fb ldr r3, [r7, #12] + 8003224: 2b00 cmp r3, #0 + 8003226: d104 bne.n 8003232 + { + /* Should not happen. Frequency is not available*/ + hrtc->State = HAL_RTC_STATE_ERROR; + 8003228: 687b ldr r3, [r7, #4] + 800322a: 2204 movs r2, #4 + 800322c: 745a strb r2, [r3, #17] + return HAL_ERROR; + 800322e: 2301 movs r3, #1 + 8003230: e030 b.n 8003294 + } + else + { + /* RTC period = RTCCLK/(RTC_PR + 1) */ + prescaler = prescaler - 1U; + 8003232: 68fb ldr r3, [r7, #12] + 8003234: 3b01 subs r3, #1 + 8003236: 60fb str r3, [r7, #12] + } + } + + /* Configure the RTC_PRLH / RTC_PRLL */ + MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U)); + 8003238: 687b ldr r3, [r7, #4] + 800323a: 681b ldr r3, [r3, #0] + 800323c: 689b ldr r3, [r3, #8] + 800323e: f023 010f bic.w r1, r3, #15 + 8003242: 68fb ldr r3, [r7, #12] + 8003244: 0c1a lsrs r2, r3, #16 + 8003246: 687b ldr r3, [r7, #4] + 8003248: 681b ldr r3, [r3, #0] + 800324a: 430a orrs r2, r1 + 800324c: 609a str r2, [r3, #8] + MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL)); + 800324e: 687b ldr r3, [r7, #4] + 8003250: 681b ldr r3, [r3, #0] + 8003252: 68db ldr r3, [r3, #12] + 8003254: 0c1b lsrs r3, r3, #16 + 8003256: 041b lsls r3, r3, #16 + 8003258: 68fa ldr r2, [r7, #12] + 800325a: b291 uxth r1, r2 + 800325c: 687a ldr r2, [r7, #4] + 800325e: 6812 ldr r2, [r2, #0] + 8003260: 430b orrs r3, r1 + 8003262: 60d3 str r3, [r2, #12] + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + 8003264: 6878 ldr r0, [r7, #4] + 8003266: f000 fb2d bl 80038c4 + 800326a: 4603 mov r3, r0 + 800326c: 2b00 cmp r3, #0 + 800326e: d004 beq.n 800327a + { + hrtc->State = HAL_RTC_STATE_ERROR; + 8003270: 687b ldr r3, [r7, #4] + 8003272: 2204 movs r2, #4 + 8003274: 745a strb r2, [r3, #17] + + return HAL_ERROR; + 8003276: 2301 movs r3, #1 + 8003278: e00c b.n 8003294 + } + + /* Initialize date to 1st of January 2000 */ + hrtc->DateToUpdate.Year = 0x00U; + 800327a: 687b ldr r3, [r7, #4] + 800327c: 2200 movs r2, #0 + 800327e: 73da strb r2, [r3, #15] + hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; + 8003280: 687b ldr r3, [r7, #4] + 8003282: 2201 movs r2, #1 + 8003284: 735a strb r2, [r3, #13] + hrtc->DateToUpdate.Date = 0x01U; + 8003286: 687b ldr r3, [r7, #4] + 8003288: 2201 movs r2, #1 + 800328a: 739a strb r2, [r3, #14] + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 800328c: 687b ldr r3, [r7, #4] + 800328e: 2201 movs r2, #1 + 8003290: 745a strb r2, [r3, #17] + + return HAL_OK; + 8003292: 2300 movs r3, #0 + } +} + 8003294: 4618 mov r0, r3 + 8003296: 3710 adds r7, #16 + 8003298: 46bd mov sp, r7 + 800329a: bd80 pop {r7, pc} + 800329c: 40006c00 .word 0x40006c00 + +080032a0 : + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + 80032a0: b590 push {r4, r7, lr} + 80032a2: b087 sub sp, #28 + 80032a4: af00 add r7, sp, #0 + 80032a6: 60f8 str r0, [r7, #12] + 80032a8: 60b9 str r1, [r7, #8] + 80032aa: 607a str r2, [r7, #4] + uint32_t counter_time = 0U, counter_alarm = 0U; + 80032ac: 2300 movs r3, #0 + 80032ae: 617b str r3, [r7, #20] + 80032b0: 2300 movs r3, #0 + 80032b2: 613b str r3, [r7, #16] + + /* Check input parameters */ + if ((hrtc == NULL) || (sTime == NULL)) + 80032b4: 68fb ldr r3, [r7, #12] + 80032b6: 2b00 cmp r3, #0 + 80032b8: d002 beq.n 80032c0 + 80032ba: 68bb ldr r3, [r7, #8] + 80032bc: 2b00 cmp r3, #0 + 80032be: d101 bne.n 80032c4 + { + return HAL_ERROR; + 80032c0: 2301 movs r3, #1 + 80032c2: e080 b.n 80033c6 + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 80032c4: 68fb ldr r3, [r7, #12] + 80032c6: 7c1b ldrb r3, [r3, #16] + 80032c8: 2b01 cmp r3, #1 + 80032ca: d101 bne.n 80032d0 + 80032cc: 2302 movs r3, #2 + 80032ce: e07a b.n 80033c6 + 80032d0: 68fb ldr r3, [r7, #12] + 80032d2: 2201 movs r2, #1 + 80032d4: 741a strb r2, [r3, #16] + + hrtc->State = HAL_RTC_STATE_BUSY; + 80032d6: 68fb ldr r3, [r7, #12] + 80032d8: 2202 movs r2, #2 + 80032da: 745a strb r2, [r3, #17] + + if (Format == RTC_FORMAT_BIN) + 80032dc: 687b ldr r3, [r7, #4] + 80032de: 2b00 cmp r3, #0 + 80032e0: d113 bne.n 800330a + { + assert_param(IS_RTC_HOUR24(sTime->Hours)); + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \ + 80032e2: 68bb ldr r3, [r7, #8] + 80032e4: 781b ldrb r3, [r3, #0] + 80032e6: 461a mov r2, r3 + 80032e8: f44f 6361 mov.w r3, #3600 ; 0xe10 + 80032ec: fb03 f202 mul.w r2, r3, r2 + ((uint32_t)sTime->Minutes * 60U) + \ + 80032f0: 68bb ldr r3, [r7, #8] + 80032f2: 785b ldrb r3, [r3, #1] + 80032f4: 4619 mov r1, r3 + 80032f6: 460b mov r3, r1 + 80032f8: 011b lsls r3, r3, #4 + 80032fa: 1a5b subs r3, r3, r1 + 80032fc: 009b lsls r3, r3, #2 + counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \ + 80032fe: 4413 add r3, r2 + ((uint32_t)sTime->Seconds)); + 8003300: 68ba ldr r2, [r7, #8] + 8003302: 7892 ldrb r2, [r2, #2] + counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \ + 8003304: 4413 add r3, r2 + 8003306: 617b str r3, [r7, #20] + 8003308: e01e b.n 8003348 + { + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + + counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \ + 800330a: 68bb ldr r3, [r7, #8] + 800330c: 781b ldrb r3, [r3, #0] + 800330e: 4618 mov r0, r3 + 8003310: f000 fb1d bl 800394e + 8003314: 4603 mov r3, r0 + 8003316: 461a mov r2, r3 + 8003318: f44f 6361 mov.w r3, #3600 ; 0xe10 + 800331c: fb03 f402 mul.w r4, r3, r2 + ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60U) + \ + 8003320: 68bb ldr r3, [r7, #8] + 8003322: 785b ldrb r3, [r3, #1] + 8003324: 4618 mov r0, r3 + 8003326: f000 fb12 bl 800394e + 800332a: 4603 mov r3, r0 + 800332c: 461a mov r2, r3 + 800332e: 4613 mov r3, r2 + 8003330: 011b lsls r3, r3, #4 + 8003332: 1a9b subs r3, r3, r2 + 8003334: 009b lsls r3, r3, #2 + counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \ + 8003336: 441c add r4, r3 + ((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds)))); + 8003338: 68bb ldr r3, [r7, #8] + 800333a: 789b ldrb r3, [r3, #2] + 800333c: 4618 mov r0, r3 + 800333e: f000 fb06 bl 800394e + 8003342: 4603 mov r3, r0 + counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \ + 8003344: 4423 add r3, r4 + 8003346: 617b str r3, [r7, #20] + } + + /* Write time counter in RTC registers */ + if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) + 8003348: 6979 ldr r1, [r7, #20] + 800334a: 68f8 ldr r0, [r7, #12] + 800334c: f000 fa2b bl 80037a6 + 8003350: 4603 mov r3, r0 + 8003352: 2b00 cmp r3, #0 + 8003354: d007 beq.n 8003366 + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 8003356: 68fb ldr r3, [r7, #12] + 8003358: 2204 movs r2, #4 + 800335a: 745a strb r2, [r3, #17] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800335c: 68fb ldr r3, [r7, #12] + 800335e: 2200 movs r2, #0 + 8003360: 741a strb r2, [r3, #16] + + return HAL_ERROR; + 8003362: 2301 movs r3, #1 + 8003364: e02f b.n 80033c6 + } + else + { + /* Clear Second and overflow flags */ + CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW)); + 8003366: 68fb ldr r3, [r7, #12] + 8003368: 681b ldr r3, [r3, #0] + 800336a: 685a ldr r2, [r3, #4] + 800336c: 68fb ldr r3, [r7, #12] + 800336e: 681b ldr r3, [r3, #0] + 8003370: f022 0205 bic.w r2, r2, #5 + 8003374: 605a str r2, [r3, #4] + + /* Read current Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + 8003376: 68f8 ldr r0, [r7, #12] + 8003378: f000 fa3c bl 80037f4 + 800337c: 6138 str r0, [r7, #16] + + /* Set again alarm to match with new time if enabled */ + if (counter_alarm != RTC_ALARM_RESETVALUE) + 800337e: 693b ldr r3, [r7, #16] + 8003380: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8003384: d018 beq.n 80033b8 + { + if (counter_alarm < counter_time) + 8003386: 693a ldr r2, [r7, #16] + 8003388: 697b ldr r3, [r7, #20] + 800338a: 429a cmp r2, r3 + 800338c: d214 bcs.n 80033b8 + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + 800338e: 693b ldr r3, [r7, #16] + 8003390: f503 33a8 add.w r3, r3, #86016 ; 0x15000 + 8003394: f503 73c0 add.w r3, r3, #384 ; 0x180 + 8003398: 613b str r3, [r7, #16] + + /* Write new Alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + 800339a: 6939 ldr r1, [r7, #16] + 800339c: 68f8 ldr r0, [r7, #12] + 800339e: f000 fa42 bl 8003826 + 80033a2: 4603 mov r3, r0 + 80033a4: 2b00 cmp r3, #0 + 80033a6: d007 beq.n 80033b8 + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 80033a8: 68fb ldr r3, [r7, #12] + 80033aa: 2204 movs r2, #4 + 80033ac: 745a strb r2, [r3, #17] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80033ae: 68fb ldr r3, [r7, #12] + 80033b0: 2200 movs r2, #0 + 80033b2: 741a strb r2, [r3, #16] + + return HAL_ERROR; + 80033b4: 2301 movs r3, #1 + 80033b6: e006 b.n 80033c6 + } + } + } + + hrtc->State = HAL_RTC_STATE_READY; + 80033b8: 68fb ldr r3, [r7, #12] + 80033ba: 2201 movs r2, #1 + 80033bc: 745a strb r2, [r3, #17] + + __HAL_UNLOCK(hrtc); + 80033be: 68fb ldr r3, [r7, #12] + 80033c0: 2200 movs r2, #0 + 80033c2: 741a strb r2, [r3, #16] + + return HAL_OK; + 80033c4: 2300 movs r3, #0 + } +} + 80033c6: 4618 mov r0, r3 + 80033c8: 371c adds r7, #28 + 80033ca: 46bd mov sp, r7 + 80033cc: bd90 pop {r4, r7, pc} + ... + +080033d0 : + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + 80033d0: b580 push {r7, lr} + 80033d2: b088 sub sp, #32 + 80033d4: af00 add r7, sp, #0 + 80033d6: 60f8 str r0, [r7, #12] + 80033d8: 60b9 str r1, [r7, #8] + 80033da: 607a str r2, [r7, #4] + uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U; + 80033dc: 2300 movs r3, #0 + 80033de: 61bb str r3, [r7, #24] + 80033e0: 2300 movs r3, #0 + 80033e2: 61fb str r3, [r7, #28] + 80033e4: 2300 movs r3, #0 + 80033e6: 617b str r3, [r7, #20] + 80033e8: 2300 movs r3, #0 + 80033ea: 613b str r3, [r7, #16] + + /* Check input parameters */ + if ((hrtc == NULL) || (sTime == NULL)) + 80033ec: 68fb ldr r3, [r7, #12] + 80033ee: 2b00 cmp r3, #0 + 80033f0: d002 beq.n 80033f8 + 80033f2: 68bb ldr r3, [r7, #8] + 80033f4: 2b00 cmp r3, #0 + 80033f6: d101 bne.n 80033fc + { + return HAL_ERROR; + 80033f8: 2301 movs r3, #1 + 80033fa: e0b5 b.n 8003568 + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Check if counter overflow occurred */ + if (__HAL_RTC_OVERFLOW_GET_FLAG(hrtc, RTC_FLAG_OW)) + 80033fc: 68fb ldr r3, [r7, #12] + 80033fe: 681b ldr r3, [r3, #0] + 8003400: 685b ldr r3, [r3, #4] + 8003402: f003 0304 and.w r3, r3, #4 + 8003406: 2b00 cmp r3, #0 + 8003408: d001 beq.n 800340e + { + return HAL_ERROR; + 800340a: 2301 movs r3, #1 + 800340c: e0ac b.n 8003568 + } + + /* Read the time counter*/ + counter_time = RTC_ReadTimeCounter(hrtc); + 800340e: 68f8 ldr r0, [r7, #12] + 8003410: f000 f999 bl 8003746 + 8003414: 61b8 str r0, [r7, #24] + + /* Fill the structure fields with the read parameters */ + hours = counter_time / 3600U; + 8003416: 69bb ldr r3, [r7, #24] + 8003418: 4a55 ldr r2, [pc, #340] ; (8003570 ) + 800341a: fba2 2303 umull r2, r3, r2, r3 + 800341e: 0adb lsrs r3, r3, #11 + 8003420: 613b str r3, [r7, #16] + sTime->Minutes = (uint8_t)((counter_time % 3600U) / 60U); + 8003422: 69ba ldr r2, [r7, #24] + 8003424: 4b52 ldr r3, [pc, #328] ; (8003570 ) + 8003426: fba3 1302 umull r1, r3, r3, r2 + 800342a: 0adb lsrs r3, r3, #11 + 800342c: f44f 6161 mov.w r1, #3600 ; 0xe10 + 8003430: fb01 f303 mul.w r3, r1, r3 + 8003434: 1ad3 subs r3, r2, r3 + 8003436: 4a4f ldr r2, [pc, #316] ; (8003574 ) + 8003438: fba2 2303 umull r2, r3, r2, r3 + 800343c: 095b lsrs r3, r3, #5 + 800343e: b2da uxtb r2, r3 + 8003440: 68bb ldr r3, [r7, #8] + 8003442: 705a strb r2, [r3, #1] + sTime->Seconds = (uint8_t)((counter_time % 3600U) % 60U); + 8003444: 69bb ldr r3, [r7, #24] + 8003446: 4a4a ldr r2, [pc, #296] ; (8003570 ) + 8003448: fba2 1203 umull r1, r2, r2, r3 + 800344c: 0ad2 lsrs r2, r2, #11 + 800344e: f44f 6161 mov.w r1, #3600 ; 0xe10 + 8003452: fb01 f202 mul.w r2, r1, r2 + 8003456: 1a9a subs r2, r3, r2 + 8003458: 4b46 ldr r3, [pc, #280] ; (8003574 ) + 800345a: fba3 1302 umull r1, r3, r3, r2 + 800345e: 0959 lsrs r1, r3, #5 + 8003460: 460b mov r3, r1 + 8003462: 011b lsls r3, r3, #4 + 8003464: 1a5b subs r3, r3, r1 + 8003466: 009b lsls r3, r3, #2 + 8003468: 1ad1 subs r1, r2, r3 + 800346a: b2ca uxtb r2, r1 + 800346c: 68bb ldr r3, [r7, #8] + 800346e: 709a strb r2, [r3, #2] + + if (hours >= 24U) + 8003470: 693b ldr r3, [r7, #16] + 8003472: 2b17 cmp r3, #23 + 8003474: d955 bls.n 8003522 + { + /* Get number of days elapsed from last calculation */ + days_elapsed = (hours / 24U); + 8003476: 693b ldr r3, [r7, #16] + 8003478: 4a3f ldr r2, [pc, #252] ; (8003578 ) + 800347a: fba2 2303 umull r2, r3, r2, r3 + 800347e: 091b lsrs r3, r3, #4 + 8003480: 617b str r3, [r7, #20] + + /* Set Hours in RTC_TimeTypeDef structure*/ + sTime->Hours = (hours % 24U); + 8003482: 6939 ldr r1, [r7, #16] + 8003484: 4b3c ldr r3, [pc, #240] ; (8003578 ) + 8003486: fba3 2301 umull r2, r3, r3, r1 + 800348a: 091a lsrs r2, r3, #4 + 800348c: 4613 mov r3, r2 + 800348e: 005b lsls r3, r3, #1 + 8003490: 4413 add r3, r2 + 8003492: 00db lsls r3, r3, #3 + 8003494: 1aca subs r2, r1, r3 + 8003496: b2d2 uxtb r2, r2 + 8003498: 68bb ldr r3, [r7, #8] + 800349a: 701a strb r2, [r3, #0] + + /* Read Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + 800349c: 68f8 ldr r0, [r7, #12] + 800349e: f000 f9a9 bl 80037f4 + 80034a2: 61f8 str r0, [r7, #28] + + /* Calculate remaining time to reach alarm (only if set and not yet expired)*/ + if ((counter_alarm != RTC_ALARM_RESETVALUE) && (counter_alarm > counter_time)) + 80034a4: 69fb ldr r3, [r7, #28] + 80034a6: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80034aa: d008 beq.n 80034be + 80034ac: 69fa ldr r2, [r7, #28] + 80034ae: 69bb ldr r3, [r7, #24] + 80034b0: 429a cmp r2, r3 + 80034b2: d904 bls.n 80034be + { + counter_alarm -= counter_time; + 80034b4: 69fa ldr r2, [r7, #28] + 80034b6: 69bb ldr r3, [r7, #24] + 80034b8: 1ad3 subs r3, r2, r3 + 80034ba: 61fb str r3, [r7, #28] + 80034bc: e002 b.n 80034c4 + } + else + { + /* In case of counter_alarm < counter_time */ + /* Alarm expiration already occurred but alarm not deactivated */ + counter_alarm = RTC_ALARM_RESETVALUE; + 80034be: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 80034c2: 61fb str r3, [r7, #28] + } + + /* Set updated time in decreasing counter by number of days elapsed */ + counter_time -= (days_elapsed * 24U * 3600U); + 80034c4: 697b ldr r3, [r7, #20] + 80034c6: 4a2d ldr r2, [pc, #180] ; (800357c ) + 80034c8: fb02 f303 mul.w r3, r2, r3 + 80034cc: 69ba ldr r2, [r7, #24] + 80034ce: 1ad3 subs r3, r2, r3 + 80034d0: 61bb str r3, [r7, #24] + + /* Write time counter in RTC registers */ + if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) + 80034d2: 69b9 ldr r1, [r7, #24] + 80034d4: 68f8 ldr r0, [r7, #12] + 80034d6: f000 f966 bl 80037a6 + 80034da: 4603 mov r3, r0 + 80034dc: 2b00 cmp r3, #0 + 80034de: d001 beq.n 80034e4 + { + return HAL_ERROR; + 80034e0: 2301 movs r3, #1 + 80034e2: e041 b.n 8003568 + } + + /* Set updated alarm to be set */ + if (counter_alarm != RTC_ALARM_RESETVALUE) + 80034e4: 69fb ldr r3, [r7, #28] + 80034e6: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80034ea: d00c beq.n 8003506 + { + counter_alarm += counter_time; + 80034ec: 69fa ldr r2, [r7, #28] + 80034ee: 69bb ldr r3, [r7, #24] + 80034f0: 4413 add r3, r2 + 80034f2: 61fb str r3, [r7, #28] + + /* Write time counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + 80034f4: 69f9 ldr r1, [r7, #28] + 80034f6: 68f8 ldr r0, [r7, #12] + 80034f8: f000 f995 bl 8003826 + 80034fc: 4603 mov r3, r0 + 80034fe: 2b00 cmp r3, #0 + 8003500: d00a beq.n 8003518 + { + return HAL_ERROR; + 8003502: 2301 movs r3, #1 + 8003504: e030 b.n 8003568 + } + } + else + { + /* Alarm already occurred. Set it to reset values to avoid unexpected expiration */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + 8003506: 69f9 ldr r1, [r7, #28] + 8003508: 68f8 ldr r0, [r7, #12] + 800350a: f000 f98c bl 8003826 + 800350e: 4603 mov r3, r0 + 8003510: 2b00 cmp r3, #0 + 8003512: d001 beq.n 8003518 + { + return HAL_ERROR; + 8003514: 2301 movs r3, #1 + 8003516: e027 b.n 8003568 + } + } + + /* Update date */ + RTC_DateUpdate(hrtc, days_elapsed); + 8003518: 6979 ldr r1, [r7, #20] + 800351a: 68f8 ldr r0, [r7, #12] + 800351c: f000 fa34 bl 8003988 + 8003520: e003 b.n 800352a + } + else + { + sTime->Hours = hours; + 8003522: 693b ldr r3, [r7, #16] + 8003524: b2da uxtb r2, r3 + 8003526: 68bb ldr r3, [r7, #8] + 8003528: 701a strb r2, [r3, #0] + } + + /* Check the input parameters format */ + if (Format != RTC_FORMAT_BIN) + 800352a: 687b ldr r3, [r7, #4] + 800352c: 2b00 cmp r3, #0 + 800352e: d01a beq.n 8003566 + { + /* Convert the time structure parameters to BCD format */ + sTime->Hours = (uint8_t)RTC_ByteToBcd2(sTime->Hours); + 8003530: 68bb ldr r3, [r7, #8] + 8003532: 781b ldrb r3, [r3, #0] + 8003534: 4618 mov r0, r3 + 8003536: f000 f9ed bl 8003914 + 800353a: 4603 mov r3, r0 + 800353c: 461a mov r2, r3 + 800353e: 68bb ldr r3, [r7, #8] + 8003540: 701a strb r2, [r3, #0] + sTime->Minutes = (uint8_t)RTC_ByteToBcd2(sTime->Minutes); + 8003542: 68bb ldr r3, [r7, #8] + 8003544: 785b ldrb r3, [r3, #1] + 8003546: 4618 mov r0, r3 + 8003548: f000 f9e4 bl 8003914 + 800354c: 4603 mov r3, r0 + 800354e: 461a mov r2, r3 + 8003550: 68bb ldr r3, [r7, #8] + 8003552: 705a strb r2, [r3, #1] + sTime->Seconds = (uint8_t)RTC_ByteToBcd2(sTime->Seconds); + 8003554: 68bb ldr r3, [r7, #8] + 8003556: 789b ldrb r3, [r3, #2] + 8003558: 4618 mov r0, r3 + 800355a: f000 f9db bl 8003914 + 800355e: 4603 mov r3, r0 + 8003560: 461a mov r2, r3 + 8003562: 68bb ldr r3, [r7, #8] + 8003564: 709a strb r2, [r3, #2] + } + + return HAL_OK; + 8003566: 2300 movs r3, #0 +} + 8003568: 4618 mov r0, r3 + 800356a: 3720 adds r7, #32 + 800356c: 46bd mov sp, r7 + 800356e: bd80 pop {r7, pc} + 8003570: 91a2b3c5 .word 0x91a2b3c5 + 8003574: 88888889 .word 0x88888889 + 8003578: aaaaaaab .word 0xaaaaaaab + 800357c: 00015180 .word 0x00015180 + +08003580 : + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + 8003580: b580 push {r7, lr} + 8003582: b088 sub sp, #32 + 8003584: af00 add r7, sp, #0 + 8003586: 60f8 str r0, [r7, #12] + 8003588: 60b9 str r1, [r7, #8] + 800358a: 607a str r2, [r7, #4] + uint32_t counter_time = 0U, counter_alarm = 0U, hours = 0U; + 800358c: 2300 movs r3, #0 + 800358e: 61fb str r3, [r7, #28] + 8003590: 2300 movs r3, #0 + 8003592: 61bb str r3, [r7, #24] + 8003594: 2300 movs r3, #0 + 8003596: 617b str r3, [r7, #20] + + /* Check input parameters */ + if ((hrtc == NULL) || (sDate == NULL)) + 8003598: 68fb ldr r3, [r7, #12] + 800359a: 2b00 cmp r3, #0 + 800359c: d002 beq.n 80035a4 + 800359e: 68bb ldr r3, [r7, #8] + 80035a0: 2b00 cmp r3, #0 + 80035a2: d101 bne.n 80035a8 + { + return HAL_ERROR; + 80035a4: 2301 movs r3, #1 + 80035a6: e097 b.n 80036d8 + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 80035a8: 68fb ldr r3, [r7, #12] + 80035aa: 7c1b ldrb r3, [r3, #16] + 80035ac: 2b01 cmp r3, #1 + 80035ae: d101 bne.n 80035b4 + 80035b0: 2302 movs r3, #2 + 80035b2: e091 b.n 80036d8 + 80035b4: 68fb ldr r3, [r7, #12] + 80035b6: 2201 movs r2, #1 + 80035b8: 741a strb r2, [r3, #16] + + hrtc->State = HAL_RTC_STATE_BUSY; + 80035ba: 68fb ldr r3, [r7, #12] + 80035bc: 2202 movs r2, #2 + 80035be: 745a strb r2, [r3, #17] + + if (Format == RTC_FORMAT_BIN) + 80035c0: 687b ldr r3, [r7, #4] + 80035c2: 2b00 cmp r3, #0 + 80035c4: d10c bne.n 80035e0 + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + /* Change the current date */ + hrtc->DateToUpdate.Year = sDate->Year; + 80035c6: 68bb ldr r3, [r7, #8] + 80035c8: 78da ldrb r2, [r3, #3] + 80035ca: 68fb ldr r3, [r7, #12] + 80035cc: 73da strb r2, [r3, #15] + hrtc->DateToUpdate.Month = sDate->Month; + 80035ce: 68bb ldr r3, [r7, #8] + 80035d0: 785a ldrb r2, [r3, #1] + 80035d2: 68fb ldr r3, [r7, #12] + 80035d4: 735a strb r2, [r3, #13] + hrtc->DateToUpdate.Date = sDate->Date; + 80035d6: 68bb ldr r3, [r7, #8] + 80035d8: 789a ldrb r2, [r3, #2] + 80035da: 68fb ldr r3, [r7, #12] + 80035dc: 739a strb r2, [r3, #14] + 80035de: e01a b.n 8003616 + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + /* Change the current date */ + hrtc->DateToUpdate.Year = RTC_Bcd2ToByte(sDate->Year); + 80035e0: 68bb ldr r3, [r7, #8] + 80035e2: 78db ldrb r3, [r3, #3] + 80035e4: 4618 mov r0, r3 + 80035e6: f000 f9b2 bl 800394e + 80035ea: 4603 mov r3, r0 + 80035ec: 461a mov r2, r3 + 80035ee: 68fb ldr r3, [r7, #12] + 80035f0: 73da strb r2, [r3, #15] + hrtc->DateToUpdate.Month = RTC_Bcd2ToByte(sDate->Month); + 80035f2: 68bb ldr r3, [r7, #8] + 80035f4: 785b ldrb r3, [r3, #1] + 80035f6: 4618 mov r0, r3 + 80035f8: f000 f9a9 bl 800394e + 80035fc: 4603 mov r3, r0 + 80035fe: 461a mov r2, r3 + 8003600: 68fb ldr r3, [r7, #12] + 8003602: 735a strb r2, [r3, #13] + hrtc->DateToUpdate.Date = RTC_Bcd2ToByte(sDate->Date); + 8003604: 68bb ldr r3, [r7, #8] + 8003606: 789b ldrb r3, [r3, #2] + 8003608: 4618 mov r0, r3 + 800360a: f000 f9a0 bl 800394e + 800360e: 4603 mov r3, r0 + 8003610: 461a mov r2, r3 + 8003612: 68fb ldr r3, [r7, #12] + 8003614: 739a strb r2, [r3, #14] + } + + /* WeekDay set by user can be ignored because automatically calculated */ + hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(hrtc->DateToUpdate.Year, hrtc->DateToUpdate.Month, hrtc->DateToUpdate.Date); + 8003616: 68fb ldr r3, [r7, #12] + 8003618: 7bdb ldrb r3, [r3, #15] + 800361a: 4618 mov r0, r3 + 800361c: 68fb ldr r3, [r7, #12] + 800361e: 7b59 ldrb r1, [r3, #13] + 8003620: 68fb ldr r3, [r7, #12] + 8003622: 7b9b ldrb r3, [r3, #14] + 8003624: 461a mov r2, r3 + 8003626: f000 fa8b bl 8003b40 + 800362a: 4603 mov r3, r0 + 800362c: 461a mov r2, r3 + 800362e: 68fb ldr r3, [r7, #12] + 8003630: 731a strb r2, [r3, #12] + sDate->WeekDay = hrtc->DateToUpdate.WeekDay; + 8003632: 68fb ldr r3, [r7, #12] + 8003634: 7b1a ldrb r2, [r3, #12] + 8003636: 68bb ldr r3, [r7, #8] + 8003638: 701a strb r2, [r3, #0] + + /* Reset time to be aligned on the same day */ + /* Read the time counter*/ + counter_time = RTC_ReadTimeCounter(hrtc); + 800363a: 68f8 ldr r0, [r7, #12] + 800363c: f000 f883 bl 8003746 + 8003640: 61f8 str r0, [r7, #28] + + /* Fill the structure fields with the read parameters */ + hours = counter_time / 3600U; + 8003642: 69fb ldr r3, [r7, #28] + 8003644: 4a26 ldr r2, [pc, #152] ; (80036e0 ) + 8003646: fba2 2303 umull r2, r3, r2, r3 + 800364a: 0adb lsrs r3, r3, #11 + 800364c: 617b str r3, [r7, #20] + if (hours > 24U) + 800364e: 697b ldr r3, [r7, #20] + 8003650: 2b18 cmp r3, #24 + 8003652: d93a bls.n 80036ca + { + /* Set updated time in decreasing counter by number of days elapsed */ + counter_time -= ((hours / 24U) * 24U * 3600U); + 8003654: 697b ldr r3, [r7, #20] + 8003656: 4a23 ldr r2, [pc, #140] ; (80036e4 ) + 8003658: fba2 2303 umull r2, r3, r2, r3 + 800365c: 091b lsrs r3, r3, #4 + 800365e: 4a22 ldr r2, [pc, #136] ; (80036e8 ) + 8003660: fb02 f303 mul.w r3, r2, r3 + 8003664: 69fa ldr r2, [r7, #28] + 8003666: 1ad3 subs r3, r2, r3 + 8003668: 61fb str r3, [r7, #28] + /* Write time counter in RTC registers */ + if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) + 800366a: 69f9 ldr r1, [r7, #28] + 800366c: 68f8 ldr r0, [r7, #12] + 800366e: f000 f89a bl 80037a6 + 8003672: 4603 mov r3, r0 + 8003674: 2b00 cmp r3, #0 + 8003676: d007 beq.n 8003688 + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 8003678: 68fb ldr r3, [r7, #12] + 800367a: 2204 movs r2, #4 + 800367c: 745a strb r2, [r3, #17] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800367e: 68fb ldr r3, [r7, #12] + 8003680: 2200 movs r2, #0 + 8003682: 741a strb r2, [r3, #16] + + return HAL_ERROR; + 8003684: 2301 movs r3, #1 + 8003686: e027 b.n 80036d8 + } + + /* Read current Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + 8003688: 68f8 ldr r0, [r7, #12] + 800368a: f000 f8b3 bl 80037f4 + 800368e: 61b8 str r0, [r7, #24] + + /* Set again alarm to match with new time if enabled */ + if (counter_alarm != RTC_ALARM_RESETVALUE) + 8003690: 69bb ldr r3, [r7, #24] + 8003692: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8003696: d018 beq.n 80036ca + { + if (counter_alarm < counter_time) + 8003698: 69ba ldr r2, [r7, #24] + 800369a: 69fb ldr r3, [r7, #28] + 800369c: 429a cmp r2, r3 + 800369e: d214 bcs.n 80036ca + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + 80036a0: 69bb ldr r3, [r7, #24] + 80036a2: f503 33a8 add.w r3, r3, #86016 ; 0x15000 + 80036a6: f503 73c0 add.w r3, r3, #384 ; 0x180 + 80036aa: 61bb str r3, [r7, #24] + + /* Write new Alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + 80036ac: 69b9 ldr r1, [r7, #24] + 80036ae: 68f8 ldr r0, [r7, #12] + 80036b0: f000 f8b9 bl 8003826 + 80036b4: 4603 mov r3, r0 + 80036b6: 2b00 cmp r3, #0 + 80036b8: d007 beq.n 80036ca + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 80036ba: 68fb ldr r3, [r7, #12] + 80036bc: 2204 movs r2, #4 + 80036be: 745a strb r2, [r3, #17] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80036c0: 68fb ldr r3, [r7, #12] + 80036c2: 2200 movs r2, #0 + 80036c4: 741a strb r2, [r3, #16] + + return HAL_ERROR; + 80036c6: 2301 movs r3, #1 + 80036c8: e006 b.n 80036d8 + } + + + } + + hrtc->State = HAL_RTC_STATE_READY ; + 80036ca: 68fb ldr r3, [r7, #12] + 80036cc: 2201 movs r2, #1 + 80036ce: 745a strb r2, [r3, #17] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80036d0: 68fb ldr r3, [r7, #12] + 80036d2: 2200 movs r2, #0 + 80036d4: 741a strb r2, [r3, #16] + + return HAL_OK; + 80036d6: 2300 movs r3, #0 +} + 80036d8: 4618 mov r0, r3 + 80036da: 3720 adds r7, #32 + 80036dc: 46bd mov sp, r7 + 80036de: bd80 pop {r7, pc} + 80036e0: 91a2b3c5 .word 0x91a2b3c5 + 80036e4: aaaaaaab .word 0xaaaaaaab + 80036e8: 00015180 .word 0x00015180 + +080036ec : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + 80036ec: b580 push {r7, lr} + 80036ee: b084 sub sp, #16 + 80036f0: af00 add r7, sp, #0 + 80036f2: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 80036f4: 2300 movs r3, #0 + 80036f6: 60fb str r3, [r7, #12] + + /* Check input parameters */ + if (hrtc == NULL) + 80036f8: 687b ldr r3, [r7, #4] + 80036fa: 2b00 cmp r3, #0 + 80036fc: d101 bne.n 8003702 + { + return HAL_ERROR; + 80036fe: 2301 movs r3, #1 + 8003700: e01d b.n 800373e + } + + /* Clear RSF flag */ + CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); + 8003702: 687b ldr r3, [r7, #4] + 8003704: 681b ldr r3, [r3, #0] + 8003706: 685a ldr r2, [r3, #4] + 8003708: 687b ldr r3, [r7, #4] + 800370a: 681b ldr r3, [r3, #0] + 800370c: f022 0208 bic.w r2, r2, #8 + 8003710: 605a str r2, [r3, #4] + + tickstart = HAL_GetTick(); + 8003712: f7fd fcc7 bl 80010a4 + 8003716: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) + 8003718: e009 b.n 800372e + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 800371a: f7fd fcc3 bl 80010a4 + 800371e: 4602 mov r2, r0 + 8003720: 68fb ldr r3, [r7, #12] + 8003722: 1ad3 subs r3, r2, r3 + 8003724: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8003728: d901 bls.n 800372e + { + return HAL_TIMEOUT; + 800372a: 2303 movs r3, #3 + 800372c: e007 b.n 800373e + while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) + 800372e: 687b ldr r3, [r7, #4] + 8003730: 681b ldr r3, [r3, #0] + 8003732: 685b ldr r3, [r3, #4] + 8003734: f003 0308 and.w r3, r3, #8 + 8003738: 2b00 cmp r3, #0 + 800373a: d0ee beq.n 800371a + } + } + + return HAL_OK; + 800373c: 2300 movs r3, #0 +} + 800373e: 4618 mov r0, r3 + 8003740: 3710 adds r7, #16 + 8003742: 46bd mov sp, r7 + 8003744: bd80 pop {r7, pc} + +08003746 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval Time counter + */ +static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc) +{ + 8003746: b480 push {r7} + 8003748: b087 sub sp, #28 + 800374a: af00 add r7, sp, #0 + 800374c: 6078 str r0, [r7, #4] + uint16_t high1 = 0U, high2 = 0U, low = 0U; + 800374e: 2300 movs r3, #0 + 8003750: 827b strh r3, [r7, #18] + 8003752: 2300 movs r3, #0 + 8003754: 823b strh r3, [r7, #16] + 8003756: 2300 movs r3, #0 + 8003758: 81fb strh r3, [r7, #14] + uint32_t timecounter = 0U; + 800375a: 2300 movs r3, #0 + 800375c: 617b str r3, [r7, #20] + + high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); + 800375e: 687b ldr r3, [r7, #4] + 8003760: 681b ldr r3, [r3, #0] + 8003762: 699b ldr r3, [r3, #24] + 8003764: 827b strh r3, [r7, #18] + low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT); + 8003766: 687b ldr r3, [r7, #4] + 8003768: 681b ldr r3, [r3, #0] + 800376a: 69db ldr r3, [r3, #28] + 800376c: 81fb strh r3, [r7, #14] + high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); + 800376e: 687b ldr r3, [r7, #4] + 8003770: 681b ldr r3, [r3, #0] + 8003772: 699b ldr r3, [r3, #24] + 8003774: 823b strh r3, [r7, #16] + + if (high1 != high2) + 8003776: 8a7a ldrh r2, [r7, #18] + 8003778: 8a3b ldrh r3, [r7, #16] + 800377a: 429a cmp r2, r3 + 800377c: d008 beq.n 8003790 + { + /* In this case the counter roll over during reading of CNTL and CNTH registers, + read again CNTL register then return the counter value */ + timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); + 800377e: 8a3b ldrh r3, [r7, #16] + 8003780: 041a lsls r2, r3, #16 + 8003782: 687b ldr r3, [r7, #4] + 8003784: 681b ldr r3, [r3, #0] + 8003786: 69db ldr r3, [r3, #28] + 8003788: b29b uxth r3, r3 + 800378a: 4313 orrs r3, r2 + 800378c: 617b str r3, [r7, #20] + 800378e: e004 b.n 800379a + } + else + { + /* No counter roll over during reading of CNTL and CNTH registers, counter + value is equal to first value of CNTL and CNTH */ + timecounter = (((uint32_t) high1 << 16U) | low); + 8003790: 8a7b ldrh r3, [r7, #18] + 8003792: 041a lsls r2, r3, #16 + 8003794: 89fb ldrh r3, [r7, #14] + 8003796: 4313 orrs r3, r2 + 8003798: 617b str r3, [r7, #20] + } + + return timecounter; + 800379a: 697b ldr r3, [r7, #20] +} + 800379c: 4618 mov r0, r3 + 800379e: 371c adds r7, #28 + 80037a0: 46bd mov sp, r7 + 80037a2: bc80 pop {r7} + 80037a4: 4770 bx lr + +080037a6 : + * the configuration information for RTC. + * @param TimeCounter: Counter to write in RTC_CNT registers + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter) +{ + 80037a6: b580 push {r7, lr} + 80037a8: b084 sub sp, #16 + 80037aa: af00 add r7, sp, #0 + 80037ac: 6078 str r0, [r7, #4] + 80037ae: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 80037b0: 2300 movs r3, #0 + 80037b2: 73fb strb r3, [r7, #15] + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + 80037b4: 6878 ldr r0, [r7, #4] + 80037b6: f000 f85d bl 8003874 + 80037ba: 4603 mov r3, r0 + 80037bc: 2b00 cmp r3, #0 + 80037be: d002 beq.n 80037c6 + { + status = HAL_ERROR; + 80037c0: 2301 movs r3, #1 + 80037c2: 73fb strb r3, [r7, #15] + 80037c4: e011 b.n 80037ea + } + else + { + /* Set RTC COUNTER MSB word */ + WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U)); + 80037c6: 687b ldr r3, [r7, #4] + 80037c8: 681b ldr r3, [r3, #0] + 80037ca: 683a ldr r2, [r7, #0] + 80037cc: 0c12 lsrs r2, r2, #16 + 80037ce: 619a str r2, [r3, #24] + /* Set RTC COUNTER LSB word */ + WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); + 80037d0: 687b ldr r3, [r7, #4] + 80037d2: 681b ldr r3, [r3, #0] + 80037d4: 683a ldr r2, [r7, #0] + 80037d6: b292 uxth r2, r2 + 80037d8: 61da str r2, [r3, #28] + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + 80037da: 6878 ldr r0, [r7, #4] + 80037dc: f000 f872 bl 80038c4 + 80037e0: 4603 mov r3, r0 + 80037e2: 2b00 cmp r3, #0 + 80037e4: d001 beq.n 80037ea + { + status = HAL_ERROR; + 80037e6: 2301 movs r3, #1 + 80037e8: 73fb strb r3, [r7, #15] + } + } + + return status; + 80037ea: 7bfb ldrb r3, [r7, #15] +} + 80037ec: 4618 mov r0, r3 + 80037ee: 3710 adds r7, #16 + 80037f0: 46bd mov sp, r7 + 80037f2: bd80 pop {r7, pc} + +080037f4 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval Time counter + */ +static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc) +{ + 80037f4: b480 push {r7} + 80037f6: b085 sub sp, #20 + 80037f8: af00 add r7, sp, #0 + 80037fa: 6078 str r0, [r7, #4] + uint16_t high1 = 0U, low = 0U; + 80037fc: 2300 movs r3, #0 + 80037fe: 81fb strh r3, [r7, #14] + 8003800: 2300 movs r3, #0 + 8003802: 81bb strh r3, [r7, #12] + + high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT); + 8003804: 687b ldr r3, [r7, #4] + 8003806: 681b ldr r3, [r3, #0] + 8003808: 6a1b ldr r3, [r3, #32] + 800380a: 81fb strh r3, [r7, #14] + low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT); + 800380c: 687b ldr r3, [r7, #4] + 800380e: 681b ldr r3, [r3, #0] + 8003810: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003812: 81bb strh r3, [r7, #12] + + return (((uint32_t) high1 << 16U) | low); + 8003814: 89fb ldrh r3, [r7, #14] + 8003816: 041a lsls r2, r3, #16 + 8003818: 89bb ldrh r3, [r7, #12] + 800381a: 4313 orrs r3, r2 +} + 800381c: 4618 mov r0, r3 + 800381e: 3714 adds r7, #20 + 8003820: 46bd mov sp, r7 + 8003822: bc80 pop {r7} + 8003824: 4770 bx lr + +08003826 : + * the configuration information for RTC. + * @param AlarmCounter: Counter to write in RTC_ALR registers + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter) +{ + 8003826: b580 push {r7, lr} + 8003828: b084 sub sp, #16 + 800382a: af00 add r7, sp, #0 + 800382c: 6078 str r0, [r7, #4] + 800382e: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8003830: 2300 movs r3, #0 + 8003832: 73fb strb r3, [r7, #15] + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + 8003834: 6878 ldr r0, [r7, #4] + 8003836: f000 f81d bl 8003874 + 800383a: 4603 mov r3, r0 + 800383c: 2b00 cmp r3, #0 + 800383e: d002 beq.n 8003846 + { + status = HAL_ERROR; + 8003840: 2301 movs r3, #1 + 8003842: 73fb strb r3, [r7, #15] + 8003844: e011 b.n 800386a + } + else + { + /* Set RTC COUNTER MSB word */ + WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U)); + 8003846: 687b ldr r3, [r7, #4] + 8003848: 681b ldr r3, [r3, #0] + 800384a: 683a ldr r2, [r7, #0] + 800384c: 0c12 lsrs r2, r2, #16 + 800384e: 621a str r2, [r3, #32] + /* Set RTC COUNTER LSB word */ + WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); + 8003850: 687b ldr r3, [r7, #4] + 8003852: 681b ldr r3, [r3, #0] + 8003854: 683a ldr r2, [r7, #0] + 8003856: b292 uxth r2, r2 + 8003858: 625a str r2, [r3, #36] ; 0x24 + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + 800385a: 6878 ldr r0, [r7, #4] + 800385c: f000 f832 bl 80038c4 + 8003860: 4603 mov r3, r0 + 8003862: 2b00 cmp r3, #0 + 8003864: d001 beq.n 800386a + { + status = HAL_ERROR; + 8003866: 2301 movs r3, #1 + 8003868: 73fb strb r3, [r7, #15] + } + } + + return status; + 800386a: 7bfb ldrb r3, [r7, #15] +} + 800386c: 4618 mov r0, r3 + 800386e: 3710 adds r7, #16 + 8003870: 46bd mov sp, r7 + 8003872: bd80 pop {r7, pc} + +08003874 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + 8003874: b580 push {r7, lr} + 8003876: b084 sub sp, #16 + 8003878: af00 add r7, sp, #0 + 800387a: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 800387c: 2300 movs r3, #0 + 800387e: 60fb str r3, [r7, #12] + + tickstart = HAL_GetTick(); + 8003880: f7fd fc10 bl 80010a4 + 8003884: 60f8 str r0, [r7, #12] + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 8003886: e009 b.n 800389c + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8003888: f7fd fc0c bl 80010a4 + 800388c: 4602 mov r2, r0 + 800388e: 68fb ldr r3, [r7, #12] + 8003890: 1ad3 subs r3, r2, r3 + 8003892: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8003896: d901 bls.n 800389c + { + return HAL_TIMEOUT; + 8003898: 2303 movs r3, #3 + 800389a: e00f b.n 80038bc + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 800389c: 687b ldr r3, [r7, #4] + 800389e: 681b ldr r3, [r3, #0] + 80038a0: 685b ldr r3, [r3, #4] + 80038a2: f003 0320 and.w r3, r3, #32 + 80038a6: 2b00 cmp r3, #0 + 80038a8: d0ee beq.n 8003888 + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 80038aa: 687b ldr r3, [r7, #4] + 80038ac: 681b ldr r3, [r3, #0] + 80038ae: 685a ldr r2, [r3, #4] + 80038b0: 687b ldr r3, [r7, #4] + 80038b2: 681b ldr r3, [r3, #0] + 80038b4: f042 0210 orr.w r2, r2, #16 + 80038b8: 605a str r2, [r3, #4] + + + return HAL_OK; + 80038ba: 2300 movs r3, #0 +} + 80038bc: 4618 mov r0, r3 + 80038be: 3710 adds r7, #16 + 80038c0: 46bd mov sp, r7 + 80038c2: bd80 pop {r7, pc} + +080038c4 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + 80038c4: b580 push {r7, lr} + 80038c6: b084 sub sp, #16 + 80038c8: af00 add r7, sp, #0 + 80038ca: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 80038cc: 2300 movs r3, #0 + 80038ce: 60fb str r3, [r7, #12] + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 80038d0: 687b ldr r3, [r7, #4] + 80038d2: 681b ldr r3, [r3, #0] + 80038d4: 685a ldr r2, [r3, #4] + 80038d6: 687b ldr r3, [r7, #4] + 80038d8: 681b ldr r3, [r3, #0] + 80038da: f022 0210 bic.w r2, r2, #16 + 80038de: 605a str r2, [r3, #4] + + tickstart = HAL_GetTick(); + 80038e0: f7fd fbe0 bl 80010a4 + 80038e4: 60f8 str r0, [r7, #12] + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 80038e6: e009 b.n 80038fc + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 80038e8: f7fd fbdc bl 80010a4 + 80038ec: 4602 mov r2, r0 + 80038ee: 68fb ldr r3, [r7, #12] + 80038f0: 1ad3 subs r3, r2, r3 + 80038f2: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 80038f6: d901 bls.n 80038fc + { + return HAL_TIMEOUT; + 80038f8: 2303 movs r3, #3 + 80038fa: e007 b.n 800390c + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + 80038fc: 687b ldr r3, [r7, #4] + 80038fe: 681b ldr r3, [r3, #0] + 8003900: 685b ldr r3, [r3, #4] + 8003902: f003 0320 and.w r3, r3, #32 + 8003906: 2b00 cmp r3, #0 + 8003908: d0ee beq.n 80038e8 + } + } + + return HAL_OK; + 800390a: 2300 movs r3, #0 +} + 800390c: 4618 mov r0, r3 + 800390e: 3710 adds r7, #16 + 8003910: 46bd mov sp, r7 + 8003912: bd80 pop {r7, pc} + +08003914 : + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted + * @retval Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + 8003914: b480 push {r7} + 8003916: b085 sub sp, #20 + 8003918: af00 add r7, sp, #0 + 800391a: 4603 mov r3, r0 + 800391c: 71fb strb r3, [r7, #7] + uint32_t bcdhigh = 0U; + 800391e: 2300 movs r3, #0 + 8003920: 60fb str r3, [r7, #12] + + while (Value >= 10U) + 8003922: e005 b.n 8003930 + { + bcdhigh++; + 8003924: 68fb ldr r3, [r7, #12] + 8003926: 3301 adds r3, #1 + 8003928: 60fb str r3, [r7, #12] + Value -= 10U; + 800392a: 79fb ldrb r3, [r7, #7] + 800392c: 3b0a subs r3, #10 + 800392e: 71fb strb r3, [r7, #7] + while (Value >= 10U) + 8003930: 79fb ldrb r3, [r7, #7] + 8003932: 2b09 cmp r3, #9 + 8003934: d8f6 bhi.n 8003924 + } + + return ((uint8_t)(bcdhigh << 4U) | Value); + 8003936: 68fb ldr r3, [r7, #12] + 8003938: b2db uxtb r3, r3 + 800393a: 011b lsls r3, r3, #4 + 800393c: b2da uxtb r2, r3 + 800393e: 79fb ldrb r3, [r7, #7] + 8003940: 4313 orrs r3, r2 + 8003942: b2db uxtb r3, r3 +} + 8003944: 4618 mov r0, r3 + 8003946: 3714 adds r7, #20 + 8003948: 46bd mov sp, r7 + 800394a: bc80 pop {r7} + 800394c: 4770 bx lr + +0800394e : + * @brief Converts from 2 digit BCD to Binary. + * @param Value: BCD value to be converted + * @retval Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + 800394e: b480 push {r7} + 8003950: b085 sub sp, #20 + 8003952: af00 add r7, sp, #0 + 8003954: 4603 mov r3, r0 + 8003956: 71fb strb r3, [r7, #7] + uint32_t tmp = 0U; + 8003958: 2300 movs r3, #0 + 800395a: 60fb str r3, [r7, #12] + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U; + 800395c: 79fb ldrb r3, [r7, #7] + 800395e: 091b lsrs r3, r3, #4 + 8003960: b2db uxtb r3, r3 + 8003962: 461a mov r2, r3 + 8003964: 4613 mov r3, r2 + 8003966: 009b lsls r3, r3, #2 + 8003968: 4413 add r3, r2 + 800396a: 005b lsls r3, r3, #1 + 800396c: 60fb str r3, [r7, #12] + return (tmp + (Value & (uint8_t)0x0F)); + 800396e: 79fb ldrb r3, [r7, #7] + 8003970: f003 030f and.w r3, r3, #15 + 8003974: b2da uxtb r2, r3 + 8003976: 68fb ldr r3, [r7, #12] + 8003978: b2db uxtb r3, r3 + 800397a: 4413 add r3, r2 + 800397c: b2db uxtb r3, r3 +} + 800397e: 4618 mov r0, r3 + 8003980: 3714 adds r7, #20 + 8003982: 46bd mov sp, r7 + 8003984: bc80 pop {r7} + 8003986: 4770 bx lr + +08003988 : + * the configuration information for RTC. + * @param DayElapsed: Number of days elapsed from last date update + * @retval None + */ +static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed) +{ + 8003988: b580 push {r7, lr} + 800398a: b086 sub sp, #24 + 800398c: af00 add r7, sp, #0 + 800398e: 6078 str r0, [r7, #4] + 8003990: 6039 str r1, [r7, #0] + uint32_t year = 0U, month = 0U, day = 0U; + 8003992: 2300 movs r3, #0 + 8003994: 617b str r3, [r7, #20] + 8003996: 2300 movs r3, #0 + 8003998: 613b str r3, [r7, #16] + 800399a: 2300 movs r3, #0 + 800399c: 60fb str r3, [r7, #12] + uint32_t loop = 0U; + 800399e: 2300 movs r3, #0 + 80039a0: 60bb str r3, [r7, #8] + + /* Get the current year*/ + year = hrtc->DateToUpdate.Year; + 80039a2: 687b ldr r3, [r7, #4] + 80039a4: 7bdb ldrb r3, [r3, #15] + 80039a6: 617b str r3, [r7, #20] + + /* Get the current month and day */ + month = hrtc->DateToUpdate.Month; + 80039a8: 687b ldr r3, [r7, #4] + 80039aa: 7b5b ldrb r3, [r3, #13] + 80039ac: 613b str r3, [r7, #16] + day = hrtc->DateToUpdate.Date; + 80039ae: 687b ldr r3, [r7, #4] + 80039b0: 7b9b ldrb r3, [r3, #14] + 80039b2: 60fb str r3, [r7, #12] + + for (loop = 0U; loop < DayElapsed; loop++) + 80039b4: 2300 movs r3, #0 + 80039b6: 60bb str r3, [r7, #8] + 80039b8: e06f b.n 8003a9a + { + if ((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \ + 80039ba: 693b ldr r3, [r7, #16] + 80039bc: 2b01 cmp r3, #1 + 80039be: d011 beq.n 80039e4 + 80039c0: 693b ldr r3, [r7, #16] + 80039c2: 2b03 cmp r3, #3 + 80039c4: d00e beq.n 80039e4 + 80039c6: 693b ldr r3, [r7, #16] + 80039c8: 2b05 cmp r3, #5 + 80039ca: d00b beq.n 80039e4 + 80039cc: 693b ldr r3, [r7, #16] + 80039ce: 2b07 cmp r3, #7 + 80039d0: d008 beq.n 80039e4 + 80039d2: 693b ldr r3, [r7, #16] + 80039d4: 2b08 cmp r3, #8 + 80039d6: d005 beq.n 80039e4 + (month == 8U) || (month == 10U) || (month == 12U)) + 80039d8: 693b ldr r3, [r7, #16] + 80039da: 2b0a cmp r3, #10 + 80039dc: d002 beq.n 80039e4 + 80039de: 693b ldr r3, [r7, #16] + 80039e0: 2b0c cmp r3, #12 + 80039e2: d117 bne.n 8003a14 + { + if (day < 31U) + 80039e4: 68fb ldr r3, [r7, #12] + 80039e6: 2b1e cmp r3, #30 + 80039e8: d803 bhi.n 80039f2 + { + day++; + 80039ea: 68fb ldr r3, [r7, #12] + 80039ec: 3301 adds r3, #1 + 80039ee: 60fb str r3, [r7, #12] + if (day < 31U) + 80039f0: e050 b.n 8003a94 + } + /* Date structure member: day = 31 */ + else + { + if (month != 12U) + 80039f2: 693b ldr r3, [r7, #16] + 80039f4: 2b0c cmp r3, #12 + 80039f6: d005 beq.n 8003a04 + { + month++; + 80039f8: 693b ldr r3, [r7, #16] + 80039fa: 3301 adds r3, #1 + 80039fc: 613b str r3, [r7, #16] + day = 1U; + 80039fe: 2301 movs r3, #1 + 8003a00: 60fb str r3, [r7, #12] + if (day < 31U) + 8003a02: e047 b.n 8003a94 + } + /* Date structure member: day = 31 & month =12 */ + else + { + month = 1U; + 8003a04: 2301 movs r3, #1 + 8003a06: 613b str r3, [r7, #16] + day = 1U; + 8003a08: 2301 movs r3, #1 + 8003a0a: 60fb str r3, [r7, #12] + year++; + 8003a0c: 697b ldr r3, [r7, #20] + 8003a0e: 3301 adds r3, #1 + 8003a10: 617b str r3, [r7, #20] + if (day < 31U) + 8003a12: e03f b.n 8003a94 + } + } + } + else if ((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U)) + 8003a14: 693b ldr r3, [r7, #16] + 8003a16: 2b04 cmp r3, #4 + 8003a18: d008 beq.n 8003a2c + 8003a1a: 693b ldr r3, [r7, #16] + 8003a1c: 2b06 cmp r3, #6 + 8003a1e: d005 beq.n 8003a2c + 8003a20: 693b ldr r3, [r7, #16] + 8003a22: 2b09 cmp r3, #9 + 8003a24: d002 beq.n 8003a2c + 8003a26: 693b ldr r3, [r7, #16] + 8003a28: 2b0b cmp r3, #11 + 8003a2a: d10c bne.n 8003a46 + { + if (day < 30U) + 8003a2c: 68fb ldr r3, [r7, #12] + 8003a2e: 2b1d cmp r3, #29 + 8003a30: d803 bhi.n 8003a3a + { + day++; + 8003a32: 68fb ldr r3, [r7, #12] + 8003a34: 3301 adds r3, #1 + 8003a36: 60fb str r3, [r7, #12] + if (day < 30U) + 8003a38: e02c b.n 8003a94 + } + /* Date structure member: day = 30 */ + else + { + month++; + 8003a3a: 693b ldr r3, [r7, #16] + 8003a3c: 3301 adds r3, #1 + 8003a3e: 613b str r3, [r7, #16] + day = 1U; + 8003a40: 2301 movs r3, #1 + 8003a42: 60fb str r3, [r7, #12] + if (day < 30U) + 8003a44: e026 b.n 8003a94 + } + } + else if (month == 2U) + 8003a46: 693b ldr r3, [r7, #16] + 8003a48: 2b02 cmp r3, #2 + 8003a4a: d123 bne.n 8003a94 + { + if (day < 28U) + 8003a4c: 68fb ldr r3, [r7, #12] + 8003a4e: 2b1b cmp r3, #27 + 8003a50: d803 bhi.n 8003a5a + { + day++; + 8003a52: 68fb ldr r3, [r7, #12] + 8003a54: 3301 adds r3, #1 + 8003a56: 60fb str r3, [r7, #12] + 8003a58: e01c b.n 8003a94 + } + else if (day == 28U) + 8003a5a: 68fb ldr r3, [r7, #12] + 8003a5c: 2b1c cmp r3, #28 + 8003a5e: d111 bne.n 8003a84 + { + /* Leap year */ + if (RTC_IsLeapYear(year)) + 8003a60: 697b ldr r3, [r7, #20] + 8003a62: b29b uxth r3, r3 + 8003a64: 4618 mov r0, r3 + 8003a66: f000 f839 bl 8003adc + 8003a6a: 4603 mov r3, r0 + 8003a6c: 2b00 cmp r3, #0 + 8003a6e: d003 beq.n 8003a78 + { + day++; + 8003a70: 68fb ldr r3, [r7, #12] + 8003a72: 3301 adds r3, #1 + 8003a74: 60fb str r3, [r7, #12] + 8003a76: e00d b.n 8003a94 + } + else + { + month++; + 8003a78: 693b ldr r3, [r7, #16] + 8003a7a: 3301 adds r3, #1 + 8003a7c: 613b str r3, [r7, #16] + day = 1U; + 8003a7e: 2301 movs r3, #1 + 8003a80: 60fb str r3, [r7, #12] + 8003a82: e007 b.n 8003a94 + } + } + else if (day == 29U) + 8003a84: 68fb ldr r3, [r7, #12] + 8003a86: 2b1d cmp r3, #29 + 8003a88: d104 bne.n 8003a94 + { + month++; + 8003a8a: 693b ldr r3, [r7, #16] + 8003a8c: 3301 adds r3, #1 + 8003a8e: 613b str r3, [r7, #16] + day = 1U; + 8003a90: 2301 movs r3, #1 + 8003a92: 60fb str r3, [r7, #12] + for (loop = 0U; loop < DayElapsed; loop++) + 8003a94: 68bb ldr r3, [r7, #8] + 8003a96: 3301 adds r3, #1 + 8003a98: 60bb str r3, [r7, #8] + 8003a9a: 68ba ldr r2, [r7, #8] + 8003a9c: 683b ldr r3, [r7, #0] + 8003a9e: 429a cmp r2, r3 + 8003aa0: d38b bcc.n 80039ba + } + } + } + + /* Update year */ + hrtc->DateToUpdate.Year = year; + 8003aa2: 697b ldr r3, [r7, #20] + 8003aa4: b2da uxtb r2, r3 + 8003aa6: 687b ldr r3, [r7, #4] + 8003aa8: 73da strb r2, [r3, #15] + + /* Update day and month */ + hrtc->DateToUpdate.Month = month; + 8003aaa: 693b ldr r3, [r7, #16] + 8003aac: b2da uxtb r2, r3 + 8003aae: 687b ldr r3, [r7, #4] + 8003ab0: 735a strb r2, [r3, #13] + hrtc->DateToUpdate.Date = day; + 8003ab2: 68fb ldr r3, [r7, #12] + 8003ab4: b2da uxtb r2, r3 + 8003ab6: 687b ldr r3, [r7, #4] + 8003ab8: 739a strb r2, [r3, #14] + + /* Update day of the week */ + hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(year, month, day); + 8003aba: 693b ldr r3, [r7, #16] + 8003abc: b2db uxtb r3, r3 + 8003abe: 68fa ldr r2, [r7, #12] + 8003ac0: b2d2 uxtb r2, r2 + 8003ac2: 4619 mov r1, r3 + 8003ac4: 6978 ldr r0, [r7, #20] + 8003ac6: f000 f83b bl 8003b40 + 8003aca: 4603 mov r3, r0 + 8003acc: 461a mov r2, r3 + 8003ace: 687b ldr r3, [r7, #4] + 8003ad0: 731a strb r2, [r3, #12] +} + 8003ad2: bf00 nop + 8003ad4: 3718 adds r7, #24 + 8003ad6: 46bd mov sp, r7 + 8003ad8: bd80 pop {r7, pc} + ... + +08003adc : + * @param nYear year to check + * @retval 1: leap year + * 0: not leap year + */ +static uint8_t RTC_IsLeapYear(uint16_t nYear) +{ + 8003adc: b480 push {r7} + 8003ade: b083 sub sp, #12 + 8003ae0: af00 add r7, sp, #0 + 8003ae2: 4603 mov r3, r0 + 8003ae4: 80fb strh r3, [r7, #6] + if ((nYear % 4U) != 0U) + 8003ae6: 88fb ldrh r3, [r7, #6] + 8003ae8: f003 0303 and.w r3, r3, #3 + 8003aec: b29b uxth r3, r3 + 8003aee: 2b00 cmp r3, #0 + 8003af0: d001 beq.n 8003af6 + { + return 0U; + 8003af2: 2300 movs r3, #0 + 8003af4: e01d b.n 8003b32 + } + + if ((nYear % 100U) != 0U) + 8003af6: 88fb ldrh r3, [r7, #6] + 8003af8: 4a10 ldr r2, [pc, #64] ; (8003b3c ) + 8003afa: fba2 1203 umull r1, r2, r2, r3 + 8003afe: 0952 lsrs r2, r2, #5 + 8003b00: 2164 movs r1, #100 ; 0x64 + 8003b02: fb01 f202 mul.w r2, r1, r2 + 8003b06: 1a9b subs r3, r3, r2 + 8003b08: b29b uxth r3, r3 + 8003b0a: 2b00 cmp r3, #0 + 8003b0c: d001 beq.n 8003b12 + { + return 1U; + 8003b0e: 2301 movs r3, #1 + 8003b10: e00f b.n 8003b32 + } + + if ((nYear % 400U) == 0U) + 8003b12: 88fb ldrh r3, [r7, #6] + 8003b14: 4a09 ldr r2, [pc, #36] ; (8003b3c ) + 8003b16: fba2 1203 umull r1, r2, r2, r3 + 8003b1a: 09d2 lsrs r2, r2, #7 + 8003b1c: f44f 71c8 mov.w r1, #400 ; 0x190 + 8003b20: fb01 f202 mul.w r2, r1, r2 + 8003b24: 1a9b subs r3, r3, r2 + 8003b26: b29b uxth r3, r3 + 8003b28: 2b00 cmp r3, #0 + 8003b2a: d101 bne.n 8003b30 + { + return 1U; + 8003b2c: 2301 movs r3, #1 + 8003b2e: e000 b.n 8003b32 + } + else + { + return 0U; + 8003b30: 2300 movs r3, #0 + } +} + 8003b32: 4618 mov r0, r3 + 8003b34: 370c adds r7, #12 + 8003b36: 46bd mov sp, r7 + 8003b38: bc80 pop {r7} + 8003b3a: 4770 bx lr + 8003b3c: 51eb851f .word 0x51eb851f + +08003b40 : + * @arg RTC_WEEKDAY_FRIDAY + * @arg RTC_WEEKDAY_SATURDAY + * @arg RTC_WEEKDAY_SUNDAY + */ +static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay) +{ + 8003b40: b480 push {r7} + 8003b42: b085 sub sp, #20 + 8003b44: af00 add r7, sp, #0 + 8003b46: 6078 str r0, [r7, #4] + 8003b48: 460b mov r3, r1 + 8003b4a: 70fb strb r3, [r7, #3] + 8003b4c: 4613 mov r3, r2 + 8003b4e: 70bb strb r3, [r7, #2] + uint32_t year = 0U, weekday = 0U; + 8003b50: 2300 movs r3, #0 + 8003b52: 60bb str r3, [r7, #8] + 8003b54: 2300 movs r3, #0 + 8003b56: 60fb str r3, [r7, #12] + + year = 2000U + nYear; + 8003b58: 687b ldr r3, [r7, #4] + 8003b5a: f503 63fa add.w r3, r3, #2000 ; 0x7d0 + 8003b5e: 60bb str r3, [r7, #8] + + if (nMonth < 3U) + 8003b60: 78fb ldrb r3, [r7, #3] + 8003b62: 2b02 cmp r3, #2 + 8003b64: d82d bhi.n 8003bc2 + { + /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/ + weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + ((year - 1U) / 4U) - ((year - 1U) / 100U) + ((year - 1U) / 400U)) % 7U; + 8003b66: 78fa ldrb r2, [r7, #3] + 8003b68: 4613 mov r3, r2 + 8003b6a: 005b lsls r3, r3, #1 + 8003b6c: 4413 add r3, r2 + 8003b6e: 00db lsls r3, r3, #3 + 8003b70: 1a9b subs r3, r3, r2 + 8003b72: 4a2c ldr r2, [pc, #176] ; (8003c24 ) + 8003b74: fba2 2303 umull r2, r3, r2, r3 + 8003b78: 085a lsrs r2, r3, #1 + 8003b7a: 78bb ldrb r3, [r7, #2] + 8003b7c: 441a add r2, r3 + 8003b7e: 68bb ldr r3, [r7, #8] + 8003b80: 441a add r2, r3 + 8003b82: 68bb ldr r3, [r7, #8] + 8003b84: 3b01 subs r3, #1 + 8003b86: 089b lsrs r3, r3, #2 + 8003b88: 441a add r2, r3 + 8003b8a: 68bb ldr r3, [r7, #8] + 8003b8c: 3b01 subs r3, #1 + 8003b8e: 4926 ldr r1, [pc, #152] ; (8003c28 ) + 8003b90: fba1 1303 umull r1, r3, r1, r3 + 8003b94: 095b lsrs r3, r3, #5 + 8003b96: 1ad2 subs r2, r2, r3 + 8003b98: 68bb ldr r3, [r7, #8] + 8003b9a: 3b01 subs r3, #1 + 8003b9c: 4922 ldr r1, [pc, #136] ; (8003c28 ) + 8003b9e: fba1 1303 umull r1, r3, r1, r3 + 8003ba2: 09db lsrs r3, r3, #7 + 8003ba4: 4413 add r3, r2 + 8003ba6: 1d1a adds r2, r3, #4 + 8003ba8: 4b20 ldr r3, [pc, #128] ; (8003c2c ) + 8003baa: fba3 1302 umull r1, r3, r3, r2 + 8003bae: 1ad1 subs r1, r2, r3 + 8003bb0: 0849 lsrs r1, r1, #1 + 8003bb2: 440b add r3, r1 + 8003bb4: 0899 lsrs r1, r3, #2 + 8003bb6: 460b mov r3, r1 + 8003bb8: 00db lsls r3, r3, #3 + 8003bba: 1a5b subs r3, r3, r1 + 8003bbc: 1ad3 subs r3, r2, r3 + 8003bbe: 60fb str r3, [r7, #12] + 8003bc0: e029 b.n 8003c16 + } + else + { + /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/ + weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + (year / 4U) - (year / 100U) + (year / 400U) - 2U) % 7U; + 8003bc2: 78fa ldrb r2, [r7, #3] + 8003bc4: 4613 mov r3, r2 + 8003bc6: 005b lsls r3, r3, #1 + 8003bc8: 4413 add r3, r2 + 8003bca: 00db lsls r3, r3, #3 + 8003bcc: 1a9b subs r3, r3, r2 + 8003bce: 4a15 ldr r2, [pc, #84] ; (8003c24 ) + 8003bd0: fba2 2303 umull r2, r3, r2, r3 + 8003bd4: 085a lsrs r2, r3, #1 + 8003bd6: 78bb ldrb r3, [r7, #2] + 8003bd8: 441a add r2, r3 + 8003bda: 68bb ldr r3, [r7, #8] + 8003bdc: 441a add r2, r3 + 8003bde: 68bb ldr r3, [r7, #8] + 8003be0: 089b lsrs r3, r3, #2 + 8003be2: 441a add r2, r3 + 8003be4: 68bb ldr r3, [r7, #8] + 8003be6: 4910 ldr r1, [pc, #64] ; (8003c28 ) + 8003be8: fba1 1303 umull r1, r3, r1, r3 + 8003bec: 095b lsrs r3, r3, #5 + 8003bee: 1ad2 subs r2, r2, r3 + 8003bf0: 68bb ldr r3, [r7, #8] + 8003bf2: 490d ldr r1, [pc, #52] ; (8003c28 ) + 8003bf4: fba1 1303 umull r1, r3, r1, r3 + 8003bf8: 09db lsrs r3, r3, #7 + 8003bfa: 4413 add r3, r2 + 8003bfc: 1c9a adds r2, r3, #2 + 8003bfe: 4b0b ldr r3, [pc, #44] ; (8003c2c ) + 8003c00: fba3 1302 umull r1, r3, r3, r2 + 8003c04: 1ad1 subs r1, r2, r3 + 8003c06: 0849 lsrs r1, r1, #1 + 8003c08: 440b add r3, r1 + 8003c0a: 0899 lsrs r1, r3, #2 + 8003c0c: 460b mov r3, r1 + 8003c0e: 00db lsls r3, r3, #3 + 8003c10: 1a5b subs r3, r3, r1 + 8003c12: 1ad3 subs r3, r2, r3 + 8003c14: 60fb str r3, [r7, #12] + } + + return (uint8_t)weekday; + 8003c16: 68fb ldr r3, [r7, #12] + 8003c18: b2db uxtb r3, r3 +} + 8003c1a: 4618 mov r0, r3 + 8003c1c: 3714 adds r7, #20 + 8003c1e: 46bd mov sp, r7 + 8003c20: bc80 pop {r7} + 8003c22: 4770 bx lr + 8003c24: 38e38e39 .word 0x38e38e39 + 8003c28: 51eb851f .word 0x51eb851f + 8003c2c: 24924925 .word 0x24924925 + +08003c30 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8003c30: b580 push {r7, lr} + 8003c32: b082 sub sp, #8 + 8003c34: af00 add r7, sp, #0 + 8003c36: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8003c38: 687b ldr r3, [r7, #4] + 8003c3a: 2b00 cmp r3, #0 + 8003c3c: d101 bne.n 8003c42 + { + return HAL_ERROR; + 8003c3e: 2301 movs r3, #1 + 8003c40: e053 b.n 8003cea + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8003c42: 687b ldr r3, [r7, #4] + 8003c44: 2200 movs r2, #0 + 8003c46: 629a str r2, [r3, #40] ; 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8003c48: 687b ldr r3, [r7, #4] + 8003c4a: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 + 8003c4e: b2db uxtb r3, r3 + 8003c50: 2b00 cmp r3, #0 + 8003c52: d106 bne.n 8003c62 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8003c54: 687b ldr r3, [r7, #4] + 8003c56: 2200 movs r2, #0 + 8003c58: f883 2050 strb.w r2, [r3, #80] ; 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8003c5c: 6878 ldr r0, [r7, #4] + 8003c5e: f006 fa0f bl 800a080 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8003c62: 687b ldr r3, [r7, #4] + 8003c64: 2202 movs r2, #2 + 8003c66: f883 2051 strb.w r2, [r3, #81] ; 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8003c6a: 687b ldr r3, [r7, #4] + 8003c6c: 681b ldr r3, [r3, #0] + 8003c6e: 681a ldr r2, [r3, #0] + 8003c70: 687b ldr r3, [r7, #4] + 8003c72: 681b ldr r3, [r3, #0] + 8003c74: f022 0240 bic.w r2, r2, #64 ; 0x40 + 8003c78: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + 8003c7a: 687b ldr r3, [r7, #4] + 8003c7c: 685a ldr r2, [r3, #4] + 8003c7e: 687b ldr r3, [r7, #4] + 8003c80: 689b ldr r3, [r3, #8] + 8003c82: 431a orrs r2, r3 + 8003c84: 687b ldr r3, [r7, #4] + 8003c86: 68db ldr r3, [r3, #12] + 8003c88: 431a orrs r2, r3 + 8003c8a: 687b ldr r3, [r7, #4] + 8003c8c: 691b ldr r3, [r3, #16] + 8003c8e: 431a orrs r2, r3 + 8003c90: 687b ldr r3, [r7, #4] + 8003c92: 695b ldr r3, [r3, #20] + 8003c94: 431a orrs r2, r3 + 8003c96: 687b ldr r3, [r7, #4] + 8003c98: 699b ldr r3, [r3, #24] + 8003c9a: f403 7300 and.w r3, r3, #512 ; 0x200 + 8003c9e: 431a orrs r2, r3 + 8003ca0: 687b ldr r3, [r7, #4] + 8003ca2: 69db ldr r3, [r3, #28] + 8003ca4: 431a orrs r2, r3 + 8003ca6: 687b ldr r3, [r7, #4] + 8003ca8: 6a1b ldr r3, [r3, #32] + 8003caa: ea42 0103 orr.w r1, r2, r3 + 8003cae: 687b ldr r3, [r7, #4] + 8003cb0: 6a9a ldr r2, [r3, #40] ; 0x28 + 8003cb2: 687b ldr r3, [r7, #4] + 8003cb4: 681b ldr r3, [r3, #0] + 8003cb6: 430a orrs r2, r1 + 8003cb8: 601a str r2, [r3, #0] + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE)); + 8003cba: 687b ldr r3, [r7, #4] + 8003cbc: 699b ldr r3, [r3, #24] + 8003cbe: 0c1a lsrs r2, r3, #16 + 8003cc0: 687b ldr r3, [r7, #4] + 8003cc2: 681b ldr r3, [r3, #0] + 8003cc4: f002 0204 and.w r2, r2, #4 + 8003cc8: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8003cca: 687b ldr r3, [r7, #4] + 8003ccc: 681b ldr r3, [r3, #0] + 8003cce: 69da ldr r2, [r3, #28] + 8003cd0: 687b ldr r3, [r7, #4] + 8003cd2: 681b ldr r3, [r3, #0] + 8003cd4: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 8003cd8: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8003cda: 687b ldr r3, [r7, #4] + 8003cdc: 2200 movs r2, #0 + 8003cde: 655a str r2, [r3, #84] ; 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8003ce0: 687b ldr r3, [r7, #4] + 8003ce2: 2201 movs r2, #1 + 8003ce4: f883 2051 strb.w r2, [r3, #81] ; 0x51 + + return HAL_OK; + 8003ce8: 2300 movs r3, #0 +} + 8003cea: 4618 mov r0, r3 + 8003cec: 3708 adds r7, #8 + 8003cee: 46bd mov sp, r7 + 8003cf0: bd80 pop {r7, pc} + +08003cf2 : + * @param Size amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8003cf2: b580 push {r7, lr} + 8003cf4: b088 sub sp, #32 + 8003cf6: af00 add r7, sp, #0 + 8003cf8: 60f8 str r0, [r7, #12] + 8003cfa: 60b9 str r1, [r7, #8] + 8003cfc: 603b str r3, [r7, #0] + 8003cfe: 4613 mov r3, r2 + 8003d00: 80fb strh r3, [r7, #6] + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + 8003d02: 2300 movs r3, #0 + 8003d04: 77fb strb r3, [r7, #31] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + 8003d06: 68fb ldr r3, [r7, #12] + 8003d08: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 + 8003d0c: 2b01 cmp r3, #1 + 8003d0e: d101 bne.n 8003d14 + 8003d10: 2302 movs r3, #2 + 8003d12: e11e b.n 8003f52 + 8003d14: 68fb ldr r3, [r7, #12] + 8003d16: 2201 movs r2, #1 + 8003d18: f883 2050 strb.w r2, [r3, #80] ; 0x50 + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8003d1c: f7fd f9c2 bl 80010a4 + 8003d20: 61b8 str r0, [r7, #24] + initial_TxXferCount = Size; + 8003d22: 88fb ldrh r3, [r7, #6] + 8003d24: 82fb strh r3, [r7, #22] + + if (hspi->State != HAL_SPI_STATE_READY) + 8003d26: 68fb ldr r3, [r7, #12] + 8003d28: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 + 8003d2c: b2db uxtb r3, r3 + 8003d2e: 2b01 cmp r3, #1 + 8003d30: d002 beq.n 8003d38 + { + errorcode = HAL_BUSY; + 8003d32: 2302 movs r3, #2 + 8003d34: 77fb strb r3, [r7, #31] + goto error; + 8003d36: e103 b.n 8003f40 + } + + if ((pData == NULL) || (Size == 0U)) + 8003d38: 68bb ldr r3, [r7, #8] + 8003d3a: 2b00 cmp r3, #0 + 8003d3c: d002 beq.n 8003d44 + 8003d3e: 88fb ldrh r3, [r7, #6] + 8003d40: 2b00 cmp r3, #0 + 8003d42: d102 bne.n 8003d4a + { + errorcode = HAL_ERROR; + 8003d44: 2301 movs r3, #1 + 8003d46: 77fb strb r3, [r7, #31] + goto error; + 8003d48: e0fa b.n 8003f40 + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 8003d4a: 68fb ldr r3, [r7, #12] + 8003d4c: 2203 movs r2, #3 + 8003d4e: f883 2051 strb.w r2, [r3, #81] ; 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8003d52: 68fb ldr r3, [r7, #12] + 8003d54: 2200 movs r2, #0 + 8003d56: 655a str r2, [r3, #84] ; 0x54 + hspi->pTxBuffPtr = (uint8_t *)pData; + 8003d58: 68fb ldr r3, [r7, #12] + 8003d5a: 68ba ldr r2, [r7, #8] + 8003d5c: 631a str r2, [r3, #48] ; 0x30 + hspi->TxXferSize = Size; + 8003d5e: 68fb ldr r3, [r7, #12] + 8003d60: 88fa ldrh r2, [r7, #6] + 8003d62: 869a strh r2, [r3, #52] ; 0x34 + hspi->TxXferCount = Size; + 8003d64: 68fb ldr r3, [r7, #12] + 8003d66: 88fa ldrh r2, [r7, #6] + 8003d68: 86da strh r2, [r3, #54] ; 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 8003d6a: 68fb ldr r3, [r7, #12] + 8003d6c: 2200 movs r2, #0 + 8003d6e: 639a str r2, [r3, #56] ; 0x38 + hspi->RxXferSize = 0U; + 8003d70: 68fb ldr r3, [r7, #12] + 8003d72: 2200 movs r2, #0 + 8003d74: 879a strh r2, [r3, #60] ; 0x3c + hspi->RxXferCount = 0U; + 8003d76: 68fb ldr r3, [r7, #12] + 8003d78: 2200 movs r2, #0 + 8003d7a: 87da strh r2, [r3, #62] ; 0x3e + hspi->TxISR = NULL; + 8003d7c: 68fb ldr r3, [r7, #12] + 8003d7e: 2200 movs r2, #0 + 8003d80: 645a str r2, [r3, #68] ; 0x44 + hspi->RxISR = NULL; + 8003d82: 68fb ldr r3, [r7, #12] + 8003d84: 2200 movs r2, #0 + 8003d86: 641a str r2, [r3, #64] ; 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8003d88: 68fb ldr r3, [r7, #12] + 8003d8a: 689b ldr r3, [r3, #8] + 8003d8c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8003d90: d107 bne.n 8003da2 + { + SPI_1LINE_TX(hspi); + 8003d92: 68fb ldr r3, [r7, #12] + 8003d94: 681b ldr r3, [r3, #0] + 8003d96: 681a ldr r2, [r3, #0] + 8003d98: 68fb ldr r3, [r7, #12] + 8003d9a: 681b ldr r3, [r3, #0] + 8003d9c: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 8003da0: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8003da2: 68fb ldr r3, [r7, #12] + 8003da4: 681b ldr r3, [r3, #0] + 8003da6: 681b ldr r3, [r3, #0] + 8003da8: f003 0340 and.w r3, r3, #64 ; 0x40 + 8003dac: 2b40 cmp r3, #64 ; 0x40 + 8003dae: d007 beq.n 8003dc0 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8003db0: 68fb ldr r3, [r7, #12] + 8003db2: 681b ldr r3, [r3, #0] + 8003db4: 681a ldr r2, [r3, #0] + 8003db6: 68fb ldr r3, [r7, #12] + 8003db8: 681b ldr r3, [r3, #0] + 8003dba: f042 0240 orr.w r2, r2, #64 ; 0x40 + 8003dbe: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8003dc0: 68fb ldr r3, [r7, #12] + 8003dc2: 68db ldr r3, [r3, #12] + 8003dc4: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8003dc8: d14b bne.n 8003e62 + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8003dca: 68fb ldr r3, [r7, #12] + 8003dcc: 685b ldr r3, [r3, #4] + 8003dce: 2b00 cmp r3, #0 + 8003dd0: d002 beq.n 8003dd8 + 8003dd2: 8afb ldrh r3, [r7, #22] + 8003dd4: 2b01 cmp r3, #1 + 8003dd6: d13e bne.n 8003e56 + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 8003dd8: 68fb ldr r3, [r7, #12] + 8003dda: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003ddc: 881a ldrh r2, [r3, #0] + 8003dde: 68fb ldr r3, [r7, #12] + 8003de0: 681b ldr r3, [r3, #0] + 8003de2: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8003de4: 68fb ldr r3, [r7, #12] + 8003de6: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003de8: 1c9a adds r2, r3, #2 + 8003dea: 68fb ldr r3, [r7, #12] + 8003dec: 631a str r2, [r3, #48] ; 0x30 + hspi->TxXferCount--; + 8003dee: 68fb ldr r3, [r7, #12] + 8003df0: 8edb ldrh r3, [r3, #54] ; 0x36 + 8003df2: b29b uxth r3, r3 + 8003df4: 3b01 subs r3, #1 + 8003df6: b29a uxth r2, r3 + 8003df8: 68fb ldr r3, [r7, #12] + 8003dfa: 86da strh r2, [r3, #54] ; 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 8003dfc: e02b b.n 8003e56 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8003dfe: 68fb ldr r3, [r7, #12] + 8003e00: 681b ldr r3, [r3, #0] + 8003e02: 689b ldr r3, [r3, #8] + 8003e04: f003 0302 and.w r3, r3, #2 + 8003e08: 2b02 cmp r3, #2 + 8003e0a: d112 bne.n 8003e32 + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 8003e0c: 68fb ldr r3, [r7, #12] + 8003e0e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003e10: 881a ldrh r2, [r3, #0] + 8003e12: 68fb ldr r3, [r7, #12] + 8003e14: 681b ldr r3, [r3, #0] + 8003e16: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8003e18: 68fb ldr r3, [r7, #12] + 8003e1a: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003e1c: 1c9a adds r2, r3, #2 + 8003e1e: 68fb ldr r3, [r7, #12] + 8003e20: 631a str r2, [r3, #48] ; 0x30 + hspi->TxXferCount--; + 8003e22: 68fb ldr r3, [r7, #12] + 8003e24: 8edb ldrh r3, [r3, #54] ; 0x36 + 8003e26: b29b uxth r3, r3 + 8003e28: 3b01 subs r3, #1 + 8003e2a: b29a uxth r2, r3 + 8003e2c: 68fb ldr r3, [r7, #12] + 8003e2e: 86da strh r2, [r3, #54] ; 0x36 + 8003e30: e011 b.n 8003e56 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8003e32: f7fd f937 bl 80010a4 + 8003e36: 4602 mov r2, r0 + 8003e38: 69bb ldr r3, [r7, #24] + 8003e3a: 1ad3 subs r3, r2, r3 + 8003e3c: 683a ldr r2, [r7, #0] + 8003e3e: 429a cmp r2, r3 + 8003e40: d803 bhi.n 8003e4a + 8003e42: 683b ldr r3, [r7, #0] + 8003e44: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8003e48: d102 bne.n 8003e50 + 8003e4a: 683b ldr r3, [r7, #0] + 8003e4c: 2b00 cmp r3, #0 + 8003e4e: d102 bne.n 8003e56 + { + errorcode = HAL_TIMEOUT; + 8003e50: 2303 movs r3, #3 + 8003e52: 77fb strb r3, [r7, #31] + goto error; + 8003e54: e074 b.n 8003f40 + while (hspi->TxXferCount > 0U) + 8003e56: 68fb ldr r3, [r7, #12] + 8003e58: 8edb ldrh r3, [r3, #54] ; 0x36 + 8003e5a: b29b uxth r3, r3 + 8003e5c: 2b00 cmp r3, #0 + 8003e5e: d1ce bne.n 8003dfe + 8003e60: e04c b.n 8003efc + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8003e62: 68fb ldr r3, [r7, #12] + 8003e64: 685b ldr r3, [r3, #4] + 8003e66: 2b00 cmp r3, #0 + 8003e68: d002 beq.n 8003e70 + 8003e6a: 8afb ldrh r3, [r7, #22] + 8003e6c: 2b01 cmp r3, #1 + 8003e6e: d140 bne.n 8003ef2 + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + 8003e70: 68fb ldr r3, [r7, #12] + 8003e72: 6b1a ldr r2, [r3, #48] ; 0x30 + 8003e74: 68fb ldr r3, [r7, #12] + 8003e76: 681b ldr r3, [r3, #0] + 8003e78: 330c adds r3, #12 + 8003e7a: 7812 ldrb r2, [r2, #0] + 8003e7c: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8003e7e: 68fb ldr r3, [r7, #12] + 8003e80: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003e82: 1c5a adds r2, r3, #1 + 8003e84: 68fb ldr r3, [r7, #12] + 8003e86: 631a str r2, [r3, #48] ; 0x30 + hspi->TxXferCount--; + 8003e88: 68fb ldr r3, [r7, #12] + 8003e8a: 8edb ldrh r3, [r3, #54] ; 0x36 + 8003e8c: b29b uxth r3, r3 + 8003e8e: 3b01 subs r3, #1 + 8003e90: b29a uxth r2, r3 + 8003e92: 68fb ldr r3, [r7, #12] + 8003e94: 86da strh r2, [r3, #54] ; 0x36 + } + while (hspi->TxXferCount > 0U) + 8003e96: e02c b.n 8003ef2 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8003e98: 68fb ldr r3, [r7, #12] + 8003e9a: 681b ldr r3, [r3, #0] + 8003e9c: 689b ldr r3, [r3, #8] + 8003e9e: f003 0302 and.w r3, r3, #2 + 8003ea2: 2b02 cmp r3, #2 + 8003ea4: d113 bne.n 8003ece + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + 8003ea6: 68fb ldr r3, [r7, #12] + 8003ea8: 6b1a ldr r2, [r3, #48] ; 0x30 + 8003eaa: 68fb ldr r3, [r7, #12] + 8003eac: 681b ldr r3, [r3, #0] + 8003eae: 330c adds r3, #12 + 8003eb0: 7812 ldrb r2, [r2, #0] + 8003eb2: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8003eb4: 68fb ldr r3, [r7, #12] + 8003eb6: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003eb8: 1c5a adds r2, r3, #1 + 8003eba: 68fb ldr r3, [r7, #12] + 8003ebc: 631a str r2, [r3, #48] ; 0x30 + hspi->TxXferCount--; + 8003ebe: 68fb ldr r3, [r7, #12] + 8003ec0: 8edb ldrh r3, [r3, #54] ; 0x36 + 8003ec2: b29b uxth r3, r3 + 8003ec4: 3b01 subs r3, #1 + 8003ec6: b29a uxth r2, r3 + 8003ec8: 68fb ldr r3, [r7, #12] + 8003eca: 86da strh r2, [r3, #54] ; 0x36 + 8003ecc: e011 b.n 8003ef2 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8003ece: f7fd f8e9 bl 80010a4 + 8003ed2: 4602 mov r2, r0 + 8003ed4: 69bb ldr r3, [r7, #24] + 8003ed6: 1ad3 subs r3, r2, r3 + 8003ed8: 683a ldr r2, [r7, #0] + 8003eda: 429a cmp r2, r3 + 8003edc: d803 bhi.n 8003ee6 + 8003ede: 683b ldr r3, [r7, #0] + 8003ee0: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8003ee4: d102 bne.n 8003eec + 8003ee6: 683b ldr r3, [r7, #0] + 8003ee8: 2b00 cmp r3, #0 + 8003eea: d102 bne.n 8003ef2 + { + errorcode = HAL_TIMEOUT; + 8003eec: 2303 movs r3, #3 + 8003eee: 77fb strb r3, [r7, #31] + goto error; + 8003ef0: e026 b.n 8003f40 + while (hspi->TxXferCount > 0U) + 8003ef2: 68fb ldr r3, [r7, #12] + 8003ef4: 8edb ldrh r3, [r3, #54] ; 0x36 + 8003ef6: b29b uxth r3, r3 + 8003ef8: 2b00 cmp r3, #0 + 8003efa: d1cd bne.n 8003e98 + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 8003efc: 69ba ldr r2, [r7, #24] + 8003efe: 6839 ldr r1, [r7, #0] + 8003f00: 68f8 ldr r0, [r7, #12] + 8003f02: f000 f894 bl 800402e + 8003f06: 4603 mov r3, r0 + 8003f08: 2b00 cmp r3, #0 + 8003f0a: d002 beq.n 8003f12 + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 8003f0c: 68fb ldr r3, [r7, #12] + 8003f0e: 2220 movs r2, #32 + 8003f10: 655a str r2, [r3, #84] ; 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 8003f12: 68fb ldr r3, [r7, #12] + 8003f14: 689b ldr r3, [r3, #8] + 8003f16: 2b00 cmp r3, #0 + 8003f18: d10a bne.n 8003f30 + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 8003f1a: 2300 movs r3, #0 + 8003f1c: 613b str r3, [r7, #16] + 8003f1e: 68fb ldr r3, [r7, #12] + 8003f20: 681b ldr r3, [r3, #0] + 8003f22: 68db ldr r3, [r3, #12] + 8003f24: 613b str r3, [r7, #16] + 8003f26: 68fb ldr r3, [r7, #12] + 8003f28: 681b ldr r3, [r3, #0] + 8003f2a: 689b ldr r3, [r3, #8] + 8003f2c: 613b str r3, [r7, #16] + 8003f2e: 693b ldr r3, [r7, #16] + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 8003f30: 68fb ldr r3, [r7, #12] + 8003f32: 6d5b ldr r3, [r3, #84] ; 0x54 + 8003f34: 2b00 cmp r3, #0 + 8003f36: d002 beq.n 8003f3e + { + errorcode = HAL_ERROR; + 8003f38: 2301 movs r3, #1 + 8003f3a: 77fb strb r3, [r7, #31] + 8003f3c: e000 b.n 8003f40 + } + +error: + 8003f3e: bf00 nop + hspi->State = HAL_SPI_STATE_READY; + 8003f40: 68fb ldr r3, [r7, #12] + 8003f42: 2201 movs r2, #1 + 8003f44: f883 2051 strb.w r2, [r3, #81] ; 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8003f48: 68fb ldr r3, [r7, #12] + 8003f4a: 2200 movs r2, #0 + 8003f4c: f883 2050 strb.w r2, [r3, #80] ; 0x50 + return errorcode; + 8003f50: 7ffb ldrb r3, [r7, #31] +} + 8003f52: 4618 mov r0, r3 + 8003f54: 3720 adds r7, #32 + 8003f56: 46bd mov sp, r7 + 8003f58: bd80 pop {r7, pc} + +08003f5a : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 8003f5a: b580 push {r7, lr} + 8003f5c: b084 sub sp, #16 + 8003f5e: af00 add r7, sp, #0 + 8003f60: 60f8 str r0, [r7, #12] + 8003f62: 60b9 str r1, [r7, #8] + 8003f64: 603b str r3, [r7, #0] + 8003f66: 4613 mov r3, r2 + 8003f68: 71fb strb r3, [r7, #7] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8003f6a: e04c b.n 8004006 + { + if (Timeout != HAL_MAX_DELAY) + 8003f6c: 683b ldr r3, [r7, #0] + 8003f6e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8003f72: d048 beq.n 8004006 + { + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + 8003f74: f7fd f896 bl 80010a4 + 8003f78: 4602 mov r2, r0 + 8003f7a: 69bb ldr r3, [r7, #24] + 8003f7c: 1ad3 subs r3, r2, r3 + 8003f7e: 683a ldr r2, [r7, #0] + 8003f80: 429a cmp r2, r3 + 8003f82: d902 bls.n 8003f8a + 8003f84: 683b ldr r3, [r7, #0] + 8003f86: 2b00 cmp r3, #0 + 8003f88: d13d bne.n 8004006 + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 8003f8a: 68fb ldr r3, [r7, #12] + 8003f8c: 681b ldr r3, [r3, #0] + 8003f8e: 685a ldr r2, [r3, #4] + 8003f90: 68fb ldr r3, [r7, #12] + 8003f92: 681b ldr r3, [r3, #0] + 8003f94: f022 02e0 bic.w r2, r2, #224 ; 0xe0 + 8003f98: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8003f9a: 68fb ldr r3, [r7, #12] + 8003f9c: 685b ldr r3, [r3, #4] + 8003f9e: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 8003fa2: d111 bne.n 8003fc8 + 8003fa4: 68fb ldr r3, [r7, #12] + 8003fa6: 689b ldr r3, [r3, #8] + 8003fa8: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8003fac: d004 beq.n 8003fb8 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 8003fae: 68fb ldr r3, [r7, #12] + 8003fb0: 689b ldr r3, [r3, #8] + 8003fb2: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8003fb6: d107 bne.n 8003fc8 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8003fb8: 68fb ldr r3, [r7, #12] + 8003fba: 681b ldr r3, [r3, #0] + 8003fbc: 681a ldr r2, [r3, #0] + 8003fbe: 68fb ldr r3, [r7, #12] + 8003fc0: 681b ldr r3, [r3, #0] + 8003fc2: f022 0240 bic.w r2, r2, #64 ; 0x40 + 8003fc6: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 8003fc8: 68fb ldr r3, [r7, #12] + 8003fca: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003fcc: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8003fd0: d10f bne.n 8003ff2 + { + SPI_RESET_CRC(hspi); + 8003fd2: 68fb ldr r3, [r7, #12] + 8003fd4: 681b ldr r3, [r3, #0] + 8003fd6: 681a ldr r2, [r3, #0] + 8003fd8: 68fb ldr r3, [r7, #12] + 8003fda: 681b ldr r3, [r3, #0] + 8003fdc: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 8003fe0: 601a str r2, [r3, #0] + 8003fe2: 68fb ldr r3, [r7, #12] + 8003fe4: 681b ldr r3, [r3, #0] + 8003fe6: 681a ldr r2, [r3, #0] + 8003fe8: 68fb ldr r3, [r7, #12] + 8003fea: 681b ldr r3, [r3, #0] + 8003fec: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 8003ff0: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 8003ff2: 68fb ldr r3, [r7, #12] + 8003ff4: 2201 movs r2, #1 + 8003ff6: f883 2051 strb.w r2, [r3, #81] ; 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8003ffa: 68fb ldr r3, [r7, #12] + 8003ffc: 2200 movs r2, #0 + 8003ffe: f883 2050 strb.w r2, [r3, #80] ; 0x50 + + return HAL_TIMEOUT; + 8004002: 2303 movs r3, #3 + 8004004: e00f b.n 8004026 + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8004006: 68fb ldr r3, [r7, #12] + 8004008: 681b ldr r3, [r3, #0] + 800400a: 689a ldr r2, [r3, #8] + 800400c: 68bb ldr r3, [r7, #8] + 800400e: 4013 ands r3, r2 + 8004010: 68ba ldr r2, [r7, #8] + 8004012: 429a cmp r2, r3 + 8004014: bf0c ite eq + 8004016: 2301 moveq r3, #1 + 8004018: 2300 movne r3, #0 + 800401a: b2db uxtb r3, r3 + 800401c: 461a mov r2, r3 + 800401e: 79fb ldrb r3, [r7, #7] + 8004020: 429a cmp r2, r3 + 8004022: d1a3 bne.n 8003f6c + } + } + } + + return HAL_OK; + 8004024: 2300 movs r3, #0 +} + 8004026: 4618 mov r0, r3 + 8004028: 3710 adds r7, #16 + 800402a: 46bd mov sp, r7 + 800402c: bd80 pop {r7, pc} + +0800402e : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 800402e: b580 push {r7, lr} + 8004030: b086 sub sp, #24 + 8004032: af02 add r7, sp, #8 + 8004034: 60f8 str r0, [r7, #12] + 8004036: 60b9 str r1, [r7, #8] + 8004038: 607a str r2, [r7, #4] + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 800403a: 687b ldr r3, [r7, #4] + 800403c: 9300 str r3, [sp, #0] + 800403e: 68bb ldr r3, [r7, #8] + 8004040: 2200 movs r2, #0 + 8004042: 2180 movs r1, #128 ; 0x80 + 8004044: 68f8 ldr r0, [r7, #12] + 8004046: f7ff ff88 bl 8003f5a + 800404a: 4603 mov r3, r0 + 800404c: 2b00 cmp r3, #0 + 800404e: d007 beq.n 8004060 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8004050: 68fb ldr r3, [r7, #12] + 8004052: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004054: f043 0220 orr.w r2, r3, #32 + 8004058: 68fb ldr r3, [r7, #12] + 800405a: 655a str r2, [r3, #84] ; 0x54 + return HAL_TIMEOUT; + 800405c: 2303 movs r3, #3 + 800405e: e000 b.n 8004062 + } + return HAL_OK; + 8004060: 2300 movs r3, #0 +} + 8004062: 4618 mov r0, r3 + 8004064: 3710 adds r7, #16 + 8004066: 46bd mov sp, r7 + 8004068: bd80 pop {r7, pc} + +0800406a : + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + 800406a: b580 push {r7, lr} + 800406c: b086 sub sp, #24 + 800406e: af00 add r7, sp, #0 + 8004070: 6078 str r0, [r7, #4] + 8004072: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + 8004074: 687b ldr r3, [r7, #4] + 8004076: 2b00 cmp r3, #0 + 8004078: d101 bne.n 800407e + { + return HAL_ERROR; + 800407a: 2301 movs r3, #1 + 800407c: e07f b.n 800417e + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + 800407e: 687b ldr r3, [r7, #4] + 8004080: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8004084: b2db uxtb r3, r3 + 8004086: 2b00 cmp r3, #0 + 8004088: d106 bne.n 8004098 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 800408a: 687b ldr r3, [r7, #4] + 800408c: 2200 movs r2, #0 + 800408e: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + 8004092: 6878 ldr r0, [r7, #4] + 8004094: f006 f840 bl 800a118 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8004098: 687b ldr r3, [r7, #4] + 800409a: 2202 movs r2, #2 + 800409c: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + 80040a0: 687b ldr r3, [r7, #4] + 80040a2: 681b ldr r3, [r3, #0] + 80040a4: 689b ldr r3, [r3, #8] + 80040a6: 687a ldr r2, [r7, #4] + 80040a8: 6812 ldr r2, [r2, #0] + 80040aa: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 80040ae: f023 0307 bic.w r3, r3, #7 + 80040b2: 6093 str r3, [r2, #8] + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 80040b4: 687b ldr r3, [r7, #4] + 80040b6: 681a ldr r2, [r3, #0] + 80040b8: 687b ldr r3, [r7, #4] + 80040ba: 3304 adds r3, #4 + 80040bc: 4619 mov r1, r3 + 80040be: 4610 mov r0, r2 + 80040c0: f000 f898 bl 80041f4 + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 80040c4: 687b ldr r3, [r7, #4] + 80040c6: 681b ldr r3, [r3, #0] + 80040c8: 689b ldr r3, [r3, #8] + 80040ca: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + 80040cc: 687b ldr r3, [r7, #4] + 80040ce: 681b ldr r3, [r3, #0] + 80040d0: 699b ldr r3, [r3, #24] + 80040d2: 613b str r3, [r7, #16] + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + 80040d4: 687b ldr r3, [r7, #4] + 80040d6: 681b ldr r3, [r3, #0] + 80040d8: 6a1b ldr r3, [r3, #32] + 80040da: 60fb str r3, [r7, #12] + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + 80040dc: 683b ldr r3, [r7, #0] + 80040de: 681b ldr r3, [r3, #0] + 80040e0: 697a ldr r2, [r7, #20] + 80040e2: 4313 orrs r3, r2 + 80040e4: 617b str r3, [r7, #20] + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + 80040e6: 693b ldr r3, [r7, #16] + 80040e8: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80040ec: f023 0303 bic.w r3, r3, #3 + 80040f0: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + 80040f2: 683b ldr r3, [r7, #0] + 80040f4: 689a ldr r2, [r3, #8] + 80040f6: 683b ldr r3, [r7, #0] + 80040f8: 699b ldr r3, [r3, #24] + 80040fa: 021b lsls r3, r3, #8 + 80040fc: 4313 orrs r3, r2 + 80040fe: 693a ldr r2, [r7, #16] + 8004100: 4313 orrs r3, r2 + 8004102: 613b str r3, [r7, #16] + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + 8004104: 693b ldr r3, [r7, #16] + 8004106: f423 6340 bic.w r3, r3, #3072 ; 0xc00 + 800410a: f023 030c bic.w r3, r3, #12 + 800410e: 613b str r3, [r7, #16] + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + 8004110: 693b ldr r3, [r7, #16] + 8004112: f423 4370 bic.w r3, r3, #61440 ; 0xf000 + 8004116: f023 03f0 bic.w r3, r3, #240 ; 0xf0 + 800411a: 613b str r3, [r7, #16] + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + 800411c: 683b ldr r3, [r7, #0] + 800411e: 68da ldr r2, [r3, #12] + 8004120: 683b ldr r3, [r7, #0] + 8004122: 69db ldr r3, [r3, #28] + 8004124: 021b lsls r3, r3, #8 + 8004126: 4313 orrs r3, r2 + 8004128: 693a ldr r2, [r7, #16] + 800412a: 4313 orrs r3, r2 + 800412c: 613b str r3, [r7, #16] + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 800412e: 683b ldr r3, [r7, #0] + 8004130: 691b ldr r3, [r3, #16] + 8004132: 011a lsls r2, r3, #4 + 8004134: 683b ldr r3, [r7, #0] + 8004136: 6a1b ldr r3, [r3, #32] + 8004138: 031b lsls r3, r3, #12 + 800413a: 4313 orrs r3, r2 + 800413c: 693a ldr r2, [r7, #16] + 800413e: 4313 orrs r3, r2 + 8004140: 613b str r3, [r7, #16] + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + 8004142: 68fb ldr r3, [r7, #12] + 8004144: f023 0322 bic.w r3, r3, #34 ; 0x22 + 8004148: 60fb str r3, [r7, #12] + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + 800414a: 683b ldr r3, [r7, #0] + 800414c: 685a ldr r2, [r3, #4] + 800414e: 683b ldr r3, [r7, #0] + 8004150: 695b ldr r3, [r3, #20] + 8004152: 011b lsls r3, r3, #4 + 8004154: 4313 orrs r3, r2 + 8004156: 68fa ldr r2, [r7, #12] + 8004158: 4313 orrs r3, r2 + 800415a: 60fb str r3, [r7, #12] + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 800415c: 687b ldr r3, [r7, #4] + 800415e: 681b ldr r3, [r3, #0] + 8004160: 697a ldr r2, [r7, #20] + 8004162: 609a str r2, [r3, #8] + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + 8004164: 687b ldr r3, [r7, #4] + 8004166: 681b ldr r3, [r3, #0] + 8004168: 693a ldr r2, [r7, #16] + 800416a: 619a str r2, [r3, #24] + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + 800416c: 687b ldr r3, [r7, #4] + 800416e: 681b ldr r3, [r3, #0] + 8004170: 68fa ldr r2, [r7, #12] + 8004172: 621a str r2, [r3, #32] + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8004174: 687b ldr r3, [r7, #4] + 8004176: 2201 movs r2, #1 + 8004178: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 800417c: 2300 movs r3, #0 +} + 800417e: 4618 mov r0, r3 + 8004180: 3718 adds r7, #24 + 8004182: 46bd mov sp, r7 + 8004184: bd80 pop {r7, pc} + +08004186 : + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 8004186: b580 push {r7, lr} + 8004188: b082 sub sp, #8 + 800418a: af00 add r7, sp, #0 + 800418c: 6078 str r0, [r7, #4] + 800418e: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + 8004190: 683b ldr r3, [r7, #0] + 8004192: 2b00 cmp r3, #0 + 8004194: d002 beq.n 800419c + 8004196: 2b04 cmp r3, #4 + 8004198: d008 beq.n 80041ac + 800419a: e00f b.n 80041bc + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 800419c: 687b ldr r3, [r7, #4] + 800419e: 681b ldr r3, [r3, #0] + 80041a0: 2201 movs r2, #1 + 80041a2: 2100 movs r1, #0 + 80041a4: 4618 mov r0, r3 + 80041a6: f000 f887 bl 80042b8 + break; + 80041aa: e016 b.n 80041da + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 80041ac: 687b ldr r3, [r7, #4] + 80041ae: 681b ldr r3, [r3, #0] + 80041b0: 2201 movs r2, #1 + 80041b2: 2104 movs r1, #4 + 80041b4: 4618 mov r0, r3 + 80041b6: f000 f87f bl 80042b8 + break; + 80041ba: e00e b.n 80041da + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 80041bc: 687b ldr r3, [r7, #4] + 80041be: 681b ldr r3, [r3, #0] + 80041c0: 2201 movs r2, #1 + 80041c2: 2100 movs r1, #0 + 80041c4: 4618 mov r0, r3 + 80041c6: f000 f877 bl 80042b8 + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 80041ca: 687b ldr r3, [r7, #4] + 80041cc: 681b ldr r3, [r3, #0] + 80041ce: 2201 movs r2, #1 + 80041d0: 2104 movs r1, #4 + 80041d2: 4618 mov r0, r3 + 80041d4: f000 f870 bl 80042b8 + break; + 80041d8: bf00 nop + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + 80041da: 687b ldr r3, [r7, #4] + 80041dc: 681b ldr r3, [r3, #0] + 80041de: 681a ldr r2, [r3, #0] + 80041e0: 687b ldr r3, [r7, #4] + 80041e2: 681b ldr r3, [r3, #0] + 80041e4: f042 0201 orr.w r2, r2, #1 + 80041e8: 601a str r2, [r3, #0] + + /* Return function status */ + return HAL_OK; + 80041ea: 2300 movs r3, #0 +} + 80041ec: 4618 mov r0, r3 + 80041ee: 3708 adds r7, #8 + 80041f0: 46bd mov sp, r7 + 80041f2: bd80 pop {r7, pc} + +080041f4 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + 80041f4: b480 push {r7} + 80041f6: b085 sub sp, #20 + 80041f8: af00 add r7, sp, #0 + 80041fa: 6078 str r0, [r7, #4] + 80041fc: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 80041fe: 687b ldr r3, [r7, #4] + 8004200: 681b ldr r3, [r3, #0] + 8004202: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 8004204: 687b ldr r3, [r7, #4] + 8004206: 4a29 ldr r2, [pc, #164] ; (80042ac ) + 8004208: 4293 cmp r3, r2 + 800420a: d00b beq.n 8004224 + 800420c: 687b ldr r3, [r7, #4] + 800420e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8004212: d007 beq.n 8004224 + 8004214: 687b ldr r3, [r7, #4] + 8004216: 4a26 ldr r2, [pc, #152] ; (80042b0 ) + 8004218: 4293 cmp r3, r2 + 800421a: d003 beq.n 8004224 + 800421c: 687b ldr r3, [r7, #4] + 800421e: 4a25 ldr r2, [pc, #148] ; (80042b4 ) + 8004220: 4293 cmp r3, r2 + 8004222: d108 bne.n 8004236 + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 8004224: 68fb ldr r3, [r7, #12] + 8004226: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800422a: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 800422c: 683b ldr r3, [r7, #0] + 800422e: 685b ldr r3, [r3, #4] + 8004230: 68fa ldr r2, [r7, #12] + 8004232: 4313 orrs r3, r2 + 8004234: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 8004236: 687b ldr r3, [r7, #4] + 8004238: 4a1c ldr r2, [pc, #112] ; (80042ac ) + 800423a: 4293 cmp r3, r2 + 800423c: d00b beq.n 8004256 + 800423e: 687b ldr r3, [r7, #4] + 8004240: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8004244: d007 beq.n 8004256 + 8004246: 687b ldr r3, [r7, #4] + 8004248: 4a19 ldr r2, [pc, #100] ; (80042b0 ) + 800424a: 4293 cmp r3, r2 + 800424c: d003 beq.n 8004256 + 800424e: 687b ldr r3, [r7, #4] + 8004250: 4a18 ldr r2, [pc, #96] ; (80042b4 ) + 8004252: 4293 cmp r3, r2 + 8004254: d108 bne.n 8004268 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 8004256: 68fb ldr r3, [r7, #12] + 8004258: f423 7340 bic.w r3, r3, #768 ; 0x300 + 800425c: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 800425e: 683b ldr r3, [r7, #0] + 8004260: 68db ldr r3, [r3, #12] + 8004262: 68fa ldr r2, [r7, #12] + 8004264: 4313 orrs r3, r2 + 8004266: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8004268: 68fb ldr r3, [r7, #12] + 800426a: f023 0280 bic.w r2, r3, #128 ; 0x80 + 800426e: 683b ldr r3, [r7, #0] + 8004270: 695b ldr r3, [r3, #20] + 8004272: 4313 orrs r3, r2 + 8004274: 60fb str r3, [r7, #12] + + TIMx->CR1 = tmpcr1; + 8004276: 687b ldr r3, [r7, #4] + 8004278: 68fa ldr r2, [r7, #12] + 800427a: 601a str r2, [r3, #0] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 800427c: 683b ldr r3, [r7, #0] + 800427e: 689a ldr r2, [r3, #8] + 8004280: 687b ldr r3, [r7, #4] + 8004282: 62da str r2, [r3, #44] ; 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8004284: 683b ldr r3, [r7, #0] + 8004286: 681a ldr r2, [r3, #0] + 8004288: 687b ldr r3, [r7, #4] + 800428a: 629a str r2, [r3, #40] ; 0x28 + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 800428c: 687b ldr r3, [r7, #4] + 800428e: 4a07 ldr r2, [pc, #28] ; (80042ac ) + 8004290: 4293 cmp r3, r2 + 8004292: d103 bne.n 800429c + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + 8004294: 683b ldr r3, [r7, #0] + 8004296: 691a ldr r2, [r3, #16] + 8004298: 687b ldr r3, [r7, #4] + 800429a: 631a str r2, [r3, #48] ; 0x30 + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 800429c: 687b ldr r3, [r7, #4] + 800429e: 2201 movs r2, #1 + 80042a0: 615a str r2, [r3, #20] +} + 80042a2: bf00 nop + 80042a4: 3714 adds r7, #20 + 80042a6: 46bd mov sp, r7 + 80042a8: bc80 pop {r7} + 80042aa: 4770 bx lr + 80042ac: 40012c00 .word 0x40012c00 + 80042b0: 40000400 .word 0x40000400 + 80042b4: 40000800 .word 0x40000800 + +080042b8 : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 80042b8: b480 push {r7} + 80042ba: b087 sub sp, #28 + 80042bc: af00 add r7, sp, #0 + 80042be: 60f8 str r0, [r7, #12] + 80042c0: 60b9 str r1, [r7, #8] + 80042c2: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 80042c4: 68bb ldr r3, [r7, #8] + 80042c6: f003 031f and.w r3, r3, #31 + 80042ca: 2201 movs r2, #1 + 80042cc: fa02 f303 lsl.w r3, r2, r3 + 80042d0: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 80042d2: 68fb ldr r3, [r7, #12] + 80042d4: 6a1a ldr r2, [r3, #32] + 80042d6: 697b ldr r3, [r7, #20] + 80042d8: 43db mvns r3, r3 + 80042da: 401a ands r2, r3 + 80042dc: 68fb ldr r3, [r7, #12] + 80042de: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 80042e0: 68fb ldr r3, [r7, #12] + 80042e2: 6a1a ldr r2, [r3, #32] + 80042e4: 68bb ldr r3, [r7, #8] + 80042e6: f003 031f and.w r3, r3, #31 + 80042ea: 6879 ldr r1, [r7, #4] + 80042ec: fa01 f303 lsl.w r3, r1, r3 + 80042f0: 431a orrs r2, r3 + 80042f2: 68fb ldr r3, [r7, #12] + 80042f4: 621a str r2, [r3, #32] +} + 80042f6: bf00 nop + 80042f8: 371c adds r7, #28 + 80042fa: 46bd mov sp, r7 + 80042fc: bc80 pop {r7} + 80042fe: 4770 bx lr + +08004300 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + 8004300: b480 push {r7} + 8004302: b085 sub sp, #20 + 8004304: af00 add r7, sp, #0 + 8004306: 6078 str r0, [r7, #4] + 8004308: 6039 str r1, [r7, #0] + assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 800430a: 687b ldr r3, [r7, #4] + 800430c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8004310: 2b01 cmp r3, #1 + 8004312: d101 bne.n 8004318 + 8004314: 2302 movs r3, #2 + 8004316: e032 b.n 800437e + 8004318: 687b ldr r3, [r7, #4] + 800431a: 2201 movs r2, #1 + 800431c: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 8004320: 687b ldr r3, [r7, #4] + 8004322: 2202 movs r2, #2 + 8004324: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 8004328: 687b ldr r3, [r7, #4] + 800432a: 681b ldr r3, [r3, #0] + 800432c: 685b ldr r3, [r3, #4] + 800432e: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8004330: 687b ldr r3, [r7, #4] + 8004332: 681b ldr r3, [r3, #0] + 8004334: 689b ldr r3, [r3, #8] + 8004336: 60bb str r3, [r7, #8] + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8004338: 68fb ldr r3, [r7, #12] + 800433a: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800433e: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8004340: 683b ldr r3, [r7, #0] + 8004342: 681b ldr r3, [r3, #0] + 8004344: 68fa ldr r2, [r7, #12] + 8004346: 4313 orrs r3, r2 + 8004348: 60fb str r3, [r7, #12] + + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 800434a: 68bb ldr r3, [r7, #8] + 800434c: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8004350: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 8004352: 683b ldr r3, [r7, #0] + 8004354: 685b ldr r3, [r3, #4] + 8004356: 68ba ldr r2, [r7, #8] + 8004358: 4313 orrs r3, r2 + 800435a: 60bb str r3, [r7, #8] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 800435c: 687b ldr r3, [r7, #4] + 800435e: 681b ldr r3, [r3, #0] + 8004360: 68fa ldr r2, [r7, #12] + 8004362: 605a str r2, [r3, #4] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8004364: 687b ldr r3, [r7, #4] + 8004366: 681b ldr r3, [r3, #0] + 8004368: 68ba ldr r2, [r7, #8] + 800436a: 609a str r2, [r3, #8] + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 800436c: 687b ldr r3, [r7, #4] + 800436e: 2201 movs r2, #1 + 8004370: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8004374: 687b ldr r3, [r7, #4] + 8004376: 2200 movs r2, #0 + 8004378: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 800437c: 2300 movs r3, #0 +} + 800437e: 4618 mov r0, r3 + 8004380: 3714 adds r7, #20 + 8004382: 46bd mov sp, r7 + 8004384: bc80 pop {r7} + 8004386: 4770 bx lr + +08004388 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 8004388: b580 push {r7, lr} + 800438a: b082 sub sp, #8 + 800438c: af00 add r7, sp, #0 + 800438e: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 8004390: 687b ldr r3, [r7, #4] + 8004392: 2b00 cmp r3, #0 + 8004394: d101 bne.n 800439a + { + return HAL_ERROR; + 8004396: 2301 movs r3, #1 + 8004398: e03f b.n 800441a + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + 800439a: 687b ldr r3, [r7, #4] + 800439c: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 + 80043a0: b2db uxtb r3, r3 + 80043a2: 2b00 cmp r3, #0 + 80043a4: d106 bne.n 80043b4 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 80043a6: 687b ldr r3, [r7, #4] + 80043a8: 2200 movs r2, #0 + 80043aa: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 80043ae: 6878 ldr r0, [r7, #4] + 80043b0: f005 feee bl 800a190 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 80043b4: 687b ldr r3, [r7, #4] + 80043b6: 2224 movs r2, #36 ; 0x24 + 80043b8: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + 80043bc: 687b ldr r3, [r7, #4] + 80043be: 681b ldr r3, [r3, #0] + 80043c0: 68da ldr r2, [r3, #12] + 80043c2: 687b ldr r3, [r7, #4] + 80043c4: 681b ldr r3, [r3, #0] + 80043c6: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 80043ca: 60da str r2, [r3, #12] + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + 80043cc: 6878 ldr r0, [r7, #4] + 80043ce: f000 f829 bl 8004424 + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 80043d2: 687b ldr r3, [r7, #4] + 80043d4: 681b ldr r3, [r3, #0] + 80043d6: 691a ldr r2, [r3, #16] + 80043d8: 687b ldr r3, [r7, #4] + 80043da: 681b ldr r3, [r3, #0] + 80043dc: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 80043e0: 611a str r2, [r3, #16] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 80043e2: 687b ldr r3, [r7, #4] + 80043e4: 681b ldr r3, [r3, #0] + 80043e6: 695a ldr r2, [r3, #20] + 80043e8: 687b ldr r3, [r7, #4] + 80043ea: 681b ldr r3, [r3, #0] + 80043ec: f022 022a bic.w r2, r2, #42 ; 0x2a + 80043f0: 615a str r2, [r3, #20] + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + 80043f2: 687b ldr r3, [r7, #4] + 80043f4: 681b ldr r3, [r3, #0] + 80043f6: 68da ldr r2, [r3, #12] + 80043f8: 687b ldr r3, [r7, #4] + 80043fa: 681b ldr r3, [r3, #0] + 80043fc: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 8004400: 60da str r2, [r3, #12] + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8004402: 687b ldr r3, [r7, #4] + 8004404: 2200 movs r2, #0 + 8004406: 63da str r2, [r3, #60] ; 0x3c + huart->gState = HAL_UART_STATE_READY; + 8004408: 687b ldr r3, [r7, #4] + 800440a: 2220 movs r2, #32 + 800440c: f883 2039 strb.w r2, [r3, #57] ; 0x39 + huart->RxState = HAL_UART_STATE_READY; + 8004410: 687b ldr r3, [r7, #4] + 8004412: 2220 movs r2, #32 + 8004414: f883 203a strb.w r2, [r3, #58] ; 0x3a + + return HAL_OK; + 8004418: 2300 movs r3, #0 +} + 800441a: 4618 mov r0, r3 + 800441c: 3708 adds r7, #8 + 800441e: 46bd mov sp, r7 + 8004420: bd80 pop {r7, pc} + ... + +08004424 : + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8004424: b580 push {r7, lr} + 8004426: b084 sub sp, #16 + 8004428: af00 add r7, sp, #0 + 800442a: 6078 str r0, [r7, #4] + assert_param(IS_UART_MODE(huart->Init.Mode)); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits + according to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 800442c: 687b ldr r3, [r7, #4] + 800442e: 681b ldr r3, [r3, #0] + 8004430: 691b ldr r3, [r3, #16] + 8004432: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8004436: 687b ldr r3, [r7, #4] + 8004438: 68da ldr r2, [r3, #12] + 800443a: 687b ldr r3, [r7, #4] + 800443c: 681b ldr r3, [r3, #0] + 800443e: 430a orrs r2, r1 + 8004440: 611a str r2, [r3, #16] + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); +#else + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; + 8004442: 687b ldr r3, [r7, #4] + 8004444: 689a ldr r2, [r3, #8] + 8004446: 687b ldr r3, [r7, #4] + 8004448: 691b ldr r3, [r3, #16] + 800444a: 431a orrs r2, r3 + 800444c: 687b ldr r3, [r7, #4] + 800444e: 695b ldr r3, [r3, #20] + 8004450: 4313 orrs r3, r2 + 8004452: 60fb str r3, [r7, #12] + MODIFY_REG(huart->Instance->CR1, + 8004454: 687b ldr r3, [r7, #4] + 8004456: 681b ldr r3, [r3, #0] + 8004458: 68db ldr r3, [r3, #12] + 800445a: f423 53b0 bic.w r3, r3, #5632 ; 0x1600 + 800445e: f023 030c bic.w r3, r3, #12 + 8004462: 687a ldr r2, [r7, #4] + 8004464: 6812 ldr r2, [r2, #0] + 8004466: 68f9 ldr r1, [r7, #12] + 8004468: 430b orrs r3, r1 + 800446a: 60d3 str r3, [r2, #12] + tmpreg); +#endif /* USART_CR1_OVER8 */ + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); + 800446c: 687b ldr r3, [r7, #4] + 800446e: 681b ldr r3, [r3, #0] + 8004470: 695b ldr r3, [r3, #20] + 8004472: f423 7140 bic.w r1, r3, #768 ; 0x300 + 8004476: 687b ldr r3, [r7, #4] + 8004478: 699a ldr r2, [r3, #24] + 800447a: 687b ldr r3, [r7, #4] + 800447c: 681b ldr r3, [r3, #0] + 800447e: 430a orrs r2, r1 + 8004480: 615a str r2, [r3, #20] + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } + } +#else + /*-------------------------- USART BRR Configuration ---------------------*/ + if(huart->Instance == USART1) + 8004482: 687b ldr r3, [r7, #4] + 8004484: 681b ldr r3, [r3, #0] + 8004486: 4a52 ldr r2, [pc, #328] ; (80045d0 ) + 8004488: 4293 cmp r3, r2 + 800448a: d14e bne.n 800452a + { + pclk = HAL_RCC_GetPCLK2Freq(); + 800448c: f7fe fcce bl 8002e2c + 8004490: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + 8004492: 68ba ldr r2, [r7, #8] + 8004494: 4613 mov r3, r2 + 8004496: 009b lsls r3, r3, #2 + 8004498: 4413 add r3, r2 + 800449a: 009a lsls r2, r3, #2 + 800449c: 441a add r2, r3 + 800449e: 687b ldr r3, [r7, #4] + 80044a0: 685b ldr r3, [r3, #4] + 80044a2: 009b lsls r3, r3, #2 + 80044a4: fbb2 f3f3 udiv r3, r2, r3 + 80044a8: 4a4a ldr r2, [pc, #296] ; (80045d4 ) + 80044aa: fba2 2303 umull r2, r3, r2, r3 + 80044ae: 095b lsrs r3, r3, #5 + 80044b0: 0119 lsls r1, r3, #4 + 80044b2: 68ba ldr r2, [r7, #8] + 80044b4: 4613 mov r3, r2 + 80044b6: 009b lsls r3, r3, #2 + 80044b8: 4413 add r3, r2 + 80044ba: 009a lsls r2, r3, #2 + 80044bc: 441a add r2, r3 + 80044be: 687b ldr r3, [r7, #4] + 80044c0: 685b ldr r3, [r3, #4] + 80044c2: 009b lsls r3, r3, #2 + 80044c4: fbb2 f2f3 udiv r2, r2, r3 + 80044c8: 4b42 ldr r3, [pc, #264] ; (80045d4 ) + 80044ca: fba3 0302 umull r0, r3, r3, r2 + 80044ce: 095b lsrs r3, r3, #5 + 80044d0: 2064 movs r0, #100 ; 0x64 + 80044d2: fb00 f303 mul.w r3, r0, r3 + 80044d6: 1ad3 subs r3, r2, r3 + 80044d8: 011b lsls r3, r3, #4 + 80044da: 3332 adds r3, #50 ; 0x32 + 80044dc: 4a3d ldr r2, [pc, #244] ; (80045d4 ) + 80044de: fba2 2303 umull r2, r3, r2, r3 + 80044e2: 095b lsrs r3, r3, #5 + 80044e4: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 80044e8: 4419 add r1, r3 + 80044ea: 68ba ldr r2, [r7, #8] + 80044ec: 4613 mov r3, r2 + 80044ee: 009b lsls r3, r3, #2 + 80044f0: 4413 add r3, r2 + 80044f2: 009a lsls r2, r3, #2 + 80044f4: 441a add r2, r3 + 80044f6: 687b ldr r3, [r7, #4] + 80044f8: 685b ldr r3, [r3, #4] + 80044fa: 009b lsls r3, r3, #2 + 80044fc: fbb2 f2f3 udiv r2, r2, r3 + 8004500: 4b34 ldr r3, [pc, #208] ; (80045d4 ) + 8004502: fba3 0302 umull r0, r3, r3, r2 + 8004506: 095b lsrs r3, r3, #5 + 8004508: 2064 movs r0, #100 ; 0x64 + 800450a: fb00 f303 mul.w r3, r0, r3 + 800450e: 1ad3 subs r3, r2, r3 + 8004510: 011b lsls r3, r3, #4 + 8004512: 3332 adds r3, #50 ; 0x32 + 8004514: 4a2f ldr r2, [pc, #188] ; (80045d4 ) + 8004516: fba2 2303 umull r2, r3, r2, r3 + 800451a: 095b lsrs r3, r3, #5 + 800451c: f003 020f and.w r2, r3, #15 + 8004520: 687b ldr r3, [r7, #4] + 8004522: 681b ldr r3, [r3, #0] + 8004524: 440a add r2, r1 + 8004526: 609a str r2, [r3, #8] + { + pclk = HAL_RCC_GetPCLK1Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } +#endif /* USART_CR1_OVER8 */ +} + 8004528: e04d b.n 80045c6 + pclk = HAL_RCC_GetPCLK1Freq(); + 800452a: f7fe fc6b bl 8002e04 + 800452e: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + 8004530: 68ba ldr r2, [r7, #8] + 8004532: 4613 mov r3, r2 + 8004534: 009b lsls r3, r3, #2 + 8004536: 4413 add r3, r2 + 8004538: 009a lsls r2, r3, #2 + 800453a: 441a add r2, r3 + 800453c: 687b ldr r3, [r7, #4] + 800453e: 685b ldr r3, [r3, #4] + 8004540: 009b lsls r3, r3, #2 + 8004542: fbb2 f3f3 udiv r3, r2, r3 + 8004546: 4a23 ldr r2, [pc, #140] ; (80045d4 ) + 8004548: fba2 2303 umull r2, r3, r2, r3 + 800454c: 095b lsrs r3, r3, #5 + 800454e: 0119 lsls r1, r3, #4 + 8004550: 68ba ldr r2, [r7, #8] + 8004552: 4613 mov r3, r2 + 8004554: 009b lsls r3, r3, #2 + 8004556: 4413 add r3, r2 + 8004558: 009a lsls r2, r3, #2 + 800455a: 441a add r2, r3 + 800455c: 687b ldr r3, [r7, #4] + 800455e: 685b ldr r3, [r3, #4] + 8004560: 009b lsls r3, r3, #2 + 8004562: fbb2 f2f3 udiv r2, r2, r3 + 8004566: 4b1b ldr r3, [pc, #108] ; (80045d4 ) + 8004568: fba3 0302 umull r0, r3, r3, r2 + 800456c: 095b lsrs r3, r3, #5 + 800456e: 2064 movs r0, #100 ; 0x64 + 8004570: fb00 f303 mul.w r3, r0, r3 + 8004574: 1ad3 subs r3, r2, r3 + 8004576: 011b lsls r3, r3, #4 + 8004578: 3332 adds r3, #50 ; 0x32 + 800457a: 4a16 ldr r2, [pc, #88] ; (80045d4 ) + 800457c: fba2 2303 umull r2, r3, r2, r3 + 8004580: 095b lsrs r3, r3, #5 + 8004582: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8004586: 4419 add r1, r3 + 8004588: 68ba ldr r2, [r7, #8] + 800458a: 4613 mov r3, r2 + 800458c: 009b lsls r3, r3, #2 + 800458e: 4413 add r3, r2 + 8004590: 009a lsls r2, r3, #2 + 8004592: 441a add r2, r3 + 8004594: 687b ldr r3, [r7, #4] + 8004596: 685b ldr r3, [r3, #4] + 8004598: 009b lsls r3, r3, #2 + 800459a: fbb2 f2f3 udiv r2, r2, r3 + 800459e: 4b0d ldr r3, [pc, #52] ; (80045d4 ) + 80045a0: fba3 0302 umull r0, r3, r3, r2 + 80045a4: 095b lsrs r3, r3, #5 + 80045a6: 2064 movs r0, #100 ; 0x64 + 80045a8: fb00 f303 mul.w r3, r0, r3 + 80045ac: 1ad3 subs r3, r2, r3 + 80045ae: 011b lsls r3, r3, #4 + 80045b0: 3332 adds r3, #50 ; 0x32 + 80045b2: 4a08 ldr r2, [pc, #32] ; (80045d4 ) + 80045b4: fba2 2303 umull r2, r3, r2, r3 + 80045b8: 095b lsrs r3, r3, #5 + 80045ba: f003 020f and.w r2, r3, #15 + 80045be: 687b ldr r3, [r7, #4] + 80045c0: 681b ldr r3, [r3, #0] + 80045c2: 440a add r2, r1 + 80045c4: 609a str r2, [r3, #8] +} + 80045c6: bf00 nop + 80045c8: 3710 adds r7, #16 + 80045ca: 46bd mov sp, r7 + 80045cc: bd80 pop {r7, pc} + 80045ce: bf00 nop + 80045d0: 40013800 .word 0x40013800 + 80045d4: 51eb851f .word 0x51eb851f + +080045d8 : + * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) +{ + 80045d8: b084 sub sp, #16 + 80045da: b480 push {r7} + 80045dc: b083 sub sp, #12 + 80045de: af00 add r7, sp, #0 + 80045e0: 6078 str r0, [r7, #4] + 80045e2: f107 0014 add.w r0, r7, #20 + 80045e6: e880 000e stmia.w r0, {r1, r2, r3} + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; + 80045ea: 2300 movs r3, #0 +} + 80045ec: 4618 mov r0, r3 + 80045ee: 370c adds r7, #12 + 80045f0: 46bd mov sp, r7 + 80045f2: bc80 pop {r7} + 80045f4: b004 add sp, #16 + 80045f6: 4770 bx lr + +080045f8 : + * Enables the controller's Global Int in the AHB Config reg + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) +{ + 80045f8: b480 push {r7} + 80045fa: b085 sub sp, #20 + 80045fc: af00 add r7, sp, #0 + 80045fe: 6078 str r0, [r7, #4] + uint16_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + 8004600: f44f 433f mov.w r3, #48896 ; 0xbf00 + 8004604: 81fb strh r3, [r7, #14] + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM; + + /* Set interrupt mask */ + USBx->CNTR |= winterruptmask; + 8004606: 687b ldr r3, [r7, #4] + 8004608: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 800460c: b29a uxth r2, r3 + 800460e: 89fb ldrh r3, [r7, #14] + 8004610: 4313 orrs r3, r2 + 8004612: b29a uxth r2, r3 + 8004614: 687b ldr r3, [r7, #4] + 8004616: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 800461a: 2300 movs r3, #0 +} + 800461c: 4618 mov r0, r3 + 800461e: 3714 adds r7, #20 + 8004620: 46bd mov sp, r7 + 8004622: bc80 pop {r7} + 8004624: 4770 bx lr + +08004626 : + * Disable the controller's Global Int in the AHB Config reg + * @param USBx : Selected device + * @retval HAL status +*/ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) +{ + 8004626: b480 push {r7} + 8004628: b085 sub sp, #20 + 800462a: af00 add r7, sp, #0 + 800462c: 6078 str r0, [r7, #4] + uint16_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + 800462e: f44f 433f mov.w r3, #48896 ; 0xbf00 + 8004632: 81fb strh r3, [r7, #14] + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM; + + /* Clear interrupt mask */ + USBx->CNTR &= ~winterruptmask; + 8004634: 687b ldr r3, [r7, #4] + 8004636: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 800463a: b29b uxth r3, r3 + 800463c: b21a sxth r2, r3 + 800463e: f9b7 300e ldrsh.w r3, [r7, #14] + 8004642: 43db mvns r3, r3 + 8004644: b21b sxth r3, r3 + 8004646: 4013 ands r3, r2 + 8004648: b21b sxth r3, r3 + 800464a: b29a uxth r2, r3 + 800464c: 687b ldr r3, [r7, #4] + 800464e: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8004652: 2300 movs r3, #0 +} + 8004654: 4618 mov r0, r3 + 8004656: 3714 adds r7, #20 + 8004658: 46bd mov sp, r7 + 800465a: bc80 pop {r7} + 800465c: 4770 bx lr + +0800465e : + * This parameter can be one of the these values: + * @arg USB_DEVICE_MODE: Peripheral mode mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) +{ + 800465e: b480 push {r7} + 8004660: b083 sub sp, #12 + 8004662: af00 add r7, sp, #0 + 8004664: 6078 str r0, [r7, #4] + 8004666: 460b mov r3, r1 + 8004668: 70fb strb r3, [r7, #3] + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; + 800466a: 2300 movs r3, #0 +} + 800466c: 4618 mov r0, r3 + 800466e: 370c adds r7, #12 + 8004670: 46bd mov sp, r7 + 8004672: bc80 pop {r7} + 8004674: 4770 bx lr + +08004676 : + * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) +{ + 8004676: b084 sub sp, #16 + 8004678: b580 push {r7, lr} + 800467a: b082 sub sp, #8 + 800467c: af00 add r7, sp, #0 + 800467e: 6078 str r0, [r7, #4] + 8004680: f107 0014 add.w r0, r7, #20 + 8004684: e880 000e stmia.w r0, {r1, r2, r3} + /* Prevent unused argument(s) compilation warning */ + UNUSED(cfg); + + /* Init Device */ + /*CNTR_FRES = 1*/ + USBx->CNTR = USB_CNTR_FRES; + 8004688: 687b ldr r3, [r7, #4] + 800468a: 2201 movs r2, #1 + 800468c: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + /*CNTR_FRES = 0*/ + USBx->CNTR = 0; + 8004690: 687b ldr r3, [r7, #4] + 8004692: 2200 movs r2, #0 + 8004694: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + /*Clear pending interrupts*/ + USBx->ISTR = 0; + 8004698: 687b ldr r3, [r7, #4] + 800469a: 2200 movs r2, #0 + 800469c: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + + /*Set Btable Address*/ + USBx->BTABLE = BTABLE_ADDRESS; + 80046a0: 687b ldr r3, [r7, #4] + 80046a2: 2200 movs r2, #0 + 80046a4: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 + + /* Enable USB Device Interrupt mask */ + (void)USB_EnableGlobalInt(USBx); + 80046a8: 6878 ldr r0, [r7, #4] + 80046aa: f7ff ffa5 bl 80045f8 + + return HAL_OK; + 80046ae: 2300 movs r3, #0 +} + 80046b0: 4618 mov r0, r3 + 80046b2: 3708 adds r7, #8 + 80046b4: 46bd mov sp, r7 + 80046b6: e8bd 4080 ldmia.w sp!, {r7, lr} + 80046ba: b004 add sp, #16 + 80046bc: 4770 bx lr + ... + +080046c0 : + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + 80046c0: b490 push {r4, r7} + 80046c2: b084 sub sp, #16 + 80046c4: af00 add r7, sp, #0 + 80046c6: 6078 str r0, [r7, #4] + 80046c8: 6039 str r1, [r7, #0] + HAL_StatusTypeDef ret = HAL_OK; + 80046ca: 2300 movs r3, #0 + 80046cc: 73fb strb r3, [r7, #15] + uint16_t wEpRegVal; + + wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; + 80046ce: 687a ldr r2, [r7, #4] + 80046d0: 683b ldr r3, [r7, #0] + 80046d2: 781b ldrb r3, [r3, #0] + 80046d4: 009b lsls r3, r3, #2 + 80046d6: 4413 add r3, r2 + 80046d8: 881b ldrh r3, [r3, #0] + 80046da: b29b uxth r3, r3 + 80046dc: f423 43ec bic.w r3, r3, #30208 ; 0x7600 + 80046e0: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80046e4: 81bb strh r3, [r7, #12] + + /* initialize Endpoint */ + switch (ep->type) + 80046e6: 683b ldr r3, [r7, #0] + 80046e8: 78db ldrb r3, [r3, #3] + 80046ea: 2b03 cmp r3, #3 + 80046ec: d819 bhi.n 8004722 + 80046ee: a201 add r2, pc, #4 ; (adr r2, 80046f4 ) + 80046f0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80046f4: 08004705 .word 0x08004705 + 80046f8: 08004719 .word 0x08004719 + 80046fc: 08004729 .word 0x08004729 + 8004700: 0800470f .word 0x0800470f + { + case EP_TYPE_CTRL: + wEpRegVal |= USB_EP_CONTROL; + 8004704: 89bb ldrh r3, [r7, #12] + 8004706: f443 7300 orr.w r3, r3, #512 ; 0x200 + 800470a: 81bb strh r3, [r7, #12] + break; + 800470c: e00d b.n 800472a + case EP_TYPE_BULK: + wEpRegVal |= USB_EP_BULK; + break; + + case EP_TYPE_INTR: + wEpRegVal |= USB_EP_INTERRUPT; + 800470e: 89bb ldrh r3, [r7, #12] + 8004710: f443 63c0 orr.w r3, r3, #1536 ; 0x600 + 8004714: 81bb strh r3, [r7, #12] + break; + 8004716: e008 b.n 800472a + + case EP_TYPE_ISOC: + wEpRegVal |= USB_EP_ISOCHRONOUS; + 8004718: 89bb ldrh r3, [r7, #12] + 800471a: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 800471e: 81bb strh r3, [r7, #12] + break; + 8004720: e003 b.n 800472a + + default: + ret = HAL_ERROR; + 8004722: 2301 movs r3, #1 + 8004724: 73fb strb r3, [r7, #15] + break; + 8004726: e000 b.n 800472a + break; + 8004728: bf00 nop + } + + PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX); + 800472a: 687a ldr r2, [r7, #4] + 800472c: 683b ldr r3, [r7, #0] + 800472e: 781b ldrb r3, [r3, #0] + 8004730: 009b lsls r3, r3, #2 + 8004732: 441a add r2, r3 + 8004734: 89bb ldrh r3, [r7, #12] + 8004736: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800473a: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800473e: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8004742: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8004746: b29b uxth r3, r3 + 8004748: 8013 strh r3, [r2, #0] + + PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); + 800474a: 687a ldr r2, [r7, #4] + 800474c: 683b ldr r3, [r7, #0] + 800474e: 781b ldrb r3, [r3, #0] + 8004750: 009b lsls r3, r3, #2 + 8004752: 4413 add r3, r2 + 8004754: 881b ldrh r3, [r3, #0] + 8004756: b29b uxth r3, r3 + 8004758: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800475c: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004760: b29a uxth r2, r3 + 8004762: 683b ldr r3, [r7, #0] + 8004764: 781b ldrb r3, [r3, #0] + 8004766: b29b uxth r3, r3 + 8004768: 4313 orrs r3, r2 + 800476a: b29c uxth r4, r3 + 800476c: 687a ldr r2, [r7, #4] + 800476e: 683b ldr r3, [r7, #0] + 8004770: 781b ldrb r3, [r3, #0] + 8004772: 009b lsls r3, r3, #2 + 8004774: 441a add r2, r3 + 8004776: 4b8a ldr r3, [pc, #552] ; (80049a0 ) + 8004778: 4323 orrs r3, r4 + 800477a: b29b uxth r3, r3 + 800477c: 8013 strh r3, [r2, #0] + + if (ep->doublebuffer == 0U) + 800477e: 683b ldr r3, [r7, #0] + 8004780: 7b1b ldrb r3, [r3, #12] + 8004782: 2b00 cmp r3, #0 + 8004784: f040 8112 bne.w 80049ac + { + if (ep->is_in != 0U) + 8004788: 683b ldr r3, [r7, #0] + 800478a: 785b ldrb r3, [r3, #1] + 800478c: 2b00 cmp r3, #0 + 800478e: d067 beq.n 8004860 + { + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); + 8004790: 687c ldr r4, [r7, #4] + 8004792: 687b ldr r3, [r7, #4] + 8004794: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8004798: b29b uxth r3, r3 + 800479a: 441c add r4, r3 + 800479c: 683b ldr r3, [r7, #0] + 800479e: 781b ldrb r3, [r3, #0] + 80047a0: 011b lsls r3, r3, #4 + 80047a2: 4423 add r3, r4 + 80047a4: f503 6380 add.w r3, r3, #1024 ; 0x400 + 80047a8: 461c mov r4, r3 + 80047aa: 683b ldr r3, [r7, #0] + 80047ac: 88db ldrh r3, [r3, #6] + 80047ae: 085b lsrs r3, r3, #1 + 80047b0: b29b uxth r3, r3 + 80047b2: 005b lsls r3, r3, #1 + 80047b4: b29b uxth r3, r3 + 80047b6: 8023 strh r3, [r4, #0] + PCD_CLEAR_TX_DTOG(USBx, ep->num); + 80047b8: 687a ldr r2, [r7, #4] + 80047ba: 683b ldr r3, [r7, #0] + 80047bc: 781b ldrb r3, [r3, #0] + 80047be: 009b lsls r3, r3, #2 + 80047c0: 4413 add r3, r2 + 80047c2: 881b ldrh r3, [r3, #0] + 80047c4: b29c uxth r4, r3 + 80047c6: 4623 mov r3, r4 + 80047c8: f003 0340 and.w r3, r3, #64 ; 0x40 + 80047cc: 2b00 cmp r3, #0 + 80047ce: d014 beq.n 80047fa + 80047d0: 687a ldr r2, [r7, #4] + 80047d2: 683b ldr r3, [r7, #0] + 80047d4: 781b ldrb r3, [r3, #0] + 80047d6: 009b lsls r3, r3, #2 + 80047d8: 4413 add r3, r2 + 80047da: 881b ldrh r3, [r3, #0] + 80047dc: b29b uxth r3, r3 + 80047de: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 80047e2: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80047e6: b29c uxth r4, r3 + 80047e8: 687a ldr r2, [r7, #4] + 80047ea: 683b ldr r3, [r7, #0] + 80047ec: 781b ldrb r3, [r3, #0] + 80047ee: 009b lsls r3, r3, #2 + 80047f0: 441a add r2, r3 + 80047f2: 4b6c ldr r3, [pc, #432] ; (80049a4 ) + 80047f4: 4323 orrs r3, r4 + 80047f6: b29b uxth r3, r3 + 80047f8: 8013 strh r3, [r2, #0] + + if (ep->type != EP_TYPE_ISOC) + 80047fa: 683b ldr r3, [r7, #0] + 80047fc: 78db ldrb r3, [r3, #3] + 80047fe: 2b01 cmp r3, #1 + 8004800: d018 beq.n 8004834 + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + 8004802: 687a ldr r2, [r7, #4] + 8004804: 683b ldr r3, [r7, #0] + 8004806: 781b ldrb r3, [r3, #0] + 8004808: 009b lsls r3, r3, #2 + 800480a: 4413 add r3, r2 + 800480c: 881b ldrh r3, [r3, #0] + 800480e: b29b uxth r3, r3 + 8004810: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004814: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8004818: b29c uxth r4, r3 + 800481a: f084 0320 eor.w r3, r4, #32 + 800481e: b29c uxth r4, r3 + 8004820: 687a ldr r2, [r7, #4] + 8004822: 683b ldr r3, [r7, #0] + 8004824: 781b ldrb r3, [r3, #0] + 8004826: 009b lsls r3, r3, #2 + 8004828: 441a add r2, r3 + 800482a: 4b5d ldr r3, [pc, #372] ; (80049a0 ) + 800482c: 4323 orrs r3, r4 + 800482e: b29b uxth r3, r3 + 8004830: 8013 strh r3, [r2, #0] + 8004832: e22b b.n 8004c8c + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + 8004834: 687a ldr r2, [r7, #4] + 8004836: 683b ldr r3, [r7, #0] + 8004838: 781b ldrb r3, [r3, #0] + 800483a: 009b lsls r3, r3, #2 + 800483c: 4413 add r3, r2 + 800483e: 881b ldrh r3, [r3, #0] + 8004840: b29b uxth r3, r3 + 8004842: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004846: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800484a: b29c uxth r4, r3 + 800484c: 687a ldr r2, [r7, #4] + 800484e: 683b ldr r3, [r7, #0] + 8004850: 781b ldrb r3, [r3, #0] + 8004852: 009b lsls r3, r3, #2 + 8004854: 441a add r2, r3 + 8004856: 4b52 ldr r3, [pc, #328] ; (80049a0 ) + 8004858: 4323 orrs r3, r4 + 800485a: b29b uxth r3, r3 + 800485c: 8013 strh r3, [r2, #0] + 800485e: e215 b.n 8004c8c + } + } + else + { + /*Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); + 8004860: 687c ldr r4, [r7, #4] + 8004862: 687b ldr r3, [r7, #4] + 8004864: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8004868: b29b uxth r3, r3 + 800486a: 441c add r4, r3 + 800486c: 683b ldr r3, [r7, #0] + 800486e: 781b ldrb r3, [r3, #0] + 8004870: 011b lsls r3, r3, #4 + 8004872: 4423 add r3, r4 + 8004874: f503 6381 add.w r3, r3, #1032 ; 0x408 + 8004878: 461c mov r4, r3 + 800487a: 683b ldr r3, [r7, #0] + 800487c: 88db ldrh r3, [r3, #6] + 800487e: 085b lsrs r3, r3, #1 + 8004880: b29b uxth r3, r3 + 8004882: 005b lsls r3, r3, #1 + 8004884: b29b uxth r3, r3 + 8004886: 8023 strh r3, [r4, #0] + /*Set the endpoint Receive buffer counter*/ + PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); + 8004888: 687c ldr r4, [r7, #4] + 800488a: 687b ldr r3, [r7, #4] + 800488c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8004890: b29b uxth r3, r3 + 8004892: 441c add r4, r3 + 8004894: 683b ldr r3, [r7, #0] + 8004896: 781b ldrb r3, [r3, #0] + 8004898: 011b lsls r3, r3, #4 + 800489a: 4423 add r3, r4 + 800489c: f203 430c addw r3, r3, #1036 ; 0x40c + 80048a0: 461c mov r4, r3 + 80048a2: 683b ldr r3, [r7, #0] + 80048a4: 691b ldr r3, [r3, #16] + 80048a6: 2b00 cmp r3, #0 + 80048a8: d10e bne.n 80048c8 + 80048aa: 8823 ldrh r3, [r4, #0] + 80048ac: b29b uxth r3, r3 + 80048ae: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00 + 80048b2: b29b uxth r3, r3 + 80048b4: 8023 strh r3, [r4, #0] + 80048b6: 8823 ldrh r3, [r4, #0] + 80048b8: b29b uxth r3, r3 + 80048ba: ea6f 4343 mvn.w r3, r3, lsl #17 + 80048be: ea6f 4353 mvn.w r3, r3, lsr #17 + 80048c2: b29b uxth r3, r3 + 80048c4: 8023 strh r3, [r4, #0] + 80048c6: e02d b.n 8004924 + 80048c8: 683b ldr r3, [r7, #0] + 80048ca: 691b ldr r3, [r3, #16] + 80048cc: 2b3e cmp r3, #62 ; 0x3e + 80048ce: d812 bhi.n 80048f6 + 80048d0: 683b ldr r3, [r7, #0] + 80048d2: 691b ldr r3, [r3, #16] + 80048d4: 085b lsrs r3, r3, #1 + 80048d6: 60bb str r3, [r7, #8] + 80048d8: 683b ldr r3, [r7, #0] + 80048da: 691b ldr r3, [r3, #16] + 80048dc: f003 0301 and.w r3, r3, #1 + 80048e0: 2b00 cmp r3, #0 + 80048e2: d002 beq.n 80048ea + 80048e4: 68bb ldr r3, [r7, #8] + 80048e6: 3301 adds r3, #1 + 80048e8: 60bb str r3, [r7, #8] + 80048ea: 68bb ldr r3, [r7, #8] + 80048ec: b29b uxth r3, r3 + 80048ee: 029b lsls r3, r3, #10 + 80048f0: b29b uxth r3, r3 + 80048f2: 8023 strh r3, [r4, #0] + 80048f4: e016 b.n 8004924 + 80048f6: 683b ldr r3, [r7, #0] + 80048f8: 691b ldr r3, [r3, #16] + 80048fa: 095b lsrs r3, r3, #5 + 80048fc: 60bb str r3, [r7, #8] + 80048fe: 683b ldr r3, [r7, #0] + 8004900: 691b ldr r3, [r3, #16] + 8004902: f003 031f and.w r3, r3, #31 + 8004906: 2b00 cmp r3, #0 + 8004908: d102 bne.n 8004910 + 800490a: 68bb ldr r3, [r7, #8] + 800490c: 3b01 subs r3, #1 + 800490e: 60bb str r3, [r7, #8] + 8004910: 68bb ldr r3, [r7, #8] + 8004912: b29b uxth r3, r3 + 8004914: 029b lsls r3, r3, #10 + 8004916: b29b uxth r3, r3 + 8004918: ea6f 4343 mvn.w r3, r3, lsl #17 + 800491c: ea6f 4353 mvn.w r3, r3, lsr #17 + 8004920: b29b uxth r3, r3 + 8004922: 8023 strh r3, [r4, #0] + PCD_CLEAR_RX_DTOG(USBx, ep->num); + 8004924: 687a ldr r2, [r7, #4] + 8004926: 683b ldr r3, [r7, #0] + 8004928: 781b ldrb r3, [r3, #0] + 800492a: 009b lsls r3, r3, #2 + 800492c: 4413 add r3, r2 + 800492e: 881b ldrh r3, [r3, #0] + 8004930: b29c uxth r4, r3 + 8004932: 4623 mov r3, r4 + 8004934: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8004938: 2b00 cmp r3, #0 + 800493a: d014 beq.n 8004966 + 800493c: 687a ldr r2, [r7, #4] + 800493e: 683b ldr r3, [r7, #0] + 8004940: 781b ldrb r3, [r3, #0] + 8004942: 009b lsls r3, r3, #2 + 8004944: 4413 add r3, r2 + 8004946: 881b ldrh r3, [r3, #0] + 8004948: b29b uxth r3, r3 + 800494a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800494e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004952: b29c uxth r4, r3 + 8004954: 687a ldr r2, [r7, #4] + 8004956: 683b ldr r3, [r7, #0] + 8004958: 781b ldrb r3, [r3, #0] + 800495a: 009b lsls r3, r3, #2 + 800495c: 441a add r2, r3 + 800495e: 4b12 ldr r3, [pc, #72] ; (80049a8 ) + 8004960: 4323 orrs r3, r4 + 8004962: b29b uxth r3, r3 + 8004964: 8013 strh r3, [r2, #0] + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + 8004966: 687a ldr r2, [r7, #4] + 8004968: 683b ldr r3, [r7, #0] + 800496a: 781b ldrb r3, [r3, #0] + 800496c: 009b lsls r3, r3, #2 + 800496e: 4413 add r3, r2 + 8004970: 881b ldrh r3, [r3, #0] + 8004972: b29b uxth r3, r3 + 8004974: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8004978: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800497c: b29c uxth r4, r3 + 800497e: f484 5380 eor.w r3, r4, #4096 ; 0x1000 + 8004982: b29c uxth r4, r3 + 8004984: f484 5300 eor.w r3, r4, #8192 ; 0x2000 + 8004988: b29c uxth r4, r3 + 800498a: 687a ldr r2, [r7, #4] + 800498c: 683b ldr r3, [r7, #0] + 800498e: 781b ldrb r3, [r3, #0] + 8004990: 009b lsls r3, r3, #2 + 8004992: 441a add r2, r3 + 8004994: 4b02 ldr r3, [pc, #8] ; (80049a0 ) + 8004996: 4323 orrs r3, r4 + 8004998: b29b uxth r3, r3 + 800499a: 8013 strh r3, [r2, #0] + 800499c: e176 b.n 8004c8c + 800499e: bf00 nop + 80049a0: ffff8080 .word 0xffff8080 + 80049a4: ffff80c0 .word 0xffff80c0 + 80049a8: ffffc080 .word 0xffffc080 + } + /*Double Buffer*/ + else + { + /* Set the endpoint as double buffered */ + PCD_SET_EP_DBUF(USBx, ep->num); + 80049ac: 687a ldr r2, [r7, #4] + 80049ae: 683b ldr r3, [r7, #0] + 80049b0: 781b ldrb r3, [r3, #0] + 80049b2: 009b lsls r3, r3, #2 + 80049b4: 4413 add r3, r2 + 80049b6: 881b ldrh r3, [r3, #0] + 80049b8: b29b uxth r3, r3 + 80049ba: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 80049be: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80049c2: b29c uxth r4, r3 + 80049c4: 687a ldr r2, [r7, #4] + 80049c6: 683b ldr r3, [r7, #0] + 80049c8: 781b ldrb r3, [r3, #0] + 80049ca: 009b lsls r3, r3, #2 + 80049cc: 441a add r2, r3 + 80049ce: 4b96 ldr r3, [pc, #600] ; (8004c28 ) + 80049d0: 4323 orrs r3, r4 + 80049d2: b29b uxth r3, r3 + 80049d4: 8013 strh r3, [r2, #0] + /* Set buffer address for double buffered mode */ + PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); + 80049d6: 687c ldr r4, [r7, #4] + 80049d8: 687b ldr r3, [r7, #4] + 80049da: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80049de: b29b uxth r3, r3 + 80049e0: 441c add r4, r3 + 80049e2: 683b ldr r3, [r7, #0] + 80049e4: 781b ldrb r3, [r3, #0] + 80049e6: 011b lsls r3, r3, #4 + 80049e8: 4423 add r3, r4 + 80049ea: f503 6380 add.w r3, r3, #1024 ; 0x400 + 80049ee: 461c mov r4, r3 + 80049f0: 683b ldr r3, [r7, #0] + 80049f2: 891b ldrh r3, [r3, #8] + 80049f4: 085b lsrs r3, r3, #1 + 80049f6: b29b uxth r3, r3 + 80049f8: 005b lsls r3, r3, #1 + 80049fa: b29b uxth r3, r3 + 80049fc: 8023 strh r3, [r4, #0] + 80049fe: 687c ldr r4, [r7, #4] + 8004a00: 687b ldr r3, [r7, #4] + 8004a02: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8004a06: b29b uxth r3, r3 + 8004a08: 441c add r4, r3 + 8004a0a: 683b ldr r3, [r7, #0] + 8004a0c: 781b ldrb r3, [r3, #0] + 8004a0e: 011b lsls r3, r3, #4 + 8004a10: 4423 add r3, r4 + 8004a12: f503 6381 add.w r3, r3, #1032 ; 0x408 + 8004a16: 461c mov r4, r3 + 8004a18: 683b ldr r3, [r7, #0] + 8004a1a: 895b ldrh r3, [r3, #10] + 8004a1c: 085b lsrs r3, r3, #1 + 8004a1e: b29b uxth r3, r3 + 8004a20: 005b lsls r3, r3, #1 + 8004a22: b29b uxth r3, r3 + 8004a24: 8023 strh r3, [r4, #0] + + if (ep->is_in == 0U) + 8004a26: 683b ldr r3, [r7, #0] + 8004a28: 785b ldrb r3, [r3, #1] + 8004a2a: 2b00 cmp r3, #0 + 8004a2c: f040 8088 bne.w 8004b40 + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + 8004a30: 687a ldr r2, [r7, #4] + 8004a32: 683b ldr r3, [r7, #0] + 8004a34: 781b ldrb r3, [r3, #0] + 8004a36: 009b lsls r3, r3, #2 + 8004a38: 4413 add r3, r2 + 8004a3a: 881b ldrh r3, [r3, #0] + 8004a3c: b29c uxth r4, r3 + 8004a3e: 4623 mov r3, r4 + 8004a40: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8004a44: 2b00 cmp r3, #0 + 8004a46: d014 beq.n 8004a72 + 8004a48: 687a ldr r2, [r7, #4] + 8004a4a: 683b ldr r3, [r7, #0] + 8004a4c: 781b ldrb r3, [r3, #0] + 8004a4e: 009b lsls r3, r3, #2 + 8004a50: 4413 add r3, r2 + 8004a52: 881b ldrh r3, [r3, #0] + 8004a54: b29b uxth r3, r3 + 8004a56: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004a5a: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004a5e: b29c uxth r4, r3 + 8004a60: 687a ldr r2, [r7, #4] + 8004a62: 683b ldr r3, [r7, #0] + 8004a64: 781b ldrb r3, [r3, #0] + 8004a66: 009b lsls r3, r3, #2 + 8004a68: 441a add r2, r3 + 8004a6a: 4b70 ldr r3, [pc, #448] ; (8004c2c ) + 8004a6c: 4323 orrs r3, r4 + 8004a6e: b29b uxth r3, r3 + 8004a70: 8013 strh r3, [r2, #0] + PCD_CLEAR_TX_DTOG(USBx, ep->num); + 8004a72: 687a ldr r2, [r7, #4] + 8004a74: 683b ldr r3, [r7, #0] + 8004a76: 781b ldrb r3, [r3, #0] + 8004a78: 009b lsls r3, r3, #2 + 8004a7a: 4413 add r3, r2 + 8004a7c: 881b ldrh r3, [r3, #0] + 8004a7e: b29c uxth r4, r3 + 8004a80: 4623 mov r3, r4 + 8004a82: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004a86: 2b00 cmp r3, #0 + 8004a88: d014 beq.n 8004ab4 + 8004a8a: 687a ldr r2, [r7, #4] + 8004a8c: 683b ldr r3, [r7, #0] + 8004a8e: 781b ldrb r3, [r3, #0] + 8004a90: 009b lsls r3, r3, #2 + 8004a92: 4413 add r3, r2 + 8004a94: 881b ldrh r3, [r3, #0] + 8004a96: b29b uxth r3, r3 + 8004a98: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004a9c: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004aa0: b29c uxth r4, r3 + 8004aa2: 687a ldr r2, [r7, #4] + 8004aa4: 683b ldr r3, [r7, #0] + 8004aa6: 781b ldrb r3, [r3, #0] + 8004aa8: 009b lsls r3, r3, #2 + 8004aaa: 441a add r2, r3 + 8004aac: 4b60 ldr r3, [pc, #384] ; (8004c30 ) + 8004aae: 4323 orrs r3, r4 + 8004ab0: b29b uxth r3, r3 + 8004ab2: 8013 strh r3, [r2, #0] + + /* Reset value of the data toggle bits for the endpoint out */ + PCD_TX_DTOG(USBx, ep->num); + 8004ab4: 687a ldr r2, [r7, #4] + 8004ab6: 683b ldr r3, [r7, #0] + 8004ab8: 781b ldrb r3, [r3, #0] + 8004aba: 009b lsls r3, r3, #2 + 8004abc: 4413 add r3, r2 + 8004abe: 881b ldrh r3, [r3, #0] + 8004ac0: b29b uxth r3, r3 + 8004ac2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004ac6: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004aca: b29c uxth r4, r3 + 8004acc: 687a ldr r2, [r7, #4] + 8004ace: 683b ldr r3, [r7, #0] + 8004ad0: 781b ldrb r3, [r3, #0] + 8004ad2: 009b lsls r3, r3, #2 + 8004ad4: 441a add r2, r3 + 8004ad6: 4b56 ldr r3, [pc, #344] ; (8004c30 ) + 8004ad8: 4323 orrs r3, r4 + 8004ada: b29b uxth r3, r3 + 8004adc: 8013 strh r3, [r2, #0] + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + 8004ade: 687a ldr r2, [r7, #4] + 8004ae0: 683b ldr r3, [r7, #0] + 8004ae2: 781b ldrb r3, [r3, #0] + 8004ae4: 009b lsls r3, r3, #2 + 8004ae6: 4413 add r3, r2 + 8004ae8: 881b ldrh r3, [r3, #0] + 8004aea: b29b uxth r3, r3 + 8004aec: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8004af0: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004af4: b29c uxth r4, r3 + 8004af6: f484 5380 eor.w r3, r4, #4096 ; 0x1000 + 8004afa: b29c uxth r4, r3 + 8004afc: f484 5300 eor.w r3, r4, #8192 ; 0x2000 + 8004b00: b29c uxth r4, r3 + 8004b02: 687a ldr r2, [r7, #4] + 8004b04: 683b ldr r3, [r7, #0] + 8004b06: 781b ldrb r3, [r3, #0] + 8004b08: 009b lsls r3, r3, #2 + 8004b0a: 441a add r2, r3 + 8004b0c: 4b49 ldr r3, [pc, #292] ; (8004c34 ) + 8004b0e: 4323 orrs r3, r4 + 8004b10: b29b uxth r3, r3 + 8004b12: 8013 strh r3, [r2, #0] + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + 8004b14: 687a ldr r2, [r7, #4] + 8004b16: 683b ldr r3, [r7, #0] + 8004b18: 781b ldrb r3, [r3, #0] + 8004b1a: 009b lsls r3, r3, #2 + 8004b1c: 4413 add r3, r2 + 8004b1e: 881b ldrh r3, [r3, #0] + 8004b20: b29b uxth r3, r3 + 8004b22: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004b26: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8004b2a: b29c uxth r4, r3 + 8004b2c: 687a ldr r2, [r7, #4] + 8004b2e: 683b ldr r3, [r7, #0] + 8004b30: 781b ldrb r3, [r3, #0] + 8004b32: 009b lsls r3, r3, #2 + 8004b34: 441a add r2, r3 + 8004b36: 4b3f ldr r3, [pc, #252] ; (8004c34 ) + 8004b38: 4323 orrs r3, r4 + 8004b3a: b29b uxth r3, r3 + 8004b3c: 8013 strh r3, [r2, #0] + 8004b3e: e0a5 b.n 8004c8c + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + 8004b40: 687a ldr r2, [r7, #4] + 8004b42: 683b ldr r3, [r7, #0] + 8004b44: 781b ldrb r3, [r3, #0] + 8004b46: 009b lsls r3, r3, #2 + 8004b48: 4413 add r3, r2 + 8004b4a: 881b ldrh r3, [r3, #0] + 8004b4c: b29c uxth r4, r3 + 8004b4e: 4623 mov r3, r4 + 8004b50: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8004b54: 2b00 cmp r3, #0 + 8004b56: d014 beq.n 8004b82 + 8004b58: 687a ldr r2, [r7, #4] + 8004b5a: 683b ldr r3, [r7, #0] + 8004b5c: 781b ldrb r3, [r3, #0] + 8004b5e: 009b lsls r3, r3, #2 + 8004b60: 4413 add r3, r2 + 8004b62: 881b ldrh r3, [r3, #0] + 8004b64: b29b uxth r3, r3 + 8004b66: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004b6a: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004b6e: b29c uxth r4, r3 + 8004b70: 687a ldr r2, [r7, #4] + 8004b72: 683b ldr r3, [r7, #0] + 8004b74: 781b ldrb r3, [r3, #0] + 8004b76: 009b lsls r3, r3, #2 + 8004b78: 441a add r2, r3 + 8004b7a: 4b2c ldr r3, [pc, #176] ; (8004c2c ) + 8004b7c: 4323 orrs r3, r4 + 8004b7e: b29b uxth r3, r3 + 8004b80: 8013 strh r3, [r2, #0] + PCD_CLEAR_TX_DTOG(USBx, ep->num); + 8004b82: 687a ldr r2, [r7, #4] + 8004b84: 683b ldr r3, [r7, #0] + 8004b86: 781b ldrb r3, [r3, #0] + 8004b88: 009b lsls r3, r3, #2 + 8004b8a: 4413 add r3, r2 + 8004b8c: 881b ldrh r3, [r3, #0] + 8004b8e: b29c uxth r4, r3 + 8004b90: 4623 mov r3, r4 + 8004b92: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004b96: 2b00 cmp r3, #0 + 8004b98: d014 beq.n 8004bc4 + 8004b9a: 687a ldr r2, [r7, #4] + 8004b9c: 683b ldr r3, [r7, #0] + 8004b9e: 781b ldrb r3, [r3, #0] + 8004ba0: 009b lsls r3, r3, #2 + 8004ba2: 4413 add r3, r2 + 8004ba4: 881b ldrh r3, [r3, #0] + 8004ba6: b29b uxth r3, r3 + 8004ba8: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004bac: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004bb0: b29c uxth r4, r3 + 8004bb2: 687a ldr r2, [r7, #4] + 8004bb4: 683b ldr r3, [r7, #0] + 8004bb6: 781b ldrb r3, [r3, #0] + 8004bb8: 009b lsls r3, r3, #2 + 8004bba: 441a add r2, r3 + 8004bbc: 4b1c ldr r3, [pc, #112] ; (8004c30 ) + 8004bbe: 4323 orrs r3, r4 + 8004bc0: b29b uxth r3, r3 + 8004bc2: 8013 strh r3, [r2, #0] + PCD_RX_DTOG(USBx, ep->num); + 8004bc4: 687a ldr r2, [r7, #4] + 8004bc6: 683b ldr r3, [r7, #0] + 8004bc8: 781b ldrb r3, [r3, #0] + 8004bca: 009b lsls r3, r3, #2 + 8004bcc: 4413 add r3, r2 + 8004bce: 881b ldrh r3, [r3, #0] + 8004bd0: b29b uxth r3, r3 + 8004bd2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004bd6: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004bda: b29c uxth r4, r3 + 8004bdc: 687a ldr r2, [r7, #4] + 8004bde: 683b ldr r3, [r7, #0] + 8004be0: 781b ldrb r3, [r3, #0] + 8004be2: 009b lsls r3, r3, #2 + 8004be4: 441a add r2, r3 + 8004be6: 4b11 ldr r3, [pc, #68] ; (8004c2c ) + 8004be8: 4323 orrs r3, r4 + 8004bea: b29b uxth r3, r3 + 8004bec: 8013 strh r3, [r2, #0] + + if (ep->type != EP_TYPE_ISOC) + 8004bee: 683b ldr r3, [r7, #0] + 8004bf0: 78db ldrb r3, [r3, #3] + 8004bf2: 2b01 cmp r3, #1 + 8004bf4: d020 beq.n 8004c38 + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + 8004bf6: 687a ldr r2, [r7, #4] + 8004bf8: 683b ldr r3, [r7, #0] + 8004bfa: 781b ldrb r3, [r3, #0] + 8004bfc: 009b lsls r3, r3, #2 + 8004bfe: 4413 add r3, r2 + 8004c00: 881b ldrh r3, [r3, #0] + 8004c02: b29b uxth r3, r3 + 8004c04: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004c08: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8004c0c: b29c uxth r4, r3 + 8004c0e: f084 0320 eor.w r3, r4, #32 + 8004c12: b29c uxth r4, r3 + 8004c14: 687a ldr r2, [r7, #4] + 8004c16: 683b ldr r3, [r7, #0] + 8004c18: 781b ldrb r3, [r3, #0] + 8004c1a: 009b lsls r3, r3, #2 + 8004c1c: 441a add r2, r3 + 8004c1e: 4b05 ldr r3, [pc, #20] ; (8004c34 ) + 8004c20: 4323 orrs r3, r4 + 8004c22: b29b uxth r3, r3 + 8004c24: 8013 strh r3, [r2, #0] + 8004c26: e01c b.n 8004c62 + 8004c28: ffff8180 .word 0xffff8180 + 8004c2c: ffffc080 .word 0xffffc080 + 8004c30: ffff80c0 .word 0xffff80c0 + 8004c34: ffff8080 .word 0xffff8080 + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + 8004c38: 687a ldr r2, [r7, #4] + 8004c3a: 683b ldr r3, [r7, #0] + 8004c3c: 781b ldrb r3, [r3, #0] + 8004c3e: 009b lsls r3, r3, #2 + 8004c40: 4413 add r3, r2 + 8004c42: 881b ldrh r3, [r3, #0] + 8004c44: b29b uxth r3, r3 + 8004c46: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004c4a: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8004c4e: b29c uxth r4, r3 + 8004c50: 687a ldr r2, [r7, #4] + 8004c52: 683b ldr r3, [r7, #0] + 8004c54: 781b ldrb r3, [r3, #0] + 8004c56: 009b lsls r3, r3, #2 + 8004c58: 441a add r2, r3 + 8004c5a: 4b0f ldr r3, [pc, #60] ; (8004c98 ) + 8004c5c: 4323 orrs r3, r4 + 8004c5e: b29b uxth r3, r3 + 8004c60: 8013 strh r3, [r2, #0] + } + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + 8004c62: 687a ldr r2, [r7, #4] + 8004c64: 683b ldr r3, [r7, #0] + 8004c66: 781b ldrb r3, [r3, #0] + 8004c68: 009b lsls r3, r3, #2 + 8004c6a: 4413 add r3, r2 + 8004c6c: 881b ldrh r3, [r3, #0] + 8004c6e: b29b uxth r3, r3 + 8004c70: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8004c74: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004c78: b29c uxth r4, r3 + 8004c7a: 687a ldr r2, [r7, #4] + 8004c7c: 683b ldr r3, [r7, #0] + 8004c7e: 781b ldrb r3, [r3, #0] + 8004c80: 009b lsls r3, r3, #2 + 8004c82: 441a add r2, r3 + 8004c84: 4b04 ldr r3, [pc, #16] ; (8004c98 ) + 8004c86: 4323 orrs r3, r4 + 8004c88: b29b uxth r3, r3 + 8004c8a: 8013 strh r3, [r2, #0] + } + } + + return ret; + 8004c8c: 7bfb ldrb r3, [r7, #15] +} + 8004c8e: 4618 mov r0, r3 + 8004c90: 3710 adds r7, #16 + 8004c92: 46bd mov sp, r7 + 8004c94: bc90 pop {r4, r7} + 8004c96: 4770 bx lr + 8004c98: ffff8080 .word 0xffff8080 + +08004c9c : + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + 8004c9c: b490 push {r4, r7} + 8004c9e: b082 sub sp, #8 + 8004ca0: af00 add r7, sp, #0 + 8004ca2: 6078 str r0, [r7, #4] + 8004ca4: 6039 str r1, [r7, #0] + if (ep->doublebuffer == 0U) + 8004ca6: 683b ldr r3, [r7, #0] + 8004ca8: 7b1b ldrb r3, [r3, #12] + 8004caa: 2b00 cmp r3, #0 + 8004cac: d171 bne.n 8004d92 + { + if (ep->is_in != 0U) + 8004cae: 683b ldr r3, [r7, #0] + 8004cb0: 785b ldrb r3, [r3, #1] + 8004cb2: 2b00 cmp r3, #0 + 8004cb4: d036 beq.n 8004d24 + { + PCD_CLEAR_TX_DTOG(USBx, ep->num); + 8004cb6: 687a ldr r2, [r7, #4] + 8004cb8: 683b ldr r3, [r7, #0] + 8004cba: 781b ldrb r3, [r3, #0] + 8004cbc: 009b lsls r3, r3, #2 + 8004cbe: 4413 add r3, r2 + 8004cc0: 881b ldrh r3, [r3, #0] + 8004cc2: b29c uxth r4, r3 + 8004cc4: 4623 mov r3, r4 + 8004cc6: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004cca: 2b00 cmp r3, #0 + 8004ccc: d014 beq.n 8004cf8 + 8004cce: 687a ldr r2, [r7, #4] + 8004cd0: 683b ldr r3, [r7, #0] + 8004cd2: 781b ldrb r3, [r3, #0] + 8004cd4: 009b lsls r3, r3, #2 + 8004cd6: 4413 add r3, r2 + 8004cd8: 881b ldrh r3, [r3, #0] + 8004cda: b29b uxth r3, r3 + 8004cdc: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004ce0: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004ce4: b29c uxth r4, r3 + 8004ce6: 687a ldr r2, [r7, #4] + 8004ce8: 683b ldr r3, [r7, #0] + 8004cea: 781b ldrb r3, [r3, #0] + 8004cec: 009b lsls r3, r3, #2 + 8004cee: 441a add r2, r3 + 8004cf0: 4b6b ldr r3, [pc, #428] ; (8004ea0 ) + 8004cf2: 4323 orrs r3, r4 + 8004cf4: b29b uxth r3, r3 + 8004cf6: 8013 strh r3, [r2, #0] + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + 8004cf8: 687a ldr r2, [r7, #4] + 8004cfa: 683b ldr r3, [r7, #0] + 8004cfc: 781b ldrb r3, [r3, #0] + 8004cfe: 009b lsls r3, r3, #2 + 8004d00: 4413 add r3, r2 + 8004d02: 881b ldrh r3, [r3, #0] + 8004d04: b29b uxth r3, r3 + 8004d06: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004d0a: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8004d0e: b29c uxth r4, r3 + 8004d10: 687a ldr r2, [r7, #4] + 8004d12: 683b ldr r3, [r7, #0] + 8004d14: 781b ldrb r3, [r3, #0] + 8004d16: 009b lsls r3, r3, #2 + 8004d18: 441a add r2, r3 + 8004d1a: 4b62 ldr r3, [pc, #392] ; (8004ea4 ) + 8004d1c: 4323 orrs r3, r4 + 8004d1e: b29b uxth r3, r3 + 8004d20: 8013 strh r3, [r2, #0] + 8004d22: e144 b.n 8004fae + } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + 8004d24: 687a ldr r2, [r7, #4] + 8004d26: 683b ldr r3, [r7, #0] + 8004d28: 781b ldrb r3, [r3, #0] + 8004d2a: 009b lsls r3, r3, #2 + 8004d2c: 4413 add r3, r2 + 8004d2e: 881b ldrh r3, [r3, #0] + 8004d30: b29c uxth r4, r3 + 8004d32: 4623 mov r3, r4 + 8004d34: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8004d38: 2b00 cmp r3, #0 + 8004d3a: d014 beq.n 8004d66 + 8004d3c: 687a ldr r2, [r7, #4] + 8004d3e: 683b ldr r3, [r7, #0] + 8004d40: 781b ldrb r3, [r3, #0] + 8004d42: 009b lsls r3, r3, #2 + 8004d44: 4413 add r3, r2 + 8004d46: 881b ldrh r3, [r3, #0] + 8004d48: b29b uxth r3, r3 + 8004d4a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004d4e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004d52: b29c uxth r4, r3 + 8004d54: 687a ldr r2, [r7, #4] + 8004d56: 683b ldr r3, [r7, #0] + 8004d58: 781b ldrb r3, [r3, #0] + 8004d5a: 009b lsls r3, r3, #2 + 8004d5c: 441a add r2, r3 + 8004d5e: 4b52 ldr r3, [pc, #328] ; (8004ea8 ) + 8004d60: 4323 orrs r3, r4 + 8004d62: b29b uxth r3, r3 + 8004d64: 8013 strh r3, [r2, #0] + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + 8004d66: 687a ldr r2, [r7, #4] + 8004d68: 683b ldr r3, [r7, #0] + 8004d6a: 781b ldrb r3, [r3, #0] + 8004d6c: 009b lsls r3, r3, #2 + 8004d6e: 4413 add r3, r2 + 8004d70: 881b ldrh r3, [r3, #0] + 8004d72: b29b uxth r3, r3 + 8004d74: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8004d78: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004d7c: b29c uxth r4, r3 + 8004d7e: 687a ldr r2, [r7, #4] + 8004d80: 683b ldr r3, [r7, #0] + 8004d82: 781b ldrb r3, [r3, #0] + 8004d84: 009b lsls r3, r3, #2 + 8004d86: 441a add r2, r3 + 8004d88: 4b46 ldr r3, [pc, #280] ; (8004ea4 ) + 8004d8a: 4323 orrs r3, r4 + 8004d8c: b29b uxth r3, r3 + 8004d8e: 8013 strh r3, [r2, #0] + 8004d90: e10d b.n 8004fae + } + } + /*Double Buffer*/ + else + { + if (ep->is_in == 0U) + 8004d92: 683b ldr r3, [r7, #0] + 8004d94: 785b ldrb r3, [r3, #1] + 8004d96: 2b00 cmp r3, #0 + 8004d98: f040 8088 bne.w 8004eac + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + 8004d9c: 687a ldr r2, [r7, #4] + 8004d9e: 683b ldr r3, [r7, #0] + 8004da0: 781b ldrb r3, [r3, #0] + 8004da2: 009b lsls r3, r3, #2 + 8004da4: 4413 add r3, r2 + 8004da6: 881b ldrh r3, [r3, #0] + 8004da8: b29c uxth r4, r3 + 8004daa: 4623 mov r3, r4 + 8004dac: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8004db0: 2b00 cmp r3, #0 + 8004db2: d014 beq.n 8004dde + 8004db4: 687a ldr r2, [r7, #4] + 8004db6: 683b ldr r3, [r7, #0] + 8004db8: 781b ldrb r3, [r3, #0] + 8004dba: 009b lsls r3, r3, #2 + 8004dbc: 4413 add r3, r2 + 8004dbe: 881b ldrh r3, [r3, #0] + 8004dc0: b29b uxth r3, r3 + 8004dc2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004dc6: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004dca: b29c uxth r4, r3 + 8004dcc: 687a ldr r2, [r7, #4] + 8004dce: 683b ldr r3, [r7, #0] + 8004dd0: 781b ldrb r3, [r3, #0] + 8004dd2: 009b lsls r3, r3, #2 + 8004dd4: 441a add r2, r3 + 8004dd6: 4b34 ldr r3, [pc, #208] ; (8004ea8 ) + 8004dd8: 4323 orrs r3, r4 + 8004dda: b29b uxth r3, r3 + 8004ddc: 8013 strh r3, [r2, #0] + PCD_CLEAR_TX_DTOG(USBx, ep->num); + 8004dde: 687a ldr r2, [r7, #4] + 8004de0: 683b ldr r3, [r7, #0] + 8004de2: 781b ldrb r3, [r3, #0] + 8004de4: 009b lsls r3, r3, #2 + 8004de6: 4413 add r3, r2 + 8004de8: 881b ldrh r3, [r3, #0] + 8004dea: b29c uxth r4, r3 + 8004dec: 4623 mov r3, r4 + 8004dee: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004df2: 2b00 cmp r3, #0 + 8004df4: d014 beq.n 8004e20 + 8004df6: 687a ldr r2, [r7, #4] + 8004df8: 683b ldr r3, [r7, #0] + 8004dfa: 781b ldrb r3, [r3, #0] + 8004dfc: 009b lsls r3, r3, #2 + 8004dfe: 4413 add r3, r2 + 8004e00: 881b ldrh r3, [r3, #0] + 8004e02: b29b uxth r3, r3 + 8004e04: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004e08: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004e0c: b29c uxth r4, r3 + 8004e0e: 687a ldr r2, [r7, #4] + 8004e10: 683b ldr r3, [r7, #0] + 8004e12: 781b ldrb r3, [r3, #0] + 8004e14: 009b lsls r3, r3, #2 + 8004e16: 441a add r2, r3 + 8004e18: 4b21 ldr r3, [pc, #132] ; (8004ea0 ) + 8004e1a: 4323 orrs r3, r4 + 8004e1c: b29b uxth r3, r3 + 8004e1e: 8013 strh r3, [r2, #0] + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(USBx, ep->num); + 8004e20: 687a ldr r2, [r7, #4] + 8004e22: 683b ldr r3, [r7, #0] + 8004e24: 781b ldrb r3, [r3, #0] + 8004e26: 009b lsls r3, r3, #2 + 8004e28: 4413 add r3, r2 + 8004e2a: 881b ldrh r3, [r3, #0] + 8004e2c: b29b uxth r3, r3 + 8004e2e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004e32: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004e36: b29c uxth r4, r3 + 8004e38: 687a ldr r2, [r7, #4] + 8004e3a: 683b ldr r3, [r7, #0] + 8004e3c: 781b ldrb r3, [r3, #0] + 8004e3e: 009b lsls r3, r3, #2 + 8004e40: 441a add r2, r3 + 8004e42: 4b17 ldr r3, [pc, #92] ; (8004ea0 ) + 8004e44: 4323 orrs r3, r4 + 8004e46: b29b uxth r3, r3 + 8004e48: 8013 strh r3, [r2, #0] + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + 8004e4a: 687a ldr r2, [r7, #4] + 8004e4c: 683b ldr r3, [r7, #0] + 8004e4e: 781b ldrb r3, [r3, #0] + 8004e50: 009b lsls r3, r3, #2 + 8004e52: 4413 add r3, r2 + 8004e54: 881b ldrh r3, [r3, #0] + 8004e56: b29b uxth r3, r3 + 8004e58: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8004e5c: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004e60: b29c uxth r4, r3 + 8004e62: 687a ldr r2, [r7, #4] + 8004e64: 683b ldr r3, [r7, #0] + 8004e66: 781b ldrb r3, [r3, #0] + 8004e68: 009b lsls r3, r3, #2 + 8004e6a: 441a add r2, r3 + 8004e6c: 4b0d ldr r3, [pc, #52] ; (8004ea4 ) + 8004e6e: 4323 orrs r3, r4 + 8004e70: b29b uxth r3, r3 + 8004e72: 8013 strh r3, [r2, #0] + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + 8004e74: 687a ldr r2, [r7, #4] + 8004e76: 683b ldr r3, [r7, #0] + 8004e78: 781b ldrb r3, [r3, #0] + 8004e7a: 009b lsls r3, r3, #2 + 8004e7c: 4413 add r3, r2 + 8004e7e: 881b ldrh r3, [r3, #0] + 8004e80: b29b uxth r3, r3 + 8004e82: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004e86: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8004e8a: b29c uxth r4, r3 + 8004e8c: 687a ldr r2, [r7, #4] + 8004e8e: 683b ldr r3, [r7, #0] + 8004e90: 781b ldrb r3, [r3, #0] + 8004e92: 009b lsls r3, r3, #2 + 8004e94: 441a add r2, r3 + 8004e96: 4b03 ldr r3, [pc, #12] ; (8004ea4 ) + 8004e98: 4323 orrs r3, r4 + 8004e9a: b29b uxth r3, r3 + 8004e9c: 8013 strh r3, [r2, #0] + 8004e9e: e086 b.n 8004fae + 8004ea0: ffff80c0 .word 0xffff80c0 + 8004ea4: ffff8080 .word 0xffff8080 + 8004ea8: ffffc080 .word 0xffffc080 + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + 8004eac: 687a ldr r2, [r7, #4] + 8004eae: 683b ldr r3, [r7, #0] + 8004eb0: 781b ldrb r3, [r3, #0] + 8004eb2: 009b lsls r3, r3, #2 + 8004eb4: 4413 add r3, r2 + 8004eb6: 881b ldrh r3, [r3, #0] + 8004eb8: b29c uxth r4, r3 + 8004eba: 4623 mov r3, r4 + 8004ebc: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8004ec0: 2b00 cmp r3, #0 + 8004ec2: d014 beq.n 8004eee + 8004ec4: 687a ldr r2, [r7, #4] + 8004ec6: 683b ldr r3, [r7, #0] + 8004ec8: 781b ldrb r3, [r3, #0] + 8004eca: 009b lsls r3, r3, #2 + 8004ecc: 4413 add r3, r2 + 8004ece: 881b ldrh r3, [r3, #0] + 8004ed0: b29b uxth r3, r3 + 8004ed2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004ed6: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004eda: b29c uxth r4, r3 + 8004edc: 687a ldr r2, [r7, #4] + 8004ede: 683b ldr r3, [r7, #0] + 8004ee0: 781b ldrb r3, [r3, #0] + 8004ee2: 009b lsls r3, r3, #2 + 8004ee4: 441a add r2, r3 + 8004ee6: 4b35 ldr r3, [pc, #212] ; (8004fbc ) + 8004ee8: 4323 orrs r3, r4 + 8004eea: b29b uxth r3, r3 + 8004eec: 8013 strh r3, [r2, #0] + PCD_CLEAR_TX_DTOG(USBx, ep->num); + 8004eee: 687a ldr r2, [r7, #4] + 8004ef0: 683b ldr r3, [r7, #0] + 8004ef2: 781b ldrb r3, [r3, #0] + 8004ef4: 009b lsls r3, r3, #2 + 8004ef6: 4413 add r3, r2 + 8004ef8: 881b ldrh r3, [r3, #0] + 8004efa: b29c uxth r4, r3 + 8004efc: 4623 mov r3, r4 + 8004efe: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004f02: 2b00 cmp r3, #0 + 8004f04: d014 beq.n 8004f30 + 8004f06: 687a ldr r2, [r7, #4] + 8004f08: 683b ldr r3, [r7, #0] + 8004f0a: 781b ldrb r3, [r3, #0] + 8004f0c: 009b lsls r3, r3, #2 + 8004f0e: 4413 add r3, r2 + 8004f10: 881b ldrh r3, [r3, #0] + 8004f12: b29b uxth r3, r3 + 8004f14: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004f18: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004f1c: b29c uxth r4, r3 + 8004f1e: 687a ldr r2, [r7, #4] + 8004f20: 683b ldr r3, [r7, #0] + 8004f22: 781b ldrb r3, [r3, #0] + 8004f24: 009b lsls r3, r3, #2 + 8004f26: 441a add r2, r3 + 8004f28: 4b25 ldr r3, [pc, #148] ; (8004fc0 ) + 8004f2a: 4323 orrs r3, r4 + 8004f2c: b29b uxth r3, r3 + 8004f2e: 8013 strh r3, [r2, #0] + PCD_RX_DTOG(USBx, ep->num); + 8004f30: 687a ldr r2, [r7, #4] + 8004f32: 683b ldr r3, [r7, #0] + 8004f34: 781b ldrb r3, [r3, #0] + 8004f36: 009b lsls r3, r3, #2 + 8004f38: 4413 add r3, r2 + 8004f3a: 881b ldrh r3, [r3, #0] + 8004f3c: b29b uxth r3, r3 + 8004f3e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004f42: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004f46: b29c uxth r4, r3 + 8004f48: 687a ldr r2, [r7, #4] + 8004f4a: 683b ldr r3, [r7, #0] + 8004f4c: 781b ldrb r3, [r3, #0] + 8004f4e: 009b lsls r3, r3, #2 + 8004f50: 441a add r2, r3 + 8004f52: 4b1a ldr r3, [pc, #104] ; (8004fbc ) + 8004f54: 4323 orrs r3, r4 + 8004f56: b29b uxth r3, r3 + 8004f58: 8013 strh r3, [r2, #0] + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + 8004f5a: 687a ldr r2, [r7, #4] + 8004f5c: 683b ldr r3, [r7, #0] + 8004f5e: 781b ldrb r3, [r3, #0] + 8004f60: 009b lsls r3, r3, #2 + 8004f62: 4413 add r3, r2 + 8004f64: 881b ldrh r3, [r3, #0] + 8004f66: b29b uxth r3, r3 + 8004f68: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8004f6c: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8004f70: b29c uxth r4, r3 + 8004f72: 687a ldr r2, [r7, #4] + 8004f74: 683b ldr r3, [r7, #0] + 8004f76: 781b ldrb r3, [r3, #0] + 8004f78: 009b lsls r3, r3, #2 + 8004f7a: 441a add r2, r3 + 8004f7c: 4b11 ldr r3, [pc, #68] ; (8004fc4 ) + 8004f7e: 4323 orrs r3, r4 + 8004f80: b29b uxth r3, r3 + 8004f82: 8013 strh r3, [r2, #0] + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + 8004f84: 687a ldr r2, [r7, #4] + 8004f86: 683b ldr r3, [r7, #0] + 8004f88: 781b ldrb r3, [r3, #0] + 8004f8a: 009b lsls r3, r3, #2 + 8004f8c: 4413 add r3, r2 + 8004f8e: 881b ldrh r3, [r3, #0] + 8004f90: b29b uxth r3, r3 + 8004f92: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8004f96: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8004f9a: b29c uxth r4, r3 + 8004f9c: 687a ldr r2, [r7, #4] + 8004f9e: 683b ldr r3, [r7, #0] + 8004fa0: 781b ldrb r3, [r3, #0] + 8004fa2: 009b lsls r3, r3, #2 + 8004fa4: 441a add r2, r3 + 8004fa6: 4b07 ldr r3, [pc, #28] ; (8004fc4 ) + 8004fa8: 4323 orrs r3, r4 + 8004faa: b29b uxth r3, r3 + 8004fac: 8013 strh r3, [r2, #0] + } + } + + return HAL_OK; + 8004fae: 2300 movs r3, #0 +} + 8004fb0: 4618 mov r0, r3 + 8004fb2: 3708 adds r7, #8 + 8004fb4: 46bd mov sp, r7 + 8004fb6: bc90 pop {r4, r7} + 8004fb8: 4770 bx lr + 8004fba: bf00 nop + 8004fbc: ffffc080 .word 0xffffc080 + 8004fc0: ffff80c0 .word 0xffff80c0 + 8004fc4: ffff8080 .word 0xffff8080 + +08004fc8 : + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + 8004fc8: b590 push {r4, r7, lr} + 8004fca: b08d sub sp, #52 ; 0x34 + 8004fcc: af00 add r7, sp, #0 + 8004fce: 6078 str r0, [r7, #4] + 8004fd0: 6039 str r1, [r7, #0] + uint16_t pmabuffer; + uint32_t len; + + /* IN endpoint */ + if (ep->is_in == 1U) + 8004fd2: 683b ldr r3, [r7, #0] + 8004fd4: 785b ldrb r3, [r3, #1] + 8004fd6: 2b01 cmp r3, #1 + 8004fd8: f040 8160 bne.w 800529c + { + /*Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + 8004fdc: 683b ldr r3, [r7, #0] + 8004fde: 699a ldr r2, [r3, #24] + 8004fe0: 683b ldr r3, [r7, #0] + 8004fe2: 691b ldr r3, [r3, #16] + 8004fe4: 429a cmp r2, r3 + 8004fe6: d909 bls.n 8004ffc + { + len = ep->maxpacket; + 8004fe8: 683b ldr r3, [r7, #0] + 8004fea: 691b ldr r3, [r3, #16] + 8004fec: 62bb str r3, [r7, #40] ; 0x28 + ep->xfer_len -= len; + 8004fee: 683b ldr r3, [r7, #0] + 8004ff0: 699a ldr r2, [r3, #24] + 8004ff2: 6abb ldr r3, [r7, #40] ; 0x28 + 8004ff4: 1ad2 subs r2, r2, r3 + 8004ff6: 683b ldr r3, [r7, #0] + 8004ff8: 619a str r2, [r3, #24] + 8004ffa: e005 b.n 8005008 + } + else + { + len = ep->xfer_len; + 8004ffc: 683b ldr r3, [r7, #0] + 8004ffe: 699b ldr r3, [r3, #24] + 8005000: 62bb str r3, [r7, #40] ; 0x28 + ep->xfer_len = 0U; + 8005002: 683b ldr r3, [r7, #0] + 8005004: 2200 movs r2, #0 + 8005006: 619a str r2, [r3, #24] + } + + /* configure and validate Tx endpoint */ + if (ep->doublebuffer == 0U) + 8005008: 683b ldr r3, [r7, #0] + 800500a: 7b1b ldrb r3, [r3, #12] + 800500c: 2b00 cmp r3, #0 + 800500e: d119 bne.n 8005044 + { + USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); + 8005010: 683b ldr r3, [r7, #0] + 8005012: 6959 ldr r1, [r3, #20] + 8005014: 683b ldr r3, [r7, #0] + 8005016: 88da ldrh r2, [r3, #6] + 8005018: 6abb ldr r3, [r7, #40] ; 0x28 + 800501a: b29b uxth r3, r3 + 800501c: 6878 ldr r0, [r7, #4] + 800501e: f000 fba2 bl 8005766 + PCD_SET_EP_TX_CNT(USBx, ep->num, len); + 8005022: 687c ldr r4, [r7, #4] + 8005024: 687b ldr r3, [r7, #4] + 8005026: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800502a: b29b uxth r3, r3 + 800502c: 441c add r4, r3 + 800502e: 683b ldr r3, [r7, #0] + 8005030: 781b ldrb r3, [r3, #0] + 8005032: 011b lsls r3, r3, #4 + 8005034: 4423 add r3, r4 + 8005036: f203 4304 addw r3, r3, #1028 ; 0x404 + 800503a: 461c mov r4, r3 + 800503c: 6abb ldr r3, [r7, #40] ; 0x28 + 800503e: b29b uxth r3, r3 + 8005040: 8023 strh r3, [r4, #0] + 8005042: e10f b.n 8005264 + } + else + { + /* Write the data to the USB endpoint */ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + 8005044: 687a ldr r2, [r7, #4] + 8005046: 683b ldr r3, [r7, #0] + 8005048: 781b ldrb r3, [r3, #0] + 800504a: 009b lsls r3, r3, #2 + 800504c: 4413 add r3, r2 + 800504e: 881b ldrh r3, [r3, #0] + 8005050: b29b uxth r3, r3 + 8005052: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005056: 2b00 cmp r3, #0 + 8005058: d065 beq.n 8005126 + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + 800505a: 687c ldr r4, [r7, #4] + 800505c: 683b ldr r3, [r7, #0] + 800505e: 785b ldrb r3, [r3, #1] + 8005060: 2b00 cmp r3, #0 + 8005062: d148 bne.n 80050f6 + 8005064: 687c ldr r4, [r7, #4] + 8005066: 687b ldr r3, [r7, #4] + 8005068: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800506c: b29b uxth r3, r3 + 800506e: 441c add r4, r3 + 8005070: 683b ldr r3, [r7, #0] + 8005072: 781b ldrb r3, [r3, #0] + 8005074: 011b lsls r3, r3, #4 + 8005076: 4423 add r3, r4 + 8005078: f203 430c addw r3, r3, #1036 ; 0x40c + 800507c: 461c mov r4, r3 + 800507e: 6abb ldr r3, [r7, #40] ; 0x28 + 8005080: 2b00 cmp r3, #0 + 8005082: d10e bne.n 80050a2 + 8005084: 8823 ldrh r3, [r4, #0] + 8005086: b29b uxth r3, r3 + 8005088: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00 + 800508c: b29b uxth r3, r3 + 800508e: 8023 strh r3, [r4, #0] + 8005090: 8823 ldrh r3, [r4, #0] + 8005092: b29b uxth r3, r3 + 8005094: ea6f 4343 mvn.w r3, r3, lsl #17 + 8005098: ea6f 4353 mvn.w r3, r3, lsr #17 + 800509c: b29b uxth r3, r3 + 800509e: 8023 strh r3, [r4, #0] + 80050a0: e03d b.n 800511e + 80050a2: 6abb ldr r3, [r7, #40] ; 0x28 + 80050a4: 2b3e cmp r3, #62 ; 0x3e + 80050a6: d810 bhi.n 80050ca + 80050a8: 6abb ldr r3, [r7, #40] ; 0x28 + 80050aa: 085b lsrs r3, r3, #1 + 80050ac: 627b str r3, [r7, #36] ; 0x24 + 80050ae: 6abb ldr r3, [r7, #40] ; 0x28 + 80050b0: f003 0301 and.w r3, r3, #1 + 80050b4: 2b00 cmp r3, #0 + 80050b6: d002 beq.n 80050be + 80050b8: 6a7b ldr r3, [r7, #36] ; 0x24 + 80050ba: 3301 adds r3, #1 + 80050bc: 627b str r3, [r7, #36] ; 0x24 + 80050be: 6a7b ldr r3, [r7, #36] ; 0x24 + 80050c0: b29b uxth r3, r3 + 80050c2: 029b lsls r3, r3, #10 + 80050c4: b29b uxth r3, r3 + 80050c6: 8023 strh r3, [r4, #0] + 80050c8: e029 b.n 800511e + 80050ca: 6abb ldr r3, [r7, #40] ; 0x28 + 80050cc: 095b lsrs r3, r3, #5 + 80050ce: 627b str r3, [r7, #36] ; 0x24 + 80050d0: 6abb ldr r3, [r7, #40] ; 0x28 + 80050d2: f003 031f and.w r3, r3, #31 + 80050d6: 2b00 cmp r3, #0 + 80050d8: d102 bne.n 80050e0 + 80050da: 6a7b ldr r3, [r7, #36] ; 0x24 + 80050dc: 3b01 subs r3, #1 + 80050de: 627b str r3, [r7, #36] ; 0x24 + 80050e0: 6a7b ldr r3, [r7, #36] ; 0x24 + 80050e2: b29b uxth r3, r3 + 80050e4: 029b lsls r3, r3, #10 + 80050e6: b29b uxth r3, r3 + 80050e8: ea6f 4343 mvn.w r3, r3, lsl #17 + 80050ec: ea6f 4353 mvn.w r3, r3, lsr #17 + 80050f0: b29b uxth r3, r3 + 80050f2: 8023 strh r3, [r4, #0] + 80050f4: e013 b.n 800511e + 80050f6: 683b ldr r3, [r7, #0] + 80050f8: 785b ldrb r3, [r3, #1] + 80050fa: 2b01 cmp r3, #1 + 80050fc: d10f bne.n 800511e + 80050fe: 687b ldr r3, [r7, #4] + 8005100: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8005104: b29b uxth r3, r3 + 8005106: 441c add r4, r3 + 8005108: 683b ldr r3, [r7, #0] + 800510a: 781b ldrb r3, [r3, #0] + 800510c: 011b lsls r3, r3, #4 + 800510e: 4423 add r3, r4 + 8005110: f203 430c addw r3, r3, #1036 ; 0x40c + 8005114: 60fb str r3, [r7, #12] + 8005116: 6abb ldr r3, [r7, #40] ; 0x28 + 8005118: b29a uxth r2, r3 + 800511a: 68fb ldr r3, [r7, #12] + 800511c: 801a strh r2, [r3, #0] + pmabuffer = ep->pmaaddr1; + 800511e: 683b ldr r3, [r7, #0] + 8005120: 895b ldrh r3, [r3, #10] + 8005122: 85fb strh r3, [r7, #46] ; 0x2e + 8005124: e063 b.n 80051ee + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + 8005126: 683b ldr r3, [r7, #0] + 8005128: 785b ldrb r3, [r3, #1] + 800512a: 2b00 cmp r3, #0 + 800512c: d148 bne.n 80051c0 + 800512e: 687c ldr r4, [r7, #4] + 8005130: 687b ldr r3, [r7, #4] + 8005132: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8005136: b29b uxth r3, r3 + 8005138: 441c add r4, r3 + 800513a: 683b ldr r3, [r7, #0] + 800513c: 781b ldrb r3, [r3, #0] + 800513e: 011b lsls r3, r3, #4 + 8005140: 4423 add r3, r4 + 8005142: f203 4304 addw r3, r3, #1028 ; 0x404 + 8005146: 461c mov r4, r3 + 8005148: 6abb ldr r3, [r7, #40] ; 0x28 + 800514a: 2b00 cmp r3, #0 + 800514c: d10e bne.n 800516c + 800514e: 8823 ldrh r3, [r4, #0] + 8005150: b29b uxth r3, r3 + 8005152: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00 + 8005156: b29b uxth r3, r3 + 8005158: 8023 strh r3, [r4, #0] + 800515a: 8823 ldrh r3, [r4, #0] + 800515c: b29b uxth r3, r3 + 800515e: ea6f 4343 mvn.w r3, r3, lsl #17 + 8005162: ea6f 4353 mvn.w r3, r3, lsr #17 + 8005166: b29b uxth r3, r3 + 8005168: 8023 strh r3, [r4, #0] + 800516a: e03d b.n 80051e8 + 800516c: 6abb ldr r3, [r7, #40] ; 0x28 + 800516e: 2b3e cmp r3, #62 ; 0x3e + 8005170: d810 bhi.n 8005194 + 8005172: 6abb ldr r3, [r7, #40] ; 0x28 + 8005174: 085b lsrs r3, r3, #1 + 8005176: 623b str r3, [r7, #32] + 8005178: 6abb ldr r3, [r7, #40] ; 0x28 + 800517a: f003 0301 and.w r3, r3, #1 + 800517e: 2b00 cmp r3, #0 + 8005180: d002 beq.n 8005188 + 8005182: 6a3b ldr r3, [r7, #32] + 8005184: 3301 adds r3, #1 + 8005186: 623b str r3, [r7, #32] + 8005188: 6a3b ldr r3, [r7, #32] + 800518a: b29b uxth r3, r3 + 800518c: 029b lsls r3, r3, #10 + 800518e: b29b uxth r3, r3 + 8005190: 8023 strh r3, [r4, #0] + 8005192: e029 b.n 80051e8 + 8005194: 6abb ldr r3, [r7, #40] ; 0x28 + 8005196: 095b lsrs r3, r3, #5 + 8005198: 623b str r3, [r7, #32] + 800519a: 6abb ldr r3, [r7, #40] ; 0x28 + 800519c: f003 031f and.w r3, r3, #31 + 80051a0: 2b00 cmp r3, #0 + 80051a2: d102 bne.n 80051aa + 80051a4: 6a3b ldr r3, [r7, #32] + 80051a6: 3b01 subs r3, #1 + 80051a8: 623b str r3, [r7, #32] + 80051aa: 6a3b ldr r3, [r7, #32] + 80051ac: b29b uxth r3, r3 + 80051ae: 029b lsls r3, r3, #10 + 80051b0: b29b uxth r3, r3 + 80051b2: ea6f 4343 mvn.w r3, r3, lsl #17 + 80051b6: ea6f 4353 mvn.w r3, r3, lsr #17 + 80051ba: b29b uxth r3, r3 + 80051bc: 8023 strh r3, [r4, #0] + 80051be: e013 b.n 80051e8 + 80051c0: 683b ldr r3, [r7, #0] + 80051c2: 785b ldrb r3, [r3, #1] + 80051c4: 2b01 cmp r3, #1 + 80051c6: d10f bne.n 80051e8 + 80051c8: 687c ldr r4, [r7, #4] + 80051ca: 687b ldr r3, [r7, #4] + 80051cc: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80051d0: b29b uxth r3, r3 + 80051d2: 441c add r4, r3 + 80051d4: 683b ldr r3, [r7, #0] + 80051d6: 781b ldrb r3, [r3, #0] + 80051d8: 011b lsls r3, r3, #4 + 80051da: 4423 add r3, r4 + 80051dc: f203 4304 addw r3, r3, #1028 ; 0x404 + 80051e0: 461c mov r4, r3 + 80051e2: 6abb ldr r3, [r7, #40] ; 0x28 + 80051e4: b29b uxth r3, r3 + 80051e6: 8023 strh r3, [r4, #0] + pmabuffer = ep->pmaaddr0; + 80051e8: 683b ldr r3, [r7, #0] + 80051ea: 891b ldrh r3, [r3, #8] + 80051ec: 85fb strh r3, [r7, #46] ; 0x2e + } + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + 80051ee: 683b ldr r3, [r7, #0] + 80051f0: 6959 ldr r1, [r3, #20] + 80051f2: 6abb ldr r3, [r7, #40] ; 0x28 + 80051f4: b29b uxth r3, r3 + 80051f6: 8dfa ldrh r2, [r7, #46] ; 0x2e + 80051f8: 6878 ldr r0, [r7, #4] + 80051fa: f000 fab4 bl 8005766 + PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); + 80051fe: 683b ldr r3, [r7, #0] + 8005200: 785b ldrb r3, [r3, #1] + 8005202: 2b00 cmp r3, #0 + 8005204: d115 bne.n 8005232 + 8005206: 687a ldr r2, [r7, #4] + 8005208: 683b ldr r3, [r7, #0] + 800520a: 781b ldrb r3, [r3, #0] + 800520c: 009b lsls r3, r3, #2 + 800520e: 4413 add r3, r2 + 8005210: 881b ldrh r3, [r3, #0] + 8005212: b29b uxth r3, r3 + 8005214: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8005218: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800521c: b29c uxth r4, r3 + 800521e: 687a ldr r2, [r7, #4] + 8005220: 683b ldr r3, [r7, #0] + 8005222: 781b ldrb r3, [r3, #0] + 8005224: 009b lsls r3, r3, #2 + 8005226: 441a add r2, r3 + 8005228: 4b9a ldr r3, [pc, #616] ; (8005494 ) + 800522a: 4323 orrs r3, r4 + 800522c: b29b uxth r3, r3 + 800522e: 8013 strh r3, [r2, #0] + 8005230: e018 b.n 8005264 + 8005232: 683b ldr r3, [r7, #0] + 8005234: 785b ldrb r3, [r3, #1] + 8005236: 2b01 cmp r3, #1 + 8005238: d114 bne.n 8005264 + 800523a: 687a ldr r2, [r7, #4] + 800523c: 683b ldr r3, [r7, #0] + 800523e: 781b ldrb r3, [r3, #0] + 8005240: 009b lsls r3, r3, #2 + 8005242: 4413 add r3, r2 + 8005244: 881b ldrh r3, [r3, #0] + 8005246: b29b uxth r3, r3 + 8005248: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800524c: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8005250: b29c uxth r4, r3 + 8005252: 687a ldr r2, [r7, #4] + 8005254: 683b ldr r3, [r7, #0] + 8005256: 781b ldrb r3, [r3, #0] + 8005258: 009b lsls r3, r3, #2 + 800525a: 441a add r2, r3 + 800525c: 4b8e ldr r3, [pc, #568] ; (8005498 ) + 800525e: 4323 orrs r3, r4 + 8005260: b29b uxth r3, r3 + 8005262: 8013 strh r3, [r2, #0] + } + + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); + 8005264: 687a ldr r2, [r7, #4] + 8005266: 683b ldr r3, [r7, #0] + 8005268: 781b ldrb r3, [r3, #0] + 800526a: 009b lsls r3, r3, #2 + 800526c: 4413 add r3, r2 + 800526e: 881b ldrh r3, [r3, #0] + 8005270: b29b uxth r3, r3 + 8005272: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8005276: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800527a: b29c uxth r4, r3 + 800527c: f084 0310 eor.w r3, r4, #16 + 8005280: b29c uxth r4, r3 + 8005282: f084 0320 eor.w r3, r4, #32 + 8005286: b29c uxth r4, r3 + 8005288: 687a ldr r2, [r7, #4] + 800528a: 683b ldr r3, [r7, #0] + 800528c: 781b ldrb r3, [r3, #0] + 800528e: 009b lsls r3, r3, #2 + 8005290: 441a add r2, r3 + 8005292: 4b82 ldr r3, [pc, #520] ; (800549c ) + 8005294: 4323 orrs r3, r4 + 8005296: b29b uxth r3, r3 + 8005298: 8013 strh r3, [r2, #0] + 800529a: e146 b.n 800552a + } + else /* OUT endpoint */ + { + /* Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + 800529c: 683b ldr r3, [r7, #0] + 800529e: 699a ldr r2, [r3, #24] + 80052a0: 683b ldr r3, [r7, #0] + 80052a2: 691b ldr r3, [r3, #16] + 80052a4: 429a cmp r2, r3 + 80052a6: d909 bls.n 80052bc + { + len = ep->maxpacket; + 80052a8: 683b ldr r3, [r7, #0] + 80052aa: 691b ldr r3, [r3, #16] + 80052ac: 62bb str r3, [r7, #40] ; 0x28 + ep->xfer_len -= len; + 80052ae: 683b ldr r3, [r7, #0] + 80052b0: 699a ldr r2, [r3, #24] + 80052b2: 6abb ldr r3, [r7, #40] ; 0x28 + 80052b4: 1ad2 subs r2, r2, r3 + 80052b6: 683b ldr r3, [r7, #0] + 80052b8: 619a str r2, [r3, #24] + 80052ba: e005 b.n 80052c8 + } + else + { + len = ep->xfer_len; + 80052bc: 683b ldr r3, [r7, #0] + 80052be: 699b ldr r3, [r3, #24] + 80052c0: 62bb str r3, [r7, #40] ; 0x28 + ep->xfer_len = 0U; + 80052c2: 683b ldr r3, [r7, #0] + 80052c4: 2200 movs r2, #0 + 80052c6: 619a str r2, [r3, #24] + } + + /* configure and validate Rx endpoint */ + if (ep->doublebuffer == 0U) + 80052c8: 683b ldr r3, [r7, #0] + 80052ca: 7b1b ldrb r3, [r3, #12] + 80052cc: 2b00 cmp r3, #0 + 80052ce: d148 bne.n 8005362 + { + /*Set RX buffer count*/ + PCD_SET_EP_RX_CNT(USBx, ep->num, len); + 80052d0: 687c ldr r4, [r7, #4] + 80052d2: 687b ldr r3, [r7, #4] + 80052d4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80052d8: b29b uxth r3, r3 + 80052da: 441c add r4, r3 + 80052dc: 683b ldr r3, [r7, #0] + 80052de: 781b ldrb r3, [r3, #0] + 80052e0: 011b lsls r3, r3, #4 + 80052e2: 4423 add r3, r4 + 80052e4: f203 430c addw r3, r3, #1036 ; 0x40c + 80052e8: 461c mov r4, r3 + 80052ea: 6abb ldr r3, [r7, #40] ; 0x28 + 80052ec: 2b00 cmp r3, #0 + 80052ee: d10e bne.n 800530e + 80052f0: 8823 ldrh r3, [r4, #0] + 80052f2: b29b uxth r3, r3 + 80052f4: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00 + 80052f8: b29b uxth r3, r3 + 80052fa: 8023 strh r3, [r4, #0] + 80052fc: 8823 ldrh r3, [r4, #0] + 80052fe: b29b uxth r3, r3 + 8005300: ea6f 4343 mvn.w r3, r3, lsl #17 + 8005304: ea6f 4353 mvn.w r3, r3, lsr #17 + 8005308: b29b uxth r3, r3 + 800530a: 8023 strh r3, [r4, #0] + 800530c: e0f2 b.n 80054f4 + 800530e: 6abb ldr r3, [r7, #40] ; 0x28 + 8005310: 2b3e cmp r3, #62 ; 0x3e + 8005312: d810 bhi.n 8005336 + 8005314: 6abb ldr r3, [r7, #40] ; 0x28 + 8005316: 085b lsrs r3, r3, #1 + 8005318: 61fb str r3, [r7, #28] + 800531a: 6abb ldr r3, [r7, #40] ; 0x28 + 800531c: f003 0301 and.w r3, r3, #1 + 8005320: 2b00 cmp r3, #0 + 8005322: d002 beq.n 800532a + 8005324: 69fb ldr r3, [r7, #28] + 8005326: 3301 adds r3, #1 + 8005328: 61fb str r3, [r7, #28] + 800532a: 69fb ldr r3, [r7, #28] + 800532c: b29b uxth r3, r3 + 800532e: 029b lsls r3, r3, #10 + 8005330: b29b uxth r3, r3 + 8005332: 8023 strh r3, [r4, #0] + 8005334: e0de b.n 80054f4 + 8005336: 6abb ldr r3, [r7, #40] ; 0x28 + 8005338: 095b lsrs r3, r3, #5 + 800533a: 61fb str r3, [r7, #28] + 800533c: 6abb ldr r3, [r7, #40] ; 0x28 + 800533e: f003 031f and.w r3, r3, #31 + 8005342: 2b00 cmp r3, #0 + 8005344: d102 bne.n 800534c + 8005346: 69fb ldr r3, [r7, #28] + 8005348: 3b01 subs r3, #1 + 800534a: 61fb str r3, [r7, #28] + 800534c: 69fb ldr r3, [r7, #28] + 800534e: b29b uxth r3, r3 + 8005350: 029b lsls r3, r3, #10 + 8005352: b29b uxth r3, r3 + 8005354: ea6f 4343 mvn.w r3, r3, lsl #17 + 8005358: ea6f 4353 mvn.w r3, r3, lsr #17 + 800535c: b29b uxth r3, r3 + 800535e: 8023 strh r3, [r4, #0] + 8005360: e0c8 b.n 80054f4 + } + else + { + /*Set the Double buffer counter*/ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + 8005362: 683b ldr r3, [r7, #0] + 8005364: 785b ldrb r3, [r3, #1] + 8005366: 2b00 cmp r3, #0 + 8005368: d148 bne.n 80053fc + 800536a: 687c ldr r4, [r7, #4] + 800536c: 687b ldr r3, [r7, #4] + 800536e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8005372: b29b uxth r3, r3 + 8005374: 441c add r4, r3 + 8005376: 683b ldr r3, [r7, #0] + 8005378: 781b ldrb r3, [r3, #0] + 800537a: 011b lsls r3, r3, #4 + 800537c: 4423 add r3, r4 + 800537e: f203 4304 addw r3, r3, #1028 ; 0x404 + 8005382: 461c mov r4, r3 + 8005384: 6abb ldr r3, [r7, #40] ; 0x28 + 8005386: 2b00 cmp r3, #0 + 8005388: d10e bne.n 80053a8 + 800538a: 8823 ldrh r3, [r4, #0] + 800538c: b29b uxth r3, r3 + 800538e: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00 + 8005392: b29b uxth r3, r3 + 8005394: 8023 strh r3, [r4, #0] + 8005396: 8823 ldrh r3, [r4, #0] + 8005398: b29b uxth r3, r3 + 800539a: ea6f 4343 mvn.w r3, r3, lsl #17 + 800539e: ea6f 4353 mvn.w r3, r3, lsr #17 + 80053a2: b29b uxth r3, r3 + 80053a4: 8023 strh r3, [r4, #0] + 80053a6: e03d b.n 8005424 + 80053a8: 6abb ldr r3, [r7, #40] ; 0x28 + 80053aa: 2b3e cmp r3, #62 ; 0x3e + 80053ac: d810 bhi.n 80053d0 + 80053ae: 6abb ldr r3, [r7, #40] ; 0x28 + 80053b0: 085b lsrs r3, r3, #1 + 80053b2: 61bb str r3, [r7, #24] + 80053b4: 6abb ldr r3, [r7, #40] ; 0x28 + 80053b6: f003 0301 and.w r3, r3, #1 + 80053ba: 2b00 cmp r3, #0 + 80053bc: d002 beq.n 80053c4 + 80053be: 69bb ldr r3, [r7, #24] + 80053c0: 3301 adds r3, #1 + 80053c2: 61bb str r3, [r7, #24] + 80053c4: 69bb ldr r3, [r7, #24] + 80053c6: b29b uxth r3, r3 + 80053c8: 029b lsls r3, r3, #10 + 80053ca: b29b uxth r3, r3 + 80053cc: 8023 strh r3, [r4, #0] + 80053ce: e029 b.n 8005424 + 80053d0: 6abb ldr r3, [r7, #40] ; 0x28 + 80053d2: 095b lsrs r3, r3, #5 + 80053d4: 61bb str r3, [r7, #24] + 80053d6: 6abb ldr r3, [r7, #40] ; 0x28 + 80053d8: f003 031f and.w r3, r3, #31 + 80053dc: 2b00 cmp r3, #0 + 80053de: d102 bne.n 80053e6 + 80053e0: 69bb ldr r3, [r7, #24] + 80053e2: 3b01 subs r3, #1 + 80053e4: 61bb str r3, [r7, #24] + 80053e6: 69bb ldr r3, [r7, #24] + 80053e8: b29b uxth r3, r3 + 80053ea: 029b lsls r3, r3, #10 + 80053ec: b29b uxth r3, r3 + 80053ee: ea6f 4343 mvn.w r3, r3, lsl #17 + 80053f2: ea6f 4353 mvn.w r3, r3, lsr #17 + 80053f6: b29b uxth r3, r3 + 80053f8: 8023 strh r3, [r4, #0] + 80053fa: e013 b.n 8005424 + 80053fc: 683b ldr r3, [r7, #0] + 80053fe: 785b ldrb r3, [r3, #1] + 8005400: 2b01 cmp r3, #1 + 8005402: d10f bne.n 8005424 + 8005404: 687c ldr r4, [r7, #4] + 8005406: 687b ldr r3, [r7, #4] + 8005408: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800540c: b29b uxth r3, r3 + 800540e: 441c add r4, r3 + 8005410: 683b ldr r3, [r7, #0] + 8005412: 781b ldrb r3, [r3, #0] + 8005414: 011b lsls r3, r3, #4 + 8005416: 4423 add r3, r4 + 8005418: f203 4304 addw r3, r3, #1028 ; 0x404 + 800541c: 461c mov r4, r3 + 800541e: 6abb ldr r3, [r7, #40] ; 0x28 + 8005420: b29b uxth r3, r3 + 8005422: 8023 strh r3, [r4, #0] + 8005424: 687c ldr r4, [r7, #4] + 8005426: 683b ldr r3, [r7, #0] + 8005428: 785b ldrb r3, [r3, #1] + 800542a: 2b00 cmp r3, #0 + 800542c: d14e bne.n 80054cc + 800542e: 687c ldr r4, [r7, #4] + 8005430: 687b ldr r3, [r7, #4] + 8005432: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8005436: b29b uxth r3, r3 + 8005438: 441c add r4, r3 + 800543a: 683b ldr r3, [r7, #0] + 800543c: 781b ldrb r3, [r3, #0] + 800543e: 011b lsls r3, r3, #4 + 8005440: 4423 add r3, r4 + 8005442: f203 430c addw r3, r3, #1036 ; 0x40c + 8005446: 461c mov r4, r3 + 8005448: 6abb ldr r3, [r7, #40] ; 0x28 + 800544a: 2b00 cmp r3, #0 + 800544c: d10e bne.n 800546c + 800544e: 8823 ldrh r3, [r4, #0] + 8005450: b29b uxth r3, r3 + 8005452: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00 + 8005456: b29b uxth r3, r3 + 8005458: 8023 strh r3, [r4, #0] + 800545a: 8823 ldrh r3, [r4, #0] + 800545c: b29b uxth r3, r3 + 800545e: ea6f 4343 mvn.w r3, r3, lsl #17 + 8005462: ea6f 4353 mvn.w r3, r3, lsr #17 + 8005466: b29b uxth r3, r3 + 8005468: 8023 strh r3, [r4, #0] + 800546a: e043 b.n 80054f4 + 800546c: 6abb ldr r3, [r7, #40] ; 0x28 + 800546e: 2b3e cmp r3, #62 ; 0x3e + 8005470: d816 bhi.n 80054a0 + 8005472: 6abb ldr r3, [r7, #40] ; 0x28 + 8005474: 085b lsrs r3, r3, #1 + 8005476: 617b str r3, [r7, #20] + 8005478: 6abb ldr r3, [r7, #40] ; 0x28 + 800547a: f003 0301 and.w r3, r3, #1 + 800547e: 2b00 cmp r3, #0 + 8005480: d002 beq.n 8005488 + 8005482: 697b ldr r3, [r7, #20] + 8005484: 3301 adds r3, #1 + 8005486: 617b str r3, [r7, #20] + 8005488: 697b ldr r3, [r7, #20] + 800548a: b29b uxth r3, r3 + 800548c: 029b lsls r3, r3, #10 + 800548e: b29b uxth r3, r3 + 8005490: 8023 strh r3, [r4, #0] + 8005492: e02f b.n 80054f4 + 8005494: ffff80c0 .word 0xffff80c0 + 8005498: ffffc080 .word 0xffffc080 + 800549c: ffff8080 .word 0xffff8080 + 80054a0: 6abb ldr r3, [r7, #40] ; 0x28 + 80054a2: 095b lsrs r3, r3, #5 + 80054a4: 617b str r3, [r7, #20] + 80054a6: 6abb ldr r3, [r7, #40] ; 0x28 + 80054a8: f003 031f and.w r3, r3, #31 + 80054ac: 2b00 cmp r3, #0 + 80054ae: d102 bne.n 80054b6 + 80054b0: 697b ldr r3, [r7, #20] + 80054b2: 3b01 subs r3, #1 + 80054b4: 617b str r3, [r7, #20] + 80054b6: 697b ldr r3, [r7, #20] + 80054b8: b29b uxth r3, r3 + 80054ba: 029b lsls r3, r3, #10 + 80054bc: b29b uxth r3, r3 + 80054be: ea6f 4343 mvn.w r3, r3, lsl #17 + 80054c2: ea6f 4353 mvn.w r3, r3, lsr #17 + 80054c6: b29b uxth r3, r3 + 80054c8: 8023 strh r3, [r4, #0] + 80054ca: e013 b.n 80054f4 + 80054cc: 683b ldr r3, [r7, #0] + 80054ce: 785b ldrb r3, [r3, #1] + 80054d0: 2b01 cmp r3, #1 + 80054d2: d10f bne.n 80054f4 + 80054d4: 687b ldr r3, [r7, #4] + 80054d6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80054da: b29b uxth r3, r3 + 80054dc: 441c add r4, r3 + 80054de: 683b ldr r3, [r7, #0] + 80054e0: 781b ldrb r3, [r3, #0] + 80054e2: 011b lsls r3, r3, #4 + 80054e4: 4423 add r3, r4 + 80054e6: f203 430c addw r3, r3, #1036 ; 0x40c + 80054ea: 613b str r3, [r7, #16] + 80054ec: 6abb ldr r3, [r7, #40] ; 0x28 + 80054ee: b29a uxth r2, r3 + 80054f0: 693b ldr r3, [r7, #16] + 80054f2: 801a strh r2, [r3, #0] + } + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + 80054f4: 687a ldr r2, [r7, #4] + 80054f6: 683b ldr r3, [r7, #0] + 80054f8: 781b ldrb r3, [r3, #0] + 80054fa: 009b lsls r3, r3, #2 + 80054fc: 4413 add r3, r2 + 80054fe: 881b ldrh r3, [r3, #0] + 8005500: b29b uxth r3, r3 + 8005502: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8005506: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800550a: b29c uxth r4, r3 + 800550c: f484 5380 eor.w r3, r4, #4096 ; 0x1000 + 8005510: b29c uxth r4, r3 + 8005512: f484 5300 eor.w r3, r4, #8192 ; 0x2000 + 8005516: b29c uxth r4, r3 + 8005518: 687a ldr r2, [r7, #4] + 800551a: 683b ldr r3, [r7, #0] + 800551c: 781b ldrb r3, [r3, #0] + 800551e: 009b lsls r3, r3, #2 + 8005520: 441a add r2, r3 + 8005522: 4b04 ldr r3, [pc, #16] ; (8005534 ) + 8005524: 4323 orrs r3, r4 + 8005526: b29b uxth r3, r3 + 8005528: 8013 strh r3, [r2, #0] + } + + return HAL_OK; + 800552a: 2300 movs r3, #0 +} + 800552c: 4618 mov r0, r3 + 800552e: 3734 adds r7, #52 ; 0x34 + 8005530: 46bd mov sp, r7 + 8005532: bd90 pop {r4, r7, pc} + 8005534: ffff8080 .word 0xffff8080 + +08005538 : + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + 8005538: b490 push {r4, r7} + 800553a: b082 sub sp, #8 + 800553c: af00 add r7, sp, #0 + 800553e: 6078 str r0, [r7, #4] + 8005540: 6039 str r1, [r7, #0] + if (ep->is_in != 0U) + 8005542: 683b ldr r3, [r7, #0] + 8005544: 785b ldrb r3, [r3, #1] + 8005546: 2b00 cmp r3, #0 + 8005548: d018 beq.n 800557c + { + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); + 800554a: 687a ldr r2, [r7, #4] + 800554c: 683b ldr r3, [r7, #0] + 800554e: 781b ldrb r3, [r3, #0] + 8005550: 009b lsls r3, r3, #2 + 8005552: 4413 add r3, r2 + 8005554: 881b ldrh r3, [r3, #0] + 8005556: b29b uxth r3, r3 + 8005558: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800555c: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8005560: b29c uxth r4, r3 + 8005562: f084 0310 eor.w r3, r4, #16 + 8005566: b29c uxth r4, r3 + 8005568: 687a ldr r2, [r7, #4] + 800556a: 683b ldr r3, [r7, #0] + 800556c: 781b ldrb r3, [r3, #0] + 800556e: 009b lsls r3, r3, #2 + 8005570: 441a add r2, r3 + 8005572: 4b11 ldr r3, [pc, #68] ; (80055b8 ) + 8005574: 4323 orrs r3, r4 + 8005576: b29b uxth r3, r3 + 8005578: 8013 strh r3, [r2, #0] + 800557a: e017 b.n 80055ac + } + else + { + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); + 800557c: 687a ldr r2, [r7, #4] + 800557e: 683b ldr r3, [r7, #0] + 8005580: 781b ldrb r3, [r3, #0] + 8005582: 009b lsls r3, r3, #2 + 8005584: 4413 add r3, r2 + 8005586: 881b ldrh r3, [r3, #0] + 8005588: b29b uxth r3, r3 + 800558a: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800558e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8005592: b29c uxth r4, r3 + 8005594: f484 5380 eor.w r3, r4, #4096 ; 0x1000 + 8005598: b29c uxth r4, r3 + 800559a: 687a ldr r2, [r7, #4] + 800559c: 683b ldr r3, [r7, #0] + 800559e: 781b ldrb r3, [r3, #0] + 80055a0: 009b lsls r3, r3, #2 + 80055a2: 441a add r2, r3 + 80055a4: 4b04 ldr r3, [pc, #16] ; (80055b8 ) + 80055a6: 4323 orrs r3, r4 + 80055a8: b29b uxth r3, r3 + 80055aa: 8013 strh r3, [r2, #0] + } + + return HAL_OK; + 80055ac: 2300 movs r3, #0 +} + 80055ae: 4618 mov r0, r3 + 80055b0: 3708 adds r7, #8 + 80055b2: 46bd mov sp, r7 + 80055b4: bc90 pop {r4, r7} + 80055b6: 4770 bx lr + 80055b8: ffff8080 .word 0xffff8080 + +080055bc : + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + 80055bc: b490 push {r4, r7} + 80055be: b082 sub sp, #8 + 80055c0: af00 add r7, sp, #0 + 80055c2: 6078 str r0, [r7, #4] + 80055c4: 6039 str r1, [r7, #0] + if (ep->doublebuffer == 0U) + 80055c6: 683b ldr r3, [r7, #0] + 80055c8: 7b1b ldrb r3, [r3, #12] + 80055ca: 2b00 cmp r3, #0 + 80055cc: d17d bne.n 80056ca + { + if (ep->is_in != 0U) + 80055ce: 683b ldr r3, [r7, #0] + 80055d0: 785b ldrb r3, [r3, #1] + 80055d2: 2b00 cmp r3, #0 + 80055d4: d03d beq.n 8005652 + { + PCD_CLEAR_TX_DTOG(USBx, ep->num); + 80055d6: 687a ldr r2, [r7, #4] + 80055d8: 683b ldr r3, [r7, #0] + 80055da: 781b ldrb r3, [r3, #0] + 80055dc: 009b lsls r3, r3, #2 + 80055de: 4413 add r3, r2 + 80055e0: 881b ldrh r3, [r3, #0] + 80055e2: b29c uxth r4, r3 + 80055e4: 4623 mov r3, r4 + 80055e6: f003 0340 and.w r3, r3, #64 ; 0x40 + 80055ea: 2b00 cmp r3, #0 + 80055ec: d014 beq.n 8005618 + 80055ee: 687a ldr r2, [r7, #4] + 80055f0: 683b ldr r3, [r7, #0] + 80055f2: 781b ldrb r3, [r3, #0] + 80055f4: 009b lsls r3, r3, #2 + 80055f6: 4413 add r3, r2 + 80055f8: 881b ldrh r3, [r3, #0] + 80055fa: b29b uxth r3, r3 + 80055fc: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8005600: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8005604: b29c uxth r4, r3 + 8005606: 687a ldr r2, [r7, #4] + 8005608: 683b ldr r3, [r7, #0] + 800560a: 781b ldrb r3, [r3, #0] + 800560c: 009b lsls r3, r3, #2 + 800560e: 441a add r2, r3 + 8005610: 4b31 ldr r3, [pc, #196] ; (80056d8 ) + 8005612: 4323 orrs r3, r4 + 8005614: b29b uxth r3, r3 + 8005616: 8013 strh r3, [r2, #0] + + if (ep->type != EP_TYPE_ISOC) + 8005618: 683b ldr r3, [r7, #0] + 800561a: 78db ldrb r3, [r3, #3] + 800561c: 2b01 cmp r3, #1 + 800561e: d054 beq.n 80056ca + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + 8005620: 687a ldr r2, [r7, #4] + 8005622: 683b ldr r3, [r7, #0] + 8005624: 781b ldrb r3, [r3, #0] + 8005626: 009b lsls r3, r3, #2 + 8005628: 4413 add r3, r2 + 800562a: 881b ldrh r3, [r3, #0] + 800562c: b29b uxth r3, r3 + 800562e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8005632: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8005636: b29c uxth r4, r3 + 8005638: f084 0320 eor.w r3, r4, #32 + 800563c: b29c uxth r4, r3 + 800563e: 687a ldr r2, [r7, #4] + 8005640: 683b ldr r3, [r7, #0] + 8005642: 781b ldrb r3, [r3, #0] + 8005644: 009b lsls r3, r3, #2 + 8005646: 441a add r2, r3 + 8005648: 4b24 ldr r3, [pc, #144] ; (80056dc ) + 800564a: 4323 orrs r3, r4 + 800564c: b29b uxth r3, r3 + 800564e: 8013 strh r3, [r2, #0] + 8005650: e03b b.n 80056ca + } + } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + 8005652: 687a ldr r2, [r7, #4] + 8005654: 683b ldr r3, [r7, #0] + 8005656: 781b ldrb r3, [r3, #0] + 8005658: 009b lsls r3, r3, #2 + 800565a: 4413 add r3, r2 + 800565c: 881b ldrh r3, [r3, #0] + 800565e: b29c uxth r4, r3 + 8005660: 4623 mov r3, r4 + 8005662: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8005666: 2b00 cmp r3, #0 + 8005668: d014 beq.n 8005694 + 800566a: 687a ldr r2, [r7, #4] + 800566c: 683b ldr r3, [r7, #0] + 800566e: 781b ldrb r3, [r3, #0] + 8005670: 009b lsls r3, r3, #2 + 8005672: 4413 add r3, r2 + 8005674: 881b ldrh r3, [r3, #0] + 8005676: b29b uxth r3, r3 + 8005678: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800567c: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8005680: b29c uxth r4, r3 + 8005682: 687a ldr r2, [r7, #4] + 8005684: 683b ldr r3, [r7, #0] + 8005686: 781b ldrb r3, [r3, #0] + 8005688: 009b lsls r3, r3, #2 + 800568a: 441a add r2, r3 + 800568c: 4b14 ldr r3, [pc, #80] ; (80056e0 ) + 800568e: 4323 orrs r3, r4 + 8005690: b29b uxth r3, r3 + 8005692: 8013 strh r3, [r2, #0] + + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + 8005694: 687a ldr r2, [r7, #4] + 8005696: 683b ldr r3, [r7, #0] + 8005698: 781b ldrb r3, [r3, #0] + 800569a: 009b lsls r3, r3, #2 + 800569c: 4413 add r3, r2 + 800569e: 881b ldrh r3, [r3, #0] + 80056a0: b29b uxth r3, r3 + 80056a2: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 80056a6: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80056aa: b29c uxth r4, r3 + 80056ac: f484 5380 eor.w r3, r4, #4096 ; 0x1000 + 80056b0: b29c uxth r4, r3 + 80056b2: f484 5300 eor.w r3, r4, #8192 ; 0x2000 + 80056b6: b29c uxth r4, r3 + 80056b8: 687a ldr r2, [r7, #4] + 80056ba: 683b ldr r3, [r7, #0] + 80056bc: 781b ldrb r3, [r3, #0] + 80056be: 009b lsls r3, r3, #2 + 80056c0: 441a add r2, r3 + 80056c2: 4b06 ldr r3, [pc, #24] ; (80056dc ) + 80056c4: 4323 orrs r3, r4 + 80056c6: b29b uxth r3, r3 + 80056c8: 8013 strh r3, [r2, #0] + } + } + + return HAL_OK; + 80056ca: 2300 movs r3, #0 +} + 80056cc: 4618 mov r0, r3 + 80056ce: 3708 adds r7, #8 + 80056d0: 46bd mov sp, r7 + 80056d2: bc90 pop {r4, r7} + 80056d4: 4770 bx lr + 80056d6: bf00 nop + 80056d8: ffff80c0 .word 0xffff80c0 + 80056dc: ffff8080 .word 0xffff8080 + 80056e0: ffffc080 .word 0xffffc080 + +080056e4 : + * @param address : new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) +{ + 80056e4: b480 push {r7} + 80056e6: b083 sub sp, #12 + 80056e8: af00 add r7, sp, #0 + 80056ea: 6078 str r0, [r7, #4] + 80056ec: 460b mov r3, r1 + 80056ee: 70fb strb r3, [r7, #3] + if (address == 0U) + 80056f0: 78fb ldrb r3, [r7, #3] + 80056f2: 2b00 cmp r3, #0 + 80056f4: d103 bne.n 80056fe + { + /* set device address and enable function */ + USBx->DADDR = USB_DADDR_EF; + 80056f6: 687b ldr r3, [r7, #4] + 80056f8: 2280 movs r2, #128 ; 0x80 + 80056fa: f8a3 204c strh.w r2, [r3, #76] ; 0x4c + } + + return HAL_OK; + 80056fe: 2300 movs r3, #0 +} + 8005700: 4618 mov r0, r3 + 8005702: 370c adds r7, #12 + 8005704: 46bd mov sp, r7 + 8005706: bc80 pop {r7} + 8005708: 4770 bx lr + +0800570a : + * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) +{ + 800570a: b480 push {r7} + 800570c: b083 sub sp, #12 + 800570e: af00 add r7, sp, #0 + 8005710: 6078 str r0, [r7, #4] + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; + 8005712: 2300 movs r3, #0 +} + 8005714: 4618 mov r0, r3 + 8005716: 370c adds r7, #12 + 8005718: 46bd mov sp, r7 + 800571a: bc80 pop {r7} + 800571c: 4770 bx lr + +0800571e : + * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) +{ + 800571e: b480 push {r7} + 8005720: b083 sub sp, #12 + 8005722: af00 add r7, sp, #0 + 8005724: 6078 str r0, [r7, #4] + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; + 8005726: 2300 movs r3, #0 +} + 8005728: 4618 mov r0, r3 + 800572a: 370c adds r7, #12 + 800572c: 46bd mov sp, r7 + 800572e: bc80 pop {r7} + 8005730: 4770 bx lr + +08005732 : + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx : Selected device + * @retval HAL status + */ +uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) +{ + 8005732: b480 push {r7} + 8005734: b085 sub sp, #20 + 8005736: af00 add r7, sp, #0 + 8005738: 6078 str r0, [r7, #4] + uint32_t tmpreg; + + tmpreg = USBx->ISTR; + 800573a: 687b ldr r3, [r7, #4] + 800573c: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8005740: b29b uxth r3, r3 + 8005742: 60fb str r3, [r7, #12] + return tmpreg; + 8005744: 68fb ldr r3, [r7, #12] +} + 8005746: 4618 mov r0, r3 + 8005748: 3714 adds r7, #20 + 800574a: 46bd mov sp, r7 + 800574c: bc80 pop {r7} + 800574e: 4770 bx lr + +08005750 : + * @param USBx Selected device + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) +{ + 8005750: b480 push {r7} + 8005752: b083 sub sp, #12 + 8005754: af00 add r7, sp, #0 + 8005756: 6078 str r0, [r7, #4] + 8005758: 6039 str r1, [r7, #0] + UNUSED(psetup); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; + 800575a: 2300 movs r3, #0 +} + 800575c: 4618 mov r0, r3 + 800575e: 370c adds r7, #12 + 8005760: 46bd mov sp, r7 + 8005762: bc80 pop {r7} + 8005764: 4770 bx lr + +08005766 : + * @param wPMABufAddr address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + 8005766: b480 push {r7} + 8005768: b08d sub sp, #52 ; 0x34 + 800576a: af00 add r7, sp, #0 + 800576c: 60f8 str r0, [r7, #12] + 800576e: 60b9 str r1, [r7, #8] + 8005770: 4611 mov r1, r2 + 8005772: 461a mov r2, r3 + 8005774: 460b mov r3, r1 + 8005776: 80fb strh r3, [r7, #6] + 8005778: 4613 mov r3, r2 + 800577a: 80bb strh r3, [r7, #4] + uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; + 800577c: 88bb ldrh r3, [r7, #4] + 800577e: 3301 adds r3, #1 + 8005780: 085b lsrs r3, r3, #1 + 8005782: 623b str r3, [r7, #32] + uint32_t BaseAddr = (uint32_t)USBx; + 8005784: 68fb ldr r3, [r7, #12] + 8005786: 61fb str r3, [r7, #28] + uint32_t i, temp1, temp2; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + 8005788: 68bb ldr r3, [r7, #8] + 800578a: 627b str r3, [r7, #36] ; 0x24 + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + 800578c: 88fb ldrh r3, [r7, #6] + 800578e: 005a lsls r2, r3, #1 + 8005790: 69fb ldr r3, [r7, #28] + 8005792: 4413 add r3, r2 + 8005794: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8005798: 62bb str r3, [r7, #40] ; 0x28 + + for (i = n; i != 0U; i--) + 800579a: 6a3b ldr r3, [r7, #32] + 800579c: 62fb str r3, [r7, #44] ; 0x2c + 800579e: e01e b.n 80057de + { + temp1 = *pBuf; + 80057a0: 6a7b ldr r3, [r7, #36] ; 0x24 + 80057a2: 781b ldrb r3, [r3, #0] + 80057a4: 61bb str r3, [r7, #24] + pBuf++; + 80057a6: 6a7b ldr r3, [r7, #36] ; 0x24 + 80057a8: 3301 adds r3, #1 + 80057aa: 627b str r3, [r7, #36] ; 0x24 + temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8)); + 80057ac: 6a7b ldr r3, [r7, #36] ; 0x24 + 80057ae: 781b ldrb r3, [r3, #0] + 80057b0: b29b uxth r3, r3 + 80057b2: 021b lsls r3, r3, #8 + 80057b4: b29b uxth r3, r3 + 80057b6: 461a mov r2, r3 + 80057b8: 69bb ldr r3, [r7, #24] + 80057ba: 4313 orrs r3, r2 + 80057bc: 617b str r3, [r7, #20] + *pdwVal = (uint16_t)temp2; + 80057be: 697b ldr r3, [r7, #20] + 80057c0: b29a uxth r2, r3 + 80057c2: 6abb ldr r3, [r7, #40] ; 0x28 + 80057c4: 801a strh r2, [r3, #0] + pdwVal++; + 80057c6: 6abb ldr r3, [r7, #40] ; 0x28 + 80057c8: 3302 adds r3, #2 + 80057ca: 62bb str r3, [r7, #40] ; 0x28 + +#if PMA_ACCESS > 1U + pdwVal++; + 80057cc: 6abb ldr r3, [r7, #40] ; 0x28 + 80057ce: 3302 adds r3, #2 + 80057d0: 62bb str r3, [r7, #40] ; 0x28 +#endif + + pBuf++; + 80057d2: 6a7b ldr r3, [r7, #36] ; 0x24 + 80057d4: 3301 adds r3, #1 + 80057d6: 627b str r3, [r7, #36] ; 0x24 + for (i = n; i != 0U; i--) + 80057d8: 6afb ldr r3, [r7, #44] ; 0x2c + 80057da: 3b01 subs r3, #1 + 80057dc: 62fb str r3, [r7, #44] ; 0x2c + 80057de: 6afb ldr r3, [r7, #44] ; 0x2c + 80057e0: 2b00 cmp r3, #0 + 80057e2: d1dd bne.n 80057a0 + } +} + 80057e4: bf00 nop + 80057e6: 3734 adds r7, #52 ; 0x34 + 80057e8: 46bd mov sp, r7 + 80057ea: bc80 pop {r7} + 80057ec: 4770 bx lr + +080057ee : + * @param wPMABufAddr address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + 80057ee: b480 push {r7} + 80057f0: b08b sub sp, #44 ; 0x2c + 80057f2: af00 add r7, sp, #0 + 80057f4: 60f8 str r0, [r7, #12] + 80057f6: 60b9 str r1, [r7, #8] + 80057f8: 4611 mov r1, r2 + 80057fa: 461a mov r2, r3 + 80057fc: 460b mov r3, r1 + 80057fe: 80fb strh r3, [r7, #6] + 8005800: 4613 mov r3, r2 + 8005802: 80bb strh r3, [r7, #4] + uint32_t n = (uint32_t)wNBytes >> 1; + 8005804: 88bb ldrh r3, [r7, #4] + 8005806: 085b lsrs r3, r3, #1 + 8005808: b29b uxth r3, r3 + 800580a: 61bb str r3, [r7, #24] + uint32_t BaseAddr = (uint32_t)USBx; + 800580c: 68fb ldr r3, [r7, #12] + 800580e: 617b str r3, [r7, #20] + uint32_t i, temp; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + 8005810: 68bb ldr r3, [r7, #8] + 8005812: 61fb str r3, [r7, #28] + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + 8005814: 88fb ldrh r3, [r7, #6] + 8005816: 005a lsls r2, r3, #1 + 8005818: 697b ldr r3, [r7, #20] + 800581a: 4413 add r3, r2 + 800581c: f503 6380 add.w r3, r3, #1024 ; 0x400 + 8005820: 623b str r3, [r7, #32] + + for (i = n; i != 0U; i--) + 8005822: 69bb ldr r3, [r7, #24] + 8005824: 627b str r3, [r7, #36] ; 0x24 + 8005826: e01b b.n 8005860 + { + temp = *(__IO uint16_t *)pdwVal; + 8005828: 6a3b ldr r3, [r7, #32] + 800582a: 881b ldrh r3, [r3, #0] + 800582c: b29b uxth r3, r3 + 800582e: 613b str r3, [r7, #16] + pdwVal++; + 8005830: 6a3b ldr r3, [r7, #32] + 8005832: 3302 adds r3, #2 + 8005834: 623b str r3, [r7, #32] + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + 8005836: 693b ldr r3, [r7, #16] + 8005838: b2da uxtb r2, r3 + 800583a: 69fb ldr r3, [r7, #28] + 800583c: 701a strb r2, [r3, #0] + pBuf++; + 800583e: 69fb ldr r3, [r7, #28] + 8005840: 3301 adds r3, #1 + 8005842: 61fb str r3, [r7, #28] + *pBuf = (uint8_t)((temp >> 8) & 0xFFU); + 8005844: 693b ldr r3, [r7, #16] + 8005846: 0a1b lsrs r3, r3, #8 + 8005848: b2da uxtb r2, r3 + 800584a: 69fb ldr r3, [r7, #28] + 800584c: 701a strb r2, [r3, #0] + pBuf++; + 800584e: 69fb ldr r3, [r7, #28] + 8005850: 3301 adds r3, #1 + 8005852: 61fb str r3, [r7, #28] + +#if PMA_ACCESS > 1U + pdwVal++; + 8005854: 6a3b ldr r3, [r7, #32] + 8005856: 3302 adds r3, #2 + 8005858: 623b str r3, [r7, #32] + for (i = n; i != 0U; i--) + 800585a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800585c: 3b01 subs r3, #1 + 800585e: 627b str r3, [r7, #36] ; 0x24 + 8005860: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005862: 2b00 cmp r3, #0 + 8005864: d1e0 bne.n 8005828 +#endif + } + + if ((wNBytes % 2U) != 0U) + 8005866: 88bb ldrh r3, [r7, #4] + 8005868: f003 0301 and.w r3, r3, #1 + 800586c: b29b uxth r3, r3 + 800586e: 2b00 cmp r3, #0 + 8005870: d007 beq.n 8005882 + { + temp = *pdwVal; + 8005872: 6a3b ldr r3, [r7, #32] + 8005874: 881b ldrh r3, [r3, #0] + 8005876: b29b uxth r3, r3 + 8005878: 613b str r3, [r7, #16] + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + 800587a: 693b ldr r3, [r7, #16] + 800587c: b2da uxtb r2, r3 + 800587e: 69fb ldr r3, [r7, #28] + 8005880: 701a strb r2, [r3, #0] + } +} + 8005882: bf00 nop + 8005884: 372c adds r7, #44 ; 0x2c + 8005886: 46bd mov sp, r7 + 8005888: bc80 pop {r7} + 800588a: 4770 bx lr + +0800588c : + +#ifndef _swap_int16_t +#define _swap_int16_t(a, b) { int16_t t = a; a = b; b = t; } +#endif + +static void ILI9341_Select() { + 800588c: b580 push {r7, lr} + 800588e: af00 add r7, sp, #0 + HAL_GPIO_WritePin(ILI9341_CS_GPIO_Port, ILI9341_CS_Pin, GPIO_PIN_RESET); + 8005890: 2200 movs r2, #0 + 8005892: 2140 movs r1, #64 ; 0x40 + 8005894: 4802 ldr r0, [pc, #8] ; (80058a0 ) + 8005896: f7fb feb0 bl 80015fa +} + 800589a: bf00 nop + 800589c: bd80 pop {r7, pc} + 800589e: bf00 nop + 80058a0: 40010800 .word 0x40010800 + +080058a4 : + +void ILI9341_Unselect() { + 80058a4: b580 push {r7, lr} + 80058a6: af00 add r7, sp, #0 + HAL_GPIO_WritePin(ILI9341_CS_GPIO_Port, ILI9341_CS_Pin, GPIO_PIN_SET); + 80058a8: 2201 movs r2, #1 + 80058aa: 2140 movs r1, #64 ; 0x40 + 80058ac: 4802 ldr r0, [pc, #8] ; (80058b8 ) + 80058ae: f7fb fea4 bl 80015fa +} + 80058b2: bf00 nop + 80058b4: bd80 pop {r7, pc} + 80058b6: bf00 nop + 80058b8: 40010800 .word 0x40010800 + +080058bc : + +static void ILI9341_Reset() { + 80058bc: b580 push {r7, lr} + 80058be: af00 add r7, sp, #0 + HAL_GPIO_WritePin(ILI9341_RES_GPIO_Port, ILI9341_RES_Pin, GPIO_PIN_RESET); + 80058c0: 2200 movs r2, #0 + 80058c2: 2180 movs r1, #128 ; 0x80 + 80058c4: 4806 ldr r0, [pc, #24] ; (80058e0 ) + 80058c6: f7fb fe98 bl 80015fa + HAL_Delay(5); + 80058ca: 2005 movs r0, #5 + 80058cc: f7fb fbf4 bl 80010b8 + HAL_GPIO_WritePin(ILI9341_RES_GPIO_Port, ILI9341_RES_Pin, GPIO_PIN_SET); + 80058d0: 2201 movs r2, #1 + 80058d2: 2180 movs r1, #128 ; 0x80 + 80058d4: 4802 ldr r0, [pc, #8] ; (80058e0 ) + 80058d6: f7fb fe90 bl 80015fa +} + 80058da: bf00 nop + 80058dc: bd80 pop {r7, pc} + 80058de: bf00 nop + 80058e0: 40010800 .word 0x40010800 + +080058e4 : + +static void ILI9341_WriteCommand(uint8_t cmd) { + 80058e4: b580 push {r7, lr} + 80058e6: b082 sub sp, #8 + 80058e8: af00 add r7, sp, #0 + 80058ea: 4603 mov r3, r0 + 80058ec: 71fb strb r3, [r7, #7] + HAL_GPIO_WritePin(ILI9341_DC_GPIO_Port, ILI9341_DC_Pin, GPIO_PIN_RESET); + 80058ee: 2200 movs r2, #0 + 80058f0: 2120 movs r1, #32 + 80058f2: 4807 ldr r0, [pc, #28] ; (8005910 ) + 80058f4: f7fb fe81 bl 80015fa + HAL_SPI_Transmit(&ILI9341_SPI_PORT, &cmd, sizeof(cmd), HAL_MAX_DELAY); + 80058f8: 1df9 adds r1, r7, #7 + 80058fa: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 80058fe: 2201 movs r2, #1 + 8005900: 4804 ldr r0, [pc, #16] ; (8005914 ) + 8005902: f7fe f9f6 bl 8003cf2 +} + 8005906: bf00 nop + 8005908: 3708 adds r7, #8 + 800590a: 46bd mov sp, r7 + 800590c: bd80 pop {r7, pc} + 800590e: bf00 nop + 8005910: 40010800 .word 0x40010800 + 8005914: 200011fc .word 0x200011fc + +08005918 : + +static void ILI9341_WriteData(uint8_t* buff, size_t buff_size) { + 8005918: b580 push {r7, lr} + 800591a: b084 sub sp, #16 + 800591c: af00 add r7, sp, #0 + 800591e: 6078 str r0, [r7, #4] + 8005920: 6039 str r1, [r7, #0] + HAL_GPIO_WritePin(ILI9341_DC_GPIO_Port, ILI9341_DC_Pin, GPIO_PIN_SET); + 8005922: 2201 movs r2, #1 + 8005924: 2120 movs r1, #32 + 8005926: 4810 ldr r0, [pc, #64] ; (8005968 ) + 8005928: f7fb fe67 bl 80015fa + + // split data in small chunks because HAL can't send more then 64K at once + while(buff_size > 0) { + 800592c: e015 b.n 800595a + uint16_t chunk_size = buff_size > 32768 ? 32768 : buff_size; + 800592e: 683b ldr r3, [r7, #0] + 8005930: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8005934: bf28 it cs + 8005936: f44f 4300 movcs.w r3, #32768 ; 0x8000 + 800593a: 81fb strh r3, [r7, #14] + HAL_SPI_Transmit(&ILI9341_SPI_PORT, buff, chunk_size, HAL_MAX_DELAY); + 800593c: 89fa ldrh r2, [r7, #14] + 800593e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8005942: 6879 ldr r1, [r7, #4] + 8005944: 4809 ldr r0, [pc, #36] ; (800596c ) + 8005946: f7fe f9d4 bl 8003cf2 + buff += chunk_size; + 800594a: 89fb ldrh r3, [r7, #14] + 800594c: 687a ldr r2, [r7, #4] + 800594e: 4413 add r3, r2 + 8005950: 607b str r3, [r7, #4] + buff_size -= chunk_size; + 8005952: 89fb ldrh r3, [r7, #14] + 8005954: 683a ldr r2, [r7, #0] + 8005956: 1ad3 subs r3, r2, r3 + 8005958: 603b str r3, [r7, #0] + while(buff_size > 0) { + 800595a: 683b ldr r3, [r7, #0] + 800595c: 2b00 cmp r3, #0 + 800595e: d1e6 bne.n 800592e + } +} + 8005960: bf00 nop + 8005962: 3710 adds r7, #16 + 8005964: 46bd mov sp, r7 + 8005966: bd80 pop {r7, pc} + 8005968: 40010800 .word 0x40010800 + 800596c: 200011fc .word 0x200011fc + +08005970 : + +static void ILI9341_SetAddressWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) { + 8005970: b590 push {r4, r7, lr} + 8005972: b085 sub sp, #20 + 8005974: af00 add r7, sp, #0 + 8005976: 4604 mov r4, r0 + 8005978: 4608 mov r0, r1 + 800597a: 4611 mov r1, r2 + 800597c: 461a mov r2, r3 + 800597e: 4623 mov r3, r4 + 8005980: 80fb strh r3, [r7, #6] + 8005982: 4603 mov r3, r0 + 8005984: 80bb strh r3, [r7, #4] + 8005986: 460b mov r3, r1 + 8005988: 807b strh r3, [r7, #2] + 800598a: 4613 mov r3, r2 + 800598c: 803b strh r3, [r7, #0] + // column address set + ILI9341_WriteCommand(0x2A); // CASET + 800598e: 202a movs r0, #42 ; 0x2a + 8005990: f7ff ffa8 bl 80058e4 + { + uint8_t data[] = { (x0 >> 8) & 0xFF, x0 & 0xFF, (x1 >> 8) & 0xFF, x1 & 0xFF }; + 8005994: 88fb ldrh r3, [r7, #6] + 8005996: 0a1b lsrs r3, r3, #8 + 8005998: b29b uxth r3, r3 + 800599a: b2db uxtb r3, r3 + 800599c: 733b strb r3, [r7, #12] + 800599e: 88fb ldrh r3, [r7, #6] + 80059a0: b2db uxtb r3, r3 + 80059a2: 737b strb r3, [r7, #13] + 80059a4: 887b ldrh r3, [r7, #2] + 80059a6: 0a1b lsrs r3, r3, #8 + 80059a8: b29b uxth r3, r3 + 80059aa: b2db uxtb r3, r3 + 80059ac: 73bb strb r3, [r7, #14] + 80059ae: 887b ldrh r3, [r7, #2] + 80059b0: b2db uxtb r3, r3 + 80059b2: 73fb strb r3, [r7, #15] + ILI9341_WriteData(data, sizeof(data)); + 80059b4: f107 030c add.w r3, r7, #12 + 80059b8: 2104 movs r1, #4 + 80059ba: 4618 mov r0, r3 + 80059bc: f7ff ffac bl 8005918 + } + + // row address set + ILI9341_WriteCommand(0x2B); // RASET + 80059c0: 202b movs r0, #43 ; 0x2b + 80059c2: f7ff ff8f bl 80058e4 + { + uint8_t data[] = { (y0 >> 8) & 0xFF, y0 & 0xFF, (y1 >> 8) & 0xFF, y1 & 0xFF }; + 80059c6: 88bb ldrh r3, [r7, #4] + 80059c8: 0a1b lsrs r3, r3, #8 + 80059ca: b29b uxth r3, r3 + 80059cc: b2db uxtb r3, r3 + 80059ce: 723b strb r3, [r7, #8] + 80059d0: 88bb ldrh r3, [r7, #4] + 80059d2: b2db uxtb r3, r3 + 80059d4: 727b strb r3, [r7, #9] + 80059d6: 883b ldrh r3, [r7, #0] + 80059d8: 0a1b lsrs r3, r3, #8 + 80059da: b29b uxth r3, r3 + 80059dc: b2db uxtb r3, r3 + 80059de: 72bb strb r3, [r7, #10] + 80059e0: 883b ldrh r3, [r7, #0] + 80059e2: b2db uxtb r3, r3 + 80059e4: 72fb strb r3, [r7, #11] + ILI9341_WriteData(data, sizeof(data)); + 80059e6: f107 0308 add.w r3, r7, #8 + 80059ea: 2104 movs r1, #4 + 80059ec: 4618 mov r0, r3 + 80059ee: f7ff ff93 bl 8005918 + } + + // write to RAM + ILI9341_WriteCommand(0x2C); // RAMWR + 80059f2: 202c movs r0, #44 ; 0x2c + 80059f4: f7ff ff76 bl 80058e4 +} + 80059f8: bf00 nop + 80059fa: 3714 adds r7, #20 + 80059fc: 46bd mov sp, r7 + 80059fe: bd90 pop {r4, r7, pc} + +08005a00 : + +void ILI9341_Init() { + 8005a00: b590 push {r4, r7, lr} + 8005a02: b09b sub sp, #108 ; 0x6c + 8005a04: af00 add r7, sp, #0 + ILI9341_Select(); + 8005a06: f7ff ff41 bl 800588c + ILI9341_Reset(); + 8005a0a: f7ff ff57 bl 80058bc + + // command list is based on https://github.com/martnak/STM32-ILI9341 + + // SOFTWARE RESET + ILI9341_WriteCommand(0x01); + 8005a0e: 2001 movs r0, #1 + 8005a10: f7ff ff68 bl 80058e4 + HAL_Delay(1000); + 8005a14: f44f 707a mov.w r0, #1000 ; 0x3e8 + 8005a18: f7fb fb4e bl 80010b8 + + // POWER CONTROL A + ILI9341_WriteCommand(0xCB); + 8005a1c: 20cb movs r0, #203 ; 0xcb + 8005a1e: f7ff ff61 bl 80058e4 + { + uint8_t data[] = { 0x39, 0x2C, 0x00, 0x34, 0x02 }; + 8005a22: 4a8b ldr r2, [pc, #556] ; (8005c50 ) + 8005a24: f107 0360 add.w r3, r7, #96 ; 0x60 + 8005a28: e892 0003 ldmia.w r2, {r0, r1} + 8005a2c: 6018 str r0, [r3, #0] + 8005a2e: 3304 adds r3, #4 + 8005a30: 7019 strb r1, [r3, #0] + ILI9341_WriteData(data, sizeof(data)); + 8005a32: f107 0360 add.w r3, r7, #96 ; 0x60 + 8005a36: 2105 movs r1, #5 + 8005a38: 4618 mov r0, r3 + 8005a3a: f7ff ff6d bl 8005918 + } + + // POWER CONTROL B + ILI9341_WriteCommand(0xCF); + 8005a3e: 20cf movs r0, #207 ; 0xcf + 8005a40: f7ff ff50 bl 80058e4 + { + uint8_t data[] = { 0x00, 0xC1, 0x30 }; + 8005a44: 4a83 ldr r2, [pc, #524] ; (8005c54 ) + 8005a46: f107 035c add.w r3, r7, #92 ; 0x5c + 8005a4a: 6812 ldr r2, [r2, #0] + 8005a4c: 4611 mov r1, r2 + 8005a4e: 8019 strh r1, [r3, #0] + 8005a50: 3302 adds r3, #2 + 8005a52: 0c12 lsrs r2, r2, #16 + 8005a54: 701a strb r2, [r3, #0] + ILI9341_WriteData(data, sizeof(data)); + 8005a56: f107 035c add.w r3, r7, #92 ; 0x5c + 8005a5a: 2103 movs r1, #3 + 8005a5c: 4618 mov r0, r3 + 8005a5e: f7ff ff5b bl 8005918 + } + + // DRIVER TIMING CONTROL A + ILI9341_WriteCommand(0xE8); + 8005a62: 20e8 movs r0, #232 ; 0xe8 + 8005a64: f7ff ff3e bl 80058e4 + { + uint8_t data[] = { 0x85, 0x00, 0x78 }; + 8005a68: 4a7b ldr r2, [pc, #492] ; (8005c58 ) + 8005a6a: f107 0358 add.w r3, r7, #88 ; 0x58 + 8005a6e: 6812 ldr r2, [r2, #0] + 8005a70: 4611 mov r1, r2 + 8005a72: 8019 strh r1, [r3, #0] + 8005a74: 3302 adds r3, #2 + 8005a76: 0c12 lsrs r2, r2, #16 + 8005a78: 701a strb r2, [r3, #0] + ILI9341_WriteData(data, sizeof(data)); + 8005a7a: f107 0358 add.w r3, r7, #88 ; 0x58 + 8005a7e: 2103 movs r1, #3 + 8005a80: 4618 mov r0, r3 + 8005a82: f7ff ff49 bl 8005918 + } + + // DRIVER TIMING CONTROL B + ILI9341_WriteCommand(0xEA); + 8005a86: 20ea movs r0, #234 ; 0xea + 8005a88: f7ff ff2c bl 80058e4 + { + uint8_t data[] = { 0x00, 0x00 }; + 8005a8c: 2300 movs r3, #0 + 8005a8e: f887 3054 strb.w r3, [r7, #84] ; 0x54 + 8005a92: 2300 movs r3, #0 + 8005a94: f887 3055 strb.w r3, [r7, #85] ; 0x55 + ILI9341_WriteData(data, sizeof(data)); + 8005a98: f107 0354 add.w r3, r7, #84 ; 0x54 + 8005a9c: 2102 movs r1, #2 + 8005a9e: 4618 mov r0, r3 + 8005aa0: f7ff ff3a bl 8005918 + } + + // POWER ON SEQUENCE CONTROL + ILI9341_WriteCommand(0xED); + 8005aa4: 20ed movs r0, #237 ; 0xed + 8005aa6: f7ff ff1d bl 80058e4 + { + uint8_t data[] = { 0x64, 0x03, 0x12, 0x81 }; + 8005aaa: 4b6c ldr r3, [pc, #432] ; (8005c5c ) + 8005aac: 681b ldr r3, [r3, #0] + 8005aae: 653b str r3, [r7, #80] ; 0x50 + ILI9341_WriteData(data, sizeof(data)); + 8005ab0: f107 0350 add.w r3, r7, #80 ; 0x50 + 8005ab4: 2104 movs r1, #4 + 8005ab6: 4618 mov r0, r3 + 8005ab8: f7ff ff2e bl 8005918 + } + + // PUMP RATIO CONTROL + ILI9341_WriteCommand(0xF7); + 8005abc: 20f7 movs r0, #247 ; 0xf7 + 8005abe: f7ff ff11 bl 80058e4 + { + uint8_t data[] = { 0x20 }; + 8005ac2: 2320 movs r3, #32 + 8005ac4: f887 304c strb.w r3, [r7, #76] ; 0x4c + ILI9341_WriteData(data, sizeof(data)); + 8005ac8: f107 034c add.w r3, r7, #76 ; 0x4c + 8005acc: 2101 movs r1, #1 + 8005ace: 4618 mov r0, r3 + 8005ad0: f7ff ff22 bl 8005918 + } + + // POWER CONTROL,VRH[5:0] + ILI9341_WriteCommand(0xC0); + 8005ad4: 20c0 movs r0, #192 ; 0xc0 + 8005ad6: f7ff ff05 bl 80058e4 + { + uint8_t data[] = { 0x23 }; + 8005ada: 2323 movs r3, #35 ; 0x23 + 8005adc: f887 3048 strb.w r3, [r7, #72] ; 0x48 + ILI9341_WriteData(data, sizeof(data)); + 8005ae0: f107 0348 add.w r3, r7, #72 ; 0x48 + 8005ae4: 2101 movs r1, #1 + 8005ae6: 4618 mov r0, r3 + 8005ae8: f7ff ff16 bl 8005918 + } + + // POWER CONTROL,SAP[2:0];BT[3:0] + ILI9341_WriteCommand(0xC1); + 8005aec: 20c1 movs r0, #193 ; 0xc1 + 8005aee: f7ff fef9 bl 80058e4 + { + uint8_t data[] = { 0x10 }; + 8005af2: 2310 movs r3, #16 + 8005af4: f887 3044 strb.w r3, [r7, #68] ; 0x44 + ILI9341_WriteData(data, sizeof(data)); + 8005af8: f107 0344 add.w r3, r7, #68 ; 0x44 + 8005afc: 2101 movs r1, #1 + 8005afe: 4618 mov r0, r3 + 8005b00: f7ff ff0a bl 8005918 + } + + // VCM CONTROL + ILI9341_WriteCommand(0xC5); + 8005b04: 20c5 movs r0, #197 ; 0xc5 + 8005b06: f7ff feed bl 80058e4 + { + uint8_t data[] = { 0x3E, 0x28 }; + 8005b0a: 4b55 ldr r3, [pc, #340] ; (8005c60 ) + 8005b0c: 881b ldrh r3, [r3, #0] + 8005b0e: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 + ILI9341_WriteData(data, sizeof(data)); + 8005b12: f107 0340 add.w r3, r7, #64 ; 0x40 + 8005b16: 2102 movs r1, #2 + 8005b18: 4618 mov r0, r3 + 8005b1a: f7ff fefd bl 8005918 + } + + // VCM CONTROL 2 + ILI9341_WriteCommand(0xC7); + 8005b1e: 20c7 movs r0, #199 ; 0xc7 + 8005b20: f7ff fee0 bl 80058e4 + { + uint8_t data[] = { 0x86 }; + 8005b24: 2386 movs r3, #134 ; 0x86 + 8005b26: f887 303c strb.w r3, [r7, #60] ; 0x3c + ILI9341_WriteData(data, sizeof(data)); + 8005b2a: f107 033c add.w r3, r7, #60 ; 0x3c + 8005b2e: 2101 movs r1, #1 + 8005b30: 4618 mov r0, r3 + 8005b32: f7ff fef1 bl 8005918 + } + + // MEMORY ACCESS CONTROL + ILI9341_WriteCommand(0x36); + 8005b36: 2036 movs r0, #54 ; 0x36 + 8005b38: f7ff fed4 bl 80058e4 + { + uint8_t data[] = { 0x48 }; + 8005b3c: 2348 movs r3, #72 ; 0x48 + 8005b3e: f887 3038 strb.w r3, [r7, #56] ; 0x38 + ILI9341_WriteData(data, sizeof(data)); + 8005b42: f107 0338 add.w r3, r7, #56 ; 0x38 + 8005b46: 2101 movs r1, #1 + 8005b48: 4618 mov r0, r3 + 8005b4a: f7ff fee5 bl 8005918 + } + + // PIXEL FORMAT + ILI9341_WriteCommand(0x3A); + 8005b4e: 203a movs r0, #58 ; 0x3a + 8005b50: f7ff fec8 bl 80058e4 + { + uint8_t data[] = { 0x55 }; + 8005b54: 2355 movs r3, #85 ; 0x55 + 8005b56: f887 3034 strb.w r3, [r7, #52] ; 0x34 + ILI9341_WriteData(data, sizeof(data)); + 8005b5a: f107 0334 add.w r3, r7, #52 ; 0x34 + 8005b5e: 2101 movs r1, #1 + 8005b60: 4618 mov r0, r3 + 8005b62: f7ff fed9 bl 8005918 + } + + // FRAME RATIO CONTROL, STANDARD RGB COLOR + ILI9341_WriteCommand(0xB1); + 8005b66: 20b1 movs r0, #177 ; 0xb1 + 8005b68: f7ff febc bl 80058e4 + { + uint8_t data[] = { 0x00, 0x18 }; + 8005b6c: 2300 movs r3, #0 + 8005b6e: f887 3030 strb.w r3, [r7, #48] ; 0x30 + 8005b72: 2318 movs r3, #24 + 8005b74: f887 3031 strb.w r3, [r7, #49] ; 0x31 + ILI9341_WriteData(data, sizeof(data)); + 8005b78: f107 0330 add.w r3, r7, #48 ; 0x30 + 8005b7c: 2102 movs r1, #2 + 8005b7e: 4618 mov r0, r3 + 8005b80: f7ff feca bl 8005918 + } + + // DISPLAY FUNCTION CONTROL + ILI9341_WriteCommand(0xB6); + 8005b84: 20b6 movs r0, #182 ; 0xb6 + 8005b86: f7ff fead bl 80058e4 + { + uint8_t data[] = { 0x08, 0x82, 0x27 }; + 8005b8a: 4a36 ldr r2, [pc, #216] ; (8005c64 ) + 8005b8c: f107 032c add.w r3, r7, #44 ; 0x2c + 8005b90: 6812 ldr r2, [r2, #0] + 8005b92: 4611 mov r1, r2 + 8005b94: 8019 strh r1, [r3, #0] + 8005b96: 3302 adds r3, #2 + 8005b98: 0c12 lsrs r2, r2, #16 + 8005b9a: 701a strb r2, [r3, #0] + ILI9341_WriteData(data, sizeof(data)); + 8005b9c: f107 032c add.w r3, r7, #44 ; 0x2c + 8005ba0: 2103 movs r1, #3 + 8005ba2: 4618 mov r0, r3 + 8005ba4: f7ff feb8 bl 8005918 + } + + // 3GAMMA FUNCTION DISABLE + ILI9341_WriteCommand(0xF2); + 8005ba8: 20f2 movs r0, #242 ; 0xf2 + 8005baa: f7ff fe9b bl 80058e4 + { + uint8_t data[] = { 0x00 }; + 8005bae: 2300 movs r3, #0 + 8005bb0: f887 3028 strb.w r3, [r7, #40] ; 0x28 + ILI9341_WriteData(data, sizeof(data)); + 8005bb4: f107 0328 add.w r3, r7, #40 ; 0x28 + 8005bb8: 2101 movs r1, #1 + 8005bba: 4618 mov r0, r3 + 8005bbc: f7ff feac bl 8005918 + } + + // GAMMA CURVE SELECTED + ILI9341_WriteCommand(0x26); + 8005bc0: 2026 movs r0, #38 ; 0x26 + 8005bc2: f7ff fe8f bl 80058e4 + { + uint8_t data[] = { 0x01 }; + 8005bc6: 2301 movs r3, #1 + 8005bc8: f887 3024 strb.w r3, [r7, #36] ; 0x24 + ILI9341_WriteData(data, sizeof(data)); + 8005bcc: f107 0324 add.w r3, r7, #36 ; 0x24 + 8005bd0: 2101 movs r1, #1 + 8005bd2: 4618 mov r0, r3 + 8005bd4: f7ff fea0 bl 8005918 + } + + // POSITIVE GAMMA CORRECTION + ILI9341_WriteCommand(0xE0); + 8005bd8: 20e0 movs r0, #224 ; 0xe0 + 8005bda: f7ff fe83 bl 80058e4 + { + uint8_t data[] = { 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, 0x4E, 0xF1, + 8005bde: 4b22 ldr r3, [pc, #136] ; (8005c68 ) + 8005be0: f107 0414 add.w r4, r7, #20 + 8005be4: cb0f ldmia r3, {r0, r1, r2, r3} + 8005be6: c407 stmia r4!, {r0, r1, r2} + 8005be8: 8023 strh r3, [r4, #0] + 8005bea: 3402 adds r4, #2 + 8005bec: 0c1b lsrs r3, r3, #16 + 8005bee: 7023 strb r3, [r4, #0] + 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00 }; + ILI9341_WriteData(data, sizeof(data)); + 8005bf0: f107 0314 add.w r3, r7, #20 + 8005bf4: 210f movs r1, #15 + 8005bf6: 4618 mov r0, r3 + 8005bf8: f7ff fe8e bl 8005918 + } + + // NEGATIVE GAMMA CORRECTION + ILI9341_WriteCommand(0xE1); + 8005bfc: 20e1 movs r0, #225 ; 0xe1 + 8005bfe: f7ff fe71 bl 80058e4 + { + uint8_t data[] = { 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, 0x31, 0xC1, + 8005c02: 4b1a ldr r3, [pc, #104] ; (8005c6c ) + 8005c04: 1d3c adds r4, r7, #4 + 8005c06: cb0f ldmia r3, {r0, r1, r2, r3} + 8005c08: c407 stmia r4!, {r0, r1, r2} + 8005c0a: 8023 strh r3, [r4, #0] + 8005c0c: 3402 adds r4, #2 + 8005c0e: 0c1b lsrs r3, r3, #16 + 8005c10: 7023 strb r3, [r4, #0] + 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F }; + ILI9341_WriteData(data, sizeof(data)); + 8005c12: 1d3b adds r3, r7, #4 + 8005c14: 210f movs r1, #15 + 8005c16: 4618 mov r0, r3 + 8005c18: f7ff fe7e bl 8005918 + } + + // EXIT SLEEP + ILI9341_WriteCommand(0x11); + 8005c1c: 2011 movs r0, #17 + 8005c1e: f7ff fe61 bl 80058e4 + HAL_Delay(120); + 8005c22: 2078 movs r0, #120 ; 0x78 + 8005c24: f7fb fa48 bl 80010b8 + + // TURN ON DISPLAY + ILI9341_WriteCommand(0x29); + 8005c28: 2029 movs r0, #41 ; 0x29 + 8005c2a: f7ff fe5b bl 80058e4 + + // MADCTL + ILI9341_WriteCommand(0x36); + 8005c2e: 2036 movs r0, #54 ; 0x36 + 8005c30: f7ff fe58 bl 80058e4 + { + uint8_t data[] = { ILI9341_ROTATION }; + 8005c34: 23e8 movs r3, #232 ; 0xe8 + 8005c36: 703b strb r3, [r7, #0] + ILI9341_WriteData(data, sizeof(data)); + 8005c38: 463b mov r3, r7 + 8005c3a: 2101 movs r1, #1 + 8005c3c: 4618 mov r0, r3 + 8005c3e: f7ff fe6b bl 8005918 + } + + ILI9341_Unselect(); + 8005c42: f7ff fe2f bl 80058a4 +} + 8005c46: bf00 nop + 8005c48: 376c adds r7, #108 ; 0x6c + 8005c4a: 46bd mov sp, r7 + 8005c4c: bd90 pop {r4, r7, pc} + 8005c4e: bf00 nop + 8005c50: 0800c668 .word 0x0800c668 + 8005c54: 0800c670 .word 0x0800c670 + 8005c58: 0800c674 .word 0x0800c674 + 8005c5c: 0800c678 .word 0x0800c678 + 8005c60: 0800c67c .word 0x0800c67c + 8005c64: 0800c680 .word 0x0800c680 + 8005c68: 0800c684 .word 0x0800c684 + 8005c6c: 0800c694 .word 0x0800c694 + +08005c70 : + +void ILI9341_DrawPixel(uint16_t x, uint16_t y, uint16_t color) { + 8005c70: b580 push {r7, lr} + 8005c72: b084 sub sp, #16 + 8005c74: af00 add r7, sp, #0 + 8005c76: 4603 mov r3, r0 + 8005c78: 80fb strh r3, [r7, #6] + 8005c7a: 460b mov r3, r1 + 8005c7c: 80bb strh r3, [r7, #4] + 8005c7e: 4613 mov r3, r2 + 8005c80: 807b strh r3, [r7, #2] + if((x >= ILI9341_WIDTH) || (y >= ILI9341_HEIGHT)) + 8005c82: 88fb ldrh r3, [r7, #6] + 8005c84: f5b3 7fa0 cmp.w r3, #320 ; 0x140 + 8005c88: d21f bcs.n 8005cca + 8005c8a: 88bb ldrh r3, [r7, #4] + 8005c8c: 2bef cmp r3, #239 ; 0xef + 8005c8e: d81c bhi.n 8005cca + return; + + ILI9341_Select(); + 8005c90: f7ff fdfc bl 800588c + + ILI9341_SetAddressWindow(x, y, x+1, y+1); + 8005c94: 88fb ldrh r3, [r7, #6] + 8005c96: 3301 adds r3, #1 + 8005c98: b29a uxth r2, r3 + 8005c9a: 88bb ldrh r3, [r7, #4] + 8005c9c: 3301 adds r3, #1 + 8005c9e: b29b uxth r3, r3 + 8005ca0: 88b9 ldrh r1, [r7, #4] + 8005ca2: 88f8 ldrh r0, [r7, #6] + 8005ca4: f7ff fe64 bl 8005970 + uint8_t data[] = { color >> 8, color & 0xFF }; + 8005ca8: 887b ldrh r3, [r7, #2] + 8005caa: 0a1b lsrs r3, r3, #8 + 8005cac: b29b uxth r3, r3 + 8005cae: b2db uxtb r3, r3 + 8005cb0: 733b strb r3, [r7, #12] + 8005cb2: 887b ldrh r3, [r7, #2] + 8005cb4: b2db uxtb r3, r3 + 8005cb6: 737b strb r3, [r7, #13] + ILI9341_WriteData(data, sizeof(data)); + 8005cb8: f107 030c add.w r3, r7, #12 + 8005cbc: 2102 movs r1, #2 + 8005cbe: 4618 mov r0, r3 + 8005cc0: f7ff fe2a bl 8005918 + + ILI9341_Unselect(); + 8005cc4: f7ff fdee bl 80058a4 + 8005cc8: e000 b.n 8005ccc + return; + 8005cca: bf00 nop +} + 8005ccc: 3710 adds r7, #16 + 8005cce: 46bd mov sp, r7 + 8005cd0: bd80 pop {r7, pc} + +08005cd2 : + +static void ILI9341_WriteChar(uint16_t x, uint16_t y, char ch, FontDef font, uint16_t color, uint16_t bgcolor) { + 8005cd2: b082 sub sp, #8 + 8005cd4: b590 push {r4, r7, lr} + 8005cd6: b089 sub sp, #36 ; 0x24 + 8005cd8: af00 add r7, sp, #0 + 8005cda: 637b str r3, [r7, #52] ; 0x34 + 8005cdc: 4603 mov r3, r0 + 8005cde: 80fb strh r3, [r7, #6] + 8005ce0: 460b mov r3, r1 + 8005ce2: 80bb strh r3, [r7, #4] + 8005ce4: 4613 mov r3, r2 + 8005ce6: 70fb strb r3, [r7, #3] + uint32_t i, b, j; + + ILI9341_SetAddressWindow(x, y, x+font.width-1, y+font.height-1); + 8005ce8: f897 3034 ldrb.w r3, [r7, #52] ; 0x34 + 8005cec: b29a uxth r2, r3 + 8005cee: 88fb ldrh r3, [r7, #6] + 8005cf0: 4413 add r3, r2 + 8005cf2: b29b uxth r3, r3 + 8005cf4: 3b01 subs r3, #1 + 8005cf6: b29c uxth r4, r3 + 8005cf8: f897 3035 ldrb.w r3, [r7, #53] ; 0x35 + 8005cfc: b29a uxth r2, r3 + 8005cfe: 88bb ldrh r3, [r7, #4] + 8005d00: 4413 add r3, r2 + 8005d02: b29b uxth r3, r3 + 8005d04: 3b01 subs r3, #1 + 8005d06: b29b uxth r3, r3 + 8005d08: 88b9 ldrh r1, [r7, #4] + 8005d0a: 88f8 ldrh r0, [r7, #6] + 8005d0c: 4622 mov r2, r4 + 8005d0e: f7ff fe2f bl 8005970 + + for(i = 0; i < font.height; i++) { + 8005d12: 2300 movs r3, #0 + 8005d14: 61fb str r3, [r7, #28] + 8005d16: e043 b.n 8005da0 + b = font.data[(ch - 32) * font.height + i]; + 8005d18: 6bba ldr r2, [r7, #56] ; 0x38 + 8005d1a: 78fb ldrb r3, [r7, #3] + 8005d1c: 3b20 subs r3, #32 + 8005d1e: f897 1035 ldrb.w r1, [r7, #53] ; 0x35 + 8005d22: fb01 f303 mul.w r3, r1, r3 + 8005d26: 4619 mov r1, r3 + 8005d28: 69fb ldr r3, [r7, #28] + 8005d2a: 440b add r3, r1 + 8005d2c: 005b lsls r3, r3, #1 + 8005d2e: 4413 add r3, r2 + 8005d30: 881b ldrh r3, [r3, #0] + 8005d32: 617b str r3, [r7, #20] + for(j = 0; j < font.width; j++) { + 8005d34: 2300 movs r3, #0 + 8005d36: 61bb str r3, [r7, #24] + 8005d38: e029 b.n 8005d8e + if((b << j) & 0x8000) { + 8005d3a: 697a ldr r2, [r7, #20] + 8005d3c: 69bb ldr r3, [r7, #24] + 8005d3e: fa02 f303 lsl.w r3, r2, r3 + 8005d42: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8005d46: 2b00 cmp r3, #0 + 8005d48: d00e beq.n 8005d68 + uint8_t data[] = { color >> 8, color & 0xFF }; + 8005d4a: 8fbb ldrh r3, [r7, #60] ; 0x3c + 8005d4c: 0a1b lsrs r3, r3, #8 + 8005d4e: b29b uxth r3, r3 + 8005d50: b2db uxtb r3, r3 + 8005d52: 743b strb r3, [r7, #16] + 8005d54: 8fbb ldrh r3, [r7, #60] ; 0x3c + 8005d56: b2db uxtb r3, r3 + 8005d58: 747b strb r3, [r7, #17] + ILI9341_WriteData(data, sizeof(data)); + 8005d5a: f107 0310 add.w r3, r7, #16 + 8005d5e: 2102 movs r1, #2 + 8005d60: 4618 mov r0, r3 + 8005d62: f7ff fdd9 bl 8005918 + 8005d66: e00f b.n 8005d88 + } else { + uint8_t data[] = { bgcolor >> 8, bgcolor & 0xFF }; + 8005d68: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 + 8005d6c: 0a1b lsrs r3, r3, #8 + 8005d6e: b29b uxth r3, r3 + 8005d70: b2db uxtb r3, r3 + 8005d72: 733b strb r3, [r7, #12] + 8005d74: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 + 8005d78: b2db uxtb r3, r3 + 8005d7a: 737b strb r3, [r7, #13] + ILI9341_WriteData(data, sizeof(data)); + 8005d7c: f107 030c add.w r3, r7, #12 + 8005d80: 2102 movs r1, #2 + 8005d82: 4618 mov r0, r3 + 8005d84: f7ff fdc8 bl 8005918 + for(j = 0; j < font.width; j++) { + 8005d88: 69bb ldr r3, [r7, #24] + 8005d8a: 3301 adds r3, #1 + 8005d8c: 61bb str r3, [r7, #24] + 8005d8e: f897 3034 ldrb.w r3, [r7, #52] ; 0x34 + 8005d92: 461a mov r2, r3 + 8005d94: 69bb ldr r3, [r7, #24] + 8005d96: 4293 cmp r3, r2 + 8005d98: d3cf bcc.n 8005d3a + for(i = 0; i < font.height; i++) { + 8005d9a: 69fb ldr r3, [r7, #28] + 8005d9c: 3301 adds r3, #1 + 8005d9e: 61fb str r3, [r7, #28] + 8005da0: f897 3035 ldrb.w r3, [r7, #53] ; 0x35 + 8005da4: 461a mov r2, r3 + 8005da6: 69fb ldr r3, [r7, #28] + 8005da8: 4293 cmp r3, r2 + 8005daa: d3b5 bcc.n 8005d18 + } + } + } +} + 8005dac: bf00 nop + 8005dae: 3724 adds r7, #36 ; 0x24 + 8005db0: 46bd mov sp, r7 + 8005db2: e8bd 4090 ldmia.w sp!, {r4, r7, lr} + 8005db6: b002 add sp, #8 + 8005db8: 4770 bx lr + +08005dba : + +void ILI9341_WriteString(uint16_t x, uint16_t y, const char* str, FontDef font, uint16_t color, uint16_t bgcolor) { + 8005dba: b082 sub sp, #8 + 8005dbc: b580 push {r7, lr} + 8005dbe: b086 sub sp, #24 + 8005dc0: af04 add r7, sp, #16 + 8005dc2: 603a str r2, [r7, #0] + 8005dc4: 617b str r3, [r7, #20] + 8005dc6: 4603 mov r3, r0 + 8005dc8: 80fb strh r3, [r7, #6] + 8005dca: 460b mov r3, r1 + 8005dcc: 80bb strh r3, [r7, #4] + ILI9341_Select(); + 8005dce: f7ff fd5d bl 800588c + + while(*str) { + 8005dd2: e02e b.n 8005e32 + if(x + font.width >= ILI9341_WIDTH) { + 8005dd4: 88fb ldrh r3, [r7, #6] + 8005dd6: 7d3a ldrb r2, [r7, #20] + 8005dd8: 4413 add r3, r2 + 8005dda: f5b3 7fa0 cmp.w r3, #320 ; 0x140 + 8005dde: db13 blt.n 8005e08 + x = 0; + 8005de0: 2300 movs r3, #0 + 8005de2: 80fb strh r3, [r7, #6] + y += font.height; + 8005de4: 7d7b ldrb r3, [r7, #21] + 8005de6: b29a uxth r2, r3 + 8005de8: 88bb ldrh r3, [r7, #4] + 8005dea: 4413 add r3, r2 + 8005dec: 80bb strh r3, [r7, #4] + if(y + font.height >= ILI9341_HEIGHT) { + 8005dee: 88bb ldrh r3, [r7, #4] + 8005df0: 7d7a ldrb r2, [r7, #21] + 8005df2: 4413 add r3, r2 + 8005df4: 2bef cmp r3, #239 ; 0xef + 8005df6: dc21 bgt.n 8005e3c + break; + } + + if(*str == ' ') { + 8005df8: 683b ldr r3, [r7, #0] + 8005dfa: 781b ldrb r3, [r3, #0] + 8005dfc: 2b20 cmp r3, #32 + 8005dfe: d103 bne.n 8005e08 + // skip spaces in the beginning of the new line + str++; + 8005e00: 683b ldr r3, [r7, #0] + 8005e02: 3301 adds r3, #1 + 8005e04: 603b str r3, [r7, #0] + continue; + 8005e06: e014 b.n 8005e32 + } + } + + ILI9341_WriteChar(x, y, *str, font, color, bgcolor); + 8005e08: 683b ldr r3, [r7, #0] + 8005e0a: 781a ldrb r2, [r3, #0] + 8005e0c: 88b9 ldrh r1, [r7, #4] + 8005e0e: 88f8 ldrh r0, [r7, #6] + 8005e10: 8c3b ldrh r3, [r7, #32] + 8005e12: 9302 str r3, [sp, #8] + 8005e14: 8bbb ldrh r3, [r7, #28] + 8005e16: 9301 str r3, [sp, #4] + 8005e18: 69bb ldr r3, [r7, #24] + 8005e1a: 9300 str r3, [sp, #0] + 8005e1c: 697b ldr r3, [r7, #20] + 8005e1e: f7ff ff58 bl 8005cd2 + x += font.width; + 8005e22: 7d3b ldrb r3, [r7, #20] + 8005e24: b29a uxth r2, r3 + 8005e26: 88fb ldrh r3, [r7, #6] + 8005e28: 4413 add r3, r2 + 8005e2a: 80fb strh r3, [r7, #6] + str++; + 8005e2c: 683b ldr r3, [r7, #0] + 8005e2e: 3301 adds r3, #1 + 8005e30: 603b str r3, [r7, #0] + while(*str) { + 8005e32: 683b ldr r3, [r7, #0] + 8005e34: 781b ldrb r3, [r3, #0] + 8005e36: 2b00 cmp r3, #0 + 8005e38: d1cc bne.n 8005dd4 + 8005e3a: e000 b.n 8005e3e + break; + 8005e3c: bf00 nop + } + + ILI9341_Unselect(); + 8005e3e: f7ff fd31 bl 80058a4 +} + 8005e42: bf00 nop + 8005e44: 3708 adds r7, #8 + 8005e46: 46bd mov sp, r7 + 8005e48: e8bd 4080 ldmia.w sp!, {r7, lr} + 8005e4c: b002 add sp, #8 + 8005e4e: 4770 bx lr + +08005e50 : + +void ILI9341_FillRectangle(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color) { + 8005e50: b590 push {r4, r7, lr} + 8005e52: b085 sub sp, #20 + 8005e54: af00 add r7, sp, #0 + 8005e56: 4604 mov r4, r0 + 8005e58: 4608 mov r0, r1 + 8005e5a: 4611 mov r1, r2 + 8005e5c: 461a mov r2, r3 + 8005e5e: 4623 mov r3, r4 + 8005e60: 80fb strh r3, [r7, #6] + 8005e62: 4603 mov r3, r0 + 8005e64: 80bb strh r3, [r7, #4] + 8005e66: 460b mov r3, r1 + 8005e68: 807b strh r3, [r7, #2] + 8005e6a: 4613 mov r3, r2 + 8005e6c: 803b strh r3, [r7, #0] + // clipping + if((x >= ILI9341_WIDTH) || (y >= ILI9341_HEIGHT)) return; + 8005e6e: 88fb ldrh r3, [r7, #6] + 8005e70: f5b3 7fa0 cmp.w r3, #320 ; 0x140 + 8005e74: d254 bcs.n 8005f20 + 8005e76: 88bb ldrh r3, [r7, #4] + 8005e78: 2bef cmp r3, #239 ; 0xef + 8005e7a: d851 bhi.n 8005f20 + if((x + w - 1) >= ILI9341_WIDTH) w = ILI9341_WIDTH - x; + 8005e7c: 88fa ldrh r2, [r7, #6] + 8005e7e: 887b ldrh r3, [r7, #2] + 8005e80: 4413 add r3, r2 + 8005e82: 3b01 subs r3, #1 + 8005e84: f5b3 7fa0 cmp.w r3, #320 ; 0x140 + 8005e88: db03 blt.n 8005e92 + 8005e8a: 88fb ldrh r3, [r7, #6] + 8005e8c: f5c3 73a0 rsb r3, r3, #320 ; 0x140 + 8005e90: 807b strh r3, [r7, #2] + if((y + h - 1) >= ILI9341_HEIGHT) h = ILI9341_HEIGHT - y; + 8005e92: 88ba ldrh r2, [r7, #4] + 8005e94: 883b ldrh r3, [r7, #0] + 8005e96: 4413 add r3, r2 + 8005e98: 3b01 subs r3, #1 + 8005e9a: 2bef cmp r3, #239 ; 0xef + 8005e9c: dd03 ble.n 8005ea6 + 8005e9e: 88bb ldrh r3, [r7, #4] + 8005ea0: f1c3 03f0 rsb r3, r3, #240 ; 0xf0 + 8005ea4: 803b strh r3, [r7, #0] + + ILI9341_Select(); + 8005ea6: f7ff fcf1 bl 800588c + ILI9341_SetAddressWindow(x, y, x+w-1, y+h-1); + 8005eaa: 88fa ldrh r2, [r7, #6] + 8005eac: 887b ldrh r3, [r7, #2] + 8005eae: 4413 add r3, r2 + 8005eb0: b29b uxth r3, r3 + 8005eb2: 3b01 subs r3, #1 + 8005eb4: b29c uxth r4, r3 + 8005eb6: 88ba ldrh r2, [r7, #4] + 8005eb8: 883b ldrh r3, [r7, #0] + 8005eba: 4413 add r3, r2 + 8005ebc: b29b uxth r3, r3 + 8005ebe: 3b01 subs r3, #1 + 8005ec0: b29b uxth r3, r3 + 8005ec2: 88b9 ldrh r1, [r7, #4] + 8005ec4: 88f8 ldrh r0, [r7, #6] + 8005ec6: 4622 mov r2, r4 + 8005ec8: f7ff fd52 bl 8005970 + + uint8_t data[] = { color >> 8, color & 0xFF }; + 8005ecc: 8c3b ldrh r3, [r7, #32] + 8005ece: 0a1b lsrs r3, r3, #8 + 8005ed0: b29b uxth r3, r3 + 8005ed2: b2db uxtb r3, r3 + 8005ed4: 733b strb r3, [r7, #12] + 8005ed6: 8c3b ldrh r3, [r7, #32] + 8005ed8: b2db uxtb r3, r3 + 8005eda: 737b strb r3, [r7, #13] + HAL_GPIO_WritePin(ILI9341_DC_GPIO_Port, ILI9341_DC_Pin, GPIO_PIN_SET); + 8005edc: 2201 movs r2, #1 + 8005ede: 2120 movs r1, #32 + 8005ee0: 4811 ldr r0, [pc, #68] ; (8005f28 ) + 8005ee2: f7fb fb8a bl 80015fa + for(y = h; y > 0; y--) { + 8005ee6: 883b ldrh r3, [r7, #0] + 8005ee8: 80bb strh r3, [r7, #4] + 8005eea: e013 b.n 8005f14 + for(x = w; x > 0; x--) { + 8005eec: 887b ldrh r3, [r7, #2] + 8005eee: 80fb strh r3, [r7, #6] + 8005ef0: e00a b.n 8005f08 + HAL_SPI_Transmit(&ILI9341_SPI_PORT, data, sizeof(data), HAL_MAX_DELAY); + 8005ef2: f107 010c add.w r1, r7, #12 + 8005ef6: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8005efa: 2202 movs r2, #2 + 8005efc: 480b ldr r0, [pc, #44] ; (8005f2c ) + 8005efe: f7fd fef8 bl 8003cf2 + for(x = w; x > 0; x--) { + 8005f02: 88fb ldrh r3, [r7, #6] + 8005f04: 3b01 subs r3, #1 + 8005f06: 80fb strh r3, [r7, #6] + 8005f08: 88fb ldrh r3, [r7, #6] + 8005f0a: 2b00 cmp r3, #0 + 8005f0c: d1f1 bne.n 8005ef2 + for(y = h; y > 0; y--) { + 8005f0e: 88bb ldrh r3, [r7, #4] + 8005f10: 3b01 subs r3, #1 + 8005f12: 80bb strh r3, [r7, #4] + 8005f14: 88bb ldrh r3, [r7, #4] + 8005f16: 2b00 cmp r3, #0 + 8005f18: d1e8 bne.n 8005eec + } + } + + ILI9341_Unselect(); + 8005f1a: f7ff fcc3 bl 80058a4 + 8005f1e: e000 b.n 8005f22 + if((x >= ILI9341_WIDTH) || (y >= ILI9341_HEIGHT)) return; + 8005f20: bf00 nop +} + 8005f22: 3714 adds r7, #20 + 8005f24: 46bd mov sp, r7 + 8005f26: bd90 pop {r4, r7, pc} + 8005f28: 40010800 .word 0x40010800 + 8005f2c: 200011fc .word 0x200011fc + +08005f30 : + +void ILI9341_writeLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color) { + 8005f30: b590 push {r4, r7, lr} + 8005f32: b089 sub sp, #36 ; 0x24 + 8005f34: af00 add r7, sp, #0 + 8005f36: 4604 mov r4, r0 + 8005f38: 4608 mov r0, r1 + 8005f3a: 4611 mov r1, r2 + 8005f3c: 461a mov r2, r3 + 8005f3e: 4623 mov r3, r4 + 8005f40: 80fb strh r3, [r7, #6] + 8005f42: 4603 mov r3, r0 + 8005f44: 80bb strh r3, [r7, #4] + 8005f46: 460b mov r3, r1 + 8005f48: 807b strh r3, [r7, #2] + 8005f4a: 4613 mov r3, r2 + 8005f4c: 803b strh r3, [r7, #0] + + int16_t steep = abs(y1 - y0) > abs(x1 - x0); + 8005f4e: f9b7 2000 ldrsh.w r2, [r7] + 8005f52: f9b7 3004 ldrsh.w r3, [r7, #4] + 8005f56: 1ad3 subs r3, r2, r3 + 8005f58: ea83 72e3 eor.w r2, r3, r3, asr #31 + 8005f5c: eba2 72e3 sub.w r2, r2, r3, asr #31 + 8005f60: f9b7 1002 ldrsh.w r1, [r7, #2] + 8005f64: f9b7 3006 ldrsh.w r3, [r7, #6] + 8005f68: 1acb subs r3, r1, r3 + 8005f6a: 2b00 cmp r3, #0 + 8005f6c: bfb8 it lt + 8005f6e: 425b neglt r3, r3 + 8005f70: 429a cmp r2, r3 + 8005f72: bfcc ite gt + 8005f74: 2301 movgt r3, #1 + 8005f76: 2300 movle r3, #0 + 8005f78: b2db uxtb r3, r3 + 8005f7a: 837b strh r3, [r7, #26] + if (steep) { + 8005f7c: f9b7 301a ldrsh.w r3, [r7, #26] + 8005f80: 2b00 cmp r3, #0 + 8005f82: d00b beq.n 8005f9c + _swap_int16_t(x0, y0); + 8005f84: 88fb ldrh r3, [r7, #6] + 8005f86: 833b strh r3, [r7, #24] + 8005f88: 88bb ldrh r3, [r7, #4] + 8005f8a: 80fb strh r3, [r7, #6] + 8005f8c: 8b3b ldrh r3, [r7, #24] + 8005f8e: 80bb strh r3, [r7, #4] + _swap_int16_t(x1, y1); + 8005f90: 887b ldrh r3, [r7, #2] + 8005f92: 82fb strh r3, [r7, #22] + 8005f94: 883b ldrh r3, [r7, #0] + 8005f96: 807b strh r3, [r7, #2] + 8005f98: 8afb ldrh r3, [r7, #22] + 8005f9a: 803b strh r3, [r7, #0] + } + + if (x0 > x1) { + 8005f9c: f9b7 2006 ldrsh.w r2, [r7, #6] + 8005fa0: f9b7 3002 ldrsh.w r3, [r7, #2] + 8005fa4: 429a cmp r2, r3 + 8005fa6: dd0b ble.n 8005fc0 + _swap_int16_t(x0, x1); + 8005fa8: 88fb ldrh r3, [r7, #6] + 8005faa: 82bb strh r3, [r7, #20] + 8005fac: 887b ldrh r3, [r7, #2] + 8005fae: 80fb strh r3, [r7, #6] + 8005fb0: 8abb ldrh r3, [r7, #20] + 8005fb2: 807b strh r3, [r7, #2] + _swap_int16_t(y0, y1); + 8005fb4: 88bb ldrh r3, [r7, #4] + 8005fb6: 827b strh r3, [r7, #18] + 8005fb8: 883b ldrh r3, [r7, #0] + 8005fba: 80bb strh r3, [r7, #4] + 8005fbc: 8a7b ldrh r3, [r7, #18] + 8005fbe: 803b strh r3, [r7, #0] + } + + int16_t dx, dy; + dx = x1 - x0; + 8005fc0: 887a ldrh r2, [r7, #2] + 8005fc2: 88fb ldrh r3, [r7, #6] + 8005fc4: 1ad3 subs r3, r2, r3 + 8005fc6: b29b uxth r3, r3 + 8005fc8: 823b strh r3, [r7, #16] + dy = abs(y1 - y0); + 8005fca: f9b7 2000 ldrsh.w r2, [r7] + 8005fce: f9b7 3004 ldrsh.w r3, [r7, #4] + 8005fd2: 1ad3 subs r3, r2, r3 + 8005fd4: 2b00 cmp r3, #0 + 8005fd6: bfb8 it lt + 8005fd8: 425b neglt r3, r3 + 8005fda: 81fb strh r3, [r7, #14] + + int16_t err = dx / 2; + 8005fdc: f9b7 3010 ldrsh.w r3, [r7, #16] + 8005fe0: 0fda lsrs r2, r3, #31 + 8005fe2: 4413 add r3, r2 + 8005fe4: 105b asrs r3, r3, #1 + 8005fe6: 83fb strh r3, [r7, #30] + int16_t ystep; + + if (y0 < y1) { + 8005fe8: f9b7 2004 ldrsh.w r2, [r7, #4] + 8005fec: f9b7 3000 ldrsh.w r3, [r7] + 8005ff0: 429a cmp r2, r3 + 8005ff2: da02 bge.n 8005ffa + ystep = 1; + 8005ff4: 2301 movs r3, #1 + 8005ff6: 83bb strh r3, [r7, #28] + 8005ff8: e031 b.n 800605e + } else { + ystep = -1; + 8005ffa: f64f 73ff movw r3, #65535 ; 0xffff + 8005ffe: 83bb strh r3, [r7, #28] + } + + for (; x0<=x1; x0++) { + 8006000: e02d b.n 800605e + if (steep) { + 8006002: f9b7 301a ldrsh.w r3, [r7, #26] + 8006006: 2b00 cmp r3, #0 + 8006008: d008 beq.n 800601c + ILI9341_writePixel(y0, x0, color); + 800600a: 8e3a ldrh r2, [r7, #48] ; 0x30 + 800600c: f9b7 1006 ldrsh.w r1, [r7, #6] + 8006010: f9b7 3004 ldrsh.w r3, [r7, #4] + 8006014: 4618 mov r0, r3 + 8006016: f000 f9c3 bl 80063a0 + 800601a: e007 b.n 800602c + } else { + ILI9341_writePixel(x0, y0, color); + 800601c: 8e3a ldrh r2, [r7, #48] ; 0x30 + 800601e: f9b7 1004 ldrsh.w r1, [r7, #4] + 8006022: f9b7 3006 ldrsh.w r3, [r7, #6] + 8006026: 4618 mov r0, r3 + 8006028: f000 f9ba bl 80063a0 + } + err -= dy; + 800602c: 8bfa ldrh r2, [r7, #30] + 800602e: 89fb ldrh r3, [r7, #14] + 8006030: 1ad3 subs r3, r2, r3 + 8006032: b29b uxth r3, r3 + 8006034: 83fb strh r3, [r7, #30] + if (err < 0) { + 8006036: f9b7 301e ldrsh.w r3, [r7, #30] + 800603a: 2b00 cmp r3, #0 + 800603c: da09 bge.n 8006052 + y0 += ystep; + 800603e: 88ba ldrh r2, [r7, #4] + 8006040: 8bbb ldrh r3, [r7, #28] + 8006042: 4413 add r3, r2 + 8006044: b29b uxth r3, r3 + 8006046: 80bb strh r3, [r7, #4] + err += dx; + 8006048: 8bfa ldrh r2, [r7, #30] + 800604a: 8a3b ldrh r3, [r7, #16] + 800604c: 4413 add r3, r2 + 800604e: b29b uxth r3, r3 + 8006050: 83fb strh r3, [r7, #30] + for (; x0<=x1; x0++) { + 8006052: f9b7 3006 ldrsh.w r3, [r7, #6] + 8006056: b29b uxth r3, r3 + 8006058: 3301 adds r3, #1 + 800605a: b29b uxth r3, r3 + 800605c: 80fb strh r3, [r7, #6] + 800605e: f9b7 2006 ldrsh.w r2, [r7, #6] + 8006062: f9b7 3002 ldrsh.w r3, [r7, #2] + 8006066: 429a cmp r2, r3 + 8006068: ddcb ble.n 8006002 + } + } +} + 800606a: bf00 nop + 800606c: 3724 adds r7, #36 ; 0x24 + 800606e: 46bd mov sp, r7 + 8006070: bd90 pop {r4, r7, pc} + +08006072 : + +void ILI9341_DrawArrow(int16_t x1, int16_t y1, int16_t x2, int16_t y2, float k, uint16_t color) +{ + 8006072: b5f0 push {r4, r5, r6, r7, lr} + 8006074: b08d sub sp, #52 ; 0x34 + 8006076: af02 add r7, sp, #8 + 8006078: 4604 mov r4, r0 + 800607a: 4608 mov r0, r1 + 800607c: 4611 mov r1, r2 + 800607e: 461a mov r2, r3 + 8006080: 4623 mov r3, r4 + 8006082: 80fb strh r3, [r7, #6] + 8006084: 4603 mov r3, r0 + 8006086: 80bb strh r3, [r7, #4] + 8006088: 460b mov r3, r1 + 800608a: 807b strh r3, [r7, #2] + 800608c: 4613 mov r3, r2 + 800608e: 803b strh r3, [r7, #0] + float dx, dy, x2Outer,y2Outer,x3,y3,x4,y4; + + dx = x2 + (x1 - x2) * k; + 8006090: f9b7 3002 ldrsh.w r3, [r7, #2] + 8006094: 4618 mov r0, r3 + 8006096: f7fa fd93 bl 8000bc0 <__aeabi_i2f> + 800609a: 4604 mov r4, r0 + 800609c: f9b7 2006 ldrsh.w r2, [r7, #6] + 80060a0: f9b7 3002 ldrsh.w r3, [r7, #2] + 80060a4: 1ad3 subs r3, r2, r3 + 80060a6: 4618 mov r0, r3 + 80060a8: f7fa fd8a bl 8000bc0 <__aeabi_i2f> + 80060ac: 4603 mov r3, r0 + 80060ae: 6c39 ldr r1, [r7, #64] ; 0x40 + 80060b0: 4618 mov r0, r3 + 80060b2: f7fa fdd9 bl 8000c68 <__aeabi_fmul> + 80060b6: 4603 mov r3, r0 + 80060b8: 4619 mov r1, r3 + 80060ba: 4620 mov r0, r4 + 80060bc: f7fa fccc bl 8000a58 <__addsf3> + 80060c0: 4603 mov r3, r0 + 80060c2: 627b str r3, [r7, #36] ; 0x24 + dy = y2 + (y1 - y2) * k; + 80060c4: f9b7 3000 ldrsh.w r3, [r7] + 80060c8: 4618 mov r0, r3 + 80060ca: f7fa fd79 bl 8000bc0 <__aeabi_i2f> + 80060ce: 4604 mov r4, r0 + 80060d0: f9b7 2004 ldrsh.w r2, [r7, #4] + 80060d4: f9b7 3000 ldrsh.w r3, [r7] + 80060d8: 1ad3 subs r3, r2, r3 + 80060da: 4618 mov r0, r3 + 80060dc: f7fa fd70 bl 8000bc0 <__aeabi_i2f> + 80060e0: 4603 mov r3, r0 + 80060e2: 6c39 ldr r1, [r7, #64] ; 0x40 + 80060e4: 4618 mov r0, r3 + 80060e6: f7fa fdbf bl 8000c68 <__aeabi_fmul> + 80060ea: 4603 mov r3, r0 + 80060ec: 4619 mov r1, r3 + 80060ee: 4620 mov r0, r4 + 80060f0: f7fa fcb2 bl 8000a58 <__addsf3> + 80060f4: 4603 mov r3, r0 + 80060f6: 623b str r3, [r7, #32] + + x2Outer = x2 - dx; + 80060f8: f9b7 3002 ldrsh.w r3, [r7, #2] + 80060fc: 4618 mov r0, r3 + 80060fe: f7fa fd5f bl 8000bc0 <__aeabi_i2f> + 8006102: 4603 mov r3, r0 + 8006104: 6a79 ldr r1, [r7, #36] ; 0x24 + 8006106: 4618 mov r0, r3 + 8006108: f7fa fca4 bl 8000a54 <__aeabi_fsub> + 800610c: 4603 mov r3, r0 + 800610e: 61fb str r3, [r7, #28] + y2Outer = dy - y2; + 8006110: f9b7 3000 ldrsh.w r3, [r7] + 8006114: 4618 mov r0, r3 + 8006116: f7fa fd53 bl 8000bc0 <__aeabi_i2f> + 800611a: 4603 mov r3, r0 + 800611c: 4619 mov r1, r3 + 800611e: 6a38 ldr r0, [r7, #32] + 8006120: f7fa fc98 bl 8000a54 <__aeabi_fsub> + 8006124: 4603 mov r3, r0 + 8006126: 61bb str r3, [r7, #24] + x3 = y2Outer * k + dx; + 8006128: 6c39 ldr r1, [r7, #64] ; 0x40 + 800612a: 69b8 ldr r0, [r7, #24] + 800612c: f7fa fd9c bl 8000c68 <__aeabi_fmul> + 8006130: 4603 mov r3, r0 + 8006132: 4619 mov r1, r3 + 8006134: 6a78 ldr r0, [r7, #36] ; 0x24 + 8006136: f7fa fc8f bl 8000a58 <__addsf3> + 800613a: 4603 mov r3, r0 + 800613c: 617b str r3, [r7, #20] + y3 = x2Outer * k + dy; + 800613e: 6c39 ldr r1, [r7, #64] ; 0x40 + 8006140: 69f8 ldr r0, [r7, #28] + 8006142: f7fa fd91 bl 8000c68 <__aeabi_fmul> + 8006146: 4603 mov r3, r0 + 8006148: 4619 mov r1, r3 + 800614a: 6a38 ldr r0, [r7, #32] + 800614c: f7fa fc84 bl 8000a58 <__addsf3> + 8006150: 4603 mov r3, r0 + 8006152: 613b str r3, [r7, #16] + x4 = dx - y2Outer * k; + 8006154: 6c39 ldr r1, [r7, #64] ; 0x40 + 8006156: 69b8 ldr r0, [r7, #24] + 8006158: f7fa fd86 bl 8000c68 <__aeabi_fmul> + 800615c: 4603 mov r3, r0 + 800615e: 4619 mov r1, r3 + 8006160: 6a78 ldr r0, [r7, #36] ; 0x24 + 8006162: f7fa fc77 bl 8000a54 <__aeabi_fsub> + 8006166: 4603 mov r3, r0 + 8006168: 60fb str r3, [r7, #12] + y4 = dy - x2Outer * k; + 800616a: 6c39 ldr r1, [r7, #64] ; 0x40 + 800616c: 69f8 ldr r0, [r7, #28] + 800616e: f7fa fd7b bl 8000c68 <__aeabi_fmul> + 8006172: 4603 mov r3, r0 + 8006174: 4619 mov r1, r3 + 8006176: 6a38 ldr r0, [r7, #32] + 8006178: f7fa fc6c bl 8000a54 <__aeabi_fsub> + 800617c: 4603 mov r3, r0 + 800617e: 60bb str r3, [r7, #8] + ILI9341_writeLine(round(x1), round(y1), round(x2), round(y2), color); + 8006180: f9b7 3006 ldrsh.w r3, [r7, #6] + 8006184: 4618 mov r0, r3 + 8006186: f7fa f935 bl 80003f4 <__aeabi_i2d> + 800618a: 4603 mov r3, r0 + 800618c: 460c mov r4, r1 + 800618e: 4618 mov r0, r3 + 8006190: 4621 mov r1, r4 + 8006192: f7fa fc33 bl 80009fc <__aeabi_d2iz> + 8006196: 4603 mov r3, r0 + 8006198: b21c sxth r4, r3 + 800619a: f9b7 3004 ldrsh.w r3, [r7, #4] + 800619e: 4618 mov r0, r3 + 80061a0: f7fa f928 bl 80003f4 <__aeabi_i2d> + 80061a4: 4602 mov r2, r0 + 80061a6: 460b mov r3, r1 + 80061a8: 4610 mov r0, r2 + 80061aa: 4619 mov r1, r3 + 80061ac: f7fa fc26 bl 80009fc <__aeabi_d2iz> + 80061b0: 4603 mov r3, r0 + 80061b2: b21d sxth r5, r3 + 80061b4: f9b7 3002 ldrsh.w r3, [r7, #2] + 80061b8: 4618 mov r0, r3 + 80061ba: f7fa f91b bl 80003f4 <__aeabi_i2d> + 80061be: 4602 mov r2, r0 + 80061c0: 460b mov r3, r1 + 80061c2: 4610 mov r0, r2 + 80061c4: 4619 mov r1, r3 + 80061c6: f7fa fc19 bl 80009fc <__aeabi_d2iz> + 80061ca: 4603 mov r3, r0 + 80061cc: b21e sxth r6, r3 + 80061ce: f9b7 3000 ldrsh.w r3, [r7] + 80061d2: 4618 mov r0, r3 + 80061d4: f7fa f90e bl 80003f4 <__aeabi_i2d> + 80061d8: 4602 mov r2, r0 + 80061da: 460b mov r3, r1 + 80061dc: 4610 mov r0, r2 + 80061de: 4619 mov r1, r3 + 80061e0: f7fa fc0c bl 80009fc <__aeabi_d2iz> + 80061e4: 4603 mov r3, r0 + 80061e6: b21a sxth r2, r3 + 80061e8: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 80061ec: 9300 str r3, [sp, #0] + 80061ee: 4613 mov r3, r2 + 80061f0: 4632 mov r2, r6 + 80061f2: 4629 mov r1, r5 + 80061f4: 4620 mov r0, r4 + 80061f6: f7ff fe9b bl 8005f30 + ILI9341_writeLine(round(x1), round(y1), round(dx), round(dy), color); + 80061fa: f9b7 3006 ldrsh.w r3, [r7, #6] + 80061fe: 4618 mov r0, r3 + 8006200: f7fa f8f8 bl 80003f4 <__aeabi_i2d> + 8006204: 4603 mov r3, r0 + 8006206: 460c mov r4, r1 + 8006208: 4618 mov r0, r3 + 800620a: 4621 mov r1, r4 + 800620c: f7fa fbf6 bl 80009fc <__aeabi_d2iz> + 8006210: 4603 mov r3, r0 + 8006212: b21c sxth r4, r3 + 8006214: f9b7 3004 ldrsh.w r3, [r7, #4] + 8006218: 4618 mov r0, r3 + 800621a: f7fa f8eb bl 80003f4 <__aeabi_i2d> + 800621e: 4602 mov r2, r0 + 8006220: 460b mov r3, r1 + 8006222: 4610 mov r0, r2 + 8006224: 4619 mov r1, r3 + 8006226: f7fa fbe9 bl 80009fc <__aeabi_d2iz> + 800622a: 4603 mov r3, r0 + 800622c: b21d sxth r5, r3 + 800622e: 6a78 ldr r0, [r7, #36] ; 0x24 + 8006230: f7fa f8f2 bl 8000418 <__aeabi_f2d> + 8006234: 4602 mov r2, r0 + 8006236: 460b mov r3, r1 + 8006238: 4610 mov r0, r2 + 800623a: 4619 mov r1, r3 + 800623c: f005 f9c2 bl 800b5c4 + 8006240: 4602 mov r2, r0 + 8006242: 460b mov r3, r1 + 8006244: 4610 mov r0, r2 + 8006246: 4619 mov r1, r3 + 8006248: f7fa fbd8 bl 80009fc <__aeabi_d2iz> + 800624c: 4603 mov r3, r0 + 800624e: b21e sxth r6, r3 + 8006250: 6a38 ldr r0, [r7, #32] + 8006252: f7fa f8e1 bl 8000418 <__aeabi_f2d> + 8006256: 4602 mov r2, r0 + 8006258: 460b mov r3, r1 + 800625a: 4610 mov r0, r2 + 800625c: 4619 mov r1, r3 + 800625e: f005 f9b1 bl 800b5c4 + 8006262: 4602 mov r2, r0 + 8006264: 460b mov r3, r1 + 8006266: 4610 mov r0, r2 + 8006268: 4619 mov r1, r3 + 800626a: f7fa fbc7 bl 80009fc <__aeabi_d2iz> + 800626e: 4603 mov r3, r0 + 8006270: b21a sxth r2, r3 + 8006272: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 8006276: 9300 str r3, [sp, #0] + 8006278: 4613 mov r3, r2 + 800627a: 4632 mov r2, r6 + 800627c: 4629 mov r1, r5 + 800627e: 4620 mov r0, r4 + 8006280: f7ff fe56 bl 8005f30 + ILI9341_writeLine(round(x3), round(y3), round(x2), round(y2), color); + 8006284: 6978 ldr r0, [r7, #20] + 8006286: f7fa f8c7 bl 8000418 <__aeabi_f2d> + 800628a: 4603 mov r3, r0 + 800628c: 460c mov r4, r1 + 800628e: 4618 mov r0, r3 + 8006290: 4621 mov r1, r4 + 8006292: f005 f997 bl 800b5c4 + 8006296: 4603 mov r3, r0 + 8006298: 460c mov r4, r1 + 800629a: 4618 mov r0, r3 + 800629c: 4621 mov r1, r4 + 800629e: f7fa fbad bl 80009fc <__aeabi_d2iz> + 80062a2: 4603 mov r3, r0 + 80062a4: b21c sxth r4, r3 + 80062a6: 6938 ldr r0, [r7, #16] + 80062a8: f7fa f8b6 bl 8000418 <__aeabi_f2d> + 80062ac: 4602 mov r2, r0 + 80062ae: 460b mov r3, r1 + 80062b0: 4610 mov r0, r2 + 80062b2: 4619 mov r1, r3 + 80062b4: f005 f986 bl 800b5c4 + 80062b8: 4602 mov r2, r0 + 80062ba: 460b mov r3, r1 + 80062bc: 4610 mov r0, r2 + 80062be: 4619 mov r1, r3 + 80062c0: f7fa fb9c bl 80009fc <__aeabi_d2iz> + 80062c4: 4603 mov r3, r0 + 80062c6: b21d sxth r5, r3 + 80062c8: f9b7 3002 ldrsh.w r3, [r7, #2] + 80062cc: 4618 mov r0, r3 + 80062ce: f7fa f891 bl 80003f4 <__aeabi_i2d> + 80062d2: 4602 mov r2, r0 + 80062d4: 460b mov r3, r1 + 80062d6: 4610 mov r0, r2 + 80062d8: 4619 mov r1, r3 + 80062da: f7fa fb8f bl 80009fc <__aeabi_d2iz> + 80062de: 4603 mov r3, r0 + 80062e0: b21e sxth r6, r3 + 80062e2: f9b7 3000 ldrsh.w r3, [r7] + 80062e6: 4618 mov r0, r3 + 80062e8: f7fa f884 bl 80003f4 <__aeabi_i2d> + 80062ec: 4602 mov r2, r0 + 80062ee: 460b mov r3, r1 + 80062f0: 4610 mov r0, r2 + 80062f2: 4619 mov r1, r3 + 80062f4: f7fa fb82 bl 80009fc <__aeabi_d2iz> + 80062f8: 4603 mov r3, r0 + 80062fa: b21a sxth r2, r3 + 80062fc: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 8006300: 9300 str r3, [sp, #0] + 8006302: 4613 mov r3, r2 + 8006304: 4632 mov r2, r6 + 8006306: 4629 mov r1, r5 + 8006308: 4620 mov r0, r4 + 800630a: f7ff fe11 bl 8005f30 + ILI9341_writeLine(round(x2), round(y2), round(x4), round(y4), color); + 800630e: f9b7 3002 ldrsh.w r3, [r7, #2] + 8006312: 4618 mov r0, r3 + 8006314: f7fa f86e bl 80003f4 <__aeabi_i2d> + 8006318: 4603 mov r3, r0 + 800631a: 460c mov r4, r1 + 800631c: 4618 mov r0, r3 + 800631e: 4621 mov r1, r4 + 8006320: f7fa fb6c bl 80009fc <__aeabi_d2iz> + 8006324: 4603 mov r3, r0 + 8006326: b21c sxth r4, r3 + 8006328: f9b7 3000 ldrsh.w r3, [r7] + 800632c: 4618 mov r0, r3 + 800632e: f7fa f861 bl 80003f4 <__aeabi_i2d> + 8006332: 4602 mov r2, r0 + 8006334: 460b mov r3, r1 + 8006336: 4610 mov r0, r2 + 8006338: 4619 mov r1, r3 + 800633a: f7fa fb5f bl 80009fc <__aeabi_d2iz> + 800633e: 4603 mov r3, r0 + 8006340: b21d sxth r5, r3 + 8006342: 68f8 ldr r0, [r7, #12] + 8006344: f7fa f868 bl 8000418 <__aeabi_f2d> + 8006348: 4602 mov r2, r0 + 800634a: 460b mov r3, r1 + 800634c: 4610 mov r0, r2 + 800634e: 4619 mov r1, r3 + 8006350: f005 f938 bl 800b5c4 + 8006354: 4602 mov r2, r0 + 8006356: 460b mov r3, r1 + 8006358: 4610 mov r0, r2 + 800635a: 4619 mov r1, r3 + 800635c: f7fa fb4e bl 80009fc <__aeabi_d2iz> + 8006360: 4603 mov r3, r0 + 8006362: b21e sxth r6, r3 + 8006364: 68b8 ldr r0, [r7, #8] + 8006366: f7fa f857 bl 8000418 <__aeabi_f2d> + 800636a: 4602 mov r2, r0 + 800636c: 460b mov r3, r1 + 800636e: 4610 mov r0, r2 + 8006370: 4619 mov r1, r3 + 8006372: f005 f927 bl 800b5c4 + 8006376: 4602 mov r2, r0 + 8006378: 460b mov r3, r1 + 800637a: 4610 mov r0, r2 + 800637c: 4619 mov r1, r3 + 800637e: f7fa fb3d bl 80009fc <__aeabi_d2iz> + 8006382: 4603 mov r3, r0 + 8006384: b21a sxth r2, r3 + 8006386: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 800638a: 9300 str r3, [sp, #0] + 800638c: 4613 mov r3, r2 + 800638e: 4632 mov r2, r6 + 8006390: 4629 mov r1, r5 + 8006392: 4620 mov r0, r4 + 8006394: f7ff fdcc bl 8005f30 +} + 8006398: bf00 nop + 800639a: 372c adds r7, #44 ; 0x2c + 800639c: 46bd mov sp, r7 + 800639e: bdf0 pop {r4, r5, r6, r7, pc} + +080063a0 : + // Can be just writeLine(x, y, x, y+h-1, color); + // or writeFillRect(x, y, 1, h, color); + ILI9341_drawFastVLine(x, y, h, color); +} + +void ILI9341_writePixel(int16_t x, int16_t y, uint16_t color){ + 80063a0: b580 push {r7, lr} + 80063a2: b082 sub sp, #8 + 80063a4: af00 add r7, sp, #0 + 80063a6: 4603 mov r3, r0 + 80063a8: 80fb strh r3, [r7, #6] + 80063aa: 460b mov r3, r1 + 80063ac: 80bb strh r3, [r7, #4] + 80063ae: 4613 mov r3, r2 + 80063b0: 807b strh r3, [r7, #2] + ILI9341_DrawPixel(x, y, color); + 80063b2: 88fb ldrh r3, [r7, #6] + 80063b4: 88b9 ldrh r1, [r7, #4] + 80063b6: 887a ldrh r2, [r7, #2] + 80063b8: 4618 mov r0, r3 + 80063ba: f7ff fc59 bl 8005c70 +} + 80063be: bf00 nop + 80063c0: 3708 adds r7, #8 + 80063c2: 46bd mov sp, r7 + 80063c4: bd80 pop {r7, pc} + +080063c6 : + ILI9341_drawCircleHelper(x+w-r-1, y+h-r-1, r, 4, color); + ILI9341_drawCircleHelper(x+r , y+h-r-1, r, 8, color); + ILI9341_Unselect(); +} + +void ILI9341_drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color) { + 80063c6: b590 push {r4, r7, lr} + 80063c8: b087 sub sp, #28 + 80063ca: af00 add r7, sp, #0 + 80063cc: 4604 mov r4, r0 + 80063ce: 4608 mov r0, r1 + 80063d0: 4611 mov r1, r2 + 80063d2: 461a mov r2, r3 + 80063d4: 4623 mov r3, r4 + 80063d6: 80fb strh r3, [r7, #6] + 80063d8: 4603 mov r3, r0 + 80063da: 80bb strh r3, [r7, #4] + 80063dc: 460b mov r3, r1 + 80063de: 807b strh r3, [r7, #2] + 80063e0: 4613 mov r3, r2 + 80063e2: 803b strh r3, [r7, #0] + int16_t f = 1 - r; + 80063e4: 887b ldrh r3, [r7, #2] + 80063e6: f1c3 0301 rsb r3, r3, #1 + 80063ea: b29b uxth r3, r3 + 80063ec: 82fb strh r3, [r7, #22] + int16_t ddF_x = 1; + 80063ee: 2301 movs r3, #1 + 80063f0: 82bb strh r3, [r7, #20] + int16_t ddF_y = -2 * r; + 80063f2: 887b ldrh r3, [r7, #2] + 80063f4: 461a mov r2, r3 + 80063f6: 03d2 lsls r2, r2, #15 + 80063f8: 1ad3 subs r3, r2, r3 + 80063fa: 005b lsls r3, r3, #1 + 80063fc: b29b uxth r3, r3 + 80063fe: 827b strh r3, [r7, #18] + int16_t x = 0; + 8006400: 2300 movs r3, #0 + 8006402: 823b strh r3, [r7, #16] + int16_t y = r; + 8006404: 887b ldrh r3, [r7, #2] + 8006406: 81fb strh r3, [r7, #14] + + ILI9341_Select(); + 8006408: f7ff fa40 bl 800588c + ILI9341_writePixel(x0 , y0+r, color); + 800640c: 88ba ldrh r2, [r7, #4] + 800640e: 887b ldrh r3, [r7, #2] + 8006410: 4413 add r3, r2 + 8006412: b29b uxth r3, r3 + 8006414: b219 sxth r1, r3 + 8006416: 883a ldrh r2, [r7, #0] + 8006418: f9b7 3006 ldrsh.w r3, [r7, #6] + 800641c: 4618 mov r0, r3 + 800641e: f7ff ffbf bl 80063a0 + ILI9341_writePixel(x0 , y0-r, color); + 8006422: 88ba ldrh r2, [r7, #4] + 8006424: 887b ldrh r3, [r7, #2] + 8006426: 1ad3 subs r3, r2, r3 + 8006428: b29b uxth r3, r3 + 800642a: b219 sxth r1, r3 + 800642c: 883a ldrh r2, [r7, #0] + 800642e: f9b7 3006 ldrsh.w r3, [r7, #6] + 8006432: 4618 mov r0, r3 + 8006434: f7ff ffb4 bl 80063a0 + ILI9341_writePixel(x0+r, y0 , color); + 8006438: 88fa ldrh r2, [r7, #6] + 800643a: 887b ldrh r3, [r7, #2] + 800643c: 4413 add r3, r2 + 800643e: b29b uxth r3, r3 + 8006440: b21b sxth r3, r3 + 8006442: 883a ldrh r2, [r7, #0] + 8006444: f9b7 1004 ldrsh.w r1, [r7, #4] + 8006448: 4618 mov r0, r3 + 800644a: f7ff ffa9 bl 80063a0 + ILI9341_writePixel(x0-r, y0 , color); + 800644e: 88fa ldrh r2, [r7, #6] + 8006450: 887b ldrh r3, [r7, #2] + 8006452: 1ad3 subs r3, r2, r3 + 8006454: b29b uxth r3, r3 + 8006456: b21b sxth r3, r3 + 8006458: 883a ldrh r2, [r7, #0] + 800645a: f9b7 1004 ldrsh.w r1, [r7, #4] + 800645e: 4618 mov r0, r3 + 8006460: f7ff ff9e bl 80063a0 + + while (x + if (f >= 0) { + 8006466: f9b7 3016 ldrsh.w r3, [r7, #22] + 800646a: 2b00 cmp r3, #0 + 800646c: db0e blt.n 800648c + y--; + 800646e: f9b7 300e ldrsh.w r3, [r7, #14] + 8006472: b29b uxth r3, r3 + 8006474: 3b01 subs r3, #1 + 8006476: b29b uxth r3, r3 + 8006478: 81fb strh r3, [r7, #14] + ddF_y += 2; + 800647a: 8a7b ldrh r3, [r7, #18] + 800647c: 3302 adds r3, #2 + 800647e: b29b uxth r3, r3 + 8006480: 827b strh r3, [r7, #18] + f += ddF_y; + 8006482: 8afa ldrh r2, [r7, #22] + 8006484: 8a7b ldrh r3, [r7, #18] + 8006486: 4413 add r3, r2 + 8006488: b29b uxth r3, r3 + 800648a: 82fb strh r3, [r7, #22] + } + x++; + 800648c: f9b7 3010 ldrsh.w r3, [r7, #16] + 8006490: b29b uxth r3, r3 + 8006492: 3301 adds r3, #1 + 8006494: b29b uxth r3, r3 + 8006496: 823b strh r3, [r7, #16] + ddF_x += 2; + 8006498: 8abb ldrh r3, [r7, #20] + 800649a: 3302 adds r3, #2 + 800649c: b29b uxth r3, r3 + 800649e: 82bb strh r3, [r7, #20] + f += ddF_x; + 80064a0: 8afa ldrh r2, [r7, #22] + 80064a2: 8abb ldrh r3, [r7, #20] + 80064a4: 4413 add r3, r2 + 80064a6: b29b uxth r3, r3 + 80064a8: 82fb strh r3, [r7, #22] + + ILI9341_writePixel(x0 + x, y0 + y, color); + 80064aa: 88fa ldrh r2, [r7, #6] + 80064ac: 8a3b ldrh r3, [r7, #16] + 80064ae: 4413 add r3, r2 + 80064b0: b29b uxth r3, r3 + 80064b2: b218 sxth r0, r3 + 80064b4: 88ba ldrh r2, [r7, #4] + 80064b6: 89fb ldrh r3, [r7, #14] + 80064b8: 4413 add r3, r2 + 80064ba: b29b uxth r3, r3 + 80064bc: b21b sxth r3, r3 + 80064be: 883a ldrh r2, [r7, #0] + 80064c0: 4619 mov r1, r3 + 80064c2: f7ff ff6d bl 80063a0 + ILI9341_writePixel(x0 - x, y0 + y, color); + 80064c6: 88fa ldrh r2, [r7, #6] + 80064c8: 8a3b ldrh r3, [r7, #16] + 80064ca: 1ad3 subs r3, r2, r3 + 80064cc: b29b uxth r3, r3 + 80064ce: b218 sxth r0, r3 + 80064d0: 88ba ldrh r2, [r7, #4] + 80064d2: 89fb ldrh r3, [r7, #14] + 80064d4: 4413 add r3, r2 + 80064d6: b29b uxth r3, r3 + 80064d8: b21b sxth r3, r3 + 80064da: 883a ldrh r2, [r7, #0] + 80064dc: 4619 mov r1, r3 + 80064de: f7ff ff5f bl 80063a0 + ILI9341_writePixel(x0 + x, y0 - y, color); + 80064e2: 88fa ldrh r2, [r7, #6] + 80064e4: 8a3b ldrh r3, [r7, #16] + 80064e6: 4413 add r3, r2 + 80064e8: b29b uxth r3, r3 + 80064ea: b218 sxth r0, r3 + 80064ec: 88ba ldrh r2, [r7, #4] + 80064ee: 89fb ldrh r3, [r7, #14] + 80064f0: 1ad3 subs r3, r2, r3 + 80064f2: b29b uxth r3, r3 + 80064f4: b21b sxth r3, r3 + 80064f6: 883a ldrh r2, [r7, #0] + 80064f8: 4619 mov r1, r3 + 80064fa: f7ff ff51 bl 80063a0 + ILI9341_writePixel(x0 - x, y0 - y, color); + 80064fe: 88fa ldrh r2, [r7, #6] + 8006500: 8a3b ldrh r3, [r7, #16] + 8006502: 1ad3 subs r3, r2, r3 + 8006504: b29b uxth r3, r3 + 8006506: b218 sxth r0, r3 + 8006508: 88ba ldrh r2, [r7, #4] + 800650a: 89fb ldrh r3, [r7, #14] + 800650c: 1ad3 subs r3, r2, r3 + 800650e: b29b uxth r3, r3 + 8006510: b21b sxth r3, r3 + 8006512: 883a ldrh r2, [r7, #0] + 8006514: 4619 mov r1, r3 + 8006516: f7ff ff43 bl 80063a0 + ILI9341_writePixel(x0 + y, y0 + x, color); + 800651a: 88fa ldrh r2, [r7, #6] + 800651c: 89fb ldrh r3, [r7, #14] + 800651e: 4413 add r3, r2 + 8006520: b29b uxth r3, r3 + 8006522: b218 sxth r0, r3 + 8006524: 88ba ldrh r2, [r7, #4] + 8006526: 8a3b ldrh r3, [r7, #16] + 8006528: 4413 add r3, r2 + 800652a: b29b uxth r3, r3 + 800652c: b21b sxth r3, r3 + 800652e: 883a ldrh r2, [r7, #0] + 8006530: 4619 mov r1, r3 + 8006532: f7ff ff35 bl 80063a0 + ILI9341_writePixel(x0 - y, y0 + x, color); + 8006536: 88fa ldrh r2, [r7, #6] + 8006538: 89fb ldrh r3, [r7, #14] + 800653a: 1ad3 subs r3, r2, r3 + 800653c: b29b uxth r3, r3 + 800653e: b218 sxth r0, r3 + 8006540: 88ba ldrh r2, [r7, #4] + 8006542: 8a3b ldrh r3, [r7, #16] + 8006544: 4413 add r3, r2 + 8006546: b29b uxth r3, r3 + 8006548: b21b sxth r3, r3 + 800654a: 883a ldrh r2, [r7, #0] + 800654c: 4619 mov r1, r3 + 800654e: f7ff ff27 bl 80063a0 + ILI9341_writePixel(x0 + y, y0 - x, color); + 8006552: 88fa ldrh r2, [r7, #6] + 8006554: 89fb ldrh r3, [r7, #14] + 8006556: 4413 add r3, r2 + 8006558: b29b uxth r3, r3 + 800655a: b218 sxth r0, r3 + 800655c: 88ba ldrh r2, [r7, #4] + 800655e: 8a3b ldrh r3, [r7, #16] + 8006560: 1ad3 subs r3, r2, r3 + 8006562: b29b uxth r3, r3 + 8006564: b21b sxth r3, r3 + 8006566: 883a ldrh r2, [r7, #0] + 8006568: 4619 mov r1, r3 + 800656a: f7ff ff19 bl 80063a0 + ILI9341_writePixel(x0 - y, y0 - x, color); + 800656e: 88fa ldrh r2, [r7, #6] + 8006570: 89fb ldrh r3, [r7, #14] + 8006572: 1ad3 subs r3, r2, r3 + 8006574: b29b uxth r3, r3 + 8006576: b218 sxth r0, r3 + 8006578: 88ba ldrh r2, [r7, #4] + 800657a: 8a3b ldrh r3, [r7, #16] + 800657c: 1ad3 subs r3, r2, r3 + 800657e: b29b uxth r3, r3 + 8006580: b21b sxth r3, r3 + 8006582: 883a ldrh r2, [r7, #0] + 8006584: 4619 mov r1, r3 + 8006586: f7ff ff0b bl 80063a0 + while (x + } + ILI9341_Unselect(); + 8006598: f7ff f984 bl 80058a4 +} + 800659c: bf00 nop + 800659e: 371c adds r7, #28 + 80065a0: 46bd mov sp, r7 + 80065a2: bd90 pop {r4, r7, pc} + +080065a4 : + + +void ILI9341_FillScreen(uint16_t color) { + 80065a4: b580 push {r7, lr} + 80065a6: b084 sub sp, #16 + 80065a8: af02 add r7, sp, #8 + 80065aa: 4603 mov r3, r0 + 80065ac: 80fb strh r3, [r7, #6] + ILI9341_FillRectangle(0, 0, ILI9341_WIDTH, ILI9341_HEIGHT, color); + 80065ae: 88fb ldrh r3, [r7, #6] + 80065b0: 9300 str r3, [sp, #0] + 80065b2: 23f0 movs r3, #240 ; 0xf0 + 80065b4: f44f 72a0 mov.w r2, #320 ; 0x140 + 80065b8: 2100 movs r1, #0 + 80065ba: 2000 movs r0, #0 + 80065bc: f7ff fc48 bl 8005e50 +} + 80065c0: bf00 nop + 80065c2: 3708 adds r7, #8 + 80065c4: 46bd mov sp, r7 + 80065c6: bd80 pop {r7, pc} + +080065c8 : + +static void ILI9341_TouchSelect() { + HAL_GPIO_WritePin(ILI9341_TOUCH_CS_GPIO_Port, ILI9341_TOUCH_CS_Pin, GPIO_PIN_RESET); +} + +void ILI9341_TouchUnselect() { + 80065c8: b580 push {r7, lr} + 80065ca: af00 add r7, sp, #0 + HAL_GPIO_WritePin(ILI9341_TOUCH_CS_GPIO_Port, ILI9341_TOUCH_CS_Pin, GPIO_PIN_SET); + 80065cc: 2201 movs r2, #1 + 80065ce: f44f 6180 mov.w r1, #1024 ; 0x400 + 80065d2: 4802 ldr r0, [pc, #8] ; (80065dc ) + 80065d4: f7fb f811 bl 80015fa +} + 80065d8: bf00 nop + 80065da: bd80 pop {r7, pc} + 80065dc: 40010800 .word 0x40010800 + +080065e0 : + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + 80065e0: b580 push {r7, lr} + 80065e2: b084 sub sp, #16 + 80065e4: af00 add r7, sp, #0 + 80065e6: 6078 str r0, [r7, #4] + 80065e8: 460b mov r3, r1 + 80065ea: 70fb strb r3, [r7, #3] + uint8_t ret = 0U; + 80065ec: 2300 movs r3, #0 + 80065ee: 73fb strb r3, [r7, #15] + USBD_CDC_HandleTypeDef *hcdc; + + if (pdev->dev_speed == USBD_SPEED_HIGH) + 80065f0: 687b ldr r3, [r7, #4] + 80065f2: 7c1b ldrb r3, [r3, #16] + 80065f4: 2b00 cmp r3, #0 + 80065f6: d115 bne.n 8006624 + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, + 80065f8: f44f 7300 mov.w r3, #512 ; 0x200 + 80065fc: 2202 movs r2, #2 + 80065fe: 2181 movs r1, #129 ; 0x81 + 8006600: 6878 ldr r0, [r7, #4] + 8006602: f004 f88e bl 800a722 + CDC_DATA_HS_IN_PACKET_SIZE); + + pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; + 8006606: 687b ldr r3, [r7, #4] + 8006608: 2201 movs r2, #1 + 800660a: 62da str r2, [r3, #44] ; 0x2c + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, + 800660c: f44f 7300 mov.w r3, #512 ; 0x200 + 8006610: 2202 movs r2, #2 + 8006612: 2101 movs r1, #1 + 8006614: 6878 ldr r0, [r7, #4] + 8006616: f004 f884 bl 800a722 + CDC_DATA_HS_OUT_PACKET_SIZE); + + pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; + 800661a: 687b ldr r3, [r7, #4] + 800661c: 2201 movs r2, #1 + 800661e: f8c3 216c str.w r2, [r3, #364] ; 0x16c + 8006622: e012 b.n 800664a + + } + else + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, + 8006624: 2340 movs r3, #64 ; 0x40 + 8006626: 2202 movs r2, #2 + 8006628: 2181 movs r1, #129 ; 0x81 + 800662a: 6878 ldr r0, [r7, #4] + 800662c: f004 f879 bl 800a722 + CDC_DATA_FS_IN_PACKET_SIZE); + + pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; + 8006630: 687b ldr r3, [r7, #4] + 8006632: 2201 movs r2, #1 + 8006634: 62da str r2, [r3, #44] ; 0x2c + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, + 8006636: 2340 movs r3, #64 ; 0x40 + 8006638: 2202 movs r2, #2 + 800663a: 2101 movs r1, #1 + 800663c: 6878 ldr r0, [r7, #4] + 800663e: f004 f870 bl 800a722 + CDC_DATA_FS_OUT_PACKET_SIZE); + + pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; + 8006642: 687b ldr r3, [r7, #4] + 8006644: 2201 movs r2, #1 + 8006646: f8c3 216c str.w r2, [r3, #364] ; 0x16c + } + /* Open Command IN EP */ + USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); + 800664a: 2308 movs r3, #8 + 800664c: 2203 movs r2, #3 + 800664e: 2182 movs r1, #130 ; 0x82 + 8006650: 6878 ldr r0, [r7, #4] + 8006652: f004 f866 bl 800a722 + pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U; + 8006656: 687b ldr r3, [r7, #4] + 8006658: 2201 movs r2, #1 + 800665a: 641a str r2, [r3, #64] ; 0x40 + + pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); + 800665c: f44f 7007 mov.w r0, #540 ; 0x21c + 8006660: f004 f980 bl 800a964 + 8006664: 4602 mov r2, r0 + 8006666: 687b ldr r3, [r7, #4] + 8006668: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 + + if (pdev->pClassData == NULL) + 800666c: 687b ldr r3, [r7, #4] + 800666e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006672: 2b00 cmp r3, #0 + 8006674: d102 bne.n 800667c + { + ret = 1U; + 8006676: 2301 movs r3, #1 + 8006678: 73fb strb r3, [r7, #15] + 800667a: e026 b.n 80066ca + } + else + { + hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + 800667c: 687b ldr r3, [r7, #4] + 800667e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006682: 60bb str r3, [r7, #8] + + /* Init physical Interface components */ + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); + 8006684: 687b ldr r3, [r7, #4] + 8006686: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc + 800668a: 681b ldr r3, [r3, #0] + 800668c: 4798 blx r3 + + /* Init Xfer states */ + hcdc->TxState = 0U; + 800668e: 68bb ldr r3, [r7, #8] + 8006690: 2200 movs r2, #0 + 8006692: f8c3 2214 str.w r2, [r3, #532] ; 0x214 + hcdc->RxState = 0U; + 8006696: 68bb ldr r3, [r7, #8] + 8006698: 2200 movs r2, #0 + 800669a: f8c3 2218 str.w r2, [r3, #536] ; 0x218 + + if (pdev->dev_speed == USBD_SPEED_HIGH) + 800669e: 687b ldr r3, [r7, #4] + 80066a0: 7c1b ldrb r3, [r3, #16] + 80066a2: 2b00 cmp r3, #0 + 80066a4: d109 bne.n 80066ba + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + 80066a6: 68bb ldr r3, [r7, #8] + 80066a8: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 80066ac: f44f 7300 mov.w r3, #512 ; 0x200 + 80066b0: 2101 movs r1, #1 + 80066b2: 6878 ldr r0, [r7, #4] + 80066b4: f004 f91f bl 800a8f6 + 80066b8: e007 b.n 80066ca + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + 80066ba: 68bb ldr r3, [r7, #8] + 80066bc: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 80066c0: 2340 movs r3, #64 ; 0x40 + 80066c2: 2101 movs r1, #1 + 80066c4: 6878 ldr r0, [r7, #4] + 80066c6: f004 f916 bl 800a8f6 + CDC_DATA_FS_OUT_PACKET_SIZE); + } + } + return ret; + 80066ca: 7bfb ldrb r3, [r7, #15] +} + 80066cc: 4618 mov r0, r3 + 80066ce: 3710 adds r7, #16 + 80066d0: 46bd mov sp, r7 + 80066d2: bd80 pop {r7, pc} + +080066d4 : + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + 80066d4: b580 push {r7, lr} + 80066d6: b084 sub sp, #16 + 80066d8: af00 add r7, sp, #0 + 80066da: 6078 str r0, [r7, #4] + 80066dc: 460b mov r3, r1 + 80066de: 70fb strb r3, [r7, #3] + uint8_t ret = 0U; + 80066e0: 2300 movs r3, #0 + 80066e2: 73fb strb r3, [r7, #15] + + /* Close EP IN */ + USBD_LL_CloseEP(pdev, CDC_IN_EP); + 80066e4: 2181 movs r1, #129 ; 0x81 + 80066e6: 6878 ldr r0, [r7, #4] + 80066e8: f004 f841 bl 800a76e + pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U; + 80066ec: 687b ldr r3, [r7, #4] + 80066ee: 2200 movs r2, #0 + 80066f0: 62da str r2, [r3, #44] ; 0x2c + + /* Close EP OUT */ + USBD_LL_CloseEP(pdev, CDC_OUT_EP); + 80066f2: 2101 movs r1, #1 + 80066f4: 6878 ldr r0, [r7, #4] + 80066f6: f004 f83a bl 800a76e + pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U; + 80066fa: 687b ldr r3, [r7, #4] + 80066fc: 2200 movs r2, #0 + 80066fe: f8c3 216c str.w r2, [r3, #364] ; 0x16c + + /* Close Command IN EP */ + USBD_LL_CloseEP(pdev, CDC_CMD_EP); + 8006702: 2182 movs r1, #130 ; 0x82 + 8006704: 6878 ldr r0, [r7, #4] + 8006706: f004 f832 bl 800a76e + pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U; + 800670a: 687b ldr r3, [r7, #4] + 800670c: 2200 movs r2, #0 + 800670e: 641a str r2, [r3, #64] ; 0x40 + + /* DeInit physical Interface components */ + if (pdev->pClassData != NULL) + 8006710: 687b ldr r3, [r7, #4] + 8006712: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006716: 2b00 cmp r3, #0 + 8006718: d00e beq.n 8006738 + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); + 800671a: 687b ldr r3, [r7, #4] + 800671c: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc + 8006720: 685b ldr r3, [r3, #4] + 8006722: 4798 blx r3 + USBD_free(pdev->pClassData); + 8006724: 687b ldr r3, [r7, #4] + 8006726: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 800672a: 4618 mov r0, r3 + 800672c: f004 f926 bl 800a97c + pdev->pClassData = NULL; + 8006730: 687b ldr r3, [r7, #4] + 8006732: 2200 movs r2, #0 + 8006734: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 + } + + return ret; + 8006738: 7bfb ldrb r3, [r7, #15] +} + 800673a: 4618 mov r0, r3 + 800673c: 3710 adds r7, #16 + 800673e: 46bd mov sp, r7 + 8006740: bd80 pop {r7, pc} + +08006742 : + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 8006742: b580 push {r7, lr} + 8006744: b086 sub sp, #24 + 8006746: af00 add r7, sp, #0 + 8006748: 6078 str r0, [r7, #4] + 800674a: 6039 str r1, [r7, #0] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + 800674c: 687b ldr r3, [r7, #4] + 800674e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006752: 613b str r3, [r7, #16] + uint8_t ifalt = 0U; + 8006754: 2300 movs r3, #0 + 8006756: 73fb strb r3, [r7, #15] + uint16_t status_info = 0U; + 8006758: 2300 movs r3, #0 + 800675a: 81bb strh r3, [r7, #12] + uint8_t ret = USBD_OK; + 800675c: 2300 movs r3, #0 + 800675e: 75fb strb r3, [r7, #23] + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + 8006760: 683b ldr r3, [r7, #0] + 8006762: 781b ldrb r3, [r3, #0] + 8006764: f003 0360 and.w r3, r3, #96 ; 0x60 + 8006768: 2b00 cmp r3, #0 + 800676a: d039 beq.n 80067e0 + 800676c: 2b20 cmp r3, #32 + 800676e: d17c bne.n 800686a + { + case USB_REQ_TYPE_CLASS : + if (req->wLength) + 8006770: 683b ldr r3, [r7, #0] + 8006772: 88db ldrh r3, [r3, #6] + 8006774: 2b00 cmp r3, #0 + 8006776: d029 beq.n 80067cc + { + if (req->bmRequest & 0x80U) + 8006778: 683b ldr r3, [r7, #0] + 800677a: 781b ldrb r3, [r3, #0] + 800677c: b25b sxtb r3, r3 + 800677e: 2b00 cmp r3, #0 + 8006780: da11 bge.n 80067a6 + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + 8006782: 687b ldr r3, [r7, #4] + 8006784: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc + 8006788: 689b ldr r3, [r3, #8] + 800678a: 683a ldr r2, [r7, #0] + 800678c: 7850 ldrb r0, [r2, #1] + (uint8_t *)(void *)hcdc->data, + 800678e: 6939 ldr r1, [r7, #16] + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + 8006790: 683a ldr r2, [r7, #0] + 8006792: 88d2 ldrh r2, [r2, #6] + 8006794: 4798 blx r3 + req->wLength); + + USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); + 8006796: 6939 ldr r1, [r7, #16] + 8006798: 683b ldr r3, [r7, #0] + 800679a: 88db ldrh r3, [r3, #6] + 800679c: 461a mov r2, r3 + 800679e: 6878 ldr r0, [r7, #4] + 80067a0: f001 f9c6 bl 8007b30 + else + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)(void *)req, 0U); + } + break; + 80067a4: e068 b.n 8006878 + hcdc->CmdOpCode = req->bRequest; + 80067a6: 683b ldr r3, [r7, #0] + 80067a8: 785a ldrb r2, [r3, #1] + 80067aa: 693b ldr r3, [r7, #16] + 80067ac: f883 2200 strb.w r2, [r3, #512] ; 0x200 + hcdc->CmdLength = (uint8_t)req->wLength; + 80067b0: 683b ldr r3, [r7, #0] + 80067b2: 88db ldrh r3, [r3, #6] + 80067b4: b2da uxtb r2, r3 + 80067b6: 693b ldr r3, [r7, #16] + 80067b8: f883 2201 strb.w r2, [r3, #513] ; 0x201 + USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); + 80067bc: 6939 ldr r1, [r7, #16] + 80067be: 683b ldr r3, [r7, #0] + 80067c0: 88db ldrh r3, [r3, #6] + 80067c2: 461a mov r2, r3 + 80067c4: 6878 ldr r0, [r7, #4] + 80067c6: f001 f9e1 bl 8007b8c + break; + 80067ca: e055 b.n 8006878 + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + 80067cc: 687b ldr r3, [r7, #4] + 80067ce: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc + 80067d2: 689b ldr r3, [r3, #8] + 80067d4: 683a ldr r2, [r7, #0] + 80067d6: 7850 ldrb r0, [r2, #1] + 80067d8: 2200 movs r2, #0 + 80067da: 6839 ldr r1, [r7, #0] + 80067dc: 4798 blx r3 + break; + 80067de: e04b b.n 8006878 + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + 80067e0: 683b ldr r3, [r7, #0] + 80067e2: 785b ldrb r3, [r3, #1] + 80067e4: 2b0a cmp r3, #10 + 80067e6: d017 beq.n 8006818 + 80067e8: 2b0b cmp r3, #11 + 80067ea: d029 beq.n 8006840 + 80067ec: 2b00 cmp r3, #0 + 80067ee: d133 bne.n 8006858 + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 80067f0: 687b ldr r3, [r7, #4] + 80067f2: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 80067f6: 2b03 cmp r3, #3 + 80067f8: d107 bne.n 800680a + { + USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); + 80067fa: f107 030c add.w r3, r7, #12 + 80067fe: 2202 movs r2, #2 + 8006800: 4619 mov r1, r3 + 8006802: 6878 ldr r0, [r7, #4] + 8006804: f001 f994 bl 8007b30 + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + 8006808: e02e b.n 8006868 + USBD_CtlError(pdev, req); + 800680a: 6839 ldr r1, [r7, #0] + 800680c: 6878 ldr r0, [r7, #4] + 800680e: f001 f925 bl 8007a5c + ret = USBD_FAIL; + 8006812: 2302 movs r3, #2 + 8006814: 75fb strb r3, [r7, #23] + break; + 8006816: e027 b.n 8006868 + + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 8006818: 687b ldr r3, [r7, #4] + 800681a: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 800681e: 2b03 cmp r3, #3 + 8006820: d107 bne.n 8006832 + { + USBD_CtlSendData(pdev, &ifalt, 1U); + 8006822: f107 030f add.w r3, r7, #15 + 8006826: 2201 movs r2, #1 + 8006828: 4619 mov r1, r3 + 800682a: 6878 ldr r0, [r7, #4] + 800682c: f001 f980 bl 8007b30 + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + 8006830: e01a b.n 8006868 + USBD_CtlError(pdev, req); + 8006832: 6839 ldr r1, [r7, #0] + 8006834: 6878 ldr r0, [r7, #4] + 8006836: f001 f911 bl 8007a5c + ret = USBD_FAIL; + 800683a: 2302 movs r3, #2 + 800683c: 75fb strb r3, [r7, #23] + break; + 800683e: e013 b.n 8006868 + + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state != USBD_STATE_CONFIGURED) + 8006840: 687b ldr r3, [r7, #4] + 8006842: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8006846: 2b03 cmp r3, #3 + 8006848: d00d beq.n 8006866 + { + USBD_CtlError(pdev, req); + 800684a: 6839 ldr r1, [r7, #0] + 800684c: 6878 ldr r0, [r7, #4] + 800684e: f001 f905 bl 8007a5c + ret = USBD_FAIL; + 8006852: 2302 movs r3, #2 + 8006854: 75fb strb r3, [r7, #23] + } + break; + 8006856: e006 b.n 8006866 + + default: + USBD_CtlError(pdev, req); + 8006858: 6839 ldr r1, [r7, #0] + 800685a: 6878 ldr r0, [r7, #4] + 800685c: f001 f8fe bl 8007a5c + ret = USBD_FAIL; + 8006860: 2302 movs r3, #2 + 8006862: 75fb strb r3, [r7, #23] + break; + 8006864: e000 b.n 8006868 + break; + 8006866: bf00 nop + } + break; + 8006868: e006 b.n 8006878 + + default: + USBD_CtlError(pdev, req); + 800686a: 6839 ldr r1, [r7, #0] + 800686c: 6878 ldr r0, [r7, #4] + 800686e: f001 f8f5 bl 8007a5c + ret = USBD_FAIL; + 8006872: 2302 movs r3, #2 + 8006874: 75fb strb r3, [r7, #23] + break; + 8006876: bf00 nop + } + + return ret; + 8006878: 7dfb ldrb r3, [r7, #23] +} + 800687a: 4618 mov r0, r3 + 800687c: 3718 adds r7, #24 + 800687e: 46bd mov sp, r7 + 8006880: bd80 pop {r7, pc} + +08006882 : + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + 8006882: b580 push {r7, lr} + 8006884: b084 sub sp, #16 + 8006886: af00 add r7, sp, #0 + 8006888: 6078 str r0, [r7, #4] + 800688a: 460b mov r3, r1 + 800688c: 70fb strb r3, [r7, #3] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + 800688e: 687b ldr r3, [r7, #4] + 8006890: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006894: 60fb str r3, [r7, #12] + PCD_HandleTypeDef *hpcd = pdev->pData; + 8006896: 687b ldr r3, [r7, #4] + 8006898: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 800689c: 60bb str r3, [r7, #8] + + if (pdev->pClassData != NULL) + 800689e: 687b ldr r3, [r7, #4] + 80068a0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 80068a4: 2b00 cmp r3, #0 + 80068a6: d037 beq.n 8006918 + { + if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) + 80068a8: 78fa ldrb r2, [r7, #3] + 80068aa: 6879 ldr r1, [r7, #4] + 80068ac: 4613 mov r3, r2 + 80068ae: 009b lsls r3, r3, #2 + 80068b0: 4413 add r3, r2 + 80068b2: 009b lsls r3, r3, #2 + 80068b4: 440b add r3, r1 + 80068b6: 331c adds r3, #28 + 80068b8: 681b ldr r3, [r3, #0] + 80068ba: 2b00 cmp r3, #0 + 80068bc: d026 beq.n 800690c + 80068be: 78fa ldrb r2, [r7, #3] + 80068c0: 6879 ldr r1, [r7, #4] + 80068c2: 4613 mov r3, r2 + 80068c4: 009b lsls r3, r3, #2 + 80068c6: 4413 add r3, r2 + 80068c8: 009b lsls r3, r3, #2 + 80068ca: 440b add r3, r1 + 80068cc: 331c adds r3, #28 + 80068ce: 681b ldr r3, [r3, #0] + 80068d0: 78fa ldrb r2, [r7, #3] + 80068d2: 68b9 ldr r1, [r7, #8] + 80068d4: 0152 lsls r2, r2, #5 + 80068d6: 440a add r2, r1 + 80068d8: 3238 adds r2, #56 ; 0x38 + 80068da: 6812 ldr r2, [r2, #0] + 80068dc: fbb3 f1f2 udiv r1, r3, r2 + 80068e0: fb02 f201 mul.w r2, r2, r1 + 80068e4: 1a9b subs r3, r3, r2 + 80068e6: 2b00 cmp r3, #0 + 80068e8: d110 bne.n 800690c + { + /* Update the packet total length */ + pdev->ep_in[epnum].total_length = 0U; + 80068ea: 78fa ldrb r2, [r7, #3] + 80068ec: 6879 ldr r1, [r7, #4] + 80068ee: 4613 mov r3, r2 + 80068f0: 009b lsls r3, r3, #2 + 80068f2: 4413 add r3, r2 + 80068f4: 009b lsls r3, r3, #2 + 80068f6: 440b add r3, r1 + 80068f8: 331c adds r3, #28 + 80068fa: 2200 movs r2, #0 + 80068fc: 601a str r2, [r3, #0] + + /* Send ZLP */ + USBD_LL_Transmit(pdev, epnum, NULL, 0U); + 80068fe: 78f9 ldrb r1, [r7, #3] + 8006900: 2300 movs r3, #0 + 8006902: 2200 movs r2, #0 + 8006904: 6878 ldr r0, [r7, #4] + 8006906: f003 ffd3 bl 800a8b0 + 800690a: e003 b.n 8006914 + } + else + { + hcdc->TxState = 0U; + 800690c: 68fb ldr r3, [r7, #12] + 800690e: 2200 movs r2, #0 + 8006910: f8c3 2214 str.w r2, [r3, #532] ; 0x214 + } + return USBD_OK; + 8006914: 2300 movs r3, #0 + 8006916: e000 b.n 800691a + } + else + { + return USBD_FAIL; + 8006918: 2302 movs r3, #2 + } +} + 800691a: 4618 mov r0, r3 + 800691c: 3710 adds r7, #16 + 800691e: 46bd mov sp, r7 + 8006920: bd80 pop {r7, pc} + +08006922 : + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + 8006922: b580 push {r7, lr} + 8006924: b084 sub sp, #16 + 8006926: af00 add r7, sp, #0 + 8006928: 6078 str r0, [r7, #4] + 800692a: 460b mov r3, r1 + 800692c: 70fb strb r3, [r7, #3] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + 800692e: 687b ldr r3, [r7, #4] + 8006930: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006934: 60fb str r3, [r7, #12] + + /* Get the received data length */ + hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); + 8006936: 78fb ldrb r3, [r7, #3] + 8006938: 4619 mov r1, r3 + 800693a: 6878 ldr r0, [r7, #4] + 800693c: f003 fffe bl 800a93c + 8006940: 4602 mov r2, r0 + 8006942: 68fb ldr r3, [r7, #12] + 8006944: f8c3 220c str.w r2, [r3, #524] ; 0x20c + + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application Xfer */ + if (pdev->pClassData != NULL) + 8006948: 687b ldr r3, [r7, #4] + 800694a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 800694e: 2b00 cmp r3, #0 + 8006950: d00d beq.n 800696e + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + 8006952: 687b ldr r3, [r7, #4] + 8006954: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc + 8006958: 68db ldr r3, [r3, #12] + 800695a: 68fa ldr r2, [r7, #12] + 800695c: f8d2 0204 ldr.w r0, [r2, #516] ; 0x204 + 8006960: 68fa ldr r2, [r7, #12] + 8006962: f502 7203 add.w r2, r2, #524 ; 0x20c + 8006966: 4611 mov r1, r2 + 8006968: 4798 blx r3 + + return USBD_OK; + 800696a: 2300 movs r3, #0 + 800696c: e000 b.n 8006970 + } + else + { + return USBD_FAIL; + 800696e: 2302 movs r3, #2 + } +} + 8006970: 4618 mov r0, r3 + 8006972: 3710 adds r7, #16 + 8006974: 46bd mov sp, r7 + 8006976: bd80 pop {r7, pc} + +08006978 : + * Handle EP0 Rx Ready event + * @param pdev: device instance + * @retval status + */ +static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) +{ + 8006978: b580 push {r7, lr} + 800697a: b084 sub sp, #16 + 800697c: af00 add r7, sp, #0 + 800697e: 6078 str r0, [r7, #4] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + 8006980: 687b ldr r3, [r7, #4] + 8006982: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006986: 60fb str r3, [r7, #12] + + if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) + 8006988: 687b ldr r3, [r7, #4] + 800698a: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc + 800698e: 2b00 cmp r3, #0 + 8006990: d015 beq.n 80069be + 8006992: 68fb ldr r3, [r7, #12] + 8006994: f893 3200 ldrb.w r3, [r3, #512] ; 0x200 + 8006998: 2bff cmp r3, #255 ; 0xff + 800699a: d010 beq.n 80069be + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, + 800699c: 687b ldr r3, [r7, #4] + 800699e: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc + 80069a2: 689b ldr r3, [r3, #8] + 80069a4: 68fa ldr r2, [r7, #12] + 80069a6: f892 0200 ldrb.w r0, [r2, #512] ; 0x200 + (uint8_t *)(void *)hcdc->data, + 80069aa: 68f9 ldr r1, [r7, #12] + (uint16_t)hcdc->CmdLength); + 80069ac: 68fa ldr r2, [r7, #12] + 80069ae: f892 2201 ldrb.w r2, [r2, #513] ; 0x201 + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, + 80069b2: b292 uxth r2, r2 + 80069b4: 4798 blx r3 + hcdc->CmdOpCode = 0xFFU; + 80069b6: 68fb ldr r3, [r7, #12] + 80069b8: 22ff movs r2, #255 ; 0xff + 80069ba: f883 2200 strb.w r2, [r3, #512] ; 0x200 + + } + return USBD_OK; + 80069be: 2300 movs r3, #0 +} + 80069c0: 4618 mov r0, r3 + 80069c2: 3710 adds r7, #16 + 80069c4: 46bd mov sp, r7 + 80069c6: bd80 pop {r7, pc} + +080069c8 : + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) +{ + 80069c8: b480 push {r7} + 80069ca: b083 sub sp, #12 + 80069cc: af00 add r7, sp, #0 + 80069ce: 6078 str r0, [r7, #4] + *length = sizeof(USBD_CDC_CfgFSDesc); + 80069d0: 687b ldr r3, [r7, #4] + 80069d2: 2243 movs r2, #67 ; 0x43 + 80069d4: 801a strh r2, [r3, #0] + return USBD_CDC_CfgFSDesc; + 80069d6: 4b03 ldr r3, [pc, #12] ; (80069e4 ) +} + 80069d8: 4618 mov r0, r3 + 80069da: 370c adds r7, #12 + 80069dc: 46bd mov sp, r7 + 80069de: bc80 pop {r7} + 80069e0: 4770 bx lr + 80069e2: bf00 nop + 80069e4: 200000a8 .word 0x200000a8 + +080069e8 : + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) +{ + 80069e8: b480 push {r7} + 80069ea: b083 sub sp, #12 + 80069ec: af00 add r7, sp, #0 + 80069ee: 6078 str r0, [r7, #4] + *length = sizeof(USBD_CDC_CfgHSDesc); + 80069f0: 687b ldr r3, [r7, #4] + 80069f2: 2243 movs r2, #67 ; 0x43 + 80069f4: 801a strh r2, [r3, #0] + return USBD_CDC_CfgHSDesc; + 80069f6: 4b03 ldr r3, [pc, #12] ; (8006a04 ) +} + 80069f8: 4618 mov r0, r3 + 80069fa: 370c adds r7, #12 + 80069fc: 46bd mov sp, r7 + 80069fe: bc80 pop {r7} + 8006a00: 4770 bx lr + 8006a02: bf00 nop + 8006a04: 20000064 .word 0x20000064 + +08006a08 : + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) +{ + 8006a08: b480 push {r7} + 8006a0a: b083 sub sp, #12 + 8006a0c: af00 add r7, sp, #0 + 8006a0e: 6078 str r0, [r7, #4] + *length = sizeof(USBD_CDC_OtherSpeedCfgDesc); + 8006a10: 687b ldr r3, [r7, #4] + 8006a12: 2243 movs r2, #67 ; 0x43 + 8006a14: 801a strh r2, [r3, #0] + return USBD_CDC_OtherSpeedCfgDesc; + 8006a16: 4b03 ldr r3, [pc, #12] ; (8006a24 ) +} + 8006a18: 4618 mov r0, r3 + 8006a1a: 370c adds r7, #12 + 8006a1c: 46bd mov sp, r7 + 8006a1e: bc80 pop {r7} + 8006a20: 4770 bx lr + 8006a22: bf00 nop + 8006a24: 200000ec .word 0x200000ec + +08006a28 : +* return Device Qualifier descriptor +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) +{ + 8006a28: b480 push {r7} + 8006a2a: b083 sub sp, #12 + 8006a2c: af00 add r7, sp, #0 + 8006a2e: 6078 str r0, [r7, #4] + *length = sizeof(USBD_CDC_DeviceQualifierDesc); + 8006a30: 687b ldr r3, [r7, #4] + 8006a32: 220a movs r2, #10 + 8006a34: 801a strh r2, [r3, #0] + return USBD_CDC_DeviceQualifierDesc; + 8006a36: 4b03 ldr r3, [pc, #12] ; (8006a44 ) +} + 8006a38: 4618 mov r0, r3 + 8006a3a: 370c adds r7, #12 + 8006a3c: 46bd mov sp, r7 + 8006a3e: bc80 pop {r7} + 8006a40: 4770 bx lr + 8006a42: bf00 nop + 8006a44: 20000020 .word 0x20000020 + +08006a48 : + * @param fops: CD Interface callback + * @retval status + */ +uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops) +{ + 8006a48: b480 push {r7} + 8006a4a: b085 sub sp, #20 + 8006a4c: af00 add r7, sp, #0 + 8006a4e: 6078 str r0, [r7, #4] + 8006a50: 6039 str r1, [r7, #0] + uint8_t ret = USBD_FAIL; + 8006a52: 2302 movs r3, #2 + 8006a54: 73fb strb r3, [r7, #15] + + if (fops != NULL) + 8006a56: 683b ldr r3, [r7, #0] + 8006a58: 2b00 cmp r3, #0 + 8006a5a: d005 beq.n 8006a68 + { + pdev->pUserData = fops; + 8006a5c: 687b ldr r3, [r7, #4] + 8006a5e: 683a ldr r2, [r7, #0] + 8006a60: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc + ret = USBD_OK; + 8006a64: 2300 movs r3, #0 + 8006a66: 73fb strb r3, [r7, #15] + } + + return ret; + 8006a68: 7bfb ldrb r3, [r7, #15] +} + 8006a6a: 4618 mov r0, r3 + 8006a6c: 3714 adds r7, #20 + 8006a6e: 46bd mov sp, r7 + 8006a70: bc80 pop {r7} + 8006a72: 4770 bx lr + +08006a74 : + * @retval status + */ +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length) +{ + 8006a74: b480 push {r7} + 8006a76: b087 sub sp, #28 + 8006a78: af00 add r7, sp, #0 + 8006a7a: 60f8 str r0, [r7, #12] + 8006a7c: 60b9 str r1, [r7, #8] + 8006a7e: 4613 mov r3, r2 + 8006a80: 80fb strh r3, [r7, #6] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + 8006a82: 68fb ldr r3, [r7, #12] + 8006a84: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006a88: 617b str r3, [r7, #20] + + hcdc->TxBuffer = pbuff; + 8006a8a: 697b ldr r3, [r7, #20] + 8006a8c: 68ba ldr r2, [r7, #8] + 8006a8e: f8c3 2208 str.w r2, [r3, #520] ; 0x208 + hcdc->TxLength = length; + 8006a92: 88fa ldrh r2, [r7, #6] + 8006a94: 697b ldr r3, [r7, #20] + 8006a96: f8c3 2210 str.w r2, [r3, #528] ; 0x210 + + return USBD_OK; + 8006a9a: 2300 movs r3, #0 +} + 8006a9c: 4618 mov r0, r3 + 8006a9e: 371c adds r7, #28 + 8006aa0: 46bd mov sp, r7 + 8006aa2: bc80 pop {r7} + 8006aa4: 4770 bx lr + +08006aa6 : + * @param pbuff: Rx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff) +{ + 8006aa6: b480 push {r7} + 8006aa8: b085 sub sp, #20 + 8006aaa: af00 add r7, sp, #0 + 8006aac: 6078 str r0, [r7, #4] + 8006aae: 6039 str r1, [r7, #0] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + 8006ab0: 687b ldr r3, [r7, #4] + 8006ab2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006ab6: 60fb str r3, [r7, #12] + + hcdc->RxBuffer = pbuff; + 8006ab8: 68fb ldr r3, [r7, #12] + 8006aba: 683a ldr r2, [r7, #0] + 8006abc: f8c3 2204 str.w r2, [r3, #516] ; 0x204 + + return USBD_OK; + 8006ac0: 2300 movs r3, #0 +} + 8006ac2: 4618 mov r0, r3 + 8006ac4: 3714 adds r7, #20 + 8006ac6: 46bd mov sp, r7 + 8006ac8: bc80 pop {r7} + 8006aca: 4770 bx lr + +08006acc : + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + 8006acc: b580 push {r7, lr} + 8006ace: b084 sub sp, #16 + 8006ad0: af00 add r7, sp, #0 + 8006ad2: 6078 str r0, [r7, #4] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + 8006ad4: 687b ldr r3, [r7, #4] + 8006ad6: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006ada: 60fb str r3, [r7, #12] + + /* Suspend or Resume USB Out process */ + if (pdev->pClassData != NULL) + 8006adc: 687b ldr r3, [r7, #4] + 8006ade: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006ae2: 2b00 cmp r3, #0 + 8006ae4: d017 beq.n 8006b16 + { + if (pdev->dev_speed == USBD_SPEED_HIGH) + 8006ae6: 687b ldr r3, [r7, #4] + 8006ae8: 7c1b ldrb r3, [r3, #16] + 8006aea: 2b00 cmp r3, #0 + 8006aec: d109 bne.n 8006b02 + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + 8006aee: 68fb ldr r3, [r7, #12] + 8006af0: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 8006af4: f44f 7300 mov.w r3, #512 ; 0x200 + 8006af8: 2101 movs r1, #1 + 8006afa: 6878 ldr r0, [r7, #4] + 8006afc: f003 fefb bl 800a8f6 + 8006b00: e007 b.n 8006b12 + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + 8006b02: 68fb ldr r3, [r7, #12] + 8006b04: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 8006b08: 2340 movs r3, #64 ; 0x40 + 8006b0a: 2101 movs r1, #1 + 8006b0c: 6878 ldr r0, [r7, #4] + 8006b0e: f003 fef2 bl 800a8f6 + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + return USBD_OK; + 8006b12: 2300 movs r3, #0 + 8006b14: e000 b.n 8006b18 + } + else + { + return USBD_FAIL; + 8006b16: 2302 movs r3, #2 + } +} + 8006b18: 4618 mov r0, r3 + 8006b1a: 3710 adds r7, #16 + 8006b1c: 46bd mov sp, r7 + 8006b1e: bd80 pop {r7, pc} + +08006b20 : +* @param id: Low level core index +* @retval None +*/ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, + USBD_DescriptorsTypeDef *pdesc, uint8_t id) +{ + 8006b20: b580 push {r7, lr} + 8006b22: b084 sub sp, #16 + 8006b24: af00 add r7, sp, #0 + 8006b26: 60f8 str r0, [r7, #12] + 8006b28: 60b9 str r1, [r7, #8] + 8006b2a: 4613 mov r3, r2 + 8006b2c: 71fb strb r3, [r7, #7] + /* Check whether the USB Host handle is valid */ + if (pdev == NULL) + 8006b2e: 68fb ldr r3, [r7, #12] + 8006b30: 2b00 cmp r3, #0 + 8006b32: d101 bne.n 8006b38 + { +#if (USBD_DEBUG_LEVEL > 1U) + USBD_ErrLog("Invalid Device handle"); +#endif + return USBD_FAIL; + 8006b34: 2302 movs r3, #2 + 8006b36: e01a b.n 8006b6e + } + + /* Unlink previous class*/ + if (pdev->pClass != NULL) + 8006b38: 68fb ldr r3, [r7, #12] + 8006b3a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006b3e: 2b00 cmp r3, #0 + 8006b40: d003 beq.n 8006b4a + { + pdev->pClass = NULL; + 8006b42: 68fb ldr r3, [r7, #12] + 8006b44: 2200 movs r2, #0 + 8006b46: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4 + } + + /* Assign USBD Descriptors */ + if (pdesc != NULL) + 8006b4a: 68bb ldr r3, [r7, #8] + 8006b4c: 2b00 cmp r3, #0 + 8006b4e: d003 beq.n 8006b58 + { + pdev->pDesc = pdesc; + 8006b50: 68fb ldr r3, [r7, #12] + 8006b52: 68ba ldr r2, [r7, #8] + 8006b54: f8c3 22b0 str.w r2, [r3, #688] ; 0x2b0 + } + + /* Set Device initial State */ + pdev->dev_state = USBD_STATE_DEFAULT; + 8006b58: 68fb ldr r3, [r7, #12] + 8006b5a: 2201 movs r2, #1 + 8006b5c: f883 229c strb.w r2, [r3, #668] ; 0x29c + pdev->id = id; + 8006b60: 68fb ldr r3, [r7, #12] + 8006b62: 79fa ldrb r2, [r7, #7] + 8006b64: 701a strb r2, [r3, #0] + /* Initialize low level driver */ + USBD_LL_Init(pdev); + 8006b66: 68f8 ldr r0, [r7, #12] + 8006b68: f003 fd66 bl 800a638 + + return USBD_OK; + 8006b6c: 2300 movs r3, #0 +} + 8006b6e: 4618 mov r0, r3 + 8006b70: 3710 adds r7, #16 + 8006b72: 46bd mov sp, r7 + 8006b74: bd80 pop {r7, pc} + +08006b76 : + * @param pDevice : Device Handle + * @param pclass: Class handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) +{ + 8006b76: b480 push {r7} + 8006b78: b085 sub sp, #20 + 8006b7a: af00 add r7, sp, #0 + 8006b7c: 6078 str r0, [r7, #4] + 8006b7e: 6039 str r1, [r7, #0] + USBD_StatusTypeDef status = USBD_OK; + 8006b80: 2300 movs r3, #0 + 8006b82: 73fb strb r3, [r7, #15] + if (pclass != NULL) + 8006b84: 683b ldr r3, [r7, #0] + 8006b86: 2b00 cmp r3, #0 + 8006b88: d006 beq.n 8006b98 + { + /* link the class to the USB Device handle */ + pdev->pClass = pclass; + 8006b8a: 687b ldr r3, [r7, #4] + 8006b8c: 683a ldr r2, [r7, #0] + 8006b8e: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4 + status = USBD_OK; + 8006b92: 2300 movs r3, #0 + 8006b94: 73fb strb r3, [r7, #15] + 8006b96: e001 b.n 8006b9c + else + { +#if (USBD_DEBUG_LEVEL > 1U) + USBD_ErrLog("Invalid Class handle"); +#endif + status = USBD_FAIL; + 8006b98: 2302 movs r3, #2 + 8006b9a: 73fb strb r3, [r7, #15] + } + + return status; + 8006b9c: 7bfb ldrb r3, [r7, #15] +} + 8006b9e: 4618 mov r0, r3 + 8006ba0: 3714 adds r7, #20 + 8006ba2: 46bd mov sp, r7 + 8006ba4: bc80 pop {r7} + 8006ba6: 4770 bx lr + +08006ba8 : + * Start the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) +{ + 8006ba8: b580 push {r7, lr} + 8006baa: b082 sub sp, #8 + 8006bac: af00 add r7, sp, #0 + 8006bae: 6078 str r0, [r7, #4] + /* Start the low level driver */ + USBD_LL_Start(pdev); + 8006bb0: 6878 ldr r0, [r7, #4] + 8006bb2: f003 fd9b bl 800a6ec + + return USBD_OK; + 8006bb6: 2300 movs r3, #0 +} + 8006bb8: 4618 mov r0, r3 + 8006bba: 3708 adds r7, #8 + 8006bbc: 46bd mov sp, r7 + 8006bbe: bd80 pop {r7, pc} + +08006bc0 : +* Launch test mode process +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) +{ + 8006bc0: b480 push {r7} + 8006bc2: b083 sub sp, #12 + 8006bc4: af00 add r7, sp, #0 + 8006bc6: 6078 str r0, [r7, #4] + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + + return USBD_OK; + 8006bc8: 2300 movs r3, #0 +} + 8006bca: 4618 mov r0, r3 + 8006bcc: 370c adds r7, #12 + 8006bce: 46bd mov sp, r7 + 8006bd0: bc80 pop {r7} + 8006bd2: 4770 bx lr + +08006bd4 : +* @param cfgidx: configuration index +* @retval status +*/ + +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + 8006bd4: b580 push {r7, lr} + 8006bd6: b084 sub sp, #16 + 8006bd8: af00 add r7, sp, #0 + 8006bda: 6078 str r0, [r7, #4] + 8006bdc: 460b mov r3, r1 + 8006bde: 70fb strb r3, [r7, #3] + USBD_StatusTypeDef ret = USBD_FAIL; + 8006be0: 2302 movs r3, #2 + 8006be2: 73fb strb r3, [r7, #15] + + if (pdev->pClass != NULL) + 8006be4: 687b ldr r3, [r7, #4] + 8006be6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006bea: 2b00 cmp r3, #0 + 8006bec: d00c beq.n 8006c08 + { + /* Set configuration and Start the Class*/ + if (pdev->pClass->Init(pdev, cfgidx) == 0U) + 8006bee: 687b ldr r3, [r7, #4] + 8006bf0: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006bf4: 681b ldr r3, [r3, #0] + 8006bf6: 78fa ldrb r2, [r7, #3] + 8006bf8: 4611 mov r1, r2 + 8006bfa: 6878 ldr r0, [r7, #4] + 8006bfc: 4798 blx r3 + 8006bfe: 4603 mov r3, r0 + 8006c00: 2b00 cmp r3, #0 + 8006c02: d101 bne.n 8006c08 + { + ret = USBD_OK; + 8006c04: 2300 movs r3, #0 + 8006c06: 73fb strb r3, [r7, #15] + } + } + + return ret; + 8006c08: 7bfb ldrb r3, [r7, #15] +} + 8006c0a: 4618 mov r0, r3 + 8006c0c: 3710 adds r7, #16 + 8006c0e: 46bd mov sp, r7 + 8006c10: bd80 pop {r7, pc} + +08006c12 : +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status: USBD_StatusTypeDef +*/ +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + 8006c12: b580 push {r7, lr} + 8006c14: b082 sub sp, #8 + 8006c16: af00 add r7, sp, #0 + 8006c18: 6078 str r0, [r7, #4] + 8006c1a: 460b mov r3, r1 + 8006c1c: 70fb strb r3, [r7, #3] + /* Clear configuration and De-initialize the Class process*/ + pdev->pClass->DeInit(pdev, cfgidx); + 8006c1e: 687b ldr r3, [r7, #4] + 8006c20: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006c24: 685b ldr r3, [r3, #4] + 8006c26: 78fa ldrb r2, [r7, #3] + 8006c28: 4611 mov r1, r2 + 8006c2a: 6878 ldr r0, [r7, #4] + 8006c2c: 4798 blx r3 + + return USBD_OK; + 8006c2e: 2300 movs r3, #0 +} + 8006c30: 4618 mov r0, r3 + 8006c32: 3708 adds r7, #8 + 8006c34: 46bd mov sp, r7 + 8006c36: bd80 pop {r7, pc} + +08006c38 : +* Handle the setup stage +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) +{ + 8006c38: b580 push {r7, lr} + 8006c3a: b082 sub sp, #8 + 8006c3c: af00 add r7, sp, #0 + 8006c3e: 6078 str r0, [r7, #4] + 8006c40: 6039 str r1, [r7, #0] + USBD_ParseSetupRequest(&pdev->request, psetup); + 8006c42: 687b ldr r3, [r7, #4] + 8006c44: f503 732a add.w r3, r3, #680 ; 0x2a8 + 8006c48: 6839 ldr r1, [r7, #0] + 8006c4a: 4618 mov r0, r3 + 8006c4c: f000 feca bl 80079e4 + + pdev->ep0_state = USBD_EP0_SETUP; + 8006c50: 687b ldr r3, [r7, #4] + 8006c52: 2201 movs r2, #1 + 8006c54: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + + pdev->ep0_data_len = pdev->request.wLength; + 8006c58: 687b ldr r3, [r7, #4] + 8006c5a: f8b3 32ae ldrh.w r3, [r3, #686] ; 0x2ae + 8006c5e: 461a mov r2, r3 + 8006c60: 687b ldr r3, [r7, #4] + 8006c62: f8c3 2298 str.w r2, [r3, #664] ; 0x298 + + switch (pdev->request.bmRequest & 0x1FU) + 8006c66: 687b ldr r3, [r7, #4] + 8006c68: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 + 8006c6c: f003 031f and.w r3, r3, #31 + 8006c70: 2b01 cmp r3, #1 + 8006c72: d00c beq.n 8006c8e + 8006c74: 2b01 cmp r3, #1 + 8006c76: d302 bcc.n 8006c7e + 8006c78: 2b02 cmp r3, #2 + 8006c7a: d010 beq.n 8006c9e + 8006c7c: e017 b.n 8006cae + { + case USB_REQ_RECIPIENT_DEVICE: + USBD_StdDevReq(pdev, &pdev->request); + 8006c7e: 687b ldr r3, [r7, #4] + 8006c80: f503 732a add.w r3, r3, #680 ; 0x2a8 + 8006c84: 4619 mov r1, r3 + 8006c86: 6878 ldr r0, [r7, #4] + 8006c88: f000 f9ca bl 8007020 + break; + 8006c8c: e01a b.n 8006cc4 + + case USB_REQ_RECIPIENT_INTERFACE: + USBD_StdItfReq(pdev, &pdev->request); + 8006c8e: 687b ldr r3, [r7, #4] + 8006c90: f503 732a add.w r3, r3, #680 ; 0x2a8 + 8006c94: 4619 mov r1, r3 + 8006c96: 6878 ldr r0, [r7, #4] + 8006c98: f000 fa2c bl 80070f4 + break; + 8006c9c: e012 b.n 8006cc4 + + case USB_REQ_RECIPIENT_ENDPOINT: + USBD_StdEPReq(pdev, &pdev->request); + 8006c9e: 687b ldr r3, [r7, #4] + 8006ca0: f503 732a add.w r3, r3, #680 ; 0x2a8 + 8006ca4: 4619 mov r1, r3 + 8006ca6: 6878 ldr r0, [r7, #4] + 8006ca8: f000 fa6a bl 8007180 + break; + 8006cac: e00a b.n 8006cc4 + + default: + USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); + 8006cae: 687b ldr r3, [r7, #4] + 8006cb0: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 + 8006cb4: f023 037f bic.w r3, r3, #127 ; 0x7f + 8006cb8: b2db uxtb r3, r3 + 8006cba: 4619 mov r1, r3 + 8006cbc: 6878 ldr r0, [r7, #4] + 8006cbe: f003 fd75 bl 800a7ac + break; + 8006cc2: bf00 nop + } + + return USBD_OK; + 8006cc4: 2300 movs r3, #0 +} + 8006cc6: 4618 mov r0, r3 + 8006cc8: 3708 adds r7, #8 + 8006cca: 46bd mov sp, r7 + 8006ccc: bd80 pop {r7, pc} + +08006cce : +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, + uint8_t epnum, uint8_t *pdata) +{ + 8006cce: b580 push {r7, lr} + 8006cd0: b086 sub sp, #24 + 8006cd2: af00 add r7, sp, #0 + 8006cd4: 60f8 str r0, [r7, #12] + 8006cd6: 460b mov r3, r1 + 8006cd8: 607a str r2, [r7, #4] + 8006cda: 72fb strb r3, [r7, #11] + USBD_EndpointTypeDef *pep; + + if (epnum == 0U) + 8006cdc: 7afb ldrb r3, [r7, #11] + 8006cde: 2b00 cmp r3, #0 + 8006ce0: d14b bne.n 8006d7a + { + pep = &pdev->ep_out[0]; + 8006ce2: 68fb ldr r3, [r7, #12] + 8006ce4: f503 73aa add.w r3, r3, #340 ; 0x154 + 8006ce8: 617b str r3, [r7, #20] + + if (pdev->ep0_state == USBD_EP0_DATA_OUT) + 8006cea: 68fb ldr r3, [r7, #12] + 8006cec: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 + 8006cf0: 2b03 cmp r3, #3 + 8006cf2: d134 bne.n 8006d5e + { + if (pep->rem_length > pep->maxpacket) + 8006cf4: 697b ldr r3, [r7, #20] + 8006cf6: 68da ldr r2, [r3, #12] + 8006cf8: 697b ldr r3, [r7, #20] + 8006cfa: 691b ldr r3, [r3, #16] + 8006cfc: 429a cmp r2, r3 + 8006cfe: d919 bls.n 8006d34 + { + pep->rem_length -= pep->maxpacket; + 8006d00: 697b ldr r3, [r7, #20] + 8006d02: 68da ldr r2, [r3, #12] + 8006d04: 697b ldr r3, [r7, #20] + 8006d06: 691b ldr r3, [r3, #16] + 8006d08: 1ad2 subs r2, r2, r3 + 8006d0a: 697b ldr r3, [r7, #20] + 8006d0c: 60da str r2, [r3, #12] + + USBD_CtlContinueRx(pdev, pdata, + (uint16_t)MIN(pep->rem_length, pep->maxpacket)); + 8006d0e: 697b ldr r3, [r7, #20] + 8006d10: 68da ldr r2, [r3, #12] + 8006d12: 697b ldr r3, [r7, #20] + 8006d14: 691b ldr r3, [r3, #16] + USBD_CtlContinueRx(pdev, pdata, + 8006d16: 429a cmp r2, r3 + 8006d18: d203 bcs.n 8006d22 + (uint16_t)MIN(pep->rem_length, pep->maxpacket)); + 8006d1a: 697b ldr r3, [r7, #20] + 8006d1c: 68db ldr r3, [r3, #12] + USBD_CtlContinueRx(pdev, pdata, + 8006d1e: b29b uxth r3, r3 + 8006d20: e002 b.n 8006d28 + (uint16_t)MIN(pep->rem_length, pep->maxpacket)); + 8006d22: 697b ldr r3, [r7, #20] + 8006d24: 691b ldr r3, [r3, #16] + USBD_CtlContinueRx(pdev, pdata, + 8006d26: b29b uxth r3, r3 + 8006d28: 461a mov r2, r3 + 8006d2a: 6879 ldr r1, [r7, #4] + 8006d2c: 68f8 ldr r0, [r7, #12] + 8006d2e: f000 ff4b bl 8007bc8 + 8006d32: e038 b.n 8006da6 + } + else + { + if ((pdev->pClass->EP0_RxReady != NULL) && + 8006d34: 68fb ldr r3, [r7, #12] + 8006d36: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006d3a: 691b ldr r3, [r3, #16] + 8006d3c: 2b00 cmp r3, #0 + 8006d3e: d00a beq.n 8006d56 + (pdev->dev_state == USBD_STATE_CONFIGURED)) + 8006d40: 68fb ldr r3, [r7, #12] + 8006d42: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + if ((pdev->pClass->EP0_RxReady != NULL) && + 8006d46: 2b03 cmp r3, #3 + 8006d48: d105 bne.n 8006d56 + { + pdev->pClass->EP0_RxReady(pdev); + 8006d4a: 68fb ldr r3, [r7, #12] + 8006d4c: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006d50: 691b ldr r3, [r3, #16] + 8006d52: 68f8 ldr r0, [r7, #12] + 8006d54: 4798 blx r3 + } + USBD_CtlSendStatus(pdev); + 8006d56: 68f8 ldr r0, [r7, #12] + 8006d58: f000 ff48 bl 8007bec + 8006d5c: e023 b.n 8006da6 + } + } + else + { + if (pdev->ep0_state == USBD_EP0_STATUS_OUT) + 8006d5e: 68fb ldr r3, [r7, #12] + 8006d60: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 + 8006d64: 2b05 cmp r3, #5 + 8006d66: d11e bne.n 8006da6 + { + /* + * STATUS PHASE completed, update ep0_state to idle + */ + pdev->ep0_state = USBD_EP0_IDLE; + 8006d68: 68fb ldr r3, [r7, #12] + 8006d6a: 2200 movs r2, #0 + 8006d6c: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + USBD_LL_StallEP(pdev, 0U); + 8006d70: 2100 movs r1, #0 + 8006d72: 68f8 ldr r0, [r7, #12] + 8006d74: f003 fd1a bl 800a7ac + 8006d78: e015 b.n 8006da6 + } + } + } + else if ((pdev->pClass->DataOut != NULL) && + 8006d7a: 68fb ldr r3, [r7, #12] + 8006d7c: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006d80: 699b ldr r3, [r3, #24] + 8006d82: 2b00 cmp r3, #0 + 8006d84: d00d beq.n 8006da2 + (pdev->dev_state == USBD_STATE_CONFIGURED)) + 8006d86: 68fb ldr r3, [r7, #12] + 8006d88: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + else if ((pdev->pClass->DataOut != NULL) && + 8006d8c: 2b03 cmp r3, #3 + 8006d8e: d108 bne.n 8006da2 + { + pdev->pClass->DataOut(pdev, epnum); + 8006d90: 68fb ldr r3, [r7, #12] + 8006d92: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006d96: 699b ldr r3, [r3, #24] + 8006d98: 7afa ldrb r2, [r7, #11] + 8006d9a: 4611 mov r1, r2 + 8006d9c: 68f8 ldr r0, [r7, #12] + 8006d9e: 4798 blx r3 + 8006da0: e001 b.n 8006da6 + } + else + { + /* should never be in this condition */ + return USBD_FAIL; + 8006da2: 2302 movs r3, #2 + 8006da4: e000 b.n 8006da8 + } + + return USBD_OK; + 8006da6: 2300 movs r3, #0 +} + 8006da8: 4618 mov r0, r3 + 8006daa: 3718 adds r7, #24 + 8006dac: 46bd mov sp, r7 + 8006dae: bd80 pop {r7, pc} + +08006db0 : +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, + uint8_t epnum, uint8_t *pdata) +{ + 8006db0: b580 push {r7, lr} + 8006db2: b086 sub sp, #24 + 8006db4: af00 add r7, sp, #0 + 8006db6: 60f8 str r0, [r7, #12] + 8006db8: 460b mov r3, r1 + 8006dba: 607a str r2, [r7, #4] + 8006dbc: 72fb strb r3, [r7, #11] + USBD_EndpointTypeDef *pep; + + if (epnum == 0U) + 8006dbe: 7afb ldrb r3, [r7, #11] + 8006dc0: 2b00 cmp r3, #0 + 8006dc2: d17f bne.n 8006ec4 + { + pep = &pdev->ep_in[0]; + 8006dc4: 68fb ldr r3, [r7, #12] + 8006dc6: 3314 adds r3, #20 + 8006dc8: 617b str r3, [r7, #20] + + if (pdev->ep0_state == USBD_EP0_DATA_IN) + 8006dca: 68fb ldr r3, [r7, #12] + 8006dcc: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 + 8006dd0: 2b02 cmp r3, #2 + 8006dd2: d15c bne.n 8006e8e + { + if (pep->rem_length > pep->maxpacket) + 8006dd4: 697b ldr r3, [r7, #20] + 8006dd6: 68da ldr r2, [r3, #12] + 8006dd8: 697b ldr r3, [r7, #20] + 8006dda: 691b ldr r3, [r3, #16] + 8006ddc: 429a cmp r2, r3 + 8006dde: d915 bls.n 8006e0c + { + pep->rem_length -= pep->maxpacket; + 8006de0: 697b ldr r3, [r7, #20] + 8006de2: 68da ldr r2, [r3, #12] + 8006de4: 697b ldr r3, [r7, #20] + 8006de6: 691b ldr r3, [r3, #16] + 8006de8: 1ad2 subs r2, r2, r3 + 8006dea: 697b ldr r3, [r7, #20] + 8006dec: 60da str r2, [r3, #12] + + USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length); + 8006dee: 697b ldr r3, [r7, #20] + 8006df0: 68db ldr r3, [r3, #12] + 8006df2: b29b uxth r3, r3 + 8006df4: 461a mov r2, r3 + 8006df6: 6879 ldr r1, [r7, #4] + 8006df8: 68f8 ldr r0, [r7, #12] + 8006dfa: f000 feb5 bl 8007b68 + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + 8006dfe: 2300 movs r3, #0 + 8006e00: 2200 movs r2, #0 + 8006e02: 2100 movs r1, #0 + 8006e04: 68f8 ldr r0, [r7, #12] + 8006e06: f003 fd76 bl 800a8f6 + 8006e0a: e04e b.n 8006eaa + } + else + { + /* last packet is MPS multiple, so send ZLP packet */ + if ((pep->total_length % pep->maxpacket == 0U) && + 8006e0c: 697b ldr r3, [r7, #20] + 8006e0e: 689b ldr r3, [r3, #8] + 8006e10: 697a ldr r2, [r7, #20] + 8006e12: 6912 ldr r2, [r2, #16] + 8006e14: fbb3 f1f2 udiv r1, r3, r2 + 8006e18: fb02 f201 mul.w r2, r2, r1 + 8006e1c: 1a9b subs r3, r3, r2 + 8006e1e: 2b00 cmp r3, #0 + 8006e20: d11c bne.n 8006e5c + (pep->total_length >= pep->maxpacket) && + 8006e22: 697b ldr r3, [r7, #20] + 8006e24: 689a ldr r2, [r3, #8] + 8006e26: 697b ldr r3, [r7, #20] + 8006e28: 691b ldr r3, [r3, #16] + if ((pep->total_length % pep->maxpacket == 0U) && + 8006e2a: 429a cmp r2, r3 + 8006e2c: d316 bcc.n 8006e5c + (pep->total_length < pdev->ep0_data_len)) + 8006e2e: 697b ldr r3, [r7, #20] + 8006e30: 689a ldr r2, [r3, #8] + 8006e32: 68fb ldr r3, [r7, #12] + 8006e34: f8d3 3298 ldr.w r3, [r3, #664] ; 0x298 + (pep->total_length >= pep->maxpacket) && + 8006e38: 429a cmp r2, r3 + 8006e3a: d20f bcs.n 8006e5c + { + USBD_CtlContinueSendData(pdev, NULL, 0U); + 8006e3c: 2200 movs r2, #0 + 8006e3e: 2100 movs r1, #0 + 8006e40: 68f8 ldr r0, [r7, #12] + 8006e42: f000 fe91 bl 8007b68 + pdev->ep0_data_len = 0U; + 8006e46: 68fb ldr r3, [r7, #12] + 8006e48: 2200 movs r2, #0 + 8006e4a: f8c3 2298 str.w r2, [r3, #664] ; 0x298 + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + 8006e4e: 2300 movs r3, #0 + 8006e50: 2200 movs r2, #0 + 8006e52: 2100 movs r1, #0 + 8006e54: 68f8 ldr r0, [r7, #12] + 8006e56: f003 fd4e bl 800a8f6 + 8006e5a: e026 b.n 8006eaa + } + else + { + if ((pdev->pClass->EP0_TxSent != NULL) && + 8006e5c: 68fb ldr r3, [r7, #12] + 8006e5e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006e62: 68db ldr r3, [r3, #12] + 8006e64: 2b00 cmp r3, #0 + 8006e66: d00a beq.n 8006e7e + (pdev->dev_state == USBD_STATE_CONFIGURED)) + 8006e68: 68fb ldr r3, [r7, #12] + 8006e6a: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + if ((pdev->pClass->EP0_TxSent != NULL) && + 8006e6e: 2b03 cmp r3, #3 + 8006e70: d105 bne.n 8006e7e + { + pdev->pClass->EP0_TxSent(pdev); + 8006e72: 68fb ldr r3, [r7, #12] + 8006e74: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006e78: 68db ldr r3, [r3, #12] + 8006e7a: 68f8 ldr r0, [r7, #12] + 8006e7c: 4798 blx r3 + } + USBD_LL_StallEP(pdev, 0x80U); + 8006e7e: 2180 movs r1, #128 ; 0x80 + 8006e80: 68f8 ldr r0, [r7, #12] + 8006e82: f003 fc93 bl 800a7ac + USBD_CtlReceiveStatus(pdev); + 8006e86: 68f8 ldr r0, [r7, #12] + 8006e88: f000 fec3 bl 8007c12 + 8006e8c: e00d b.n 8006eaa + } + } + } + else + { + if ((pdev->ep0_state == USBD_EP0_STATUS_IN) || + 8006e8e: 68fb ldr r3, [r7, #12] + 8006e90: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 + 8006e94: 2b04 cmp r3, #4 + 8006e96: d004 beq.n 8006ea2 + (pdev->ep0_state == USBD_EP0_IDLE)) + 8006e98: 68fb ldr r3, [r7, #12] + 8006e9a: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 + if ((pdev->ep0_state == USBD_EP0_STATUS_IN) || + 8006e9e: 2b00 cmp r3, #0 + 8006ea0: d103 bne.n 8006eaa + { + USBD_LL_StallEP(pdev, 0x80U); + 8006ea2: 2180 movs r1, #128 ; 0x80 + 8006ea4: 68f8 ldr r0, [r7, #12] + 8006ea6: f003 fc81 bl 800a7ac + } + } + + if (pdev->dev_test_mode == 1U) + 8006eaa: 68fb ldr r3, [r7, #12] + 8006eac: f893 32a0 ldrb.w r3, [r3, #672] ; 0x2a0 + 8006eb0: 2b01 cmp r3, #1 + 8006eb2: d11d bne.n 8006ef0 + { + USBD_RunTestMode(pdev); + 8006eb4: 68f8 ldr r0, [r7, #12] + 8006eb6: f7ff fe83 bl 8006bc0 + pdev->dev_test_mode = 0U; + 8006eba: 68fb ldr r3, [r7, #12] + 8006ebc: 2200 movs r2, #0 + 8006ebe: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 + 8006ec2: e015 b.n 8006ef0 + } + } + else if ((pdev->pClass->DataIn != NULL) && + 8006ec4: 68fb ldr r3, [r7, #12] + 8006ec6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006eca: 695b ldr r3, [r3, #20] + 8006ecc: 2b00 cmp r3, #0 + 8006ece: d00d beq.n 8006eec + (pdev->dev_state == USBD_STATE_CONFIGURED)) + 8006ed0: 68fb ldr r3, [r7, #12] + 8006ed2: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + else if ((pdev->pClass->DataIn != NULL) && + 8006ed6: 2b03 cmp r3, #3 + 8006ed8: d108 bne.n 8006eec + { + pdev->pClass->DataIn(pdev, epnum); + 8006eda: 68fb ldr r3, [r7, #12] + 8006edc: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006ee0: 695b ldr r3, [r3, #20] + 8006ee2: 7afa ldrb r2, [r7, #11] + 8006ee4: 4611 mov r1, r2 + 8006ee6: 68f8 ldr r0, [r7, #12] + 8006ee8: 4798 blx r3 + 8006eea: e001 b.n 8006ef0 + } + else + { + /* should never be in this condition */ + return USBD_FAIL; + 8006eec: 2302 movs r3, #2 + 8006eee: e000 b.n 8006ef2 + } + + return USBD_OK; + 8006ef0: 2300 movs r3, #0 +} + 8006ef2: 4618 mov r0, r3 + 8006ef4: 3718 adds r7, #24 + 8006ef6: 46bd mov sp, r7 + 8006ef8: bd80 pop {r7, pc} + +08006efa : +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) +{ + 8006efa: b580 push {r7, lr} + 8006efc: b082 sub sp, #8 + 8006efe: af00 add r7, sp, #0 + 8006f00: 6078 str r0, [r7, #4] + /* Open EP0 OUT */ + USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + 8006f02: 2340 movs r3, #64 ; 0x40 + 8006f04: 2200 movs r2, #0 + 8006f06: 2100 movs r1, #0 + 8006f08: 6878 ldr r0, [r7, #4] + 8006f0a: f003 fc0a bl 800a722 + pdev->ep_out[0x00U & 0xFU].is_used = 1U; + 8006f0e: 687b ldr r3, [r7, #4] + 8006f10: 2201 movs r2, #1 + 8006f12: f8c3 2158 str.w r2, [r3, #344] ; 0x158 + + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + 8006f16: 687b ldr r3, [r7, #4] + 8006f18: 2240 movs r2, #64 ; 0x40 + 8006f1a: f8c3 2164 str.w r2, [r3, #356] ; 0x164 + + /* Open EP0 IN */ + USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + 8006f1e: 2340 movs r3, #64 ; 0x40 + 8006f20: 2200 movs r2, #0 + 8006f22: 2180 movs r1, #128 ; 0x80 + 8006f24: 6878 ldr r0, [r7, #4] + 8006f26: f003 fbfc bl 800a722 + pdev->ep_in[0x80U & 0xFU].is_used = 1U; + 8006f2a: 687b ldr r3, [r7, #4] + 8006f2c: 2201 movs r2, #1 + 8006f2e: 619a str r2, [r3, #24] + + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + 8006f30: 687b ldr r3, [r7, #4] + 8006f32: 2240 movs r2, #64 ; 0x40 + 8006f34: 625a str r2, [r3, #36] ; 0x24 + + /* Upon Reset call user call back */ + pdev->dev_state = USBD_STATE_DEFAULT; + 8006f36: 687b ldr r3, [r7, #4] + 8006f38: 2201 movs r2, #1 + 8006f3a: f883 229c strb.w r2, [r3, #668] ; 0x29c + pdev->ep0_state = USBD_EP0_IDLE; + 8006f3e: 687b ldr r3, [r7, #4] + 8006f40: 2200 movs r2, #0 + 8006f42: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + pdev->dev_config = 0U; + 8006f46: 687b ldr r3, [r7, #4] + 8006f48: 2200 movs r2, #0 + 8006f4a: 605a str r2, [r3, #4] + pdev->dev_remote_wakeup = 0U; + 8006f4c: 687b ldr r3, [r7, #4] + 8006f4e: 2200 movs r2, #0 + 8006f50: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 + + if (pdev->pClassData) + 8006f54: 687b ldr r3, [r7, #4] + 8006f56: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8006f5a: 2b00 cmp r3, #0 + 8006f5c: d009 beq.n 8006f72 + { + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + 8006f5e: 687b ldr r3, [r7, #4] + 8006f60: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8006f64: 685b ldr r3, [r3, #4] + 8006f66: 687a ldr r2, [r7, #4] + 8006f68: 6852 ldr r2, [r2, #4] + 8006f6a: b2d2 uxtb r2, r2 + 8006f6c: 4611 mov r1, r2 + 8006f6e: 6878 ldr r0, [r7, #4] + 8006f70: 4798 blx r3 + } + + return USBD_OK; + 8006f72: 2300 movs r3, #0 +} + 8006f74: 4618 mov r0, r3 + 8006f76: 3708 adds r7, #8 + 8006f78: 46bd mov sp, r7 + 8006f7a: bd80 pop {r7, pc} + +08006f7c : +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, + USBD_SpeedTypeDef speed) +{ + 8006f7c: b480 push {r7} + 8006f7e: b083 sub sp, #12 + 8006f80: af00 add r7, sp, #0 + 8006f82: 6078 str r0, [r7, #4] + 8006f84: 460b mov r3, r1 + 8006f86: 70fb strb r3, [r7, #3] + pdev->dev_speed = speed; + 8006f88: 687b ldr r3, [r7, #4] + 8006f8a: 78fa ldrb r2, [r7, #3] + 8006f8c: 741a strb r2, [r3, #16] + + return USBD_OK; + 8006f8e: 2300 movs r3, #0 +} + 8006f90: 4618 mov r0, r3 + 8006f92: 370c adds r7, #12 + 8006f94: 46bd mov sp, r7 + 8006f96: bc80 pop {r7} + 8006f98: 4770 bx lr + +08006f9a : +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) +{ + 8006f9a: b480 push {r7} + 8006f9c: b083 sub sp, #12 + 8006f9e: af00 add r7, sp, #0 + 8006fa0: 6078 str r0, [r7, #4] + pdev->dev_old_state = pdev->dev_state; + 8006fa2: 687b ldr r3, [r7, #4] + 8006fa4: f893 229c ldrb.w r2, [r3, #668] ; 0x29c + 8006fa8: 687b ldr r3, [r7, #4] + 8006faa: f883 229d strb.w r2, [r3, #669] ; 0x29d + pdev->dev_state = USBD_STATE_SUSPENDED; + 8006fae: 687b ldr r3, [r7, #4] + 8006fb0: 2204 movs r2, #4 + 8006fb2: f883 229c strb.w r2, [r3, #668] ; 0x29c + + return USBD_OK; + 8006fb6: 2300 movs r3, #0 +} + 8006fb8: 4618 mov r0, r3 + 8006fba: 370c adds r7, #12 + 8006fbc: 46bd mov sp, r7 + 8006fbe: bc80 pop {r7} + 8006fc0: 4770 bx lr + +08006fc2 : +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) +{ + 8006fc2: b480 push {r7} + 8006fc4: b083 sub sp, #12 + 8006fc6: af00 add r7, sp, #0 + 8006fc8: 6078 str r0, [r7, #4] + if (pdev->dev_state == USBD_STATE_SUSPENDED) + 8006fca: 687b ldr r3, [r7, #4] + 8006fcc: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8006fd0: 2b04 cmp r3, #4 + 8006fd2: d105 bne.n 8006fe0 + { + pdev->dev_state = pdev->dev_old_state; + 8006fd4: 687b ldr r3, [r7, #4] + 8006fd6: f893 229d ldrb.w r2, [r3, #669] ; 0x29d + 8006fda: 687b ldr r3, [r7, #4] + 8006fdc: f883 229c strb.w r2, [r3, #668] ; 0x29c + } + + return USBD_OK; + 8006fe0: 2300 movs r3, #0 +} + 8006fe2: 4618 mov r0, r3 + 8006fe4: 370c adds r7, #12 + 8006fe6: 46bd mov sp, r7 + 8006fe8: bc80 pop {r7} + 8006fea: 4770 bx lr + +08006fec : +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) +{ + 8006fec: b580 push {r7, lr} + 8006fee: b082 sub sp, #8 + 8006ff0: af00 add r7, sp, #0 + 8006ff2: 6078 str r0, [r7, #4] + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 8006ff4: 687b ldr r3, [r7, #4] + 8006ff6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8006ffa: 2b03 cmp r3, #3 + 8006ffc: d10b bne.n 8007016 + { + if (pdev->pClass->SOF != NULL) + 8006ffe: 687b ldr r3, [r7, #4] + 8007000: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8007004: 69db ldr r3, [r3, #28] + 8007006: 2b00 cmp r3, #0 + 8007008: d005 beq.n 8007016 + { + pdev->pClass->SOF(pdev); + 800700a: 687b ldr r3, [r7, #4] + 800700c: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8007010: 69db ldr r3, [r3, #28] + 8007012: 6878 ldr r0, [r7, #4] + 8007014: 4798 blx r3 + } + } + + return USBD_OK; + 8007016: 2300 movs r3, #0 +} + 8007018: 4618 mov r0, r3 + 800701a: 3708 adds r7, #8 + 800701c: 46bd mov sp, r7 + 800701e: bd80 pop {r7, pc} + +08007020 : +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 8007020: b580 push {r7, lr} + 8007022: b084 sub sp, #16 + 8007024: af00 add r7, sp, #0 + 8007026: 6078 str r0, [r7, #4] + 8007028: 6039 str r1, [r7, #0] + USBD_StatusTypeDef ret = USBD_OK; + 800702a: 2300 movs r3, #0 + 800702c: 73fb strb r3, [r7, #15] + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + 800702e: 683b ldr r3, [r7, #0] + 8007030: 781b ldrb r3, [r3, #0] + 8007032: f003 0360 and.w r3, r3, #96 ; 0x60 + 8007036: 2b20 cmp r3, #32 + 8007038: d004 beq.n 8007044 + 800703a: 2b40 cmp r3, #64 ; 0x40 + 800703c: d002 beq.n 8007044 + 800703e: 2b00 cmp r3, #0 + 8007040: d008 beq.n 8007054 + 8007042: e04c b.n 80070de + { + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + pdev->pClass->Setup(pdev, req); + 8007044: 687b ldr r3, [r7, #4] + 8007046: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 800704a: 689b ldr r3, [r3, #8] + 800704c: 6839 ldr r1, [r7, #0] + 800704e: 6878 ldr r0, [r7, #4] + 8007050: 4798 blx r3 + break; + 8007052: e049 b.n 80070e8 + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + 8007054: 683b ldr r3, [r7, #0] + 8007056: 785b ldrb r3, [r3, #1] + 8007058: 2b09 cmp r3, #9 + 800705a: d83a bhi.n 80070d2 + 800705c: a201 add r2, pc, #4 ; (adr r2, 8007064 ) + 800705e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8007062: bf00 nop + 8007064: 080070b5 .word 0x080070b5 + 8007068: 080070c9 .word 0x080070c9 + 800706c: 080070d3 .word 0x080070d3 + 8007070: 080070bf .word 0x080070bf + 8007074: 080070d3 .word 0x080070d3 + 8007078: 08007097 .word 0x08007097 + 800707c: 0800708d .word 0x0800708d + 8007080: 080070d3 .word 0x080070d3 + 8007084: 080070ab .word 0x080070ab + 8007088: 080070a1 .word 0x080070a1 + { + case USB_REQ_GET_DESCRIPTOR: + USBD_GetDescriptor(pdev, req); + 800708c: 6839 ldr r1, [r7, #0] + 800708e: 6878 ldr r0, [r7, #4] + 8007090: f000 f9d4 bl 800743c + break; + 8007094: e022 b.n 80070dc + + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + 8007096: 6839 ldr r1, [r7, #0] + 8007098: 6878 ldr r0, [r7, #4] + 800709a: f000 fb37 bl 800770c + break; + 800709e: e01d b.n 80070dc + + case USB_REQ_SET_CONFIGURATION: + USBD_SetConfig(pdev, req); + 80070a0: 6839 ldr r1, [r7, #0] + 80070a2: 6878 ldr r0, [r7, #4] + 80070a4: f000 fb74 bl 8007790 + break; + 80070a8: e018 b.n 80070dc + + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig(pdev, req); + 80070aa: 6839 ldr r1, [r7, #0] + 80070ac: 6878 ldr r0, [r7, #4] + 80070ae: f000 fbfd bl 80078ac + break; + 80070b2: e013 b.n 80070dc + + case USB_REQ_GET_STATUS: + USBD_GetStatus(pdev, req); + 80070b4: 6839 ldr r1, [r7, #0] + 80070b6: 6878 ldr r0, [r7, #4] + 80070b8: f000 fc2c bl 8007914 + break; + 80070bc: e00e b.n 80070dc + + case USB_REQ_SET_FEATURE: + USBD_SetFeature(pdev, req); + 80070be: 6839 ldr r1, [r7, #0] + 80070c0: 6878 ldr r0, [r7, #4] + 80070c2: f000 fc5a bl 800797a + break; + 80070c6: e009 b.n 80070dc + + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature(pdev, req); + 80070c8: 6839 ldr r1, [r7, #0] + 80070ca: 6878 ldr r0, [r7, #4] + 80070cc: f000 fc69 bl 80079a2 + break; + 80070d0: e004 b.n 80070dc + + default: + USBD_CtlError(pdev, req); + 80070d2: 6839 ldr r1, [r7, #0] + 80070d4: 6878 ldr r0, [r7, #4] + 80070d6: f000 fcc1 bl 8007a5c + break; + 80070da: bf00 nop + } + break; + 80070dc: e004 b.n 80070e8 + + default: + USBD_CtlError(pdev, req); + 80070de: 6839 ldr r1, [r7, #0] + 80070e0: 6878 ldr r0, [r7, #4] + 80070e2: f000 fcbb bl 8007a5c + break; + 80070e6: bf00 nop + } + + return ret; + 80070e8: 7bfb ldrb r3, [r7, #15] +} + 80070ea: 4618 mov r0, r3 + 80070ec: 3710 adds r7, #16 + 80070ee: 46bd mov sp, r7 + 80070f0: bd80 pop {r7, pc} + 80070f2: bf00 nop + +080070f4 : +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 80070f4: b580 push {r7, lr} + 80070f6: b084 sub sp, #16 + 80070f8: af00 add r7, sp, #0 + 80070fa: 6078 str r0, [r7, #4] + 80070fc: 6039 str r1, [r7, #0] + USBD_StatusTypeDef ret = USBD_OK; + 80070fe: 2300 movs r3, #0 + 8007100: 73fb strb r3, [r7, #15] + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + 8007102: 683b ldr r3, [r7, #0] + 8007104: 781b ldrb r3, [r3, #0] + 8007106: f003 0360 and.w r3, r3, #96 ; 0x60 + 800710a: 2b20 cmp r3, #32 + 800710c: d003 beq.n 8007116 + 800710e: 2b40 cmp r3, #64 ; 0x40 + 8007110: d001 beq.n 8007116 + 8007112: 2b00 cmp r3, #0 + 8007114: d12a bne.n 800716c + { + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + case USB_REQ_TYPE_STANDARD: + switch (pdev->dev_state) + 8007116: 687b ldr r3, [r7, #4] + 8007118: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 800711c: 3b01 subs r3, #1 + 800711e: 2b02 cmp r3, #2 + 8007120: d81d bhi.n 800715e + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + + if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) + 8007122: 683b ldr r3, [r7, #0] + 8007124: 889b ldrh r3, [r3, #4] + 8007126: b2db uxtb r3, r3 + 8007128: 2b01 cmp r3, #1 + 800712a: d813 bhi.n 8007154 + { + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + 800712c: 687b ldr r3, [r7, #4] + 800712e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8007132: 689b ldr r3, [r3, #8] + 8007134: 6839 ldr r1, [r7, #0] + 8007136: 6878 ldr r0, [r7, #4] + 8007138: 4798 blx r3 + 800713a: 4603 mov r3, r0 + 800713c: 73fb strb r3, [r7, #15] + + if ((req->wLength == 0U) && (ret == USBD_OK)) + 800713e: 683b ldr r3, [r7, #0] + 8007140: 88db ldrh r3, [r3, #6] + 8007142: 2b00 cmp r3, #0 + 8007144: d110 bne.n 8007168 + 8007146: 7bfb ldrb r3, [r7, #15] + 8007148: 2b00 cmp r3, #0 + 800714a: d10d bne.n 8007168 + { + USBD_CtlSendStatus(pdev); + 800714c: 6878 ldr r0, [r7, #4] + 800714e: f000 fd4d bl 8007bec + } + else + { + USBD_CtlError(pdev, req); + } + break; + 8007152: e009 b.n 8007168 + USBD_CtlError(pdev, req); + 8007154: 6839 ldr r1, [r7, #0] + 8007156: 6878 ldr r0, [r7, #4] + 8007158: f000 fc80 bl 8007a5c + break; + 800715c: e004 b.n 8007168 + + default: + USBD_CtlError(pdev, req); + 800715e: 6839 ldr r1, [r7, #0] + 8007160: 6878 ldr r0, [r7, #4] + 8007162: f000 fc7b bl 8007a5c + break; + 8007166: e000 b.n 800716a + break; + 8007168: bf00 nop + } + break; + 800716a: e004 b.n 8007176 + + default: + USBD_CtlError(pdev, req); + 800716c: 6839 ldr r1, [r7, #0] + 800716e: 6878 ldr r0, [r7, #4] + 8007170: f000 fc74 bl 8007a5c + break; + 8007174: bf00 nop + } + + return USBD_OK; + 8007176: 2300 movs r3, #0 +} + 8007178: 4618 mov r0, r3 + 800717a: 3710 adds r7, #16 + 800717c: 46bd mov sp, r7 + 800717e: bd80 pop {r7, pc} + +08007180 : +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 8007180: b580 push {r7, lr} + 8007182: b084 sub sp, #16 + 8007184: af00 add r7, sp, #0 + 8007186: 6078 str r0, [r7, #4] + 8007188: 6039 str r1, [r7, #0] + USBD_EndpointTypeDef *pep; + uint8_t ep_addr; + USBD_StatusTypeDef ret = USBD_OK; + 800718a: 2300 movs r3, #0 + 800718c: 73fb strb r3, [r7, #15] + ep_addr = LOBYTE(req->wIndex); + 800718e: 683b ldr r3, [r7, #0] + 8007190: 889b ldrh r3, [r3, #4] + 8007192: 73bb strb r3, [r7, #14] + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + 8007194: 683b ldr r3, [r7, #0] + 8007196: 781b ldrb r3, [r3, #0] + 8007198: f003 0360 and.w r3, r3, #96 ; 0x60 + 800719c: 2b20 cmp r3, #32 + 800719e: d004 beq.n 80071aa + 80071a0: 2b40 cmp r3, #64 ; 0x40 + 80071a2: d002 beq.n 80071aa + 80071a4: 2b00 cmp r3, #0 + 80071a6: d008 beq.n 80071ba + 80071a8: e13d b.n 8007426 + { + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + pdev->pClass->Setup(pdev, req); + 80071aa: 687b ldr r3, [r7, #4] + 80071ac: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80071b0: 689b ldr r3, [r3, #8] + 80071b2: 6839 ldr r1, [r7, #0] + 80071b4: 6878 ldr r0, [r7, #4] + 80071b6: 4798 blx r3 + break; + 80071b8: e13a b.n 8007430 + + case USB_REQ_TYPE_STANDARD: + /* Check if it is a class request */ + if ((req->bmRequest & 0x60U) == 0x20U) + 80071ba: 683b ldr r3, [r7, #0] + 80071bc: 781b ldrb r3, [r3, #0] + 80071be: f003 0360 and.w r3, r3, #96 ; 0x60 + 80071c2: 2b20 cmp r3, #32 + 80071c4: d10a bne.n 80071dc + { + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + 80071c6: 687b ldr r3, [r7, #4] + 80071c8: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80071cc: 689b ldr r3, [r3, #8] + 80071ce: 6839 ldr r1, [r7, #0] + 80071d0: 6878 ldr r0, [r7, #4] + 80071d2: 4798 blx r3 + 80071d4: 4603 mov r3, r0 + 80071d6: 73fb strb r3, [r7, #15] + + return ret; + 80071d8: 7bfb ldrb r3, [r7, #15] + 80071da: e12a b.n 8007432 + } + + switch (req->bRequest) + 80071dc: 683b ldr r3, [r7, #0] + 80071de: 785b ldrb r3, [r3, #1] + 80071e0: 2b01 cmp r3, #1 + 80071e2: d03e beq.n 8007262 + 80071e4: 2b03 cmp r3, #3 + 80071e6: d002 beq.n 80071ee + 80071e8: 2b00 cmp r3, #0 + 80071ea: d070 beq.n 80072ce + 80071ec: e115 b.n 800741a + { + case USB_REQ_SET_FEATURE: + switch (pdev->dev_state) + 80071ee: 687b ldr r3, [r7, #4] + 80071f0: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 80071f4: 2b02 cmp r3, #2 + 80071f6: d002 beq.n 80071fe + 80071f8: 2b03 cmp r3, #3 + 80071fa: d015 beq.n 8007228 + 80071fc: e02b b.n 8007256 + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + 80071fe: 7bbb ldrb r3, [r7, #14] + 8007200: 2b00 cmp r3, #0 + 8007202: d00c beq.n 800721e + 8007204: 7bbb ldrb r3, [r7, #14] + 8007206: 2b80 cmp r3, #128 ; 0x80 + 8007208: d009 beq.n 800721e + { + USBD_LL_StallEP(pdev, ep_addr); + 800720a: 7bbb ldrb r3, [r7, #14] + 800720c: 4619 mov r1, r3 + 800720e: 6878 ldr r0, [r7, #4] + 8007210: f003 facc bl 800a7ac + USBD_LL_StallEP(pdev, 0x80U); + 8007214: 2180 movs r1, #128 ; 0x80 + 8007216: 6878 ldr r0, [r7, #4] + 8007218: f003 fac8 bl 800a7ac + } + else + { + USBD_CtlError(pdev, req); + } + break; + 800721c: e020 b.n 8007260 + USBD_CtlError(pdev, req); + 800721e: 6839 ldr r1, [r7, #0] + 8007220: 6878 ldr r0, [r7, #4] + 8007222: f000 fc1b bl 8007a5c + break; + 8007226: e01b b.n 8007260 + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + 8007228: 683b ldr r3, [r7, #0] + 800722a: 885b ldrh r3, [r3, #2] + 800722c: 2b00 cmp r3, #0 + 800722e: d10e bne.n 800724e + { + if ((ep_addr != 0x00U) && + 8007230: 7bbb ldrb r3, [r7, #14] + 8007232: 2b00 cmp r3, #0 + 8007234: d00b beq.n 800724e + 8007236: 7bbb ldrb r3, [r7, #14] + 8007238: 2b80 cmp r3, #128 ; 0x80 + 800723a: d008 beq.n 800724e + (ep_addr != 0x80U) && (req->wLength == 0x00U)) + 800723c: 683b ldr r3, [r7, #0] + 800723e: 88db ldrh r3, [r3, #6] + 8007240: 2b00 cmp r3, #0 + 8007242: d104 bne.n 800724e + { + USBD_LL_StallEP(pdev, ep_addr); + 8007244: 7bbb ldrb r3, [r7, #14] + 8007246: 4619 mov r1, r3 + 8007248: 6878 ldr r0, [r7, #4] + 800724a: f003 faaf bl 800a7ac + } + } + USBD_CtlSendStatus(pdev); + 800724e: 6878 ldr r0, [r7, #4] + 8007250: f000 fccc bl 8007bec + + break; + 8007254: e004 b.n 8007260 + + default: + USBD_CtlError(pdev, req); + 8007256: 6839 ldr r1, [r7, #0] + 8007258: 6878 ldr r0, [r7, #4] + 800725a: f000 fbff bl 8007a5c + break; + 800725e: bf00 nop + } + break; + 8007260: e0e0 b.n 8007424 + + case USB_REQ_CLEAR_FEATURE: + + switch (pdev->dev_state) + 8007262: 687b ldr r3, [r7, #4] + 8007264: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8007268: 2b02 cmp r3, #2 + 800726a: d002 beq.n 8007272 + 800726c: 2b03 cmp r3, #3 + 800726e: d015 beq.n 800729c + 8007270: e026 b.n 80072c0 + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + 8007272: 7bbb ldrb r3, [r7, #14] + 8007274: 2b00 cmp r3, #0 + 8007276: d00c beq.n 8007292 + 8007278: 7bbb ldrb r3, [r7, #14] + 800727a: 2b80 cmp r3, #128 ; 0x80 + 800727c: d009 beq.n 8007292 + { + USBD_LL_StallEP(pdev, ep_addr); + 800727e: 7bbb ldrb r3, [r7, #14] + 8007280: 4619 mov r1, r3 + 8007282: 6878 ldr r0, [r7, #4] + 8007284: f003 fa92 bl 800a7ac + USBD_LL_StallEP(pdev, 0x80U); + 8007288: 2180 movs r1, #128 ; 0x80 + 800728a: 6878 ldr r0, [r7, #4] + 800728c: f003 fa8e bl 800a7ac + } + else + { + USBD_CtlError(pdev, req); + } + break; + 8007290: e01c b.n 80072cc + USBD_CtlError(pdev, req); + 8007292: 6839 ldr r1, [r7, #0] + 8007294: 6878 ldr r0, [r7, #4] + 8007296: f000 fbe1 bl 8007a5c + break; + 800729a: e017 b.n 80072cc + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + 800729c: 683b ldr r3, [r7, #0] + 800729e: 885b ldrh r3, [r3, #2] + 80072a0: 2b00 cmp r3, #0 + 80072a2: d112 bne.n 80072ca + { + if ((ep_addr & 0x7FU) != 0x00U) + 80072a4: 7bbb ldrb r3, [r7, #14] + 80072a6: f003 037f and.w r3, r3, #127 ; 0x7f + 80072aa: 2b00 cmp r3, #0 + 80072ac: d004 beq.n 80072b8 + { + USBD_LL_ClearStallEP(pdev, ep_addr); + 80072ae: 7bbb ldrb r3, [r7, #14] + 80072b0: 4619 mov r1, r3 + 80072b2: 6878 ldr r0, [r7, #4] + 80072b4: f003 fa99 bl 800a7ea + } + USBD_CtlSendStatus(pdev); + 80072b8: 6878 ldr r0, [r7, #4] + 80072ba: f000 fc97 bl 8007bec + } + break; + 80072be: e004 b.n 80072ca + + default: + USBD_CtlError(pdev, req); + 80072c0: 6839 ldr r1, [r7, #0] + 80072c2: 6878 ldr r0, [r7, #4] + 80072c4: f000 fbca bl 8007a5c + break; + 80072c8: e000 b.n 80072cc + break; + 80072ca: bf00 nop + } + break; + 80072cc: e0aa b.n 8007424 + + case USB_REQ_GET_STATUS: + switch (pdev->dev_state) + 80072ce: 687b ldr r3, [r7, #4] + 80072d0: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 80072d4: 2b02 cmp r3, #2 + 80072d6: d002 beq.n 80072de + 80072d8: 2b03 cmp r3, #3 + 80072da: d032 beq.n 8007342 + 80072dc: e097 b.n 800740e + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + 80072de: 7bbb ldrb r3, [r7, #14] + 80072e0: 2b00 cmp r3, #0 + 80072e2: d007 beq.n 80072f4 + 80072e4: 7bbb ldrb r3, [r7, #14] + 80072e6: 2b80 cmp r3, #128 ; 0x80 + 80072e8: d004 beq.n 80072f4 + { + USBD_CtlError(pdev, req); + 80072ea: 6839 ldr r1, [r7, #0] + 80072ec: 6878 ldr r0, [r7, #4] + 80072ee: f000 fbb5 bl 8007a5c + break; + 80072f2: e091 b.n 8007418 + } + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + 80072f4: f997 300e ldrsb.w r3, [r7, #14] + 80072f8: 2b00 cmp r3, #0 + 80072fa: da0b bge.n 8007314 + 80072fc: 7bbb ldrb r3, [r7, #14] + 80072fe: f003 027f and.w r2, r3, #127 ; 0x7f + 8007302: 4613 mov r3, r2 + 8007304: 009b lsls r3, r3, #2 + 8007306: 4413 add r3, r2 + 8007308: 009b lsls r3, r3, #2 + 800730a: 3310 adds r3, #16 + 800730c: 687a ldr r2, [r7, #4] + 800730e: 4413 add r3, r2 + 8007310: 3304 adds r3, #4 + 8007312: e00b b.n 800732c + &pdev->ep_out[ep_addr & 0x7FU]; + 8007314: 7bbb ldrb r3, [r7, #14] + 8007316: f003 027f and.w r2, r3, #127 ; 0x7f + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + 800731a: 4613 mov r3, r2 + 800731c: 009b lsls r3, r3, #2 + 800731e: 4413 add r3, r2 + 8007320: 009b lsls r3, r3, #2 + 8007322: f503 73a8 add.w r3, r3, #336 ; 0x150 + 8007326: 687a ldr r2, [r7, #4] + 8007328: 4413 add r3, r2 + 800732a: 3304 adds r3, #4 + 800732c: 60bb str r3, [r7, #8] + + pep->status = 0x0000U; + 800732e: 68bb ldr r3, [r7, #8] + 8007330: 2200 movs r2, #0 + 8007332: 601a str r2, [r3, #0] + + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); + 8007334: 68bb ldr r3, [r7, #8] + 8007336: 2202 movs r2, #2 + 8007338: 4619 mov r1, r3 + 800733a: 6878 ldr r0, [r7, #4] + 800733c: f000 fbf8 bl 8007b30 + break; + 8007340: e06a b.n 8007418 + + case USBD_STATE_CONFIGURED: + if ((ep_addr & 0x80U) == 0x80U) + 8007342: f997 300e ldrsb.w r3, [r7, #14] + 8007346: 2b00 cmp r3, #0 + 8007348: da11 bge.n 800736e + { + if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) + 800734a: 7bbb ldrb r3, [r7, #14] + 800734c: f003 020f and.w r2, r3, #15 + 8007350: 6879 ldr r1, [r7, #4] + 8007352: 4613 mov r3, r2 + 8007354: 009b lsls r3, r3, #2 + 8007356: 4413 add r3, r2 + 8007358: 009b lsls r3, r3, #2 + 800735a: 440b add r3, r1 + 800735c: 3318 adds r3, #24 + 800735e: 681b ldr r3, [r3, #0] + 8007360: 2b00 cmp r3, #0 + 8007362: d117 bne.n 8007394 + { + USBD_CtlError(pdev, req); + 8007364: 6839 ldr r1, [r7, #0] + 8007366: 6878 ldr r0, [r7, #4] + 8007368: f000 fb78 bl 8007a5c + break; + 800736c: e054 b.n 8007418 + } + } + else + { + if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) + 800736e: 7bbb ldrb r3, [r7, #14] + 8007370: f003 020f and.w r2, r3, #15 + 8007374: 6879 ldr r1, [r7, #4] + 8007376: 4613 mov r3, r2 + 8007378: 009b lsls r3, r3, #2 + 800737a: 4413 add r3, r2 + 800737c: 009b lsls r3, r3, #2 + 800737e: 440b add r3, r1 + 8007380: f503 73ac add.w r3, r3, #344 ; 0x158 + 8007384: 681b ldr r3, [r3, #0] + 8007386: 2b00 cmp r3, #0 + 8007388: d104 bne.n 8007394 + { + USBD_CtlError(pdev, req); + 800738a: 6839 ldr r1, [r7, #0] + 800738c: 6878 ldr r0, [r7, #4] + 800738e: f000 fb65 bl 8007a5c + break; + 8007392: e041 b.n 8007418 + } + } + + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + 8007394: f997 300e ldrsb.w r3, [r7, #14] + 8007398: 2b00 cmp r3, #0 + 800739a: da0b bge.n 80073b4 + 800739c: 7bbb ldrb r3, [r7, #14] + 800739e: f003 027f and.w r2, r3, #127 ; 0x7f + 80073a2: 4613 mov r3, r2 + 80073a4: 009b lsls r3, r3, #2 + 80073a6: 4413 add r3, r2 + 80073a8: 009b lsls r3, r3, #2 + 80073aa: 3310 adds r3, #16 + 80073ac: 687a ldr r2, [r7, #4] + 80073ae: 4413 add r3, r2 + 80073b0: 3304 adds r3, #4 + 80073b2: e00b b.n 80073cc + &pdev->ep_out[ep_addr & 0x7FU]; + 80073b4: 7bbb ldrb r3, [r7, #14] + 80073b6: f003 027f and.w r2, r3, #127 ; 0x7f + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + 80073ba: 4613 mov r3, r2 + 80073bc: 009b lsls r3, r3, #2 + 80073be: 4413 add r3, r2 + 80073c0: 009b lsls r3, r3, #2 + 80073c2: f503 73a8 add.w r3, r3, #336 ; 0x150 + 80073c6: 687a ldr r2, [r7, #4] + 80073c8: 4413 add r3, r2 + 80073ca: 3304 adds r3, #4 + 80073cc: 60bb str r3, [r7, #8] + + if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) + 80073ce: 7bbb ldrb r3, [r7, #14] + 80073d0: 2b00 cmp r3, #0 + 80073d2: d002 beq.n 80073da + 80073d4: 7bbb ldrb r3, [r7, #14] + 80073d6: 2b80 cmp r3, #128 ; 0x80 + 80073d8: d103 bne.n 80073e2 + { + pep->status = 0x0000U; + 80073da: 68bb ldr r3, [r7, #8] + 80073dc: 2200 movs r2, #0 + 80073de: 601a str r2, [r3, #0] + 80073e0: e00e b.n 8007400 + } + else if (USBD_LL_IsStallEP(pdev, ep_addr)) + 80073e2: 7bbb ldrb r3, [r7, #14] + 80073e4: 4619 mov r1, r3 + 80073e6: 6878 ldr r0, [r7, #4] + 80073e8: f003 fa1e bl 800a828 + 80073ec: 4603 mov r3, r0 + 80073ee: 2b00 cmp r3, #0 + 80073f0: d003 beq.n 80073fa + { + pep->status = 0x0001U; + 80073f2: 68bb ldr r3, [r7, #8] + 80073f4: 2201 movs r2, #1 + 80073f6: 601a str r2, [r3, #0] + 80073f8: e002 b.n 8007400 + } + else + { + pep->status = 0x0000U; + 80073fa: 68bb ldr r3, [r7, #8] + 80073fc: 2200 movs r2, #0 + 80073fe: 601a str r2, [r3, #0] + } + + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); + 8007400: 68bb ldr r3, [r7, #8] + 8007402: 2202 movs r2, #2 + 8007404: 4619 mov r1, r3 + 8007406: 6878 ldr r0, [r7, #4] + 8007408: f000 fb92 bl 8007b30 + break; + 800740c: e004 b.n 8007418 + + default: + USBD_CtlError(pdev, req); + 800740e: 6839 ldr r1, [r7, #0] + 8007410: 6878 ldr r0, [r7, #4] + 8007412: f000 fb23 bl 8007a5c + break; + 8007416: bf00 nop + } + break; + 8007418: e004 b.n 8007424 + + default: + USBD_CtlError(pdev, req); + 800741a: 6839 ldr r1, [r7, #0] + 800741c: 6878 ldr r0, [r7, #4] + 800741e: f000 fb1d bl 8007a5c + break; + 8007422: bf00 nop + } + break; + 8007424: e004 b.n 8007430 + + default: + USBD_CtlError(pdev, req); + 8007426: 6839 ldr r1, [r7, #0] + 8007428: 6878 ldr r0, [r7, #4] + 800742a: f000 fb17 bl 8007a5c + break; + 800742e: bf00 nop + } + + return ret; + 8007430: 7bfb ldrb r3, [r7, #15] +} + 8007432: 4618 mov r0, r3 + 8007434: 3710 adds r7, #16 + 8007436: 46bd mov sp, r7 + 8007438: bd80 pop {r7, pc} + ... + +0800743c : +* @param req: usb request +* @retval status +*/ +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 800743c: b580 push {r7, lr} + 800743e: b084 sub sp, #16 + 8007440: af00 add r7, sp, #0 + 8007442: 6078 str r0, [r7, #4] + 8007444: 6039 str r1, [r7, #0] + uint16_t len = 0U; + 8007446: 2300 movs r3, #0 + 8007448: 813b strh r3, [r7, #8] + uint8_t *pbuf = NULL; + 800744a: 2300 movs r3, #0 + 800744c: 60fb str r3, [r7, #12] + uint8_t err = 0U; + 800744e: 2300 movs r3, #0 + 8007450: 72fb strb r3, [r7, #11] + + switch (req->wValue >> 8) + 8007452: 683b ldr r3, [r7, #0] + 8007454: 885b ldrh r3, [r3, #2] + 8007456: 0a1b lsrs r3, r3, #8 + 8007458: b29b uxth r3, r3 + 800745a: 3b01 subs r3, #1 + 800745c: 2b06 cmp r3, #6 + 800745e: f200 8128 bhi.w 80076b2 + 8007462: a201 add r2, pc, #4 ; (adr r2, 8007468 ) + 8007464: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8007468: 08007485 .word 0x08007485 + 800746c: 0800749d .word 0x0800749d + 8007470: 080074dd .word 0x080074dd + 8007474: 080076b3 .word 0x080076b3 + 8007478: 080076b3 .word 0x080076b3 + 800747c: 08007653 .word 0x08007653 + 8007480: 0800767f .word 0x0800767f + err++; + } + break; +#endif + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + 8007484: 687b ldr r3, [r7, #4] + 8007486: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 800748a: 681b ldr r3, [r3, #0] + 800748c: 687a ldr r2, [r7, #4] + 800748e: 7c12 ldrb r2, [r2, #16] + 8007490: f107 0108 add.w r1, r7, #8 + 8007494: 4610 mov r0, r2 + 8007496: 4798 blx r3 + 8007498: 60f8 str r0, [r7, #12] + break; + 800749a: e112 b.n 80076c2 + + case USB_DESC_TYPE_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + 800749c: 687b ldr r3, [r7, #4] + 800749e: 7c1b ldrb r3, [r3, #16] + 80074a0: 2b00 cmp r3, #0 + 80074a2: d10d bne.n 80074c0 + { + pbuf = pdev->pClass->GetHSConfigDescriptor(&len); + 80074a4: 687b ldr r3, [r7, #4] + 80074a6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80074aa: 6a9b ldr r3, [r3, #40] ; 0x28 + 80074ac: f107 0208 add.w r2, r7, #8 + 80074b0: 4610 mov r0, r2 + 80074b2: 4798 blx r3 + 80074b4: 60f8 str r0, [r7, #12] + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 80074b6: 68fb ldr r3, [r7, #12] + 80074b8: 3301 adds r3, #1 + 80074ba: 2202 movs r2, #2 + 80074bc: 701a strb r2, [r3, #0] + else + { + pbuf = pdev->pClass->GetFSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + break; + 80074be: e100 b.n 80076c2 + pbuf = pdev->pClass->GetFSConfigDescriptor(&len); + 80074c0: 687b ldr r3, [r7, #4] + 80074c2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80074c6: 6adb ldr r3, [r3, #44] ; 0x2c + 80074c8: f107 0208 add.w r2, r7, #8 + 80074cc: 4610 mov r0, r2 + 80074ce: 4798 blx r3 + 80074d0: 60f8 str r0, [r7, #12] + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 80074d2: 68fb ldr r3, [r7, #12] + 80074d4: 3301 adds r3, #1 + 80074d6: 2202 movs r2, #2 + 80074d8: 701a strb r2, [r3, #0] + break; + 80074da: e0f2 b.n 80076c2 + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + 80074dc: 683b ldr r3, [r7, #0] + 80074de: 885b ldrh r3, [r3, #2] + 80074e0: b2db uxtb r3, r3 + 80074e2: 2b05 cmp r3, #5 + 80074e4: f200 80ac bhi.w 8007640 + 80074e8: a201 add r2, pc, #4 ; (adr r2, 80074f0 ) + 80074ea: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80074ee: bf00 nop + 80074f0: 08007509 .word 0x08007509 + 80074f4: 0800753d .word 0x0800753d + 80074f8: 08007571 .word 0x08007571 + 80074fc: 080075a5 .word 0x080075a5 + 8007500: 080075d9 .word 0x080075d9 + 8007504: 0800760d .word 0x0800760d + { + case USBD_IDX_LANGID_STR: + if (pdev->pDesc->GetLangIDStrDescriptor != NULL) + 8007508: 687b ldr r3, [r7, #4] + 800750a: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 800750e: 685b ldr r3, [r3, #4] + 8007510: 2b00 cmp r3, #0 + 8007512: d00b beq.n 800752c + { + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); + 8007514: 687b ldr r3, [r7, #4] + 8007516: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 800751a: 685b ldr r3, [r3, #4] + 800751c: 687a ldr r2, [r7, #4] + 800751e: 7c12 ldrb r2, [r2, #16] + 8007520: f107 0108 add.w r1, r7, #8 + 8007524: 4610 mov r0, r2 + 8007526: 4798 blx r3 + 8007528: 60f8 str r0, [r7, #12] + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + 800752a: e091 b.n 8007650 + USBD_CtlError(pdev, req); + 800752c: 6839 ldr r1, [r7, #0] + 800752e: 6878 ldr r0, [r7, #4] + 8007530: f000 fa94 bl 8007a5c + err++; + 8007534: 7afb ldrb r3, [r7, #11] + 8007536: 3301 adds r3, #1 + 8007538: 72fb strb r3, [r7, #11] + break; + 800753a: e089 b.n 8007650 + + case USBD_IDX_MFC_STR: + if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) + 800753c: 687b ldr r3, [r7, #4] + 800753e: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 8007542: 689b ldr r3, [r3, #8] + 8007544: 2b00 cmp r3, #0 + 8007546: d00b beq.n 8007560 + { + pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); + 8007548: 687b ldr r3, [r7, #4] + 800754a: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 800754e: 689b ldr r3, [r3, #8] + 8007550: 687a ldr r2, [r7, #4] + 8007552: 7c12 ldrb r2, [r2, #16] + 8007554: f107 0108 add.w r1, r7, #8 + 8007558: 4610 mov r0, r2 + 800755a: 4798 blx r3 + 800755c: 60f8 str r0, [r7, #12] + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + 800755e: e077 b.n 8007650 + USBD_CtlError(pdev, req); + 8007560: 6839 ldr r1, [r7, #0] + 8007562: 6878 ldr r0, [r7, #4] + 8007564: f000 fa7a bl 8007a5c + err++; + 8007568: 7afb ldrb r3, [r7, #11] + 800756a: 3301 adds r3, #1 + 800756c: 72fb strb r3, [r7, #11] + break; + 800756e: e06f b.n 8007650 + + case USBD_IDX_PRODUCT_STR: + if (pdev->pDesc->GetProductStrDescriptor != NULL) + 8007570: 687b ldr r3, [r7, #4] + 8007572: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 8007576: 68db ldr r3, [r3, #12] + 8007578: 2b00 cmp r3, #0 + 800757a: d00b beq.n 8007594 + { + pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + 800757c: 687b ldr r3, [r7, #4] + 800757e: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 8007582: 68db ldr r3, [r3, #12] + 8007584: 687a ldr r2, [r7, #4] + 8007586: 7c12 ldrb r2, [r2, #16] + 8007588: f107 0108 add.w r1, r7, #8 + 800758c: 4610 mov r0, r2 + 800758e: 4798 blx r3 + 8007590: 60f8 str r0, [r7, #12] + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + 8007592: e05d b.n 8007650 + USBD_CtlError(pdev, req); + 8007594: 6839 ldr r1, [r7, #0] + 8007596: 6878 ldr r0, [r7, #4] + 8007598: f000 fa60 bl 8007a5c + err++; + 800759c: 7afb ldrb r3, [r7, #11] + 800759e: 3301 adds r3, #1 + 80075a0: 72fb strb r3, [r7, #11] + break; + 80075a2: e055 b.n 8007650 + + case USBD_IDX_SERIAL_STR: + if (pdev->pDesc->GetSerialStrDescriptor != NULL) + 80075a4: 687b ldr r3, [r7, #4] + 80075a6: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 80075aa: 691b ldr r3, [r3, #16] + 80075ac: 2b00 cmp r3, #0 + 80075ae: d00b beq.n 80075c8 + { + pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + 80075b0: 687b ldr r3, [r7, #4] + 80075b2: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 80075b6: 691b ldr r3, [r3, #16] + 80075b8: 687a ldr r2, [r7, #4] + 80075ba: 7c12 ldrb r2, [r2, #16] + 80075bc: f107 0108 add.w r1, r7, #8 + 80075c0: 4610 mov r0, r2 + 80075c2: 4798 blx r3 + 80075c4: 60f8 str r0, [r7, #12] + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + 80075c6: e043 b.n 8007650 + USBD_CtlError(pdev, req); + 80075c8: 6839 ldr r1, [r7, #0] + 80075ca: 6878 ldr r0, [r7, #4] + 80075cc: f000 fa46 bl 8007a5c + err++; + 80075d0: 7afb ldrb r3, [r7, #11] + 80075d2: 3301 adds r3, #1 + 80075d4: 72fb strb r3, [r7, #11] + break; + 80075d6: e03b b.n 8007650 + + case USBD_IDX_CONFIG_STR: + if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) + 80075d8: 687b ldr r3, [r7, #4] + 80075da: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 80075de: 695b ldr r3, [r3, #20] + 80075e0: 2b00 cmp r3, #0 + 80075e2: d00b beq.n 80075fc + { + pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); + 80075e4: 687b ldr r3, [r7, #4] + 80075e6: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 80075ea: 695b ldr r3, [r3, #20] + 80075ec: 687a ldr r2, [r7, #4] + 80075ee: 7c12 ldrb r2, [r2, #16] + 80075f0: f107 0108 add.w r1, r7, #8 + 80075f4: 4610 mov r0, r2 + 80075f6: 4798 blx r3 + 80075f8: 60f8 str r0, [r7, #12] + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + 80075fa: e029 b.n 8007650 + USBD_CtlError(pdev, req); + 80075fc: 6839 ldr r1, [r7, #0] + 80075fe: 6878 ldr r0, [r7, #4] + 8007600: f000 fa2c bl 8007a5c + err++; + 8007604: 7afb ldrb r3, [r7, #11] + 8007606: 3301 adds r3, #1 + 8007608: 72fb strb r3, [r7, #11] + break; + 800760a: e021 b.n 8007650 + + case USBD_IDX_INTERFACE_STR: + if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) + 800760c: 687b ldr r3, [r7, #4] + 800760e: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 8007612: 699b ldr r3, [r3, #24] + 8007614: 2b00 cmp r3, #0 + 8007616: d00b beq.n 8007630 + { + pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); + 8007618: 687b ldr r3, [r7, #4] + 800761a: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0 + 800761e: 699b ldr r3, [r3, #24] + 8007620: 687a ldr r2, [r7, #4] + 8007622: 7c12 ldrb r2, [r2, #16] + 8007624: f107 0108 add.w r1, r7, #8 + 8007628: 4610 mov r0, r2 + 800762a: 4798 blx r3 + 800762c: 60f8 str r0, [r7, #12] + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + 800762e: e00f b.n 8007650 + USBD_CtlError(pdev, req); + 8007630: 6839 ldr r1, [r7, #0] + 8007632: 6878 ldr r0, [r7, #4] + 8007634: f000 fa12 bl 8007a5c + err++; + 8007638: 7afb ldrb r3, [r7, #11] + 800763a: 3301 adds r3, #1 + 800763c: 72fb strb r3, [r7, #11] + break; + 800763e: e007 b.n 8007650 + USBD_CtlError(pdev, req); + err++; + } + break; +#else + USBD_CtlError(pdev, req); + 8007640: 6839 ldr r1, [r7, #0] + 8007642: 6878 ldr r0, [r7, #4] + 8007644: f000 fa0a bl 8007a5c + err++; + 8007648: 7afb ldrb r3, [r7, #11] + 800764a: 3301 adds r3, #1 + 800764c: 72fb strb r3, [r7, #11] +#endif + } + break; + 800764e: e038 b.n 80076c2 + 8007650: e037 b.n 80076c2 + + case USB_DESC_TYPE_DEVICE_QUALIFIER: + if (pdev->dev_speed == USBD_SPEED_HIGH) + 8007652: 687b ldr r3, [r7, #4] + 8007654: 7c1b ldrb r3, [r3, #16] + 8007656: 2b00 cmp r3, #0 + 8007658: d109 bne.n 800766e + { + pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); + 800765a: 687b ldr r3, [r7, #4] + 800765c: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8007660: 6b5b ldr r3, [r3, #52] ; 0x34 + 8007662: f107 0208 add.w r2, r7, #8 + 8007666: 4610 mov r0, r2 + 8007668: 4798 blx r3 + 800766a: 60f8 str r0, [r7, #12] + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + 800766c: e029 b.n 80076c2 + USBD_CtlError(pdev, req); + 800766e: 6839 ldr r1, [r7, #0] + 8007670: 6878 ldr r0, [r7, #4] + 8007672: f000 f9f3 bl 8007a5c + err++; + 8007676: 7afb ldrb r3, [r7, #11] + 8007678: 3301 adds r3, #1 + 800767a: 72fb strb r3, [r7, #11] + break; + 800767c: e021 b.n 80076c2 + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + 800767e: 687b ldr r3, [r7, #4] + 8007680: 7c1b ldrb r3, [r3, #16] + 8007682: 2b00 cmp r3, #0 + 8007684: d10d bne.n 80076a2 + { + pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); + 8007686: 687b ldr r3, [r7, #4] + 8007688: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 800768c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800768e: f107 0208 add.w r2, r7, #8 + 8007692: 4610 mov r0, r2 + 8007694: 4798 blx r3 + 8007696: 60f8 str r0, [r7, #12] + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + 8007698: 68fb ldr r3, [r7, #12] + 800769a: 3301 adds r3, #1 + 800769c: 2207 movs r2, #7 + 800769e: 701a strb r2, [r3, #0] + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + 80076a0: e00f b.n 80076c2 + USBD_CtlError(pdev, req); + 80076a2: 6839 ldr r1, [r7, #0] + 80076a4: 6878 ldr r0, [r7, #4] + 80076a6: f000 f9d9 bl 8007a5c + err++; + 80076aa: 7afb ldrb r3, [r7, #11] + 80076ac: 3301 adds r3, #1 + 80076ae: 72fb strb r3, [r7, #11] + break; + 80076b0: e007 b.n 80076c2 + + default: + USBD_CtlError(pdev, req); + 80076b2: 6839 ldr r1, [r7, #0] + 80076b4: 6878 ldr r0, [r7, #4] + 80076b6: f000 f9d1 bl 8007a5c + err++; + 80076ba: 7afb ldrb r3, [r7, #11] + 80076bc: 3301 adds r3, #1 + 80076be: 72fb strb r3, [r7, #11] + break; + 80076c0: bf00 nop + } + + if (err != 0U) + 80076c2: 7afb ldrb r3, [r7, #11] + 80076c4: 2b00 cmp r3, #0 + 80076c6: d11c bne.n 8007702 + { + return; + } + else + { + if ((len != 0U) && (req->wLength != 0U)) + 80076c8: 893b ldrh r3, [r7, #8] + 80076ca: 2b00 cmp r3, #0 + 80076cc: d011 beq.n 80076f2 + 80076ce: 683b ldr r3, [r7, #0] + 80076d0: 88db ldrh r3, [r3, #6] + 80076d2: 2b00 cmp r3, #0 + 80076d4: d00d beq.n 80076f2 + { + len = MIN(len, req->wLength); + 80076d6: 683b ldr r3, [r7, #0] + 80076d8: 88da ldrh r2, [r3, #6] + 80076da: 893b ldrh r3, [r7, #8] + 80076dc: 4293 cmp r3, r2 + 80076de: bf28 it cs + 80076e0: 4613 movcs r3, r2 + 80076e2: b29b uxth r3, r3 + 80076e4: 813b strh r3, [r7, #8] + (void)USBD_CtlSendData(pdev, pbuf, len); + 80076e6: 893b ldrh r3, [r7, #8] + 80076e8: 461a mov r2, r3 + 80076ea: 68f9 ldr r1, [r7, #12] + 80076ec: 6878 ldr r0, [r7, #4] + 80076ee: f000 fa1f bl 8007b30 + } + + if (req->wLength == 0U) + 80076f2: 683b ldr r3, [r7, #0] + 80076f4: 88db ldrh r3, [r3, #6] + 80076f6: 2b00 cmp r3, #0 + 80076f8: d104 bne.n 8007704 + { + (void)USBD_CtlSendStatus(pdev); + 80076fa: 6878 ldr r0, [r7, #4] + 80076fc: f000 fa76 bl 8007bec + 8007700: e000 b.n 8007704 + return; + 8007702: bf00 nop + } + } +} + 8007704: 3710 adds r7, #16 + 8007706: 46bd mov sp, r7 + 8007708: bd80 pop {r7, pc} + 800770a: bf00 nop + +0800770c : +* @param req: usb request +* @retval status +*/ +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 800770c: b580 push {r7, lr} + 800770e: b084 sub sp, #16 + 8007710: af00 add r7, sp, #0 + 8007712: 6078 str r0, [r7, #4] + 8007714: 6039 str r1, [r7, #0] + uint8_t dev_addr; + + if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) + 8007716: 683b ldr r3, [r7, #0] + 8007718: 889b ldrh r3, [r3, #4] + 800771a: 2b00 cmp r3, #0 + 800771c: d130 bne.n 8007780 + 800771e: 683b ldr r3, [r7, #0] + 8007720: 88db ldrh r3, [r3, #6] + 8007722: 2b00 cmp r3, #0 + 8007724: d12c bne.n 8007780 + 8007726: 683b ldr r3, [r7, #0] + 8007728: 885b ldrh r3, [r3, #2] + 800772a: 2b7f cmp r3, #127 ; 0x7f + 800772c: d828 bhi.n 8007780 + { + dev_addr = (uint8_t)(req->wValue) & 0x7FU; + 800772e: 683b ldr r3, [r7, #0] + 8007730: 885b ldrh r3, [r3, #2] + 8007732: b2db uxtb r3, r3 + 8007734: f003 037f and.w r3, r3, #127 ; 0x7f + 8007738: 73fb strb r3, [r7, #15] + + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 800773a: 687b ldr r3, [r7, #4] + 800773c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8007740: 2b03 cmp r3, #3 + 8007742: d104 bne.n 800774e + { + USBD_CtlError(pdev, req); + 8007744: 6839 ldr r1, [r7, #0] + 8007746: 6878 ldr r0, [r7, #4] + 8007748: f000 f988 bl 8007a5c + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 800774c: e01c b.n 8007788 + } + else + { + pdev->dev_address = dev_addr; + 800774e: 687b ldr r3, [r7, #4] + 8007750: 7bfa ldrb r2, [r7, #15] + 8007752: f883 229e strb.w r2, [r3, #670] ; 0x29e + USBD_LL_SetUSBAddress(pdev, dev_addr); + 8007756: 7bfb ldrb r3, [r7, #15] + 8007758: 4619 mov r1, r3 + 800775a: 6878 ldr r0, [r7, #4] + 800775c: f003 f889 bl 800a872 + USBD_CtlSendStatus(pdev); + 8007760: 6878 ldr r0, [r7, #4] + 8007762: f000 fa43 bl 8007bec + + if (dev_addr != 0U) + 8007766: 7bfb ldrb r3, [r7, #15] + 8007768: 2b00 cmp r3, #0 + 800776a: d004 beq.n 8007776 + { + pdev->dev_state = USBD_STATE_ADDRESSED; + 800776c: 687b ldr r3, [r7, #4] + 800776e: 2202 movs r2, #2 + 8007770: f883 229c strb.w r2, [r3, #668] ; 0x29c + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 8007774: e008 b.n 8007788 + } + else + { + pdev->dev_state = USBD_STATE_DEFAULT; + 8007776: 687b ldr r3, [r7, #4] + 8007778: 2201 movs r2, #1 + 800777a: f883 229c strb.w r2, [r3, #668] ; 0x29c + if (pdev->dev_state == USBD_STATE_CONFIGURED) + 800777e: e003 b.n 8007788 + } + } + } + else + { + USBD_CtlError(pdev, req); + 8007780: 6839 ldr r1, [r7, #0] + 8007782: 6878 ldr r0, [r7, #4] + 8007784: f000 f96a bl 8007a5c + } +} + 8007788: bf00 nop + 800778a: 3710 adds r7, #16 + 800778c: 46bd mov sp, r7 + 800778e: bd80 pop {r7, pc} + +08007790 : +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + 8007790: b580 push {r7, lr} + 8007792: b082 sub sp, #8 + 8007794: af00 add r7, sp, #0 + 8007796: 6078 str r0, [r7, #4] + 8007798: 6039 str r1, [r7, #0] + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + 800779a: 683b ldr r3, [r7, #0] + 800779c: 885b ldrh r3, [r3, #2] + 800779e: b2da uxtb r2, r3 + 80077a0: 4b41 ldr r3, [pc, #260] ; (80078a8 ) + 80077a2: 701a strb r2, [r3, #0] + + if (cfgidx > USBD_MAX_NUM_CONFIGURATION) + 80077a4: 4b40 ldr r3, [pc, #256] ; (80078a8 ) + 80077a6: 781b ldrb r3, [r3, #0] + 80077a8: 2b01 cmp r3, #1 + 80077aa: d904 bls.n 80077b6 + { + USBD_CtlError(pdev, req); + 80077ac: 6839 ldr r1, [r7, #0] + 80077ae: 6878 ldr r0, [r7, #4] + 80077b0: f000 f954 bl 8007a5c + 80077b4: e075 b.n 80078a2 + } + else + { + switch (pdev->dev_state) + 80077b6: 687b ldr r3, [r7, #4] + 80077b8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 80077bc: 2b02 cmp r3, #2 + 80077be: d002 beq.n 80077c6 + 80077c0: 2b03 cmp r3, #3 + 80077c2: d023 beq.n 800780c + 80077c4: e062 b.n 800788c + { + case USBD_STATE_ADDRESSED: + if (cfgidx) + 80077c6: 4b38 ldr r3, [pc, #224] ; (80078a8 ) + 80077c8: 781b ldrb r3, [r3, #0] + 80077ca: 2b00 cmp r3, #0 + 80077cc: d01a beq.n 8007804 + { + pdev->dev_config = cfgidx; + 80077ce: 4b36 ldr r3, [pc, #216] ; (80078a8 ) + 80077d0: 781b ldrb r3, [r3, #0] + 80077d2: 461a mov r2, r3 + 80077d4: 687b ldr r3, [r7, #4] + 80077d6: 605a str r2, [r3, #4] + pdev->dev_state = USBD_STATE_CONFIGURED; + 80077d8: 687b ldr r3, [r7, #4] + 80077da: 2203 movs r2, #3 + 80077dc: f883 229c strb.w r2, [r3, #668] ; 0x29c + if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) + 80077e0: 4b31 ldr r3, [pc, #196] ; (80078a8 ) + 80077e2: 781b ldrb r3, [r3, #0] + 80077e4: 4619 mov r1, r3 + 80077e6: 6878 ldr r0, [r7, #4] + 80077e8: f7ff f9f4 bl 8006bd4 + 80077ec: 4603 mov r3, r0 + 80077ee: 2b02 cmp r3, #2 + 80077f0: d104 bne.n 80077fc + { + USBD_CtlError(pdev, req); + 80077f2: 6839 ldr r1, [r7, #0] + 80077f4: 6878 ldr r0, [r7, #4] + 80077f6: f000 f931 bl 8007a5c + return; + 80077fa: e052 b.n 80078a2 + } + USBD_CtlSendStatus(pdev); + 80077fc: 6878 ldr r0, [r7, #4] + 80077fe: f000 f9f5 bl 8007bec + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + 8007802: e04e b.n 80078a2 + USBD_CtlSendStatus(pdev); + 8007804: 6878 ldr r0, [r7, #4] + 8007806: f000 f9f1 bl 8007bec + break; + 800780a: e04a b.n 80078a2 + + case USBD_STATE_CONFIGURED: + if (cfgidx == 0U) + 800780c: 4b26 ldr r3, [pc, #152] ; (80078a8 ) + 800780e: 781b ldrb r3, [r3, #0] + 8007810: 2b00 cmp r3, #0 + 8007812: d112 bne.n 800783a + { + pdev->dev_state = USBD_STATE_ADDRESSED; + 8007814: 687b ldr r3, [r7, #4] + 8007816: 2202 movs r2, #2 + 8007818: f883 229c strb.w r2, [r3, #668] ; 0x29c + pdev->dev_config = cfgidx; + 800781c: 4b22 ldr r3, [pc, #136] ; (80078a8 ) + 800781e: 781b ldrb r3, [r3, #0] + 8007820: 461a mov r2, r3 + 8007822: 687b ldr r3, [r7, #4] + 8007824: 605a str r2, [r3, #4] + USBD_ClrClassConfig(pdev, cfgidx); + 8007826: 4b20 ldr r3, [pc, #128] ; (80078a8 ) + 8007828: 781b ldrb r3, [r3, #0] + 800782a: 4619 mov r1, r3 + 800782c: 6878 ldr r0, [r7, #4] + 800782e: f7ff f9f0 bl 8006c12 + USBD_CtlSendStatus(pdev); + 8007832: 6878 ldr r0, [r7, #4] + 8007834: f000 f9da bl 8007bec + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + 8007838: e033 b.n 80078a2 + else if (cfgidx != pdev->dev_config) + 800783a: 4b1b ldr r3, [pc, #108] ; (80078a8 ) + 800783c: 781b ldrb r3, [r3, #0] + 800783e: 461a mov r2, r3 + 8007840: 687b ldr r3, [r7, #4] + 8007842: 685b ldr r3, [r3, #4] + 8007844: 429a cmp r2, r3 + 8007846: d01d beq.n 8007884 + USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + 8007848: 687b ldr r3, [r7, #4] + 800784a: 685b ldr r3, [r3, #4] + 800784c: b2db uxtb r3, r3 + 800784e: 4619 mov r1, r3 + 8007850: 6878 ldr r0, [r7, #4] + 8007852: f7ff f9de bl 8006c12 + pdev->dev_config = cfgidx; + 8007856: 4b14 ldr r3, [pc, #80] ; (80078a8 ) + 8007858: 781b ldrb r3, [r3, #0] + 800785a: 461a mov r2, r3 + 800785c: 687b ldr r3, [r7, #4] + 800785e: 605a str r2, [r3, #4] + if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) + 8007860: 4b11 ldr r3, [pc, #68] ; (80078a8 ) + 8007862: 781b ldrb r3, [r3, #0] + 8007864: 4619 mov r1, r3 + 8007866: 6878 ldr r0, [r7, #4] + 8007868: f7ff f9b4 bl 8006bd4 + 800786c: 4603 mov r3, r0 + 800786e: 2b02 cmp r3, #2 + 8007870: d104 bne.n 800787c + USBD_CtlError(pdev, req); + 8007872: 6839 ldr r1, [r7, #0] + 8007874: 6878 ldr r0, [r7, #4] + 8007876: f000 f8f1 bl 8007a5c + return; + 800787a: e012 b.n 80078a2 + USBD_CtlSendStatus(pdev); + 800787c: 6878 ldr r0, [r7, #4] + 800787e: f000 f9b5 bl 8007bec + break; + 8007882: e00e b.n 80078a2 + USBD_CtlSendStatus(pdev); + 8007884: 6878 ldr r0, [r7, #4] + 8007886: f000 f9b1 bl 8007bec + break; + 800788a: e00a b.n 80078a2 + + default: + USBD_CtlError(pdev, req); + 800788c: 6839 ldr r1, [r7, #0] + 800788e: 6878 ldr r0, [r7, #4] + 8007890: f000 f8e4 bl 8007a5c + USBD_ClrClassConfig(pdev, cfgidx); + 8007894: 4b04 ldr r3, [pc, #16] ; (80078a8 ) + 8007896: 781b ldrb r3, [r3, #0] + 8007898: 4619 mov r1, r3 + 800789a: 6878 ldr r0, [r7, #4] + 800789c: f7ff f9b9 bl 8006c12 + break; + 80078a0: bf00 nop + } + } +} + 80078a2: 3708 adds r7, #8 + 80078a4: 46bd mov sp, r7 + 80078a6: bd80 pop {r7, pc} + 80078a8: 20000224 .word 0x20000224 + +080078ac : +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + 80078ac: b580 push {r7, lr} + 80078ae: b082 sub sp, #8 + 80078b0: af00 add r7, sp, #0 + 80078b2: 6078 str r0, [r7, #4] + 80078b4: 6039 str r1, [r7, #0] + if (req->wLength != 1U) + 80078b6: 683b ldr r3, [r7, #0] + 80078b8: 88db ldrh r3, [r3, #6] + 80078ba: 2b01 cmp r3, #1 + 80078bc: d004 beq.n 80078c8 + { + USBD_CtlError(pdev, req); + 80078be: 6839 ldr r1, [r7, #0] + 80078c0: 6878 ldr r0, [r7, #4] + 80078c2: f000 f8cb bl 8007a5c + default: + USBD_CtlError(pdev, req); + break; + } + } +} + 80078c6: e021 b.n 800790c + switch (pdev->dev_state) + 80078c8: 687b ldr r3, [r7, #4] + 80078ca: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 80078ce: 2b01 cmp r3, #1 + 80078d0: db17 blt.n 8007902 + 80078d2: 2b02 cmp r3, #2 + 80078d4: dd02 ble.n 80078dc + 80078d6: 2b03 cmp r3, #3 + 80078d8: d00b beq.n 80078f2 + 80078da: e012 b.n 8007902 + pdev->dev_default_config = 0U; + 80078dc: 687b ldr r3, [r7, #4] + 80078de: 2200 movs r2, #0 + 80078e0: 609a str r2, [r3, #8] + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U); + 80078e2: 687b ldr r3, [r7, #4] + 80078e4: 3308 adds r3, #8 + 80078e6: 2201 movs r2, #1 + 80078e8: 4619 mov r1, r3 + 80078ea: 6878 ldr r0, [r7, #4] + 80078ec: f000 f920 bl 8007b30 + break; + 80078f0: e00c b.n 800790c + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U); + 80078f2: 687b ldr r3, [r7, #4] + 80078f4: 3304 adds r3, #4 + 80078f6: 2201 movs r2, #1 + 80078f8: 4619 mov r1, r3 + 80078fa: 6878 ldr r0, [r7, #4] + 80078fc: f000 f918 bl 8007b30 + break; + 8007900: e004 b.n 800790c + USBD_CtlError(pdev, req); + 8007902: 6839 ldr r1, [r7, #0] + 8007904: 6878 ldr r0, [r7, #4] + 8007906: f000 f8a9 bl 8007a5c + break; + 800790a: bf00 nop +} + 800790c: bf00 nop + 800790e: 3708 adds r7, #8 + 8007910: 46bd mov sp, r7 + 8007912: bd80 pop {r7, pc} + +08007914 : +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + 8007914: b580 push {r7, lr} + 8007916: b082 sub sp, #8 + 8007918: af00 add r7, sp, #0 + 800791a: 6078 str r0, [r7, #4] + 800791c: 6039 str r1, [r7, #0] + switch (pdev->dev_state) + 800791e: 687b ldr r3, [r7, #4] + 8007920: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8007924: 3b01 subs r3, #1 + 8007926: 2b02 cmp r3, #2 + 8007928: d81e bhi.n 8007968 + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wLength != 0x2U) + 800792a: 683b ldr r3, [r7, #0] + 800792c: 88db ldrh r3, [r3, #6] + 800792e: 2b02 cmp r3, #2 + 8007930: d004 beq.n 800793c + { + USBD_CtlError(pdev, req); + 8007932: 6839 ldr r1, [r7, #0] + 8007934: 6878 ldr r0, [r7, #4] + 8007936: f000 f891 bl 8007a5c + break; + 800793a: e01a b.n 8007972 + } + +#if (USBD_SELF_POWERED == 1U) + pdev->dev_config_status = USB_CONFIG_SELF_POWERED; + 800793c: 687b ldr r3, [r7, #4] + 800793e: 2201 movs r2, #1 + 8007940: 60da str r2, [r3, #12] +#else + pdev->dev_config_status = 0U; +#endif + + if (pdev->dev_remote_wakeup) + 8007942: 687b ldr r3, [r7, #4] + 8007944: f8d3 32a4 ldr.w r3, [r3, #676] ; 0x2a4 + 8007948: 2b00 cmp r3, #0 + 800794a: d005 beq.n 8007958 + { + pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + 800794c: 687b ldr r3, [r7, #4] + 800794e: 68db ldr r3, [r3, #12] + 8007950: f043 0202 orr.w r2, r3, #2 + 8007954: 687b ldr r3, [r7, #4] + 8007956: 60da str r2, [r3, #12] + } + + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U); + 8007958: 687b ldr r3, [r7, #4] + 800795a: 330c adds r3, #12 + 800795c: 2202 movs r2, #2 + 800795e: 4619 mov r1, r3 + 8007960: 6878 ldr r0, [r7, #4] + 8007962: f000 f8e5 bl 8007b30 + break; + 8007966: e004 b.n 8007972 + + default: + USBD_CtlError(pdev, req); + 8007968: 6839 ldr r1, [r7, #0] + 800796a: 6878 ldr r0, [r7, #4] + 800796c: f000 f876 bl 8007a5c + break; + 8007970: bf00 nop + } +} + 8007972: bf00 nop + 8007974: 3708 adds r7, #8 + 8007976: 46bd mov sp, r7 + 8007978: bd80 pop {r7, pc} + +0800797a : +* @param req: usb request +* @retval status +*/ +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 800797a: b580 push {r7, lr} + 800797c: b082 sub sp, #8 + 800797e: af00 add r7, sp, #0 + 8007980: 6078 str r0, [r7, #4] + 8007982: 6039 str r1, [r7, #0] + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + 8007984: 683b ldr r3, [r7, #0] + 8007986: 885b ldrh r3, [r3, #2] + 8007988: 2b01 cmp r3, #1 + 800798a: d106 bne.n 800799a + { + pdev->dev_remote_wakeup = 1U; + 800798c: 687b ldr r3, [r7, #4] + 800798e: 2201 movs r2, #1 + 8007990: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 + USBD_CtlSendStatus(pdev); + 8007994: 6878 ldr r0, [r7, #4] + 8007996: f000 f929 bl 8007bec + } +} + 800799a: bf00 nop + 800799c: 3708 adds r7, #8 + 800799e: 46bd mov sp, r7 + 80079a0: bd80 pop {r7, pc} + +080079a2 : +* @param req: usb request +* @retval status +*/ +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 80079a2: b580 push {r7, lr} + 80079a4: b082 sub sp, #8 + 80079a6: af00 add r7, sp, #0 + 80079a8: 6078 str r0, [r7, #4] + 80079aa: 6039 str r1, [r7, #0] + switch (pdev->dev_state) + 80079ac: 687b ldr r3, [r7, #4] + 80079ae: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 80079b2: 3b01 subs r3, #1 + 80079b4: 2b02 cmp r3, #2 + 80079b6: d80b bhi.n 80079d0 + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + 80079b8: 683b ldr r3, [r7, #0] + 80079ba: 885b ldrh r3, [r3, #2] + 80079bc: 2b01 cmp r3, #1 + 80079be: d10c bne.n 80079da + { + pdev->dev_remote_wakeup = 0U; + 80079c0: 687b ldr r3, [r7, #4] + 80079c2: 2200 movs r2, #0 + 80079c4: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 + USBD_CtlSendStatus(pdev); + 80079c8: 6878 ldr r0, [r7, #4] + 80079ca: f000 f90f bl 8007bec + } + break; + 80079ce: e004 b.n 80079da + + default: + USBD_CtlError(pdev, req); + 80079d0: 6839 ldr r1, [r7, #0] + 80079d2: 6878 ldr r0, [r7, #4] + 80079d4: f000 f842 bl 8007a5c + break; + 80079d8: e000 b.n 80079dc + break; + 80079da: bf00 nop + } +} + 80079dc: bf00 nop + 80079de: 3708 adds r7, #8 + 80079e0: 46bd mov sp, r7 + 80079e2: bd80 pop {r7, pc} + +080079e4 : +* @param req: usb request +* @retval None +*/ + +void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) +{ + 80079e4: b480 push {r7} + 80079e6: b083 sub sp, #12 + 80079e8: af00 add r7, sp, #0 + 80079ea: 6078 str r0, [r7, #4] + 80079ec: 6039 str r1, [r7, #0] + req->bmRequest = *(uint8_t *)(pdata); + 80079ee: 683b ldr r3, [r7, #0] + 80079f0: 781a ldrb r2, [r3, #0] + 80079f2: 687b ldr r3, [r7, #4] + 80079f4: 701a strb r2, [r3, #0] + req->bRequest = *(uint8_t *)(pdata + 1U); + 80079f6: 683b ldr r3, [r7, #0] + 80079f8: 785a ldrb r2, [r3, #1] + 80079fa: 687b ldr r3, [r7, #4] + 80079fc: 705a strb r2, [r3, #1] + req->wValue = SWAPBYTE(pdata + 2U); + 80079fe: 683b ldr r3, [r7, #0] + 8007a00: 3302 adds r3, #2 + 8007a02: 781b ldrb r3, [r3, #0] + 8007a04: b29a uxth r2, r3 + 8007a06: 683b ldr r3, [r7, #0] + 8007a08: 3303 adds r3, #3 + 8007a0a: 781b ldrb r3, [r3, #0] + 8007a0c: b29b uxth r3, r3 + 8007a0e: 021b lsls r3, r3, #8 + 8007a10: b29b uxth r3, r3 + 8007a12: 4413 add r3, r2 + 8007a14: b29a uxth r2, r3 + 8007a16: 687b ldr r3, [r7, #4] + 8007a18: 805a strh r2, [r3, #2] + req->wIndex = SWAPBYTE(pdata + 4U); + 8007a1a: 683b ldr r3, [r7, #0] + 8007a1c: 3304 adds r3, #4 + 8007a1e: 781b ldrb r3, [r3, #0] + 8007a20: b29a uxth r2, r3 + 8007a22: 683b ldr r3, [r7, #0] + 8007a24: 3305 adds r3, #5 + 8007a26: 781b ldrb r3, [r3, #0] + 8007a28: b29b uxth r3, r3 + 8007a2a: 021b lsls r3, r3, #8 + 8007a2c: b29b uxth r3, r3 + 8007a2e: 4413 add r3, r2 + 8007a30: b29a uxth r2, r3 + 8007a32: 687b ldr r3, [r7, #4] + 8007a34: 809a strh r2, [r3, #4] + req->wLength = SWAPBYTE(pdata + 6U); + 8007a36: 683b ldr r3, [r7, #0] + 8007a38: 3306 adds r3, #6 + 8007a3a: 781b ldrb r3, [r3, #0] + 8007a3c: b29a uxth r2, r3 + 8007a3e: 683b ldr r3, [r7, #0] + 8007a40: 3307 adds r3, #7 + 8007a42: 781b ldrb r3, [r3, #0] + 8007a44: b29b uxth r3, r3 + 8007a46: 021b lsls r3, r3, #8 + 8007a48: b29b uxth r3, r3 + 8007a4a: 4413 add r3, r2 + 8007a4c: b29a uxth r2, r3 + 8007a4e: 687b ldr r3, [r7, #4] + 8007a50: 80da strh r2, [r3, #6] + +} + 8007a52: bf00 nop + 8007a54: 370c adds r7, #12 + 8007a56: 46bd mov sp, r7 + 8007a58: bc80 pop {r7} + 8007a5a: 4770 bx lr + +08007a5c : +* @retval None +*/ + +void USBD_CtlError(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 8007a5c: b580 push {r7, lr} + 8007a5e: b082 sub sp, #8 + 8007a60: af00 add r7, sp, #0 + 8007a62: 6078 str r0, [r7, #4] + 8007a64: 6039 str r1, [r7, #0] + USBD_LL_StallEP(pdev, 0x80U); + 8007a66: 2180 movs r1, #128 ; 0x80 + 8007a68: 6878 ldr r0, [r7, #4] + 8007a6a: f002 fe9f bl 800a7ac + USBD_LL_StallEP(pdev, 0U); + 8007a6e: 2100 movs r1, #0 + 8007a70: 6878 ldr r0, [r7, #4] + 8007a72: f002 fe9b bl 800a7ac +} + 8007a76: bf00 nop + 8007a78: 3708 adds r7, #8 + 8007a7a: 46bd mov sp, r7 + 8007a7c: bd80 pop {r7, pc} + +08007a7e : + * @param unicode : Formatted string buffer (unicode) + * @param len : descriptor length + * @retval None + */ +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + 8007a7e: b580 push {r7, lr} + 8007a80: b086 sub sp, #24 + 8007a82: af00 add r7, sp, #0 + 8007a84: 60f8 str r0, [r7, #12] + 8007a86: 60b9 str r1, [r7, #8] + 8007a88: 607a str r2, [r7, #4] + uint8_t idx = 0U; + 8007a8a: 2300 movs r3, #0 + 8007a8c: 75fb strb r3, [r7, #23] + + if (desc != NULL) + 8007a8e: 68fb ldr r3, [r7, #12] + 8007a90: 2b00 cmp r3, #0 + 8007a92: d032 beq.n 8007afa + { + *len = (uint16_t)USBD_GetLen(desc) * 2U + 2U; + 8007a94: 68f8 ldr r0, [r7, #12] + 8007a96: f000 f834 bl 8007b02 + 8007a9a: 4603 mov r3, r0 + 8007a9c: 3301 adds r3, #1 + 8007a9e: b29b uxth r3, r3 + 8007aa0: 005b lsls r3, r3, #1 + 8007aa2: b29a uxth r2, r3 + 8007aa4: 687b ldr r3, [r7, #4] + 8007aa6: 801a strh r2, [r3, #0] + unicode[idx++] = *(uint8_t *)(void *)len; + 8007aa8: 7dfb ldrb r3, [r7, #23] + 8007aaa: 1c5a adds r2, r3, #1 + 8007aac: 75fa strb r2, [r7, #23] + 8007aae: 461a mov r2, r3 + 8007ab0: 68bb ldr r3, [r7, #8] + 8007ab2: 4413 add r3, r2 + 8007ab4: 687a ldr r2, [r7, #4] + 8007ab6: 7812 ldrb r2, [r2, #0] + 8007ab8: 701a strb r2, [r3, #0] + unicode[idx++] = USB_DESC_TYPE_STRING; + 8007aba: 7dfb ldrb r3, [r7, #23] + 8007abc: 1c5a adds r2, r3, #1 + 8007abe: 75fa strb r2, [r7, #23] + 8007ac0: 461a mov r2, r3 + 8007ac2: 68bb ldr r3, [r7, #8] + 8007ac4: 4413 add r3, r2 + 8007ac6: 2203 movs r2, #3 + 8007ac8: 701a strb r2, [r3, #0] + + while (*desc != '\0') + 8007aca: e012 b.n 8007af2 + { + unicode[idx++] = *desc++; + 8007acc: 68fb ldr r3, [r7, #12] + 8007ace: 1c5a adds r2, r3, #1 + 8007ad0: 60fa str r2, [r7, #12] + 8007ad2: 7dfa ldrb r2, [r7, #23] + 8007ad4: 1c51 adds r1, r2, #1 + 8007ad6: 75f9 strb r1, [r7, #23] + 8007ad8: 4611 mov r1, r2 + 8007ada: 68ba ldr r2, [r7, #8] + 8007adc: 440a add r2, r1 + 8007ade: 781b ldrb r3, [r3, #0] + 8007ae0: 7013 strb r3, [r2, #0] + unicode[idx++] = 0U; + 8007ae2: 7dfb ldrb r3, [r7, #23] + 8007ae4: 1c5a adds r2, r3, #1 + 8007ae6: 75fa strb r2, [r7, #23] + 8007ae8: 461a mov r2, r3 + 8007aea: 68bb ldr r3, [r7, #8] + 8007aec: 4413 add r3, r2 + 8007aee: 2200 movs r2, #0 + 8007af0: 701a strb r2, [r3, #0] + while (*desc != '\0') + 8007af2: 68fb ldr r3, [r7, #12] + 8007af4: 781b ldrb r3, [r3, #0] + 8007af6: 2b00 cmp r3, #0 + 8007af8: d1e8 bne.n 8007acc + } + } +} + 8007afa: bf00 nop + 8007afc: 3718 adds r7, #24 + 8007afe: 46bd mov sp, r7 + 8007b00: bd80 pop {r7, pc} + +08007b02 : + * return the string length + * @param buf : pointer to the ascii string buffer + * @retval string length + */ +static uint8_t USBD_GetLen(uint8_t *buf) +{ + 8007b02: b480 push {r7} + 8007b04: b085 sub sp, #20 + 8007b06: af00 add r7, sp, #0 + 8007b08: 6078 str r0, [r7, #4] + uint8_t len = 0U; + 8007b0a: 2300 movs r3, #0 + 8007b0c: 73fb strb r3, [r7, #15] + + while (*buf != '\0') + 8007b0e: e005 b.n 8007b1c + { + len++; + 8007b10: 7bfb ldrb r3, [r7, #15] + 8007b12: 3301 adds r3, #1 + 8007b14: 73fb strb r3, [r7, #15] + buf++; + 8007b16: 687b ldr r3, [r7, #4] + 8007b18: 3301 adds r3, #1 + 8007b1a: 607b str r3, [r7, #4] + while (*buf != '\0') + 8007b1c: 687b ldr r3, [r7, #4] + 8007b1e: 781b ldrb r3, [r3, #0] + 8007b20: 2b00 cmp r3, #0 + 8007b22: d1f5 bne.n 8007b10 + } + + return len; + 8007b24: 7bfb ldrb r3, [r7, #15] +} + 8007b26: 4618 mov r0, r3 + 8007b28: 3714 adds r7, #20 + 8007b2a: 46bd mov sp, r7 + 8007b2c: bc80 pop {r7} + 8007b2e: 4770 bx lr + +08007b30 : +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint16_t len) +{ + 8007b30: b580 push {r7, lr} + 8007b32: b084 sub sp, #16 + 8007b34: af00 add r7, sp, #0 + 8007b36: 60f8 str r0, [r7, #12] + 8007b38: 60b9 str r1, [r7, #8] + 8007b3a: 4613 mov r3, r2 + 8007b3c: 80fb strh r3, [r7, #6] + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_IN; + 8007b3e: 68fb ldr r3, [r7, #12] + 8007b40: 2202 movs r2, #2 + 8007b42: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + pdev->ep_in[0].total_length = len; + 8007b46: 88fa ldrh r2, [r7, #6] + 8007b48: 68fb ldr r3, [r7, #12] + 8007b4a: 61da str r2, [r3, #28] + pdev->ep_in[0].rem_length = len; + 8007b4c: 88fa ldrh r2, [r7, #6] + 8007b4e: 68fb ldr r3, [r7, #12] + 8007b50: 621a str r2, [r3, #32] + + /* Start the transfer */ + USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + 8007b52: 88fb ldrh r3, [r7, #6] + 8007b54: 68ba ldr r2, [r7, #8] + 8007b56: 2100 movs r1, #0 + 8007b58: 68f8 ldr r0, [r7, #12] + 8007b5a: f002 fea9 bl 800a8b0 + + return USBD_OK; + 8007b5e: 2300 movs r3, #0 +} + 8007b60: 4618 mov r0, r3 + 8007b62: 3710 adds r7, #16 + 8007b64: 46bd mov sp, r7 + 8007b66: bd80 pop {r7, pc} + +08007b68 : +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint16_t len) +{ + 8007b68: b580 push {r7, lr} + 8007b6a: b084 sub sp, #16 + 8007b6c: af00 add r7, sp, #0 + 8007b6e: 60f8 str r0, [r7, #12] + 8007b70: 60b9 str r1, [r7, #8] + 8007b72: 4613 mov r3, r2 + 8007b74: 80fb strh r3, [r7, #6] + /* Start the next transfer */ + USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + 8007b76: 88fb ldrh r3, [r7, #6] + 8007b78: 68ba ldr r2, [r7, #8] + 8007b7a: 2100 movs r1, #0 + 8007b7c: 68f8 ldr r0, [r7, #12] + 8007b7e: f002 fe97 bl 800a8b0 + + return USBD_OK; + 8007b82: 2300 movs r3, #0 +} + 8007b84: 4618 mov r0, r3 + 8007b86: 3710 adds r7, #16 + 8007b88: 46bd mov sp, r7 + 8007b8a: bd80 pop {r7, pc} + +08007b8c : +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint16_t len) +{ + 8007b8c: b580 push {r7, lr} + 8007b8e: b084 sub sp, #16 + 8007b90: af00 add r7, sp, #0 + 8007b92: 60f8 str r0, [r7, #12] + 8007b94: 60b9 str r1, [r7, #8] + 8007b96: 4613 mov r3, r2 + 8007b98: 80fb strh r3, [r7, #6] + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_OUT; + 8007b9a: 68fb ldr r3, [r7, #12] + 8007b9c: 2203 movs r2, #3 + 8007b9e: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + pdev->ep_out[0].total_length = len; + 8007ba2: 88fa ldrh r2, [r7, #6] + 8007ba4: 68fb ldr r3, [r7, #12] + 8007ba6: f8c3 215c str.w r2, [r3, #348] ; 0x15c + pdev->ep_out[0].rem_length = len; + 8007baa: 88fa ldrh r2, [r7, #6] + 8007bac: 68fb ldr r3, [r7, #12] + 8007bae: f8c3 2160 str.w r2, [r3, #352] ; 0x160 + + /* Start the transfer */ + USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + 8007bb2: 88fb ldrh r3, [r7, #6] + 8007bb4: 68ba ldr r2, [r7, #8] + 8007bb6: 2100 movs r1, #0 + 8007bb8: 68f8 ldr r0, [r7, #12] + 8007bba: f002 fe9c bl 800a8f6 + + return USBD_OK; + 8007bbe: 2300 movs r3, #0 +} + 8007bc0: 4618 mov r0, r3 + 8007bc2: 3710 adds r7, #16 + 8007bc4: 46bd mov sp, r7 + 8007bc6: bd80 pop {r7, pc} + +08007bc8 : +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint16_t len) +{ + 8007bc8: b580 push {r7, lr} + 8007bca: b084 sub sp, #16 + 8007bcc: af00 add r7, sp, #0 + 8007bce: 60f8 str r0, [r7, #12] + 8007bd0: 60b9 str r1, [r7, #8] + 8007bd2: 4613 mov r3, r2 + 8007bd4: 80fb strh r3, [r7, #6] + USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + 8007bd6: 88fb ldrh r3, [r7, #6] + 8007bd8: 68ba ldr r2, [r7, #8] + 8007bda: 2100 movs r1, #0 + 8007bdc: 68f8 ldr r0, [r7, #12] + 8007bde: f002 fe8a bl 800a8f6 + + return USBD_OK; + 8007be2: 2300 movs r3, #0 +} + 8007be4: 4618 mov r0, r3 + 8007be6: 3710 adds r7, #16 + 8007be8: 46bd mov sp, r7 + 8007bea: bd80 pop {r7, pc} + +08007bec : +* send zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) +{ + 8007bec: b580 push {r7, lr} + 8007bee: b082 sub sp, #8 + 8007bf0: af00 add r7, sp, #0 + 8007bf2: 6078 str r0, [r7, #4] + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_IN; + 8007bf4: 687b ldr r3, [r7, #4] + 8007bf6: 2204 movs r2, #4 + 8007bf8: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + + /* Start the transfer */ + USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); + 8007bfc: 2300 movs r3, #0 + 8007bfe: 2200 movs r2, #0 + 8007c00: 2100 movs r1, #0 + 8007c02: 6878 ldr r0, [r7, #4] + 8007c04: f002 fe54 bl 800a8b0 + + return USBD_OK; + 8007c08: 2300 movs r3, #0 +} + 8007c0a: 4618 mov r0, r3 + 8007c0c: 3708 adds r7, #8 + 8007c0e: 46bd mov sp, r7 + 8007c10: bd80 pop {r7, pc} + +08007c12 : +* receive zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) +{ + 8007c12: b580 push {r7, lr} + 8007c14: b082 sub sp, #8 + 8007c16: af00 add r7, sp, #0 + 8007c18: 6078 str r0, [r7, #4] + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_OUT; + 8007c1a: 687b ldr r3, [r7, #4] + 8007c1c: 2205 movs r2, #5 + 8007c1e: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + + /* Start the transfer */ + USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + 8007c22: 2300 movs r3, #0 + 8007c24: 2200 movs r2, #0 + 8007c26: 2100 movs r1, #0 + 8007c28: 6878 ldr r0, [r7, #4] + 8007c2a: f002 fe64 bl 800a8f6 + + return USBD_OK; + 8007c2e: 2300 movs r3, #0 +} + 8007c30: 4618 mov r0, r3 + 8007c32: 3708 adds r7, #8 + 8007c34: 46bd mov sp, r7 + 8007c36: bd80 pop {r7, pc} + +08007c38 : + +extern void xPortSysTickHandler(void); + +/* Convert from CMSIS type osPriority to FreeRTOS priority number */ +static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority) +{ + 8007c38: b480 push {r7} + 8007c3a: b085 sub sp, #20 + 8007c3c: af00 add r7, sp, #0 + 8007c3e: 4603 mov r3, r0 + 8007c40: 80fb strh r3, [r7, #6] + unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY; + 8007c42: 2300 movs r3, #0 + 8007c44: 60fb str r3, [r7, #12] + + if (priority != osPriorityError) { + 8007c46: f9b7 3006 ldrsh.w r3, [r7, #6] + 8007c4a: 2b84 cmp r3, #132 ; 0x84 + 8007c4c: d005 beq.n 8007c5a + fpriority += (priority - osPriorityIdle); + 8007c4e: f9b7 2006 ldrsh.w r2, [r7, #6] + 8007c52: 68fb ldr r3, [r7, #12] + 8007c54: 4413 add r3, r2 + 8007c56: 3303 adds r3, #3 + 8007c58: 60fb str r3, [r7, #12] + } + + return fpriority; + 8007c5a: 68fb ldr r3, [r7, #12] +} + 8007c5c: 4618 mov r0, r3 + 8007c5e: 3714 adds r7, #20 + 8007c60: 46bd mov sp, r7 + 8007c62: bc80 pop {r7} + 8007c64: 4770 bx lr + +08007c66 : +* @param argument pointer that is passed to the thread function as start argument. +* @retval status code that indicates the execution status of the function +* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +*/ +osStatus osKernelStart (void) +{ + 8007c66: b580 push {r7, lr} + 8007c68: af00 add r7, sp, #0 + vTaskStartScheduler(); + 8007c6a: f000 fa4b bl 8008104 + + return osOK; + 8007c6e: 2300 movs r3, #0 +} + 8007c70: 4618 mov r0, r3 + 8007c72: bd80 pop {r7, pc} + +08007c74 : +* @param argument pointer that is passed to the thread function as start argument. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) +{ + 8007c74: b5f0 push {r4, r5, r6, r7, lr} + 8007c76: b087 sub sp, #28 + 8007c78: af02 add r7, sp, #8 + 8007c7a: 6078 str r0, [r7, #4] + 8007c7c: 6039 str r1, [r7, #0] + + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); +#else + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 8007c7e: 687b ldr r3, [r7, #4] + 8007c80: 685c ldr r4, [r3, #4] + 8007c82: 687b ldr r3, [r7, #4] + 8007c84: 681d ldr r5, [r3, #0] + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + 8007c86: 687b ldr r3, [r7, #4] + 8007c88: 691b ldr r3, [r3, #16] + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 8007c8a: b29e uxth r6, r3 + 8007c8c: 687b ldr r3, [r7, #4] + 8007c8e: f9b3 3008 ldrsh.w r3, [r3, #8] + 8007c92: 4618 mov r0, r3 + 8007c94: f7ff ffd0 bl 8007c38 + 8007c98: 4602 mov r2, r0 + 8007c9a: f107 030c add.w r3, r7, #12 + 8007c9e: 9301 str r3, [sp, #4] + 8007ca0: 9200 str r2, [sp, #0] + 8007ca2: 683b ldr r3, [r7, #0] + 8007ca4: 4632 mov r2, r6 + 8007ca6: 4629 mov r1, r5 + 8007ca8: 4620 mov r0, r4 + 8007caa: f000 f8cd bl 8007e48 + 8007cae: 4603 mov r3, r0 + 8007cb0: 2b01 cmp r3, #1 + 8007cb2: d001 beq.n 8007cb8 + &handle) != pdPASS) { + return NULL; + 8007cb4: 2300 movs r3, #0 + 8007cb6: e000 b.n 8007cba + } +#endif + + return handle; + 8007cb8: 68fb ldr r3, [r7, #12] +} + 8007cba: 4618 mov r0, r3 + 8007cbc: 3714 adds r7, #20 + 8007cbe: 46bd mov sp, r7 + 8007cc0: bdf0 pop {r4, r5, r6, r7, pc} + +08007cc2 : +* @brief Wait for Timeout (Time Delay) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelay (uint32_t millisec) +{ + 8007cc2: b580 push {r7, lr} + 8007cc4: b084 sub sp, #16 + 8007cc6: af00 add r7, sp, #0 + 8007cc8: 6078 str r0, [r7, #4] +#if INCLUDE_vTaskDelay + TickType_t ticks = millisec / portTICK_PERIOD_MS; + 8007cca: 687b ldr r3, [r7, #4] + 8007ccc: 60fb str r3, [r7, #12] + + vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */ + 8007cce: 68fb ldr r3, [r7, #12] + 8007cd0: 2b00 cmp r3, #0 + 8007cd2: d001 beq.n 8007cd8 + 8007cd4: 68fb ldr r3, [r7, #12] + 8007cd6: e000 b.n 8007cda + 8007cd8: 2301 movs r3, #1 + 8007cda: 4618 mov r0, r3 + 8007cdc: f000 f9de bl 800809c + + return osOK; + 8007ce0: 2300 movs r3, #0 +#else + (void) millisec; + + return osErrorResource; +#endif +} + 8007ce2: 4618 mov r0, r3 + 8007ce4: 3710 adds r7, #16 + 8007ce6: 46bd mov sp, r7 + 8007ce8: bd80 pop {r7, pc} + +08007cea : +/*----------------------------------------------------------- + * PUBLIC LIST API documented in list.h + *----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + 8007cea: b480 push {r7} + 8007cec: b083 sub sp, #12 + 8007cee: af00 add r7, sp, #0 + 8007cf0: 6078 str r0, [r7, #4] + /* The list structure contains a list item which is used to mark the + end of the list. To initialise the list the list end is inserted + as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 8007cf2: 687b ldr r3, [r7, #4] + 8007cf4: f103 0208 add.w r2, r3, #8 + 8007cf8: 687b ldr r3, [r7, #4] + 8007cfa: 605a str r2, [r3, #4] + + /* The list end value is the highest possible value in the list to + ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + 8007cfc: 687b ldr r3, [r7, #4] + 8007cfe: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8007d02: 609a str r2, [r3, #8] + + /* The list end next and previous pointers point to itself so we know + when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 8007d04: 687b ldr r3, [r7, #4] + 8007d06: f103 0208 add.w r2, r3, #8 + 8007d0a: 687b ldr r3, [r7, #4] + 8007d0c: 60da str r2, [r3, #12] + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 8007d0e: 687b ldr r3, [r7, #4] + 8007d10: f103 0208 add.w r2, r3, #8 + 8007d14: 687b ldr r3, [r7, #4] + 8007d16: 611a str r2, [r3, #16] + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + 8007d18: 687b ldr r3, [r7, #4] + 8007d1a: 2200 movs r2, #0 + 8007d1c: 601a str r2, [r3, #0] + + /* Write known values into the list if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} + 8007d1e: bf00 nop + 8007d20: 370c adds r7, #12 + 8007d22: 46bd mov sp, r7 + 8007d24: bc80 pop {r7} + 8007d26: 4770 bx lr + +08007d28 : +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + 8007d28: b480 push {r7} + 8007d2a: b083 sub sp, #12 + 8007d2c: af00 add r7, sp, #0 + 8007d2e: 6078 str r0, [r7, #4] + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pvContainer = NULL; + 8007d30: 687b ldr r3, [r7, #4] + 8007d32: 2200 movs r2, #0 + 8007d34: 611a str r2, [r3, #16] + + /* Write known values into the list item if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} + 8007d36: bf00 nop + 8007d38: 370c adds r7, #12 + 8007d3a: 46bd mov sp, r7 + 8007d3c: bc80 pop {r7} + 8007d3e: 4770 bx lr + +08007d40 : +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 8007d40: b480 push {r7} + 8007d42: b085 sub sp, #20 + 8007d44: af00 add r7, sp, #0 + 8007d46: 6078 str r0, [r7, #4] + 8007d48: 6039 str r1, [r7, #0] +ListItem_t * const pxIndex = pxList->pxIndex; + 8007d4a: 687b ldr r3, [r7, #4] + 8007d4c: 685b ldr r3, [r3, #4] + 8007d4e: 60fb str r3, [r7, #12] + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + makes the new list item the last item to be removed by a call to + listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + 8007d50: 683b ldr r3, [r7, #0] + 8007d52: 68fa ldr r2, [r7, #12] + 8007d54: 605a str r2, [r3, #4] + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + 8007d56: 68fb ldr r3, [r7, #12] + 8007d58: 689a ldr r2, [r3, #8] + 8007d5a: 683b ldr r3, [r7, #0] + 8007d5c: 609a str r2, [r3, #8] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + 8007d5e: 68fb ldr r3, [r7, #12] + 8007d60: 689b ldr r3, [r3, #8] + 8007d62: 683a ldr r2, [r7, #0] + 8007d64: 605a str r2, [r3, #4] + pxIndex->pxPrevious = pxNewListItem; + 8007d66: 68fb ldr r3, [r7, #12] + 8007d68: 683a ldr r2, [r7, #0] + 8007d6a: 609a str r2, [r3, #8] + + /* Remember which list the item is in. */ + pxNewListItem->pvContainer = ( void * ) pxList; + 8007d6c: 683b ldr r3, [r7, #0] + 8007d6e: 687a ldr r2, [r7, #4] + 8007d70: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 8007d72: 687b ldr r3, [r7, #4] + 8007d74: 681b ldr r3, [r3, #0] + 8007d76: 1c5a adds r2, r3, #1 + 8007d78: 687b ldr r3, [r7, #4] + 8007d7a: 601a str r2, [r3, #0] +} + 8007d7c: bf00 nop + 8007d7e: 3714 adds r7, #20 + 8007d80: 46bd mov sp, r7 + 8007d82: bc80 pop {r7} + 8007d84: 4770 bx lr + +08007d86 : +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 8007d86: b480 push {r7} + 8007d88: b085 sub sp, #20 + 8007d8a: af00 add r7, sp, #0 + 8007d8c: 6078 str r0, [r7, #4] + 8007d8e: 6039 str r1, [r7, #0] +ListItem_t *pxIterator; +const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + 8007d90: 683b ldr r3, [r7, #0] + 8007d92: 681b ldr r3, [r3, #0] + 8007d94: 60bb str r3, [r7, #8] + new list item should be placed after it. This ensures that TCB's which are + stored in ready lists (all of which have the same xItemValue value) get a + share of the CPU. However, if the xItemValue is the same as the back marker + the iteration loop below will not end. Therefore the value is checked + first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + 8007d96: 68bb ldr r3, [r7, #8] + 8007d98: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8007d9c: d103 bne.n 8007da6 + { + pxIterator = pxList->xListEnd.pxPrevious; + 8007d9e: 687b ldr r3, [r7, #4] + 8007da0: 691b ldr r3, [r3, #16] + 8007da2: 60fb str r3, [r7, #12] + 8007da4: e00c b.n 8007dc0 + 4) Using a queue or semaphore before it has been initialised or + before the scheduler has been started (are interrupts firing + before vTaskStartScheduler() has been called?). + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 8007da6: 687b ldr r3, [r7, #4] + 8007da8: 3308 adds r3, #8 + 8007daa: 60fb str r3, [r7, #12] + 8007dac: e002 b.n 8007db4 + 8007dae: 68fb ldr r3, [r7, #12] + 8007db0: 685b ldr r3, [r3, #4] + 8007db2: 60fb str r3, [r7, #12] + 8007db4: 68fb ldr r3, [r7, #12] + 8007db6: 685b ldr r3, [r3, #4] + 8007db8: 681b ldr r3, [r3, #0] + 8007dba: 68ba ldr r2, [r7, #8] + 8007dbc: 429a cmp r2, r3 + 8007dbe: d2f6 bcs.n 8007dae + /* There is nothing to do here, just iterating to the wanted + insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + 8007dc0: 68fb ldr r3, [r7, #12] + 8007dc2: 685a ldr r2, [r3, #4] + 8007dc4: 683b ldr r3, [r7, #0] + 8007dc6: 605a str r2, [r3, #4] + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + 8007dc8: 683b ldr r3, [r7, #0] + 8007dca: 685b ldr r3, [r3, #4] + 8007dcc: 683a ldr r2, [r7, #0] + 8007dce: 609a str r2, [r3, #8] + pxNewListItem->pxPrevious = pxIterator; + 8007dd0: 683b ldr r3, [r7, #0] + 8007dd2: 68fa ldr r2, [r7, #12] + 8007dd4: 609a str r2, [r3, #8] + pxIterator->pxNext = pxNewListItem; + 8007dd6: 68fb ldr r3, [r7, #12] + 8007dd8: 683a ldr r2, [r7, #0] + 8007dda: 605a str r2, [r3, #4] + + /* Remember which list the item is in. This allows fast removal of the + item later. */ + pxNewListItem->pvContainer = ( void * ) pxList; + 8007ddc: 683b ldr r3, [r7, #0] + 8007dde: 687a ldr r2, [r7, #4] + 8007de0: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 8007de2: 687b ldr r3, [r7, #4] + 8007de4: 681b ldr r3, [r3, #0] + 8007de6: 1c5a adds r2, r3, #1 + 8007de8: 687b ldr r3, [r7, #4] + 8007dea: 601a str r2, [r3, #0] +} + 8007dec: bf00 nop + 8007dee: 3714 adds r7, #20 + 8007df0: 46bd mov sp, r7 + 8007df2: bc80 pop {r7} + 8007df4: 4770 bx lr + +08007df6 : +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ + 8007df6: b480 push {r7} + 8007df8: b085 sub sp, #20 + 8007dfa: af00 add r7, sp, #0 + 8007dfc: 6078 str r0, [r7, #4] +/* The list item knows which list it is in. Obtain the list from the list +item. */ +List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer; + 8007dfe: 687b ldr r3, [r7, #4] + 8007e00: 691b ldr r3, [r3, #16] + 8007e02: 60fb str r3, [r7, #12] + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + 8007e04: 687b ldr r3, [r7, #4] + 8007e06: 685b ldr r3, [r3, #4] + 8007e08: 687a ldr r2, [r7, #4] + 8007e0a: 6892 ldr r2, [r2, #8] + 8007e0c: 609a str r2, [r3, #8] + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + 8007e0e: 687b ldr r3, [r7, #4] + 8007e10: 689b ldr r3, [r3, #8] + 8007e12: 687a ldr r2, [r7, #4] + 8007e14: 6852 ldr r2, [r2, #4] + 8007e16: 605a str r2, [r3, #4] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + 8007e18: 68fb ldr r3, [r7, #12] + 8007e1a: 685b ldr r3, [r3, #4] + 8007e1c: 687a ldr r2, [r7, #4] + 8007e1e: 429a cmp r2, r3 + 8007e20: d103 bne.n 8007e2a + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + 8007e22: 687b ldr r3, [r7, #4] + 8007e24: 689a ldr r2, [r3, #8] + 8007e26: 68fb ldr r3, [r7, #12] + 8007e28: 605a str r2, [r3, #4] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pvContainer = NULL; + 8007e2a: 687b ldr r3, [r7, #4] + 8007e2c: 2200 movs r2, #0 + 8007e2e: 611a str r2, [r3, #16] + ( pxList->uxNumberOfItems )--; + 8007e30: 68fb ldr r3, [r7, #12] + 8007e32: 681b ldr r3, [r3, #0] + 8007e34: 1e5a subs r2, r3, #1 + 8007e36: 68fb ldr r3, [r7, #12] + 8007e38: 601a str r2, [r3, #0] + + return pxList->uxNumberOfItems; + 8007e3a: 68fb ldr r3, [r7, #12] + 8007e3c: 681b ldr r3, [r3, #0] +} + 8007e3e: 4618 mov r0, r3 + 8007e40: 3714 adds r7, #20 + 8007e42: 46bd mov sp, r7 + 8007e44: bc80 pop {r7} + 8007e46: 4770 bx lr + +08007e48 : + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + 8007e48: b580 push {r7, lr} + 8007e4a: b08c sub sp, #48 ; 0x30 + 8007e4c: af04 add r7, sp, #16 + 8007e4e: 60f8 str r0, [r7, #12] + 8007e50: 60b9 str r1, [r7, #8] + 8007e52: 603b str r3, [r7, #0] + 8007e54: 4613 mov r3, r2 + 8007e56: 80fb strh r3, [r7, #6] + #else /* portSTACK_GROWTH */ + { + StackType_t *pxStack; + + /* Allocate space for the stack used by the task being created. */ + pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8007e58: 88fb ldrh r3, [r7, #6] + 8007e5a: 009b lsls r3, r3, #2 + 8007e5c: 4618 mov r0, r3 + 8007e5e: f000 fe35 bl 8008acc + 8007e62: 6178 str r0, [r7, #20] + + if( pxStack != NULL ) + 8007e64: 697b ldr r3, [r7, #20] + 8007e66: 2b00 cmp r3, #0 + 8007e68: d00e beq.n 8007e88 + { + /* Allocate space for the TCB. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e961 MISRA exception as the casts are only redundant for some paths. */ + 8007e6a: 2054 movs r0, #84 ; 0x54 + 8007e6c: f000 fe2e bl 8008acc + 8007e70: 61f8 str r0, [r7, #28] + + if( pxNewTCB != NULL ) + 8007e72: 69fb ldr r3, [r7, #28] + 8007e74: 2b00 cmp r3, #0 + 8007e76: d003 beq.n 8007e80 + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + 8007e78: 69fb ldr r3, [r7, #28] + 8007e7a: 697a ldr r2, [r7, #20] + 8007e7c: 631a str r2, [r3, #48] ; 0x30 + 8007e7e: e005 b.n 8007e8c + } + else + { + /* The stack cannot be used as the TCB was not created. Free + it again. */ + vPortFree( pxStack ); + 8007e80: 6978 ldr r0, [r7, #20] + 8007e82: f000 fee5 bl 8008c50 + 8007e86: e001 b.n 8007e8c + } + } + else + { + pxNewTCB = NULL; + 8007e88: 2300 movs r3, #0 + 8007e8a: 61fb str r3, [r7, #28] + } + } + #endif /* portSTACK_GROWTH */ + + if( pxNewTCB != NULL ) + 8007e8c: 69fb ldr r3, [r7, #28] + 8007e8e: 2b00 cmp r3, #0 + 8007e90: d013 beq.n 8007eba + task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + 8007e92: 88fa ldrh r2, [r7, #6] + 8007e94: 2300 movs r3, #0 + 8007e96: 9303 str r3, [sp, #12] + 8007e98: 69fb ldr r3, [r7, #28] + 8007e9a: 9302 str r3, [sp, #8] + 8007e9c: 6afb ldr r3, [r7, #44] ; 0x2c + 8007e9e: 9301 str r3, [sp, #4] + 8007ea0: 6abb ldr r3, [r7, #40] ; 0x28 + 8007ea2: 9300 str r3, [sp, #0] + 8007ea4: 683b ldr r3, [r7, #0] + 8007ea6: 68b9 ldr r1, [r7, #8] + 8007ea8: 68f8 ldr r0, [r7, #12] + 8007eaa: f000 f80e bl 8007eca + prvAddNewTaskToReadyList( pxNewTCB ); + 8007eae: 69f8 ldr r0, [r7, #28] + 8007eb0: f000 f88a bl 8007fc8 + xReturn = pdPASS; + 8007eb4: 2301 movs r3, #1 + 8007eb6: 61bb str r3, [r7, #24] + 8007eb8: e002 b.n 8007ec0 + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + 8007eba: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8007ebe: 61bb str r3, [r7, #24] + } + + return xReturn; + 8007ec0: 69bb ldr r3, [r7, #24] + } + 8007ec2: 4618 mov r0, r3 + 8007ec4: 3720 adds r7, #32 + 8007ec6: 46bd mov sp, r7 + 8007ec8: bd80 pop {r7, pc} + +08007eca : + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t *pxNewTCB, + const MemoryRegion_t * const xRegions ) +{ + 8007eca: b580 push {r7, lr} + 8007ecc: b088 sub sp, #32 + 8007ece: af00 add r7, sp, #0 + 8007ed0: 60f8 str r0, [r7, #12] + 8007ed2: 60b9 str r1, [r7, #8] + 8007ed4: 607a str r2, [r7, #4] + 8007ed6: 603b str r3, [r7, #0] + grows from high memory to low (as per the 80x86) or vice versa. + portSTACK_GROWTH is used to make the result positive or negative as required + by the port. */ + #if( portSTACK_GROWTH < 0 ) + { + pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + 8007ed8: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007eda: 6b1a ldr r2, [r3, #48] ; 0x30 + 8007edc: 687b ldr r3, [r7, #4] + 8007ede: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 + 8007ee2: 3b01 subs r3, #1 + 8007ee4: 009b lsls r3, r3, #2 + 8007ee6: 4413 add r3, r2 + 8007ee8: 61bb str r3, [r7, #24] + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. */ + 8007eea: 69bb ldr r3, [r7, #24] + 8007eec: f023 0307 bic.w r3, r3, #7 + 8007ef0: 61bb str r3, [r7, #24] + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + 8007ef2: 69bb ldr r3, [r7, #24] + 8007ef4: f003 0307 and.w r3, r3, #7 + 8007ef8: 2b00 cmp r3, #0 + 8007efa: d009 beq.n 8007f10 + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ +uint32_t ulNewBASEPRI; + + __asm volatile + 8007efc: f04f 0350 mov.w r3, #80 ; 0x50 + 8007f00: f383 8811 msr BASEPRI, r3 + 8007f04: f3bf 8f6f isb sy + 8007f08: f3bf 8f4f dsb sy + 8007f0c: 617b str r3, [r7, #20] + 8007f0e: e7fe b.n 8007f0e + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + } + #endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 8007f10: 2300 movs r3, #0 + 8007f12: 61fb str r3, [r7, #28] + 8007f14: e012 b.n 8007f3c + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + 8007f16: 68ba ldr r2, [r7, #8] + 8007f18: 69fb ldr r3, [r7, #28] + 8007f1a: 4413 add r3, r2 + 8007f1c: 7819 ldrb r1, [r3, #0] + 8007f1e: 6b3a ldr r2, [r7, #48] ; 0x30 + 8007f20: 69fb ldr r3, [r7, #28] + 8007f22: 4413 add r3, r2 + 8007f24: 3334 adds r3, #52 ; 0x34 + 8007f26: 460a mov r2, r1 + 8007f28: 701a strb r2, [r3, #0] + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + configMAX_TASK_NAME_LEN characters just in case the memory after the + string is not accessible (extremely unlikely). */ + if( pcName[ x ] == 0x00 ) + 8007f2a: 68ba ldr r2, [r7, #8] + 8007f2c: 69fb ldr r3, [r7, #28] + 8007f2e: 4413 add r3, r2 + 8007f30: 781b ldrb r3, [r3, #0] + 8007f32: 2b00 cmp r3, #0 + 8007f34: d006 beq.n 8007f44 + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 8007f36: 69fb ldr r3, [r7, #28] + 8007f38: 3301 adds r3, #1 + 8007f3a: 61fb str r3, [r7, #28] + 8007f3c: 69fb ldr r3, [r7, #28] + 8007f3e: 2b0f cmp r3, #15 + 8007f40: d9e9 bls.n 8007f16 + 8007f42: e000 b.n 8007f46 + { + break; + 8007f44: bf00 nop + } + } + + /* Ensure the name string is terminated in the case that the string length + was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + 8007f46: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f48: 2200 movs r2, #0 + 8007f4a: f883 2043 strb.w r2, [r3, #67] ; 0x43 + + /* This is used as an array index so must ensure it's not too large. First + remove the privilege bit if one is present. */ + if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + 8007f4e: 6abb ldr r3, [r7, #40] ; 0x28 + 8007f50: 2b06 cmp r3, #6 + 8007f52: d901 bls.n 8007f58 + { + uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + 8007f54: 2306 movs r3, #6 + 8007f56: 62bb str r3, [r7, #40] ; 0x28 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; + 8007f58: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f5a: 6aba ldr r2, [r7, #40] ; 0x28 + 8007f5c: 62da str r2, [r3, #44] ; 0x2c + #if ( configUSE_MUTEXES == 1 ) + { + pxNewTCB->uxBasePriority = uxPriority; + 8007f5e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f60: 6aba ldr r2, [r7, #40] ; 0x28 + 8007f62: 645a str r2, [r3, #68] ; 0x44 + pxNewTCB->uxMutexesHeld = 0; + 8007f64: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f66: 2200 movs r2, #0 + 8007f68: 649a str r2, [r3, #72] ; 0x48 + } + #endif /* configUSE_MUTEXES */ + + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + 8007f6a: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f6c: 3304 adds r3, #4 + 8007f6e: 4618 mov r0, r3 + 8007f70: f7ff feda bl 8007d28 + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + 8007f74: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f76: 3318 adds r3, #24 + 8007f78: 4618 mov r0, r3 + 8007f7a: f7ff fed5 bl 8007d28 + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + 8007f7e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f80: 6b3a ldr r2, [r7, #48] ; 0x30 + 8007f82: 611a str r2, [r3, #16] + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 8007f84: 6abb ldr r3, [r7, #40] ; 0x28 + 8007f86: f1c3 0207 rsb r2, r3, #7 + 8007f8a: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f8c: 619a str r2, [r3, #24] + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + 8007f8e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f90: 6b3a ldr r2, [r7, #48] ; 0x30 + 8007f92: 625a str r2, [r3, #36] ; 0x24 + } + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + pxNewTCB->ulNotifiedValue = 0; + 8007f94: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f96: 2200 movs r2, #0 + 8007f98: 64da str r2, [r3, #76] ; 0x4c + pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; + 8007f9a: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007f9c: 2200 movs r2, #0 + 8007f9e: f883 2050 strb.w r2, [r3, #80] ; 0x50 + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #else /* portUSING_MPU_WRAPPERS */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + 8007fa2: 683a ldr r2, [r7, #0] + 8007fa4: 68f9 ldr r1, [r7, #12] + 8007fa6: 69b8 ldr r0, [r7, #24] + 8007fa8: f000 fbee bl 8008788 + 8007fac: 4602 mov r2, r0 + 8007fae: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007fb0: 601a str r2, [r3, #0] + } + #endif /* portUSING_MPU_WRAPPERS */ + + if( ( void * ) pxCreatedTask != NULL ) + 8007fb2: 6afb ldr r3, [r7, #44] ; 0x2c + 8007fb4: 2b00 cmp r3, #0 + 8007fb6: d002 beq.n 8007fbe + { + /* Pass the handle out in an anonymous way. The handle can be used to + change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + 8007fb8: 6afb ldr r3, [r7, #44] ; 0x2c + 8007fba: 6b3a ldr r2, [r7, #48] ; 0x30 + 8007fbc: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 8007fbe: bf00 nop + 8007fc0: 3720 adds r7, #32 + 8007fc2: 46bd mov sp, r7 + 8007fc4: bd80 pop {r7, pc} + ... + +08007fc8 : +/*-----------------------------------------------------------*/ + +static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) +{ + 8007fc8: b580 push {r7, lr} + 8007fca: b082 sub sp, #8 + 8007fcc: af00 add r7, sp, #0 + 8007fce: 6078 str r0, [r7, #4] + /* Ensure interrupts don't access the task lists while the lists are being + updated. */ + taskENTER_CRITICAL(); + 8007fd0: f000 fcc2 bl 8008958 + { + uxCurrentNumberOfTasks++; + 8007fd4: 4b2a ldr r3, [pc, #168] ; (8008080 ) + 8007fd6: 681b ldr r3, [r3, #0] + 8007fd8: 3301 adds r3, #1 + 8007fda: 4a29 ldr r2, [pc, #164] ; (8008080 ) + 8007fdc: 6013 str r3, [r2, #0] + if( pxCurrentTCB == NULL ) + 8007fde: 4b29 ldr r3, [pc, #164] ; (8008084 ) + 8007fe0: 681b ldr r3, [r3, #0] + 8007fe2: 2b00 cmp r3, #0 + 8007fe4: d109 bne.n 8007ffa + { + /* There are no other tasks, or all the other tasks are in + the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + 8007fe6: 4a27 ldr r2, [pc, #156] ; (8008084 ) + 8007fe8: 687b ldr r3, [r7, #4] + 8007fea: 6013 str r3, [r2, #0] + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + 8007fec: 4b24 ldr r3, [pc, #144] ; (8008080 ) + 8007fee: 681b ldr r3, [r3, #0] + 8007ff0: 2b01 cmp r3, #1 + 8007ff2: d110 bne.n 8008016 + { + /* This is the first task to be created so do the preliminary + initialisation required. We will not recover if this call + fails, but we will report the failure. */ + prvInitialiseTaskLists(); + 8007ff4: f000 faa4 bl 8008540 + 8007ff8: e00d b.n 8008016 + else + { + /* If the scheduler is not already running, make this task the + current task if it is the highest priority task to be created + so far. */ + if( xSchedulerRunning == pdFALSE ) + 8007ffa: 4b23 ldr r3, [pc, #140] ; (8008088 ) + 8007ffc: 681b ldr r3, [r3, #0] + 8007ffe: 2b00 cmp r3, #0 + 8008000: d109 bne.n 8008016 + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + 8008002: 4b20 ldr r3, [pc, #128] ; (8008084 ) + 8008004: 681b ldr r3, [r3, #0] + 8008006: 6ada ldr r2, [r3, #44] ; 0x2c + 8008008: 687b ldr r3, [r7, #4] + 800800a: 6adb ldr r3, [r3, #44] ; 0x2c + 800800c: 429a cmp r2, r3 + 800800e: d802 bhi.n 8008016 + { + pxCurrentTCB = pxNewTCB; + 8008010: 4a1c ldr r2, [pc, #112] ; (8008084 ) + 8008012: 687b ldr r3, [r7, #4] + 8008014: 6013 str r3, [r2, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + 8008016: 4b1d ldr r3, [pc, #116] ; (800808c ) + 8008018: 681b ldr r3, [r3, #0] + 800801a: 3301 adds r3, #1 + 800801c: 4a1b ldr r2, [pc, #108] ; (800808c ) + 800801e: 6013 str r3, [r2, #0] + pxNewTCB->uxTCBNumber = uxTaskNumber; + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + 8008020: 687b ldr r3, [r7, #4] + 8008022: 6adb ldr r3, [r3, #44] ; 0x2c + 8008024: 2201 movs r2, #1 + 8008026: 409a lsls r2, r3 + 8008028: 4b19 ldr r3, [pc, #100] ; (8008090 ) + 800802a: 681b ldr r3, [r3, #0] + 800802c: 4313 orrs r3, r2 + 800802e: 4a18 ldr r2, [pc, #96] ; (8008090 ) + 8008030: 6013 str r3, [r2, #0] + 8008032: 687b ldr r3, [r7, #4] + 8008034: 6ada ldr r2, [r3, #44] ; 0x2c + 8008036: 4613 mov r3, r2 + 8008038: 009b lsls r3, r3, #2 + 800803a: 4413 add r3, r2 + 800803c: 009b lsls r3, r3, #2 + 800803e: 4a15 ldr r2, [pc, #84] ; (8008094 ) + 8008040: 441a add r2, r3 + 8008042: 687b ldr r3, [r7, #4] + 8008044: 3304 adds r3, #4 + 8008046: 4619 mov r1, r3 + 8008048: 4610 mov r0, r2 + 800804a: f7ff fe79 bl 8007d40 + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + 800804e: f000 fcb1 bl 80089b4 + + if( xSchedulerRunning != pdFALSE ) + 8008052: 4b0d ldr r3, [pc, #52] ; (8008088 ) + 8008054: 681b ldr r3, [r3, #0] + 8008056: 2b00 cmp r3, #0 + 8008058: d00e beq.n 8008078 + { + /* If the created task is of a higher priority than the current task + then it should run now. */ + if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + 800805a: 4b0a ldr r3, [pc, #40] ; (8008084 ) + 800805c: 681b ldr r3, [r3, #0] + 800805e: 6ada ldr r2, [r3, #44] ; 0x2c + 8008060: 687b ldr r3, [r7, #4] + 8008062: 6adb ldr r3, [r3, #44] ; 0x2c + 8008064: 429a cmp r2, r3 + 8008066: d207 bcs.n 8008078 + { + taskYIELD_IF_USING_PREEMPTION(); + 8008068: 4b0b ldr r3, [pc, #44] ; (8008098 ) + 800806a: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800806e: 601a str r2, [r3, #0] + 8008070: f3bf 8f4f dsb sy + 8008074: f3bf 8f6f isb sy + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 8008078: bf00 nop + 800807a: 3708 adds r7, #8 + 800807c: 46bd mov sp, r7 + 800807e: bd80 pop {r7, pc} + 8008080: 20000328 .word 0x20000328 + 8008084: 20000228 .word 0x20000228 + 8008088: 20000334 .word 0x20000334 + 800808c: 20000344 .word 0x20000344 + 8008090: 20000330 .word 0x20000330 + 8008094: 2000022c .word 0x2000022c + 8008098: e000ed04 .word 0xe000ed04 + +0800809c : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( const TickType_t xTicksToDelay ) + { + 800809c: b580 push {r7, lr} + 800809e: b084 sub sp, #16 + 80080a0: af00 add r7, sp, #0 + 80080a2: 6078 str r0, [r7, #4] + BaseType_t xAlreadyYielded = pdFALSE; + 80080a4: 2300 movs r3, #0 + 80080a6: 60fb str r3, [r7, #12] + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( TickType_t ) 0U ) + 80080a8: 687b ldr r3, [r7, #4] + 80080aa: 2b00 cmp r3, #0 + 80080ac: d016 beq.n 80080dc + { + configASSERT( uxSchedulerSuspended == 0 ); + 80080ae: 4b13 ldr r3, [pc, #76] ; (80080fc ) + 80080b0: 681b ldr r3, [r3, #0] + 80080b2: 2b00 cmp r3, #0 + 80080b4: d009 beq.n 80080ca + 80080b6: f04f 0350 mov.w r3, #80 ; 0x50 + 80080ba: f383 8811 msr BASEPRI, r3 + 80080be: f3bf 8f6f isb sy + 80080c2: f3bf 8f4f dsb sy + 80080c6: 60bb str r3, [r7, #8] + 80080c8: e7fe b.n 80080c8 + vTaskSuspendAll(); + 80080ca: f000 f861 bl 8008190 + list or removed from the blocked list until the scheduler + is resumed. + + This task cannot be in an event list as it is the currently + executing task. */ + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + 80080ce: 2100 movs r1, #0 + 80080d0: 6878 ldr r0, [r7, #4] + 80080d2: f000 faf3 bl 80086bc + } + xAlreadyYielded = xTaskResumeAll(); + 80080d6: f000 f869 bl 80081ac + 80080da: 60f8 str r0, [r7, #12] + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + 80080dc: 68fb ldr r3, [r7, #12] + 80080de: 2b00 cmp r3, #0 + 80080e0: d107 bne.n 80080f2 + { + portYIELD_WITHIN_API(); + 80080e2: 4b07 ldr r3, [pc, #28] ; (8008100 ) + 80080e4: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80080e8: 601a str r2, [r3, #0] + 80080ea: f3bf 8f4f dsb sy + 80080ee: f3bf 8f6f isb sy + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + 80080f2: bf00 nop + 80080f4: 3710 adds r7, #16 + 80080f6: 46bd mov sp, r7 + 80080f8: bd80 pop {r7, pc} + 80080fa: bf00 nop + 80080fc: 20000350 .word 0x20000350 + 8008100: e000ed04 .word 0xe000ed04 + +08008104 : + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ +/*-----------------------------------------------------------*/ + +void vTaskStartScheduler( void ) +{ + 8008104: b580 push {r7, lr} + 8008106: b086 sub sp, #24 + 8008108: af02 add r7, sp, #8 + } + } + #else + { + /* The Idle task is being created using dynamically allocated RAM. */ + xReturn = xTaskCreate( prvIdleTask, + 800810a: 4b1b ldr r3, [pc, #108] ; (8008178 ) + 800810c: 9301 str r3, [sp, #4] + 800810e: 2300 movs r3, #0 + 8008110: 9300 str r3, [sp, #0] + 8008112: 2300 movs r3, #0 + 8008114: 2280 movs r2, #128 ; 0x80 + 8008116: 4919 ldr r1, [pc, #100] ; (800817c ) + 8008118: 4819 ldr r0, [pc, #100] ; (8008180 ) + 800811a: f7ff fe95 bl 8007e48 + 800811e: 60f8 str r0, [r7, #12] + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TIMERS */ + + if( xReturn == pdPASS ) + 8008120: 68fb ldr r3, [r7, #12] + 8008122: 2b01 cmp r3, #1 + 8008124: d115 bne.n 8008152 + 8008126: f04f 0350 mov.w r3, #80 ; 0x50 + 800812a: f383 8811 msr BASEPRI, r3 + 800812e: f3bf 8f6f isb sy + 8008132: f3bf 8f4f dsb sy + 8008136: 60bb str r3, [r7, #8] + structure specific to the task that will run first. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + + xNextTaskUnblockTime = portMAX_DELAY; + 8008138: 4b12 ldr r3, [pc, #72] ; (8008184 ) + 800813a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800813e: 601a str r2, [r3, #0] + xSchedulerRunning = pdTRUE; + 8008140: 4b11 ldr r3, [pc, #68] ; (8008188 ) + 8008142: 2201 movs r2, #1 + 8008144: 601a str r2, [r3, #0] + xTickCount = ( TickType_t ) 0U; + 8008146: 4b11 ldr r3, [pc, #68] ; (800818c ) + 8008148: 2200 movs r2, #0 + 800814a: 601a str r2, [r3, #0] + FreeRTOSConfig.h file. */ + portCONFIGURE_TIMER_FOR_RUN_TIME_STATS(); + + /* Setting up the timer tick is hardware specific and thus in the + portable interface. */ + if( xPortStartScheduler() != pdFALSE ) + 800814c: f000 fb94 bl 8008878 + } + + /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, + meaning xIdleTaskHandle is not used anywhere else. */ + ( void ) xIdleTaskHandle; +} + 8008150: e00d b.n 800816e + configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); + 8008152: 68fb ldr r3, [r7, #12] + 8008154: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8008158: d109 bne.n 800816e + 800815a: f04f 0350 mov.w r3, #80 ; 0x50 + 800815e: f383 8811 msr BASEPRI, r3 + 8008162: f3bf 8f6f isb sy + 8008166: f3bf 8f4f dsb sy + 800816a: 607b str r3, [r7, #4] + 800816c: e7fe b.n 800816c +} + 800816e: bf00 nop + 8008170: 3710 adds r7, #16 + 8008172: 46bd mov sp, r7 + 8008174: bd80 pop {r7, pc} + 8008176: bf00 nop + 8008178: 2000034c .word 0x2000034c + 800817c: 0800c6a4 .word 0x0800c6a4 + 8008180: 08008511 .word 0x08008511 + 8008184: 20000348 .word 0x20000348 + 8008188: 20000334 .word 0x20000334 + 800818c: 2000032c .word 0x2000032c + +08008190 : + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + 8008190: b480 push {r7} + 8008192: af00 add r7, sp, #0 + /* A critical section is not required as the variable is of type + BaseType_t. Please read Richard Barry's reply in the following link to a + post in the FreeRTOS support forum before reporting this as a bug! - + http://goo.gl/wu4acr */ + ++uxSchedulerSuspended; + 8008194: 4b04 ldr r3, [pc, #16] ; (80081a8 ) + 8008196: 681b ldr r3, [r3, #0] + 8008198: 3301 adds r3, #1 + 800819a: 4a03 ldr r2, [pc, #12] ; (80081a8 ) + 800819c: 6013 str r3, [r2, #0] +} + 800819e: bf00 nop + 80081a0: 46bd mov sp, r7 + 80081a2: bc80 pop {r7} + 80081a4: 4770 bx lr + 80081a6: bf00 nop + 80081a8: 20000350 .word 0x20000350 + +080081ac : + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll( void ) +{ + 80081ac: b580 push {r7, lr} + 80081ae: b084 sub sp, #16 + 80081b0: af00 add r7, sp, #0 +TCB_t *pxTCB = NULL; + 80081b2: 2300 movs r3, #0 + 80081b4: 60fb str r3, [r7, #12] +BaseType_t xAlreadyYielded = pdFALSE; + 80081b6: 2300 movs r3, #0 + 80081b8: 60bb str r3, [r7, #8] + + /* If uxSchedulerSuspended is zero then this function does not match a + previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended ); + 80081ba: 4b41 ldr r3, [pc, #260] ; (80082c0 ) + 80081bc: 681b ldr r3, [r3, #0] + 80081be: 2b00 cmp r3, #0 + 80081c0: d109 bne.n 80081d6 + 80081c2: f04f 0350 mov.w r3, #80 ; 0x50 + 80081c6: f383 8811 msr BASEPRI, r3 + 80081ca: f3bf 8f6f isb sy + 80081ce: f3bf 8f4f dsb sy + 80081d2: 603b str r3, [r7, #0] + 80081d4: e7fe b.n 80081d4 + /* It is possible that an ISR caused a task to be removed from an event + list while the scheduler was suspended. If this was the case then the + removed task will have been added to the xPendingReadyList. Once the + scheduler has been resumed it is safe to move all the pending ready + tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + 80081d6: f000 fbbf bl 8008958 + { + --uxSchedulerSuspended; + 80081da: 4b39 ldr r3, [pc, #228] ; (80082c0 ) + 80081dc: 681b ldr r3, [r3, #0] + 80081de: 3b01 subs r3, #1 + 80081e0: 4a37 ldr r2, [pc, #220] ; (80082c0 ) + 80081e2: 6013 str r3, [r2, #0] + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 80081e4: 4b36 ldr r3, [pc, #216] ; (80082c0 ) + 80081e6: 681b ldr r3, [r3, #0] + 80081e8: 2b00 cmp r3, #0 + 80081ea: d161 bne.n 80082b0 + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + 80081ec: 4b35 ldr r3, [pc, #212] ; (80082c4 ) + 80081ee: 681b ldr r3, [r3, #0] + 80081f0: 2b00 cmp r3, #0 + 80081f2: d05d beq.n 80082b0 + { + /* Move any readied tasks from the pending list into the + appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 80081f4: e02e b.n 8008254 + { + pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); + 80081f6: 4b34 ldr r3, [pc, #208] ; (80082c8 ) + 80081f8: 68db ldr r3, [r3, #12] + 80081fa: 68db ldr r3, [r3, #12] + 80081fc: 60fb str r3, [r7, #12] + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 80081fe: 68fb ldr r3, [r7, #12] + 8008200: 3318 adds r3, #24 + 8008202: 4618 mov r0, r3 + 8008204: f7ff fdf7 bl 8007df6 + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8008208: 68fb ldr r3, [r7, #12] + 800820a: 3304 adds r3, #4 + 800820c: 4618 mov r0, r3 + 800820e: f7ff fdf2 bl 8007df6 + prvAddTaskToReadyList( pxTCB ); + 8008212: 68fb ldr r3, [r7, #12] + 8008214: 6adb ldr r3, [r3, #44] ; 0x2c + 8008216: 2201 movs r2, #1 + 8008218: 409a lsls r2, r3 + 800821a: 4b2c ldr r3, [pc, #176] ; (80082cc ) + 800821c: 681b ldr r3, [r3, #0] + 800821e: 4313 orrs r3, r2 + 8008220: 4a2a ldr r2, [pc, #168] ; (80082cc ) + 8008222: 6013 str r3, [r2, #0] + 8008224: 68fb ldr r3, [r7, #12] + 8008226: 6ada ldr r2, [r3, #44] ; 0x2c + 8008228: 4613 mov r3, r2 + 800822a: 009b lsls r3, r3, #2 + 800822c: 4413 add r3, r2 + 800822e: 009b lsls r3, r3, #2 + 8008230: 4a27 ldr r2, [pc, #156] ; (80082d0 ) + 8008232: 441a add r2, r3 + 8008234: 68fb ldr r3, [r7, #12] + 8008236: 3304 adds r3, #4 + 8008238: 4619 mov r1, r3 + 800823a: 4610 mov r0, r2 + 800823c: f7ff fd80 bl 8007d40 + + /* If the moved task has a priority higher than the current + task then a yield must be performed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 8008240: 68fb ldr r3, [r7, #12] + 8008242: 6ada ldr r2, [r3, #44] ; 0x2c + 8008244: 4b23 ldr r3, [pc, #140] ; (80082d4 ) + 8008246: 681b ldr r3, [r3, #0] + 8008248: 6adb ldr r3, [r3, #44] ; 0x2c + 800824a: 429a cmp r2, r3 + 800824c: d302 bcc.n 8008254 + { + xYieldPending = pdTRUE; + 800824e: 4b22 ldr r3, [pc, #136] ; (80082d8 ) + 8008250: 2201 movs r2, #1 + 8008252: 601a str r2, [r3, #0] + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 8008254: 4b1c ldr r3, [pc, #112] ; (80082c8 ) + 8008256: 681b ldr r3, [r3, #0] + 8008258: 2b00 cmp r3, #0 + 800825a: d1cc bne.n 80081f6 + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( pxTCB != NULL ) + 800825c: 68fb ldr r3, [r7, #12] + 800825e: 2b00 cmp r3, #0 + 8008260: d001 beq.n 8008266 + which may have prevented the next unblock time from being + re-calculated, in which case re-calculate it now. Mainly + important for low power tickless implementations, where + this can prevent an unnecessary exit from low power + state. */ + prvResetNextTaskUnblockTime(); + 8008262: f000 f9e9 bl 8008638 + /* If any ticks occurred while the scheduler was suspended then + they should be processed now. This ensures the tick count does + not slip, and that any delayed tasks are resumed at the correct + time. */ + { + UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */ + 8008266: 4b1d ldr r3, [pc, #116] ; (80082dc ) + 8008268: 681b ldr r3, [r3, #0] + 800826a: 607b str r3, [r7, #4] + + if( uxPendedCounts > ( UBaseType_t ) 0U ) + 800826c: 687b ldr r3, [r7, #4] + 800826e: 2b00 cmp r3, #0 + 8008270: d010 beq.n 8008294 + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + 8008272: f000 f837 bl 80082e4 + 8008276: 4603 mov r3, r0 + 8008278: 2b00 cmp r3, #0 + 800827a: d002 beq.n 8008282 + { + xYieldPending = pdTRUE; + 800827c: 4b16 ldr r3, [pc, #88] ; (80082d8 ) + 800827e: 2201 movs r2, #1 + 8008280: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + --uxPendedCounts; + 8008282: 687b ldr r3, [r7, #4] + 8008284: 3b01 subs r3, #1 + 8008286: 607b str r3, [r7, #4] + } while( uxPendedCounts > ( UBaseType_t ) 0U ); + 8008288: 687b ldr r3, [r7, #4] + 800828a: 2b00 cmp r3, #0 + 800828c: d1f1 bne.n 8008272 + + uxPendedTicks = 0; + 800828e: 4b13 ldr r3, [pc, #76] ; (80082dc ) + 8008290: 2200 movs r2, #0 + 8008292: 601a str r2, [r3, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xYieldPending != pdFALSE ) + 8008294: 4b10 ldr r3, [pc, #64] ; (80082d8 ) + 8008296: 681b ldr r3, [r3, #0] + 8008298: 2b00 cmp r3, #0 + 800829a: d009 beq.n 80082b0 + { + #if( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + 800829c: 2301 movs r3, #1 + 800829e: 60bb str r3, [r7, #8] + } + #endif + taskYIELD_IF_USING_PREEMPTION(); + 80082a0: 4b0f ldr r3, [pc, #60] ; (80082e0 ) + 80082a2: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80082a6: 601a str r2, [r3, #0] + 80082a8: f3bf 8f4f dsb sy + 80082ac: f3bf 8f6f isb sy + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + 80082b0: f000 fb80 bl 80089b4 + + return xAlreadyYielded; + 80082b4: 68bb ldr r3, [r7, #8] +} + 80082b6: 4618 mov r0, r3 + 80082b8: 3710 adds r7, #16 + 80082ba: 46bd mov sp, r7 + 80082bc: bd80 pop {r7, pc} + 80082be: bf00 nop + 80082c0: 20000350 .word 0x20000350 + 80082c4: 20000328 .word 0x20000328 + 80082c8: 200002e8 .word 0x200002e8 + 80082cc: 20000330 .word 0x20000330 + 80082d0: 2000022c .word 0x2000022c + 80082d4: 20000228 .word 0x20000228 + 80082d8: 2000033c .word 0x2000033c + 80082dc: 20000338 .word 0x20000338 + 80082e0: e000ed04 .word 0xe000ed04 + +080082e4 : + +#endif /* INCLUDE_xTaskAbortDelay */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick( void ) +{ + 80082e4: b580 push {r7, lr} + 80082e6: b086 sub sp, #24 + 80082e8: af00 add r7, sp, #0 +TCB_t * pxTCB; +TickType_t xItemValue; +BaseType_t xSwitchRequired = pdFALSE; + 80082ea: 2300 movs r3, #0 + 80082ec: 617b str r3, [r7, #20] + + /* Called by the portable layer each time a tick interrupt occurs. + Increments the tick then checks to see if the new tick value will cause any + tasks to be unblocked. */ + traceTASK_INCREMENT_TICK( xTickCount ); + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 80082ee: 4b50 ldr r3, [pc, #320] ; (8008430 ) + 80082f0: 681b ldr r3, [r3, #0] + 80082f2: 2b00 cmp r3, #0 + 80082f4: f040 808c bne.w 8008410 + { + /* Minor optimisation. The tick count cannot change in this + block. */ + const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; + 80082f8: 4b4e ldr r3, [pc, #312] ; (8008434 ) + 80082fa: 681b ldr r3, [r3, #0] + 80082fc: 3301 adds r3, #1 + 80082fe: 613b str r3, [r7, #16] + + /* Increment the RTOS tick, switching the delayed and overflowed + delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + 8008300: 4a4c ldr r2, [pc, #304] ; (8008434 ) + 8008302: 693b ldr r3, [r7, #16] + 8008304: 6013 str r3, [r2, #0] + + if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + 8008306: 693b ldr r3, [r7, #16] + 8008308: 2b00 cmp r3, #0 + 800830a: d11f bne.n 800834c + { + taskSWITCH_DELAYED_LISTS(); + 800830c: 4b4a ldr r3, [pc, #296] ; (8008438 ) + 800830e: 681b ldr r3, [r3, #0] + 8008310: 681b ldr r3, [r3, #0] + 8008312: 2b00 cmp r3, #0 + 8008314: d009 beq.n 800832a + 8008316: f04f 0350 mov.w r3, #80 ; 0x50 + 800831a: f383 8811 msr BASEPRI, r3 + 800831e: f3bf 8f6f isb sy + 8008322: f3bf 8f4f dsb sy + 8008326: 603b str r3, [r7, #0] + 8008328: e7fe b.n 8008328 + 800832a: 4b43 ldr r3, [pc, #268] ; (8008438 ) + 800832c: 681b ldr r3, [r3, #0] + 800832e: 60fb str r3, [r7, #12] + 8008330: 4b42 ldr r3, [pc, #264] ; (800843c ) + 8008332: 681b ldr r3, [r3, #0] + 8008334: 4a40 ldr r2, [pc, #256] ; (8008438 ) + 8008336: 6013 str r3, [r2, #0] + 8008338: 4a40 ldr r2, [pc, #256] ; (800843c ) + 800833a: 68fb ldr r3, [r7, #12] + 800833c: 6013 str r3, [r2, #0] + 800833e: 4b40 ldr r3, [pc, #256] ; (8008440 ) + 8008340: 681b ldr r3, [r3, #0] + 8008342: 3301 adds r3, #1 + 8008344: 4a3e ldr r2, [pc, #248] ; (8008440 ) + 8008346: 6013 str r3, [r2, #0] + 8008348: f000 f976 bl 8008638 + + /* See if this tick has made a timeout expire. Tasks are stored in + the queue in the order of their wake time - meaning once one task + has been found whose block time has not expired there is no need to + look any further down the list. */ + if( xConstTickCount >= xNextTaskUnblockTime ) + 800834c: 4b3d ldr r3, [pc, #244] ; (8008444 ) + 800834e: 681b ldr r3, [r3, #0] + 8008350: 693a ldr r2, [r7, #16] + 8008352: 429a cmp r2, r3 + 8008354: d34d bcc.n 80083f2 + { + for( ;; ) + { + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 8008356: 4b38 ldr r3, [pc, #224] ; (8008438 ) + 8008358: 681b ldr r3, [r3, #0] + 800835a: 681b ldr r3, [r3, #0] + 800835c: 2b00 cmp r3, #0 + 800835e: d101 bne.n 8008364 + 8008360: 2301 movs r3, #1 + 8008362: e000 b.n 8008366 + 8008364: 2300 movs r3, #0 + 8008366: 2b00 cmp r3, #0 + 8008368: d004 beq.n 8008374 + /* The delayed list is empty. Set xNextTaskUnblockTime + to the maximum possible value so it is extremely + unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass + next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800836a: 4b36 ldr r3, [pc, #216] ; (8008444 ) + 800836c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8008370: 601a str r2, [r3, #0] + break; + 8008372: e03e b.n 80083f2 + { + /* The delayed list is not empty, get the value of the + item at the head of the delayed list. This is the time + at which the task at the head of the delayed list must + be removed from the Blocked state. */ + pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); + 8008374: 4b30 ldr r3, [pc, #192] ; (8008438 ) + 8008376: 681b ldr r3, [r3, #0] + 8008378: 68db ldr r3, [r3, #12] + 800837a: 68db ldr r3, [r3, #12] + 800837c: 60bb str r3, [r7, #8] + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + 800837e: 68bb ldr r3, [r7, #8] + 8008380: 685b ldr r3, [r3, #4] + 8008382: 607b str r3, [r7, #4] + + if( xConstTickCount < xItemValue ) + 8008384: 693a ldr r2, [r7, #16] + 8008386: 687b ldr r3, [r7, #4] + 8008388: 429a cmp r2, r3 + 800838a: d203 bcs.n 8008394 + /* It is not time to unblock this item yet, but the + item value is the time at which the task at the head + of the blocked list must be removed from the Blocked + state - so record the item value in + xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + 800838c: 4a2d ldr r2, [pc, #180] ; (8008444 ) + 800838e: 687b ldr r3, [r7, #4] + 8008390: 6013 str r3, [r2, #0] + break; + 8008392: e02e b.n 80083f2 + { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 8008394: 68bb ldr r3, [r7, #8] + 8008396: 3304 adds r3, #4 + 8008398: 4618 mov r0, r3 + 800839a: f7ff fd2c bl 8007df6 + + /* Is the task waiting on an event also? If so remove + it from the event list. */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + 800839e: 68bb ldr r3, [r7, #8] + 80083a0: 6a9b ldr r3, [r3, #40] ; 0x28 + 80083a2: 2b00 cmp r3, #0 + 80083a4: d004 beq.n 80083b0 + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 80083a6: 68bb ldr r3, [r7, #8] + 80083a8: 3318 adds r3, #24 + 80083aa: 4618 mov r0, r3 + 80083ac: f7ff fd23 bl 8007df6 + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + list. */ + prvAddTaskToReadyList( pxTCB ); + 80083b0: 68bb ldr r3, [r7, #8] + 80083b2: 6adb ldr r3, [r3, #44] ; 0x2c + 80083b4: 2201 movs r2, #1 + 80083b6: 409a lsls r2, r3 + 80083b8: 4b23 ldr r3, [pc, #140] ; (8008448 ) + 80083ba: 681b ldr r3, [r3, #0] + 80083bc: 4313 orrs r3, r2 + 80083be: 4a22 ldr r2, [pc, #136] ; (8008448 ) + 80083c0: 6013 str r3, [r2, #0] + 80083c2: 68bb ldr r3, [r7, #8] + 80083c4: 6ada ldr r2, [r3, #44] ; 0x2c + 80083c6: 4613 mov r3, r2 + 80083c8: 009b lsls r3, r3, #2 + 80083ca: 4413 add r3, r2 + 80083cc: 009b lsls r3, r3, #2 + 80083ce: 4a1f ldr r2, [pc, #124] ; (800844c ) + 80083d0: 441a add r2, r3 + 80083d2: 68bb ldr r3, [r7, #8] + 80083d4: 3304 adds r3, #4 + 80083d6: 4619 mov r1, r3 + 80083d8: 4610 mov r0, r2 + 80083da: f7ff fcb1 bl 8007d40 + { + /* Preemption is on, but a context switch should + only be performed if the unblocked task has a + priority that is equal to or higher than the + currently executing task. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 80083de: 68bb ldr r3, [r7, #8] + 80083e0: 6ada ldr r2, [r3, #44] ; 0x2c + 80083e2: 4b1b ldr r3, [pc, #108] ; (8008450 ) + 80083e4: 681b ldr r3, [r3, #0] + 80083e6: 6adb ldr r3, [r3, #44] ; 0x2c + 80083e8: 429a cmp r2, r3 + 80083ea: d3b4 bcc.n 8008356 + { + xSwitchRequired = pdTRUE; + 80083ec: 2301 movs r3, #1 + 80083ee: 617b str r3, [r7, #20] + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 80083f0: e7b1 b.n 8008356 + /* Tasks of equal priority to the currently running task will share + processing time (time slice) if preemption is on, and the application + writer has not explicitly turned time slicing off. */ + #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + 80083f2: 4b17 ldr r3, [pc, #92] ; (8008450 ) + 80083f4: 681b ldr r3, [r3, #0] + 80083f6: 6ada ldr r2, [r3, #44] ; 0x2c + 80083f8: 4914 ldr r1, [pc, #80] ; (800844c ) + 80083fa: 4613 mov r3, r2 + 80083fc: 009b lsls r3, r3, #2 + 80083fe: 4413 add r3, r2 + 8008400: 009b lsls r3, r3, #2 + 8008402: 440b add r3, r1 + 8008404: 681b ldr r3, [r3, #0] + 8008406: 2b01 cmp r3, #1 + 8008408: d907 bls.n 800841a + { + xSwitchRequired = pdTRUE; + 800840a: 2301 movs r3, #1 + 800840c: 617b str r3, [r7, #20] + 800840e: e004 b.n 800841a + } + #endif /* configUSE_TICK_HOOK */ + } + else + { + ++uxPendedTicks; + 8008410: 4b10 ldr r3, [pc, #64] ; (8008454 ) + 8008412: 681b ldr r3, [r3, #0] + 8008414: 3301 adds r3, #1 + 8008416: 4a0f ldr r2, [pc, #60] ; (8008454 ) + 8008418: 6013 str r3, [r2, #0] + #endif + } + + #if ( configUSE_PREEMPTION == 1 ) + { + if( xYieldPending != pdFALSE ) + 800841a: 4b0f ldr r3, [pc, #60] ; (8008458 ) + 800841c: 681b ldr r3, [r3, #0] + 800841e: 2b00 cmp r3, #0 + 8008420: d001 beq.n 8008426 + { + xSwitchRequired = pdTRUE; + 8008422: 2301 movs r3, #1 + 8008424: 617b str r3, [r7, #20] + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + + return xSwitchRequired; + 8008426: 697b ldr r3, [r7, #20] +} + 8008428: 4618 mov r0, r3 + 800842a: 3718 adds r7, #24 + 800842c: 46bd mov sp, r7 + 800842e: bd80 pop {r7, pc} + 8008430: 20000350 .word 0x20000350 + 8008434: 2000032c .word 0x2000032c + 8008438: 200002e0 .word 0x200002e0 + 800843c: 200002e4 .word 0x200002e4 + 8008440: 20000340 .word 0x20000340 + 8008444: 20000348 .word 0x20000348 + 8008448: 20000330 .word 0x20000330 + 800844c: 2000022c .word 0x2000022c + 8008450: 20000228 .word 0x20000228 + 8008454: 20000338 .word 0x20000338 + 8008458: 2000033c .word 0x2000033c + +0800845c : + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + 800845c: b480 push {r7} + 800845e: b087 sub sp, #28 + 8008460: af00 add r7, sp, #0 + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + 8008462: 4b26 ldr r3, [pc, #152] ; (80084fc ) + 8008464: 681b ldr r3, [r3, #0] + 8008466: 2b00 cmp r3, #0 + 8008468: d003 beq.n 8008472 + { + /* The scheduler is currently suspended - do not allow a context + switch. */ + xYieldPending = pdTRUE; + 800846a: 4b25 ldr r3, [pc, #148] ; (8008500 ) + 800846c: 2201 movs r2, #1 + 800846e: 601a str r2, [r3, #0] + structure specific to this task. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + } +} + 8008470: e03e b.n 80084f0 + xYieldPending = pdFALSE; + 8008472: 4b23 ldr r3, [pc, #140] ; (8008500 ) + 8008474: 2200 movs r2, #0 + 8008476: 601a str r2, [r3, #0] + taskSELECT_HIGHEST_PRIORITY_TASK(); + 8008478: 4b22 ldr r3, [pc, #136] ; (8008504 ) + 800847a: 681b ldr r3, [r3, #0] + 800847c: 60fb str r3, [r7, #12] + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + 800847e: 68fb ldr r3, [r7, #12] + 8008480: fab3 f383 clz r3, r3 + 8008484: 72fb strb r3, [r7, #11] + return ucReturn; + 8008486: 7afb ldrb r3, [r7, #11] + 8008488: f1c3 031f rsb r3, r3, #31 + 800848c: 617b str r3, [r7, #20] + 800848e: 491e ldr r1, [pc, #120] ; (8008508 ) + 8008490: 697a ldr r2, [r7, #20] + 8008492: 4613 mov r3, r2 + 8008494: 009b lsls r3, r3, #2 + 8008496: 4413 add r3, r2 + 8008498: 009b lsls r3, r3, #2 + 800849a: 440b add r3, r1 + 800849c: 681b ldr r3, [r3, #0] + 800849e: 2b00 cmp r3, #0 + 80084a0: d109 bne.n 80084b6 + __asm volatile + 80084a2: f04f 0350 mov.w r3, #80 ; 0x50 + 80084a6: f383 8811 msr BASEPRI, r3 + 80084aa: f3bf 8f6f isb sy + 80084ae: f3bf 8f4f dsb sy + 80084b2: 607b str r3, [r7, #4] + 80084b4: e7fe b.n 80084b4 + 80084b6: 697a ldr r2, [r7, #20] + 80084b8: 4613 mov r3, r2 + 80084ba: 009b lsls r3, r3, #2 + 80084bc: 4413 add r3, r2 + 80084be: 009b lsls r3, r3, #2 + 80084c0: 4a11 ldr r2, [pc, #68] ; (8008508 ) + 80084c2: 4413 add r3, r2 + 80084c4: 613b str r3, [r7, #16] + 80084c6: 693b ldr r3, [r7, #16] + 80084c8: 685b ldr r3, [r3, #4] + 80084ca: 685a ldr r2, [r3, #4] + 80084cc: 693b ldr r3, [r7, #16] + 80084ce: 605a str r2, [r3, #4] + 80084d0: 693b ldr r3, [r7, #16] + 80084d2: 685a ldr r2, [r3, #4] + 80084d4: 693b ldr r3, [r7, #16] + 80084d6: 3308 adds r3, #8 + 80084d8: 429a cmp r2, r3 + 80084da: d104 bne.n 80084e6 + 80084dc: 693b ldr r3, [r7, #16] + 80084de: 685b ldr r3, [r3, #4] + 80084e0: 685a ldr r2, [r3, #4] + 80084e2: 693b ldr r3, [r7, #16] + 80084e4: 605a str r2, [r3, #4] + 80084e6: 693b ldr r3, [r7, #16] + 80084e8: 685b ldr r3, [r3, #4] + 80084ea: 68db ldr r3, [r3, #12] + 80084ec: 4a07 ldr r2, [pc, #28] ; (800850c ) + 80084ee: 6013 str r3, [r2, #0] +} + 80084f0: bf00 nop + 80084f2: 371c adds r7, #28 + 80084f4: 46bd mov sp, r7 + 80084f6: bc80 pop {r7} + 80084f8: 4770 bx lr + 80084fa: bf00 nop + 80084fc: 20000350 .word 0x20000350 + 8008500: 2000033c .word 0x2000033c + 8008504: 20000330 .word 0x20000330 + 8008508: 2000022c .word 0x2000022c + 800850c: 20000228 .word 0x20000228 + +08008510 : + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + 8008510: b580 push {r7, lr} + 8008512: b082 sub sp, #8 + 8008514: af00 add r7, sp, #0 + 8008516: 6078 str r0, [r7, #4] + + for( ;; ) + { + /* See if any tasks have deleted themselves - if so then the idle task + is responsible for freeing the deleted task's TCB and stack. */ + prvCheckTasksWaitingTermination(); + 8008518: f000 f852 bl 80085c0 + + A critical region is not required here as we are just reading from + the list, and an occasional incorrect value will not matter. If + the ready list at the idle priority contains more than one task + then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) + 800851c: 4b06 ldr r3, [pc, #24] ; (8008538 ) + 800851e: 681b ldr r3, [r3, #0] + 8008520: 2b01 cmp r3, #1 + 8008522: d9f9 bls.n 8008518 + { + taskYIELD(); + 8008524: 4b05 ldr r3, [pc, #20] ; (800853c ) + 8008526: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800852a: 601a str r2, [r3, #0] + 800852c: f3bf 8f4f dsb sy + 8008530: f3bf 8f6f isb sy + prvCheckTasksWaitingTermination(); + 8008534: e7f0 b.n 8008518 + 8008536: bf00 nop + 8008538: 2000022c .word 0x2000022c + 800853c: e000ed04 .word 0xe000ed04 + +08008540 : + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ + 8008540: b580 push {r7, lr} + 8008542: b082 sub sp, #8 + 8008544: af00 add r7, sp, #0 +UBaseType_t uxPriority; + + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 8008546: 2300 movs r3, #0 + 8008548: 607b str r3, [r7, #4] + 800854a: e00c b.n 8008566 + { + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + 800854c: 687a ldr r2, [r7, #4] + 800854e: 4613 mov r3, r2 + 8008550: 009b lsls r3, r3, #2 + 8008552: 4413 add r3, r2 + 8008554: 009b lsls r3, r3, #2 + 8008556: 4a12 ldr r2, [pc, #72] ; (80085a0 ) + 8008558: 4413 add r3, r2 + 800855a: 4618 mov r0, r3 + 800855c: f7ff fbc5 bl 8007cea + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 8008560: 687b ldr r3, [r7, #4] + 8008562: 3301 adds r3, #1 + 8008564: 607b str r3, [r7, #4] + 8008566: 687b ldr r3, [r7, #4] + 8008568: 2b06 cmp r3, #6 + 800856a: d9ef bls.n 800854c + } + + vListInitialise( &xDelayedTaskList1 ); + 800856c: 480d ldr r0, [pc, #52] ; (80085a4 ) + 800856e: f7ff fbbc bl 8007cea + vListInitialise( &xDelayedTaskList2 ); + 8008572: 480d ldr r0, [pc, #52] ; (80085a8 ) + 8008574: f7ff fbb9 bl 8007cea + vListInitialise( &xPendingReadyList ); + 8008578: 480c ldr r0, [pc, #48] ; (80085ac ) + 800857a: f7ff fbb6 bl 8007cea + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( &xTasksWaitingTermination ); + 800857e: 480c ldr r0, [pc, #48] ; (80085b0 ) + 8008580: f7ff fbb3 bl 8007cea + } + #endif /* INCLUDE_vTaskDelete */ + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( &xSuspendedTaskList ); + 8008584: 480b ldr r0, [pc, #44] ; (80085b4 ) + 8008586: f7ff fbb0 bl 8007cea + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + 800858a: 4b0b ldr r3, [pc, #44] ; (80085b8 ) + 800858c: 4a05 ldr r2, [pc, #20] ; (80085a4 ) + 800858e: 601a str r2, [r3, #0] + pxOverflowDelayedTaskList = &xDelayedTaskList2; + 8008590: 4b0a ldr r3, [pc, #40] ; (80085bc ) + 8008592: 4a05 ldr r2, [pc, #20] ; (80085a8 ) + 8008594: 601a str r2, [r3, #0] +} + 8008596: bf00 nop + 8008598: 3708 adds r7, #8 + 800859a: 46bd mov sp, r7 + 800859c: bd80 pop {r7, pc} + 800859e: bf00 nop + 80085a0: 2000022c .word 0x2000022c + 80085a4: 200002b8 .word 0x200002b8 + 80085a8: 200002cc .word 0x200002cc + 80085ac: 200002e8 .word 0x200002e8 + 80085b0: 200002fc .word 0x200002fc + 80085b4: 20000314 .word 0x20000314 + 80085b8: 200002e0 .word 0x200002e0 + 80085bc: 200002e4 .word 0x200002e4 + +080085c0 : +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + 80085c0: b580 push {r7, lr} + 80085c2: b082 sub sp, #8 + 80085c4: af00 add r7, sp, #0 + { + TCB_t *pxTCB; + + /* uxDeletedTasksWaitingCleanUp is used to prevent vTaskSuspendAll() + being called too often in the idle task. */ + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + 80085c6: e019 b.n 80085fc + { + taskENTER_CRITICAL(); + 80085c8: f000 f9c6 bl 8008958 + { + pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); + 80085cc: 4b0f ldr r3, [pc, #60] ; (800860c ) + 80085ce: 68db ldr r3, [r3, #12] + 80085d0: 68db ldr r3, [r3, #12] + 80085d2: 607b str r3, [r7, #4] + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 80085d4: 687b ldr r3, [r7, #4] + 80085d6: 3304 adds r3, #4 + 80085d8: 4618 mov r0, r3 + 80085da: f7ff fc0c bl 8007df6 + --uxCurrentNumberOfTasks; + 80085de: 4b0c ldr r3, [pc, #48] ; (8008610 ) + 80085e0: 681b ldr r3, [r3, #0] + 80085e2: 3b01 subs r3, #1 + 80085e4: 4a0a ldr r2, [pc, #40] ; (8008610 ) + 80085e6: 6013 str r3, [r2, #0] + --uxDeletedTasksWaitingCleanUp; + 80085e8: 4b0a ldr r3, [pc, #40] ; (8008614 ) + 80085ea: 681b ldr r3, [r3, #0] + 80085ec: 3b01 subs r3, #1 + 80085ee: 4a09 ldr r2, [pc, #36] ; (8008614 ) + 80085f0: 6013 str r3, [r2, #0] + } + taskEXIT_CRITICAL(); + 80085f2: f000 f9df bl 80089b4 + + prvDeleteTCB( pxTCB ); + 80085f6: 6878 ldr r0, [r7, #4] + 80085f8: f000 f80e bl 8008618 + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + 80085fc: 4b05 ldr r3, [pc, #20] ; (8008614 ) + 80085fe: 681b ldr r3, [r3, #0] + 8008600: 2b00 cmp r3, #0 + 8008602: d1e1 bne.n 80085c8 + } + } + #endif /* INCLUDE_vTaskDelete */ +} + 8008604: bf00 nop + 8008606: 3708 adds r7, #8 + 8008608: 46bd mov sp, r7 + 800860a: bd80 pop {r7, pc} + 800860c: 200002fc .word 0x200002fc + 8008610: 20000328 .word 0x20000328 + 8008614: 20000310 .word 0x20000310 + +08008618 : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t *pxTCB ) + { + 8008618: b580 push {r7, lr} + 800861a: b082 sub sp, #8 + 800861c: af00 add r7, sp, #0 + 800861e: 6078 str r0, [r7, #4] + + #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) + { + /* The task can only have been allocated dynamically - free both + the stack and TCB. */ + vPortFree( pxTCB->pxStack ); + 8008620: 687b ldr r3, [r7, #4] + 8008622: 6b1b ldr r3, [r3, #48] ; 0x30 + 8008624: 4618 mov r0, r3 + 8008626: f000 fb13 bl 8008c50 + vPortFree( pxTCB ); + 800862a: 6878 ldr r0, [r7, #4] + 800862c: f000 fb10 bl 8008c50 + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + 8008630: bf00 nop + 8008632: 3708 adds r7, #8 + 8008634: 46bd mov sp, r7 + 8008636: bd80 pop {r7, pc} + +08008638 : + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime( void ) +{ + 8008638: b480 push {r7} + 800863a: b083 sub sp, #12 + 800863c: af00 add r7, sp, #0 +TCB_t *pxTCB; + + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 800863e: 4b0e ldr r3, [pc, #56] ; (8008678 ) + 8008640: 681b ldr r3, [r3, #0] + 8008642: 681b ldr r3, [r3, #0] + 8008644: 2b00 cmp r3, #0 + 8008646: d101 bne.n 800864c + 8008648: 2301 movs r3, #1 + 800864a: e000 b.n 800864e + 800864c: 2300 movs r3, #0 + 800864e: 2b00 cmp r3, #0 + 8008650: d004 beq.n 800865c + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + the maximum possible value so it is extremely unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass until + there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + 8008652: 4b0a ldr r3, [pc, #40] ; (800867c ) + 8008654: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8008658: 601a str r2, [r3, #0] + which the task at the head of the delayed list should be removed + from the Blocked state. */ + ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + } +} + 800865a: e008 b.n 800866e + ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); + 800865c: 4b06 ldr r3, [pc, #24] ; (8008678 ) + 800865e: 681b ldr r3, [r3, #0] + 8008660: 68db ldr r3, [r3, #12] + 8008662: 68db ldr r3, [r3, #12] + 8008664: 607b str r3, [r7, #4] + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + 8008666: 687b ldr r3, [r7, #4] + 8008668: 685b ldr r3, [r3, #4] + 800866a: 4a04 ldr r2, [pc, #16] ; (800867c ) + 800866c: 6013 str r3, [r2, #0] +} + 800866e: bf00 nop + 8008670: 370c adds r7, #12 + 8008672: 46bd mov sp, r7 + 8008674: bc80 pop {r7} + 8008676: 4770 bx lr + 8008678: 200002e0 .word 0x200002e0 + 800867c: 20000348 .word 0x20000348 + +08008680 : +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + + BaseType_t xTaskGetSchedulerState( void ) + { + 8008680: b480 push {r7} + 8008682: b083 sub sp, #12 + 8008684: af00 add r7, sp, #0 + BaseType_t xReturn; + + if( xSchedulerRunning == pdFALSE ) + 8008686: 4b0b ldr r3, [pc, #44] ; (80086b4 ) + 8008688: 681b ldr r3, [r3, #0] + 800868a: 2b00 cmp r3, #0 + 800868c: d102 bne.n 8008694 + { + xReturn = taskSCHEDULER_NOT_STARTED; + 800868e: 2301 movs r3, #1 + 8008690: 607b str r3, [r7, #4] + 8008692: e008 b.n 80086a6 + } + else + { + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 8008694: 4b08 ldr r3, [pc, #32] ; (80086b8 ) + 8008696: 681b ldr r3, [r3, #0] + 8008698: 2b00 cmp r3, #0 + 800869a: d102 bne.n 80086a2 + { + xReturn = taskSCHEDULER_RUNNING; + 800869c: 2302 movs r3, #2 + 800869e: 607b str r3, [r7, #4] + 80086a0: e001 b.n 80086a6 + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + 80086a2: 2300 movs r3, #0 + 80086a4: 607b str r3, [r7, #4] + } + } + + return xReturn; + 80086a6: 687b ldr r3, [r7, #4] + } + 80086a8: 4618 mov r0, r3 + 80086aa: 370c adds r7, #12 + 80086ac: 46bd mov sp, r7 + 80086ae: bc80 pop {r7} + 80086b0: 4770 bx lr + 80086b2: bf00 nop + 80086b4: 20000334 .word 0x20000334 + 80086b8: 20000350 .word 0x20000350 + +080086bc : +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) +{ + 80086bc: b580 push {r7, lr} + 80086be: b084 sub sp, #16 + 80086c0: af00 add r7, sp, #0 + 80086c2: 6078 str r0, [r7, #4] + 80086c4: 6039 str r1, [r7, #0] +TickType_t xTimeToWake; +const TickType_t xConstTickCount = xTickCount; + 80086c6: 4b29 ldr r3, [pc, #164] ; (800876c ) + 80086c8: 681b ldr r3, [r3, #0] + 80086ca: 60fb str r3, [r7, #12] + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 80086cc: 4b28 ldr r3, [pc, #160] ; (8008770 ) + 80086ce: 681b ldr r3, [r3, #0] + 80086d0: 3304 adds r3, #4 + 80086d2: 4618 mov r0, r3 + 80086d4: f7ff fb8f bl 8007df6 + 80086d8: 4603 mov r3, r0 + 80086da: 2b00 cmp r3, #0 + 80086dc: d10b bne.n 80086f6 + { + /* The current task must be in a ready list, so there is no need to + check, and the port reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); + 80086de: 4b24 ldr r3, [pc, #144] ; (8008770 ) + 80086e0: 681b ldr r3, [r3, #0] + 80086e2: 6adb ldr r3, [r3, #44] ; 0x2c + 80086e4: 2201 movs r2, #1 + 80086e6: fa02 f303 lsl.w r3, r2, r3 + 80086ea: 43da mvns r2, r3 + 80086ec: 4b21 ldr r3, [pc, #132] ; (8008774 ) + 80086ee: 681b ldr r3, [r3, #0] + 80086f0: 4013 ands r3, r2 + 80086f2: 4a20 ldr r2, [pc, #128] ; (8008774 ) + 80086f4: 6013 str r3, [r2, #0] + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + 80086f6: 687b ldr r3, [r7, #4] + 80086f8: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80086fc: d10a bne.n 8008714 + 80086fe: 683b ldr r3, [r7, #0] + 8008700: 2b00 cmp r3, #0 + 8008702: d007 beq.n 8008714 + { + /* Add the task to the suspended task list instead of a delayed task + list to ensure it is not woken by a timing event. It will block + indefinitely. */ + vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8008704: 4b1a ldr r3, [pc, #104] ; (8008770 ) + 8008706: 681b ldr r3, [r3, #0] + 8008708: 3304 adds r3, #4 + 800870a: 4619 mov r1, r3 + 800870c: 481a ldr r0, [pc, #104] ; (8008778 ) + 800870e: f7ff fb17 bl 8007d40 + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} + 8008712: e026 b.n 8008762 + xTimeToWake = xConstTickCount + xTicksToWait; + 8008714: 68fa ldr r2, [r7, #12] + 8008716: 687b ldr r3, [r7, #4] + 8008718: 4413 add r3, r2 + 800871a: 60bb str r3, [r7, #8] + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + 800871c: 4b14 ldr r3, [pc, #80] ; (8008770 ) + 800871e: 681b ldr r3, [r3, #0] + 8008720: 68ba ldr r2, [r7, #8] + 8008722: 605a str r2, [r3, #4] + if( xTimeToWake < xConstTickCount ) + 8008724: 68ba ldr r2, [r7, #8] + 8008726: 68fb ldr r3, [r7, #12] + 8008728: 429a cmp r2, r3 + 800872a: d209 bcs.n 8008740 + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 800872c: 4b13 ldr r3, [pc, #76] ; (800877c ) + 800872e: 681a ldr r2, [r3, #0] + 8008730: 4b0f ldr r3, [pc, #60] ; (8008770 ) + 8008732: 681b ldr r3, [r3, #0] + 8008734: 3304 adds r3, #4 + 8008736: 4619 mov r1, r3 + 8008738: 4610 mov r0, r2 + 800873a: f7ff fb24 bl 8007d86 +} + 800873e: e010 b.n 8008762 + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 8008740: 4b0f ldr r3, [pc, #60] ; (8008780 ) + 8008742: 681a ldr r2, [r3, #0] + 8008744: 4b0a ldr r3, [pc, #40] ; (8008770 ) + 8008746: 681b ldr r3, [r3, #0] + 8008748: 3304 adds r3, #4 + 800874a: 4619 mov r1, r3 + 800874c: 4610 mov r0, r2 + 800874e: f7ff fb1a bl 8007d86 + if( xTimeToWake < xNextTaskUnblockTime ) + 8008752: 4b0c ldr r3, [pc, #48] ; (8008784 ) + 8008754: 681b ldr r3, [r3, #0] + 8008756: 68ba ldr r2, [r7, #8] + 8008758: 429a cmp r2, r3 + 800875a: d202 bcs.n 8008762 + xNextTaskUnblockTime = xTimeToWake; + 800875c: 4a09 ldr r2, [pc, #36] ; (8008784 ) + 800875e: 68bb ldr r3, [r7, #8] + 8008760: 6013 str r3, [r2, #0] +} + 8008762: bf00 nop + 8008764: 3710 adds r7, #16 + 8008766: 46bd mov sp, r7 + 8008768: bd80 pop {r7, pc} + 800876a: bf00 nop + 800876c: 2000032c .word 0x2000032c + 8008770: 20000228 .word 0x20000228 + 8008774: 20000330 .word 0x20000330 + 8008778: 20000314 .word 0x20000314 + 800877c: 200002e4 .word 0x200002e4 + 8008780: 200002e0 .word 0x200002e0 + 8008784: 20000348 .word 0x20000348 + +08008788 : + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + 8008788: b480 push {r7} + 800878a: b085 sub sp, #20 + 800878c: af00 add r7, sp, #0 + 800878e: 60f8 str r0, [r7, #12] + 8008790: 60b9 str r1, [r7, #8] + 8008792: 607a str r2, [r7, #4] + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + 8008794: 68fb ldr r3, [r7, #12] + 8008796: 3b04 subs r3, #4 + 8008798: 60fb str r3, [r7, #12] + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + 800879a: 68fb ldr r3, [r7, #12] + 800879c: f04f 7280 mov.w r2, #16777216 ; 0x1000000 + 80087a0: 601a str r2, [r3, #0] + pxTopOfStack--; + 80087a2: 68fb ldr r3, [r7, #12] + 80087a4: 3b04 subs r3, #4 + 80087a6: 60fb str r3, [r7, #12] + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + 80087a8: 68bb ldr r3, [r7, #8] + 80087aa: f023 0201 bic.w r2, r3, #1 + 80087ae: 68fb ldr r3, [r7, #12] + 80087b0: 601a str r2, [r3, #0] + pxTopOfStack--; + 80087b2: 68fb ldr r3, [r7, #12] + 80087b4: 3b04 subs r3, #4 + 80087b6: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + 80087b8: 4a08 ldr r2, [pc, #32] ; (80087dc ) + 80087ba: 68fb ldr r3, [r7, #12] + 80087bc: 601a str r2, [r3, #0] + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + 80087be: 68fb ldr r3, [r7, #12] + 80087c0: 3b14 subs r3, #20 + 80087c2: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + 80087c4: 687a ldr r2, [r7, #4] + 80087c6: 68fb ldr r3, [r7, #12] + 80087c8: 601a str r2, [r3, #0] + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + 80087ca: 68fb ldr r3, [r7, #12] + 80087cc: 3b20 subs r3, #32 + 80087ce: 60fb str r3, [r7, #12] + + return pxTopOfStack; + 80087d0: 68fb ldr r3, [r7, #12] +} + 80087d2: 4618 mov r0, r3 + 80087d4: 3714 adds r7, #20 + 80087d6: 46bd mov sp, r7 + 80087d8: bc80 pop {r7} + 80087da: 4770 bx lr + 80087dc: 080087e1 .word 0x080087e1 + +080087e0 : +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + 80087e0: b480 push {r7} + 80087e2: b085 sub sp, #20 + 80087e4: af00 add r7, sp, #0 +volatile uint32_t ulDummy = 0UL; + 80087e6: 2300 movs r3, #0 + 80087e8: 607b str r3, [r7, #4] + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + 80087ea: 4b10 ldr r3, [pc, #64] ; (800882c ) + 80087ec: 681b ldr r3, [r3, #0] + 80087ee: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80087f2: d009 beq.n 8008808 + 80087f4: f04f 0350 mov.w r3, #80 ; 0x50 + 80087f8: f383 8811 msr BASEPRI, r3 + 80087fc: f3bf 8f6f isb sy + 8008800: f3bf 8f4f dsb sy + 8008804: 60fb str r3, [r7, #12] + 8008806: e7fe b.n 8008806 + 8008808: f04f 0350 mov.w r3, #80 ; 0x50 + 800880c: f383 8811 msr BASEPRI, r3 + 8008810: f3bf 8f6f isb sy + 8008814: f3bf 8f4f dsb sy + 8008818: 60bb str r3, [r7, #8] + portDISABLE_INTERRUPTS(); + while( ulDummy == 0 ) + 800881a: bf00 nop + 800881c: 687b ldr r3, [r7, #4] + 800881e: 2b00 cmp r3, #0 + 8008820: d0fc beq.n 800881c + about code appearing after this function is called - making ulDummy + volatile makes the compiler think the function could return and + therefore not output an 'unreachable code' warning for code that appears + after it. */ + } +} + 8008822: bf00 nop + 8008824: 3714 adds r7, #20 + 8008826: 46bd mov sp, r7 + 8008828: bc80 pop {r7} + 800882a: 4770 bx lr + 800882c: 20000130 .word 0x20000130 + +08008830 : +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + 8008830: 4b07 ldr r3, [pc, #28] ; (8008850 ) + 8008832: 6819 ldr r1, [r3, #0] + 8008834: 6808 ldr r0, [r1, #0] + 8008836: e8b0 0ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp} + 800883a: f380 8809 msr PSP, r0 + 800883e: f3bf 8f6f isb sy + 8008842: f04f 0000 mov.w r0, #0 + 8008846: f380 8811 msr BASEPRI, r0 + 800884a: f04e 0e0d orr.w lr, lr, #13 + 800884e: 4770 bx lr + +08008850 : + 8008850: 20000228 .word 0x20000228 + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} + 8008854: bf00 nop + 8008856: bf00 nop + +08008858 : +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + __asm volatile( + 8008858: 4806 ldr r0, [pc, #24] ; (8008874 ) + 800885a: 6800 ldr r0, [r0, #0] + 800885c: 6800 ldr r0, [r0, #0] + 800885e: f380 8808 msr MSP, r0 + 8008862: b662 cpsie i + 8008864: b661 cpsie f + 8008866: f3bf 8f4f dsb sy + 800886a: f3bf 8f6f isb sy + 800886e: df00 svc 0 + 8008870: bf00 nop + " dsb \n" + " isb \n" + " svc 0 \n" /* System call to start first task. */ + " nop \n" + ); +} + 8008872: bf00 nop + 8008874: e000ed08 .word 0xe000ed08 + +08008878 : + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + 8008878: b580 push {r7, lr} + 800887a: b084 sub sp, #16 + 800887c: af00 add r7, sp, #0 + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + 800887e: 4b31 ldr r3, [pc, #196] ; (8008944 ) + 8008880: 60fb str r3, [r7, #12] + functions can be called. ISR safe functions are those that end in + "FromISR". FreeRTOS maintains separate thread and ISR API functions to + ensure interrupt entry is as fast and simple as possible. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + 8008882: 68fb ldr r3, [r7, #12] + 8008884: 781b ldrb r3, [r3, #0] + 8008886: b2db uxtb r3, r3 + 8008888: 607b str r3, [r7, #4] + + /* Determine the number of priority bits available. First write to all + possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + 800888a: 68fb ldr r3, [r7, #12] + 800888c: 22ff movs r2, #255 ; 0xff + 800888e: 701a strb r2, [r3, #0] + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + 8008890: 68fb ldr r3, [r7, #12] + 8008892: 781b ldrb r3, [r3, #0] + 8008894: b2db uxtb r3, r3 + 8008896: 70fb strb r3, [r7, #3] + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + 8008898: 78fb ldrb r3, [r7, #3] + 800889a: b2db uxtb r3, r3 + 800889c: f003 0350 and.w r3, r3, #80 ; 0x50 + 80088a0: b2da uxtb r2, r3 + 80088a2: 4b29 ldr r3, [pc, #164] ; (8008948 ) + 80088a4: 701a strb r2, [r3, #0] + + /* Calculate the maximum acceptable priority group value for the number + of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + 80088a6: 4b29 ldr r3, [pc, #164] ; (800894c ) + 80088a8: 2207 movs r2, #7 + 80088aa: 601a str r2, [r3, #0] + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + 80088ac: e009 b.n 80088c2 + { + ulMaxPRIGROUPValue--; + 80088ae: 4b27 ldr r3, [pc, #156] ; (800894c ) + 80088b0: 681b ldr r3, [r3, #0] + 80088b2: 3b01 subs r3, #1 + 80088b4: 4a25 ldr r2, [pc, #148] ; (800894c ) + 80088b6: 6013 str r3, [r2, #0] + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + 80088b8: 78fb ldrb r3, [r7, #3] + 80088ba: b2db uxtb r3, r3 + 80088bc: 005b lsls r3, r3, #1 + 80088be: b2db uxtb r3, r3 + 80088c0: 70fb strb r3, [r7, #3] + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + 80088c2: 78fb ldrb r3, [r7, #3] + 80088c4: b2db uxtb r3, r3 + 80088c6: f003 0380 and.w r3, r3, #128 ; 0x80 + 80088ca: 2b80 cmp r3, #128 ; 0x80 + 80088cc: d0ef beq.n 80088ae + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + 80088ce: 4b1f ldr r3, [pc, #124] ; (800894c ) + 80088d0: 681b ldr r3, [r3, #0] + 80088d2: f1c3 0307 rsb r3, r3, #7 + 80088d6: 2b04 cmp r3, #4 + 80088d8: d009 beq.n 80088ee + 80088da: f04f 0350 mov.w r3, #80 ; 0x50 + 80088de: f383 8811 msr BASEPRI, r3 + 80088e2: f3bf 8f6f isb sy + 80088e6: f3bf 8f4f dsb sy + 80088ea: 60bb str r3, [r7, #8] + 80088ec: e7fe b.n 80088ec + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + 80088ee: 4b17 ldr r3, [pc, #92] ; (800894c ) + 80088f0: 681b ldr r3, [r3, #0] + 80088f2: 021b lsls r3, r3, #8 + 80088f4: 4a15 ldr r2, [pc, #84] ; (800894c ) + 80088f6: 6013 str r3, [r2, #0] + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + 80088f8: 4b14 ldr r3, [pc, #80] ; (800894c ) + 80088fa: 681b ldr r3, [r3, #0] + 80088fc: f403 63e0 and.w r3, r3, #1792 ; 0x700 + 8008900: 4a12 ldr r2, [pc, #72] ; (800894c ) + 8008902: 6013 str r3, [r2, #0] + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + 8008904: 687b ldr r3, [r7, #4] + 8008906: b2da uxtb r2, r3 + 8008908: 68fb ldr r3, [r7, #12] + 800890a: 701a strb r2, [r3, #0] + } + #endif /* conifgASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; + 800890c: 4b10 ldr r3, [pc, #64] ; (8008950 ) + 800890e: 681b ldr r3, [r3, #0] + 8008910: 4a0f ldr r2, [pc, #60] ; (8008950 ) + 8008912: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8008916: 6013 str r3, [r2, #0] + portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; + 8008918: 4b0d ldr r3, [pc, #52] ; (8008950 ) + 800891a: 681b ldr r3, [r3, #0] + 800891c: 4a0c ldr r2, [pc, #48] ; (8008950 ) + 800891e: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000 + 8008922: 6013 str r3, [r2, #0] + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + vPortSetupTimerInterrupt(); + 8008924: f000 f8b0 bl 8008a88 + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + 8008928: 4b0a ldr r3, [pc, #40] ; (8008954 ) + 800892a: 2200 movs r2, #0 + 800892c: 601a str r2, [r3, #0] + + /* Start the first task. */ + prvPortStartFirstTask(); + 800892e: f7ff ff93 bl 8008858 + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. Call + vTaskSwitchContext() so link time optimisation does not remove the + symbol. */ + vTaskSwitchContext(); + 8008932: f7ff fd93 bl 800845c + prvTaskExitError(); + 8008936: f7ff ff53 bl 80087e0 + + /* Should not get here! */ + return 0; + 800893a: 2300 movs r3, #0 +} + 800893c: 4618 mov r0, r3 + 800893e: 3710 adds r7, #16 + 8008940: 46bd mov sp, r7 + 8008942: bd80 pop {r7, pc} + 8008944: e000e400 .word 0xe000e400 + 8008948: 20000354 .word 0x20000354 + 800894c: 20000358 .word 0x20000358 + 8008950: e000ed20 .word 0xe000ed20 + 8008954: 20000130 .word 0x20000130 + +08008958 : + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + 8008958: b480 push {r7} + 800895a: b083 sub sp, #12 + 800895c: af00 add r7, sp, #0 + 800895e: f04f 0350 mov.w r3, #80 ; 0x50 + 8008962: f383 8811 msr BASEPRI, r3 + 8008966: f3bf 8f6f isb sy + 800896a: f3bf 8f4f dsb sy + 800896e: 607b str r3, [r7, #4] + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + 8008970: 4b0e ldr r3, [pc, #56] ; (80089ac ) + 8008972: 681b ldr r3, [r3, #0] + 8008974: 3301 adds r3, #1 + 8008976: 4a0d ldr r2, [pc, #52] ; (80089ac ) + 8008978: 6013 str r3, [r2, #0] + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + 800897a: 4b0c ldr r3, [pc, #48] ; (80089ac ) + 800897c: 681b ldr r3, [r3, #0] + 800897e: 2b01 cmp r3, #1 + 8008980: d10e bne.n 80089a0 + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + 8008982: 4b0b ldr r3, [pc, #44] ; (80089b0 ) + 8008984: 681b ldr r3, [r3, #0] + 8008986: b2db uxtb r3, r3 + 8008988: 2b00 cmp r3, #0 + 800898a: d009 beq.n 80089a0 + 800898c: f04f 0350 mov.w r3, #80 ; 0x50 + 8008990: f383 8811 msr BASEPRI, r3 + 8008994: f3bf 8f6f isb sy + 8008998: f3bf 8f4f dsb sy + 800899c: 603b str r3, [r7, #0] + 800899e: e7fe b.n 800899e + } +} + 80089a0: bf00 nop + 80089a2: 370c adds r7, #12 + 80089a4: 46bd mov sp, r7 + 80089a6: bc80 pop {r7} + 80089a8: 4770 bx lr + 80089aa: bf00 nop + 80089ac: 20000130 .word 0x20000130 + 80089b0: e000ed04 .word 0xe000ed04 + +080089b4 : +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + 80089b4: b480 push {r7} + 80089b6: b083 sub sp, #12 + 80089b8: af00 add r7, sp, #0 + configASSERT( uxCriticalNesting ); + 80089ba: 4b10 ldr r3, [pc, #64] ; (80089fc ) + 80089bc: 681b ldr r3, [r3, #0] + 80089be: 2b00 cmp r3, #0 + 80089c0: d109 bne.n 80089d6 + 80089c2: f04f 0350 mov.w r3, #80 ; 0x50 + 80089c6: f383 8811 msr BASEPRI, r3 + 80089ca: f3bf 8f6f isb sy + 80089ce: f3bf 8f4f dsb sy + 80089d2: 607b str r3, [r7, #4] + 80089d4: e7fe b.n 80089d4 + uxCriticalNesting--; + 80089d6: 4b09 ldr r3, [pc, #36] ; (80089fc ) + 80089d8: 681b ldr r3, [r3, #0] + 80089da: 3b01 subs r3, #1 + 80089dc: 4a07 ldr r2, [pc, #28] ; (80089fc ) + 80089de: 6013 str r3, [r2, #0] + if( uxCriticalNesting == 0 ) + 80089e0: 4b06 ldr r3, [pc, #24] ; (80089fc ) + 80089e2: 681b ldr r3, [r3, #0] + 80089e4: 2b00 cmp r3, #0 + 80089e6: d104 bne.n 80089f2 + 80089e8: 2300 movs r3, #0 + 80089ea: 603b str r3, [r7, #0] +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + 80089ec: 683b ldr r3, [r7, #0] + 80089ee: f383 8811 msr BASEPRI, r3 + { + portENABLE_INTERRUPTS(); + } +} + 80089f2: bf00 nop + 80089f4: 370c adds r7, #12 + 80089f6: 46bd mov sp, r7 + 80089f8: bc80 pop {r7} + 80089fa: 4770 bx lr + 80089fc: 20000130 .word 0x20000130 + +08008a00 : + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + 8008a00: f3ef 8009 mrs r0, PSP + 8008a04: f3bf 8f6f isb sy + 8008a08: 4b0d ldr r3, [pc, #52] ; (8008a40 ) + 8008a0a: 681a ldr r2, [r3, #0] + 8008a0c: e920 0ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp} + 8008a10: 6010 str r0, [r2, #0] + 8008a12: e92d 4008 stmdb sp!, {r3, lr} + 8008a16: f04f 0050 mov.w r0, #80 ; 0x50 + 8008a1a: f380 8811 msr BASEPRI, r0 + 8008a1e: f7ff fd1d bl 800845c + 8008a22: f04f 0000 mov.w r0, #0 + 8008a26: f380 8811 msr BASEPRI, r0 + 8008a2a: e8bd 4008 ldmia.w sp!, {r3, lr} + 8008a2e: 6819 ldr r1, [r3, #0] + 8008a30: 6808 ldr r0, [r1, #0] + 8008a32: e8b0 0ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp} + 8008a36: f380 8809 msr PSP, r0 + 8008a3a: f3bf 8f6f isb sy + 8008a3e: 4770 bx lr + +08008a40 : + 8008a40: 20000228 .word 0x20000228 + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) + ); +} + 8008a44: bf00 nop + 8008a46: bf00 nop + +08008a48 : +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + 8008a48: b580 push {r7, lr} + 8008a4a: b082 sub sp, #8 + 8008a4c: af00 add r7, sp, #0 + __asm volatile + 8008a4e: f04f 0350 mov.w r3, #80 ; 0x50 + 8008a52: f383 8811 msr BASEPRI, r3 + 8008a56: f3bf 8f6f isb sy + 8008a5a: f3bf 8f4f dsb sy + 8008a5e: 607b str r3, [r7, #4] + save and then restore the interrupt mask value as its value is already + known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + 8008a60: f7ff fc40 bl 80082e4 + 8008a64: 4603 mov r3, r0 + 8008a66: 2b00 cmp r3, #0 + 8008a68: d003 beq.n 8008a72 + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + 8008a6a: 4b06 ldr r3, [pc, #24] ; (8008a84 ) + 8008a6c: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8008a70: 601a str r2, [r3, #0] + 8008a72: 2300 movs r3, #0 + 8008a74: 603b str r3, [r7, #0] + __asm volatile + 8008a76: 683b ldr r3, [r7, #0] + 8008a78: f383 8811 msr BASEPRI, r3 + } + } + portENABLE_INTERRUPTS(); +} + 8008a7c: bf00 nop + 8008a7e: 3708 adds r7, #8 + 8008a80: 46bd mov sp, r7 + 8008a82: bd80 pop {r7, pc} + 8008a84: e000ed04 .word 0xe000ed04 + +08008a88 : +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__(( weak )) void vPortSetupTimerInterrupt( void ) +{ + 8008a88: b480 push {r7} + 8008a8a: af00 add r7, sp, #0 + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + 8008a8c: 4b0a ldr r3, [pc, #40] ; (8008ab8 ) + 8008a8e: 2200 movs r2, #0 + 8008a90: 601a str r2, [r3, #0] + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + 8008a92: 4b0a ldr r3, [pc, #40] ; (8008abc ) + 8008a94: 2200 movs r2, #0 + 8008a96: 601a str r2, [r3, #0] + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + 8008a98: 4b09 ldr r3, [pc, #36] ; (8008ac0 ) + 8008a9a: 681b ldr r3, [r3, #0] + 8008a9c: 4a09 ldr r2, [pc, #36] ; (8008ac4 ) + 8008a9e: fba2 2303 umull r2, r3, r2, r3 + 8008aa2: 099b lsrs r3, r3, #6 + 8008aa4: 4a08 ldr r2, [pc, #32] ; (8008ac8 ) + 8008aa6: 3b01 subs r3, #1 + 8008aa8: 6013 str r3, [r2, #0] + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + 8008aaa: 4b03 ldr r3, [pc, #12] ; (8008ab8 ) + 8008aac: 2207 movs r2, #7 + 8008aae: 601a str r2, [r3, #0] +} + 8008ab0: bf00 nop + 8008ab2: 46bd mov sp, r7 + 8008ab4: bc80 pop {r7} + 8008ab6: 4770 bx lr + 8008ab8: e000e010 .word 0xe000e010 + 8008abc: e000e018 .word 0xe000e018 + 8008ac0: 20000140 .word 0x20000140 + 8008ac4: 10624dd3 .word 0x10624dd3 + 8008ac8: e000e014 .word 0xe000e014 + +08008acc : +static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ + 8008acc: b580 push {r7, lr} + 8008ace: b08a sub sp, #40 ; 0x28 + 8008ad0: af00 add r7, sp, #0 + 8008ad2: 6078 str r0, [r7, #4] +BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; +void *pvReturn = NULL; + 8008ad4: 2300 movs r3, #0 + 8008ad6: 61fb str r3, [r7, #28] + + vTaskSuspendAll(); + 8008ad8: f7ff fb5a bl 8008190 + { + /* If this is the first call to malloc then the heap will require + initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + 8008adc: 4b57 ldr r3, [pc, #348] ; (8008c3c ) + 8008ade: 681b ldr r3, [r3, #0] + 8008ae0: 2b00 cmp r3, #0 + 8008ae2: d101 bne.n 8008ae8 + { + prvHeapInit(); + 8008ae4: f000 f90c bl 8008d00 + + /* Check the requested block size is not so large that the top bit is + set. The top bit of the block size member of the BlockLink_t structure + is used to determine who owns the block - the application or the + kernel, so it must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + 8008ae8: 4b55 ldr r3, [pc, #340] ; (8008c40 ) + 8008aea: 681a ldr r2, [r3, #0] + 8008aec: 687b ldr r3, [r7, #4] + 8008aee: 4013 ands r3, r2 + 8008af0: 2b00 cmp r3, #0 + 8008af2: f040 808c bne.w 8008c0e + { + /* The wanted size is increased so it can contain a BlockLink_t + structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + 8008af6: 687b ldr r3, [r7, #4] + 8008af8: 2b00 cmp r3, #0 + 8008afa: d01c beq.n 8008b36 + { + xWantedSize += xHeapStructSize; + 8008afc: 2208 movs r2, #8 + 8008afe: 687b ldr r3, [r7, #4] + 8008b00: 4413 add r3, r2 + 8008b02: 607b str r3, [r7, #4] + + /* Ensure that blocks are always aligned to the required number + of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + 8008b04: 687b ldr r3, [r7, #4] + 8008b06: f003 0307 and.w r3, r3, #7 + 8008b0a: 2b00 cmp r3, #0 + 8008b0c: d013 beq.n 8008b36 + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + 8008b0e: 687b ldr r3, [r7, #4] + 8008b10: f023 0307 bic.w r3, r3, #7 + 8008b14: 3308 adds r3, #8 + 8008b16: 607b str r3, [r7, #4] + configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); + 8008b18: 687b ldr r3, [r7, #4] + 8008b1a: f003 0307 and.w r3, r3, #7 + 8008b1e: 2b00 cmp r3, #0 + 8008b20: d009 beq.n 8008b36 + __asm volatile + 8008b22: f04f 0350 mov.w r3, #80 ; 0x50 + 8008b26: f383 8811 msr BASEPRI, r3 + 8008b2a: f3bf 8f6f isb sy + 8008b2e: f3bf 8f4f dsb sy + 8008b32: 617b str r3, [r7, #20] + 8008b34: e7fe b.n 8008b34 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + 8008b36: 687b ldr r3, [r7, #4] + 8008b38: 2b00 cmp r3, #0 + 8008b3a: d068 beq.n 8008c0e + 8008b3c: 4b41 ldr r3, [pc, #260] ; (8008c44 ) + 8008b3e: 681b ldr r3, [r3, #0] + 8008b40: 687a ldr r2, [r7, #4] + 8008b42: 429a cmp r2, r3 + 8008b44: d863 bhi.n 8008c0e + { + /* Traverse the list from the start (lowest address) block until + one of adequate size is found. */ + pxPreviousBlock = &xStart; + 8008b46: 4b40 ldr r3, [pc, #256] ; (8008c48 ) + 8008b48: 623b str r3, [r7, #32] + pxBlock = xStart.pxNextFreeBlock; + 8008b4a: 4b3f ldr r3, [pc, #252] ; (8008c48 ) + 8008b4c: 681b ldr r3, [r3, #0] + 8008b4e: 627b str r3, [r7, #36] ; 0x24 + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 8008b50: e004 b.n 8008b5c + { + pxPreviousBlock = pxBlock; + 8008b52: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008b54: 623b str r3, [r7, #32] + pxBlock = pxBlock->pxNextFreeBlock; + 8008b56: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008b58: 681b ldr r3, [r3, #0] + 8008b5a: 627b str r3, [r7, #36] ; 0x24 + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 8008b5c: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008b5e: 685b ldr r3, [r3, #4] + 8008b60: 687a ldr r2, [r7, #4] + 8008b62: 429a cmp r2, r3 + 8008b64: d903 bls.n 8008b6e + 8008b66: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008b68: 681b ldr r3, [r3, #0] + 8008b6a: 2b00 cmp r3, #0 + 8008b6c: d1f1 bne.n 8008b52 + } + + /* If the end marker was reached then a block of adequate size + was not found. */ + if( pxBlock != pxEnd ) + 8008b6e: 4b33 ldr r3, [pc, #204] ; (8008c3c ) + 8008b70: 681b ldr r3, [r3, #0] + 8008b72: 6a7a ldr r2, [r7, #36] ; 0x24 + 8008b74: 429a cmp r2, r3 + 8008b76: d04a beq.n 8008c0e + { + /* Return the memory space pointed to - jumping over the + BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + 8008b78: 6a3b ldr r3, [r7, #32] + 8008b7a: 681b ldr r3, [r3, #0] + 8008b7c: 2208 movs r2, #8 + 8008b7e: 4413 add r3, r2 + 8008b80: 61fb str r3, [r7, #28] + + /* This block is being returned for use so must be taken out + of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + 8008b82: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008b84: 681a ldr r2, [r3, #0] + 8008b86: 6a3b ldr r3, [r7, #32] + 8008b88: 601a str r2, [r3, #0] + + /* If the block is larger than required it can be split into + two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + 8008b8a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008b8c: 685a ldr r2, [r3, #4] + 8008b8e: 687b ldr r3, [r7, #4] + 8008b90: 1ad2 subs r2, r2, r3 + 8008b92: 2308 movs r3, #8 + 8008b94: 005b lsls r3, r3, #1 + 8008b96: 429a cmp r2, r3 + 8008b98: d91e bls.n 8008bd8 + { + /* This block is to be split into two. Create a new + block following the number of bytes requested. The void + cast is used to prevent byte alignment warnings from the + compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + 8008b9a: 6a7a ldr r2, [r7, #36] ; 0x24 + 8008b9c: 687b ldr r3, [r7, #4] + 8008b9e: 4413 add r3, r2 + 8008ba0: 61bb str r3, [r7, #24] + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + 8008ba2: 69bb ldr r3, [r7, #24] + 8008ba4: f003 0307 and.w r3, r3, #7 + 8008ba8: 2b00 cmp r3, #0 + 8008baa: d009 beq.n 8008bc0 + 8008bac: f04f 0350 mov.w r3, #80 ; 0x50 + 8008bb0: f383 8811 msr BASEPRI, r3 + 8008bb4: f3bf 8f6f isb sy + 8008bb8: f3bf 8f4f dsb sy + 8008bbc: 613b str r3, [r7, #16] + 8008bbe: e7fe b.n 8008bbe + + /* Calculate the sizes of two blocks split from the + single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + 8008bc0: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008bc2: 685a ldr r2, [r3, #4] + 8008bc4: 687b ldr r3, [r7, #4] + 8008bc6: 1ad2 subs r2, r2, r3 + 8008bc8: 69bb ldr r3, [r7, #24] + 8008bca: 605a str r2, [r3, #4] + pxBlock->xBlockSize = xWantedSize; + 8008bcc: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008bce: 687a ldr r2, [r7, #4] + 8008bd0: 605a str r2, [r3, #4] + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + 8008bd2: 69b8 ldr r0, [r7, #24] + 8008bd4: f000 f8f6 bl 8008dc4 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + 8008bd8: 4b1a ldr r3, [pc, #104] ; (8008c44 ) + 8008bda: 681a ldr r2, [r3, #0] + 8008bdc: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008bde: 685b ldr r3, [r3, #4] + 8008be0: 1ad3 subs r3, r2, r3 + 8008be2: 4a18 ldr r2, [pc, #96] ; (8008c44 ) + 8008be4: 6013 str r3, [r2, #0] + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + 8008be6: 4b17 ldr r3, [pc, #92] ; (8008c44 ) + 8008be8: 681a ldr r2, [r3, #0] + 8008bea: 4b18 ldr r3, [pc, #96] ; (8008c4c ) + 8008bec: 681b ldr r3, [r3, #0] + 8008bee: 429a cmp r2, r3 + 8008bf0: d203 bcs.n 8008bfa + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + 8008bf2: 4b14 ldr r3, [pc, #80] ; (8008c44 ) + 8008bf4: 681b ldr r3, [r3, #0] + 8008bf6: 4a15 ldr r2, [pc, #84] ; (8008c4c ) + 8008bf8: 6013 str r3, [r2, #0] + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + 8008bfa: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008bfc: 685a ldr r2, [r3, #4] + 8008bfe: 4b10 ldr r3, [pc, #64] ; (8008c40 ) + 8008c00: 681b ldr r3, [r3, #0] + 8008c02: 431a orrs r2, r3 + 8008c04: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008c06: 605a str r2, [r3, #4] + pxBlock->pxNextFreeBlock = NULL; + 8008c08: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008c0a: 2200 movs r2, #0 + 8008c0c: 601a str r2, [r3, #0] + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + 8008c0e: f7ff facd bl 80081ac + mtCOVERAGE_TEST_MARKER(); + } + } + #endif + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + 8008c12: 69fb ldr r3, [r7, #28] + 8008c14: f003 0307 and.w r3, r3, #7 + 8008c18: 2b00 cmp r3, #0 + 8008c1a: d009 beq.n 8008c30 + 8008c1c: f04f 0350 mov.w r3, #80 ; 0x50 + 8008c20: f383 8811 msr BASEPRI, r3 + 8008c24: f3bf 8f6f isb sy + 8008c28: f3bf 8f4f dsb sy + 8008c2c: 60fb str r3, [r7, #12] + 8008c2e: e7fe b.n 8008c2e + return pvReturn; + 8008c30: 69fb ldr r3, [r7, #28] +} + 8008c32: 4618 mov r0, r3 + 8008c34: 3728 adds r7, #40 ; 0x28 + 8008c36: 46bd mov sp, r7 + 8008c38: bd80 pop {r7, pc} + 8008c3a: bf00 nop + 8008c3c: 20000f64 .word 0x20000f64 + 8008c40: 20000f70 .word 0x20000f70 + 8008c44: 20000f68 .word 0x20000f68 + 8008c48: 20000f5c .word 0x20000f5c + 8008c4c: 20000f6c .word 0x20000f6c + +08008c50 : +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + 8008c50: b580 push {r7, lr} + 8008c52: b086 sub sp, #24 + 8008c54: af00 add r7, sp, #0 + 8008c56: 6078 str r0, [r7, #4] +uint8_t *puc = ( uint8_t * ) pv; + 8008c58: 687b ldr r3, [r7, #4] + 8008c5a: 617b str r3, [r7, #20] +BlockLink_t *pxLink; + + if( pv != NULL ) + 8008c5c: 687b ldr r3, [r7, #4] + 8008c5e: 2b00 cmp r3, #0 + 8008c60: d046 beq.n 8008cf0 + { + /* The memory being freed will have an BlockLink_t structure immediately + before it. */ + puc -= xHeapStructSize; + 8008c62: 2308 movs r3, #8 + 8008c64: 425b negs r3, r3 + 8008c66: 697a ldr r2, [r7, #20] + 8008c68: 4413 add r3, r2 + 8008c6a: 617b str r3, [r7, #20] + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + 8008c6c: 697b ldr r3, [r7, #20] + 8008c6e: 613b str r3, [r7, #16] + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + 8008c70: 693b ldr r3, [r7, #16] + 8008c72: 685a ldr r2, [r3, #4] + 8008c74: 4b20 ldr r3, [pc, #128] ; (8008cf8 ) + 8008c76: 681b ldr r3, [r3, #0] + 8008c78: 4013 ands r3, r2 + 8008c7a: 2b00 cmp r3, #0 + 8008c7c: d109 bne.n 8008c92 + 8008c7e: f04f 0350 mov.w r3, #80 ; 0x50 + 8008c82: f383 8811 msr BASEPRI, r3 + 8008c86: f3bf 8f6f isb sy + 8008c8a: f3bf 8f4f dsb sy + 8008c8e: 60fb str r3, [r7, #12] + 8008c90: e7fe b.n 8008c90 + configASSERT( pxLink->pxNextFreeBlock == NULL ); + 8008c92: 693b ldr r3, [r7, #16] + 8008c94: 681b ldr r3, [r3, #0] + 8008c96: 2b00 cmp r3, #0 + 8008c98: d009 beq.n 8008cae + 8008c9a: f04f 0350 mov.w r3, #80 ; 0x50 + 8008c9e: f383 8811 msr BASEPRI, r3 + 8008ca2: f3bf 8f6f isb sy + 8008ca6: f3bf 8f4f dsb sy + 8008caa: 60bb str r3, [r7, #8] + 8008cac: e7fe b.n 8008cac + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + 8008cae: 693b ldr r3, [r7, #16] + 8008cb0: 685a ldr r2, [r3, #4] + 8008cb2: 4b11 ldr r3, [pc, #68] ; (8008cf8 ) + 8008cb4: 681b ldr r3, [r3, #0] + 8008cb6: 4013 ands r3, r2 + 8008cb8: 2b00 cmp r3, #0 + 8008cba: d019 beq.n 8008cf0 + { + if( pxLink->pxNextFreeBlock == NULL ) + 8008cbc: 693b ldr r3, [r7, #16] + 8008cbe: 681b ldr r3, [r3, #0] + 8008cc0: 2b00 cmp r3, #0 + 8008cc2: d115 bne.n 8008cf0 + { + /* The block is being returned to the heap - it is no longer + allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + 8008cc4: 693b ldr r3, [r7, #16] + 8008cc6: 685a ldr r2, [r3, #4] + 8008cc8: 4b0b ldr r3, [pc, #44] ; (8008cf8 ) + 8008cca: 681b ldr r3, [r3, #0] + 8008ccc: 43db mvns r3, r3 + 8008cce: 401a ands r2, r3 + 8008cd0: 693b ldr r3, [r7, #16] + 8008cd2: 605a str r2, [r3, #4] + + vTaskSuspendAll(); + 8008cd4: f7ff fa5c bl 8008190 + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + 8008cd8: 693b ldr r3, [r7, #16] + 8008cda: 685a ldr r2, [r3, #4] + 8008cdc: 4b07 ldr r3, [pc, #28] ; (8008cfc ) + 8008cde: 681b ldr r3, [r3, #0] + 8008ce0: 4413 add r3, r2 + 8008ce2: 4a06 ldr r2, [pc, #24] ; (8008cfc ) + 8008ce4: 6013 str r3, [r2, #0] + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + 8008ce6: 6938 ldr r0, [r7, #16] + 8008ce8: f000 f86c bl 8008dc4 + } + ( void ) xTaskResumeAll(); + 8008cec: f7ff fa5e bl 80081ac + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} + 8008cf0: bf00 nop + 8008cf2: 3718 adds r7, #24 + 8008cf4: 46bd mov sp, r7 + 8008cf6: bd80 pop {r7, pc} + 8008cf8: 20000f70 .word 0x20000f70 + 8008cfc: 20000f68 .word 0x20000f68 + +08008d00 : + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + 8008d00: b480 push {r7} + 8008d02: b085 sub sp, #20 + 8008d04: af00 add r7, sp, #0 +BlockLink_t *pxFirstFreeBlock; +uint8_t *pucAlignedHeap; +size_t uxAddress; +size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + 8008d06: f44f 6340 mov.w r3, #3072 ; 0xc00 + 8008d0a: 60bb str r3, [r7, #8] + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + 8008d0c: 4b27 ldr r3, [pc, #156] ; (8008dac ) + 8008d0e: 60fb str r3, [r7, #12] + + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + 8008d10: 68fb ldr r3, [r7, #12] + 8008d12: f003 0307 and.w r3, r3, #7 + 8008d16: 2b00 cmp r3, #0 + 8008d18: d00c beq.n 8008d34 + { + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + 8008d1a: 68fb ldr r3, [r7, #12] + 8008d1c: 3307 adds r3, #7 + 8008d1e: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 8008d20: 68fb ldr r3, [r7, #12] + 8008d22: f023 0307 bic.w r3, r3, #7 + 8008d26: 60fb str r3, [r7, #12] + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + 8008d28: 68ba ldr r2, [r7, #8] + 8008d2a: 68fb ldr r3, [r7, #12] + 8008d2c: 1ad3 subs r3, r2, r3 + 8008d2e: 4a1f ldr r2, [pc, #124] ; (8008dac ) + 8008d30: 4413 add r3, r2 + 8008d32: 60bb str r3, [r7, #8] + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + 8008d34: 68fb ldr r3, [r7, #12] + 8008d36: 607b str r3, [r7, #4] + + /* xStart is used to hold a pointer to the first item in the list of free + blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + 8008d38: 4a1d ldr r2, [pc, #116] ; (8008db0 ) + 8008d3a: 687b ldr r3, [r7, #4] + 8008d3c: 6013 str r3, [r2, #0] + xStart.xBlockSize = ( size_t ) 0; + 8008d3e: 4b1c ldr r3, [pc, #112] ; (8008db0 ) + 8008d40: 2200 movs r2, #0 + 8008d42: 605a str r2, [r3, #4] + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + 8008d44: 687b ldr r3, [r7, #4] + 8008d46: 68ba ldr r2, [r7, #8] + 8008d48: 4413 add r3, r2 + 8008d4a: 60fb str r3, [r7, #12] + uxAddress -= xHeapStructSize; + 8008d4c: 2208 movs r2, #8 + 8008d4e: 68fb ldr r3, [r7, #12] + 8008d50: 1a9b subs r3, r3, r2 + 8008d52: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 8008d54: 68fb ldr r3, [r7, #12] + 8008d56: f023 0307 bic.w r3, r3, #7 + 8008d5a: 60fb str r3, [r7, #12] + pxEnd = ( void * ) uxAddress; + 8008d5c: 68fb ldr r3, [r7, #12] + 8008d5e: 4a15 ldr r2, [pc, #84] ; (8008db4 ) + 8008d60: 6013 str r3, [r2, #0] + pxEnd->xBlockSize = 0; + 8008d62: 4b14 ldr r3, [pc, #80] ; (8008db4 ) + 8008d64: 681b ldr r3, [r3, #0] + 8008d66: 2200 movs r2, #0 + 8008d68: 605a str r2, [r3, #4] + pxEnd->pxNextFreeBlock = NULL; + 8008d6a: 4b12 ldr r3, [pc, #72] ; (8008db4 ) + 8008d6c: 681b ldr r3, [r3, #0] + 8008d6e: 2200 movs r2, #0 + 8008d70: 601a str r2, [r3, #0] + + /* To start with there is a single free block that is sized to take up the + entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + 8008d72: 687b ldr r3, [r7, #4] + 8008d74: 603b str r3, [r7, #0] + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + 8008d76: 683b ldr r3, [r7, #0] + 8008d78: 68fa ldr r2, [r7, #12] + 8008d7a: 1ad2 subs r2, r2, r3 + 8008d7c: 683b ldr r3, [r7, #0] + 8008d7e: 605a str r2, [r3, #4] + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + 8008d80: 4b0c ldr r3, [pc, #48] ; (8008db4 ) + 8008d82: 681a ldr r2, [r3, #0] + 8008d84: 683b ldr r3, [r7, #0] + 8008d86: 601a str r2, [r3, #0] + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 8008d88: 683b ldr r3, [r7, #0] + 8008d8a: 685b ldr r3, [r3, #4] + 8008d8c: 4a0a ldr r2, [pc, #40] ; (8008db8 ) + 8008d8e: 6013 str r3, [r2, #0] + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 8008d90: 683b ldr r3, [r7, #0] + 8008d92: 685b ldr r3, [r3, #4] + 8008d94: 4a09 ldr r2, [pc, #36] ; (8008dbc ) + 8008d96: 6013 str r3, [r2, #0] + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); + 8008d98: 4b09 ldr r3, [pc, #36] ; (8008dc0 ) + 8008d9a: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 + 8008d9e: 601a str r2, [r3, #0] +} + 8008da0: bf00 nop + 8008da2: 3714 adds r7, #20 + 8008da4: 46bd mov sp, r7 + 8008da6: bc80 pop {r7} + 8008da8: 4770 bx lr + 8008daa: bf00 nop + 8008dac: 2000035c .word 0x2000035c + 8008db0: 20000f5c .word 0x20000f5c + 8008db4: 20000f64 .word 0x20000f64 + 8008db8: 20000f6c .word 0x20000f6c + 8008dbc: 20000f68 .word 0x20000f68 + 8008dc0: 20000f70 .word 0x20000f70 + +08008dc4 : +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) +{ + 8008dc4: b480 push {r7} + 8008dc6: b085 sub sp, #20 + 8008dc8: af00 add r7, sp, #0 + 8008dca: 6078 str r0, [r7, #4] +BlockLink_t *pxIterator; +uint8_t *puc; + + /* Iterate through the list until a block is found that has a higher address + than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + 8008dcc: 4b27 ldr r3, [pc, #156] ; (8008e6c ) + 8008dce: 60fb str r3, [r7, #12] + 8008dd0: e002 b.n 8008dd8 + 8008dd2: 68fb ldr r3, [r7, #12] + 8008dd4: 681b ldr r3, [r3, #0] + 8008dd6: 60fb str r3, [r7, #12] + 8008dd8: 68fb ldr r3, [r7, #12] + 8008dda: 681b ldr r3, [r3, #0] + 8008ddc: 687a ldr r2, [r7, #4] + 8008dde: 429a cmp r2, r3 + 8008de0: d8f7 bhi.n 8008dd2 + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + 8008de2: 68fb ldr r3, [r7, #12] + 8008de4: 60bb str r3, [r7, #8] + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + 8008de6: 68fb ldr r3, [r7, #12] + 8008de8: 685b ldr r3, [r3, #4] + 8008dea: 68ba ldr r2, [r7, #8] + 8008dec: 4413 add r3, r2 + 8008dee: 687a ldr r2, [r7, #4] + 8008df0: 429a cmp r2, r3 + 8008df2: d108 bne.n 8008e06 + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + 8008df4: 68fb ldr r3, [r7, #12] + 8008df6: 685a ldr r2, [r3, #4] + 8008df8: 687b ldr r3, [r7, #4] + 8008dfa: 685b ldr r3, [r3, #4] + 8008dfc: 441a add r2, r3 + 8008dfe: 68fb ldr r3, [r7, #12] + 8008e00: 605a str r2, [r3, #4] + pxBlockToInsert = pxIterator; + 8008e02: 68fb ldr r3, [r7, #12] + 8008e04: 607b str r3, [r7, #4] + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + 8008e06: 687b ldr r3, [r7, #4] + 8008e08: 60bb str r3, [r7, #8] + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + 8008e0a: 687b ldr r3, [r7, #4] + 8008e0c: 685b ldr r3, [r3, #4] + 8008e0e: 68ba ldr r2, [r7, #8] + 8008e10: 441a add r2, r3 + 8008e12: 68fb ldr r3, [r7, #12] + 8008e14: 681b ldr r3, [r3, #0] + 8008e16: 429a cmp r2, r3 + 8008e18: d118 bne.n 8008e4c + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + 8008e1a: 68fb ldr r3, [r7, #12] + 8008e1c: 681a ldr r2, [r3, #0] + 8008e1e: 4b14 ldr r3, [pc, #80] ; (8008e70 ) + 8008e20: 681b ldr r3, [r3, #0] + 8008e22: 429a cmp r2, r3 + 8008e24: d00d beq.n 8008e42 + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + 8008e26: 687b ldr r3, [r7, #4] + 8008e28: 685a ldr r2, [r3, #4] + 8008e2a: 68fb ldr r3, [r7, #12] + 8008e2c: 681b ldr r3, [r3, #0] + 8008e2e: 685b ldr r3, [r3, #4] + 8008e30: 441a add r2, r3 + 8008e32: 687b ldr r3, [r7, #4] + 8008e34: 605a str r2, [r3, #4] + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + 8008e36: 68fb ldr r3, [r7, #12] + 8008e38: 681b ldr r3, [r3, #0] + 8008e3a: 681a ldr r2, [r3, #0] + 8008e3c: 687b ldr r3, [r7, #4] + 8008e3e: 601a str r2, [r3, #0] + 8008e40: e008 b.n 8008e54 + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + 8008e42: 4b0b ldr r3, [pc, #44] ; (8008e70 ) + 8008e44: 681a ldr r2, [r3, #0] + 8008e46: 687b ldr r3, [r7, #4] + 8008e48: 601a str r2, [r3, #0] + 8008e4a: e003 b.n 8008e54 + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + 8008e4c: 68fb ldr r3, [r7, #12] + 8008e4e: 681a ldr r2, [r3, #0] + 8008e50: 687b ldr r3, [r7, #4] + 8008e52: 601a str r2, [r3, #0] + + /* If the block being inserted plugged a gab, so was merged with the block + before and the block after, then it's pxNextFreeBlock pointer will have + already been set, and should not be set here as that would make it point + to itself. */ + if( pxIterator != pxBlockToInsert ) + 8008e54: 68fa ldr r2, [r7, #12] + 8008e56: 687b ldr r3, [r7, #4] + 8008e58: 429a cmp r2, r3 + 8008e5a: d002 beq.n 8008e62 + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + 8008e5c: 68fb ldr r3, [r7, #12] + 8008e5e: 687a ldr r2, [r7, #4] + 8008e60: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 8008e62: bf00 nop + 8008e64: 3714 adds r7, #20 + 8008e66: 46bd mov sp, r7 + 8008e68: bc80 pop {r7} + 8008e6a: 4770 bx lr + 8008e6c: 20000f5c .word 0x20000f5c + 8008e70: 20000f64 .word 0x20000f64 + +08008e74
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8008e74: b5b0 push {r4, r5, r7, lr} + 8008e76: b08a sub sp, #40 ; 0x28 + 8008e78: af00 add r7, sp, #0 + + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8008e7a: f7f8 f8bb bl 8000ff4 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8008e7e: f000 f837 bl 8008ef0 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8008e82: f000 f9c1 bl 8009208 + MX_I2C1_Init(); + 8008e86: f000 f893 bl 8008fb0 + MX_SPI2_Init(); + 8008e8a: f000 f909 bl 80090a0 + MX_USART2_UART_Init(); + 8008e8e: f000 f991 bl 80091b4 + MX_TIM2_Init(); + 8008e92: f000 f93b bl 800910c + MX_RTC_Init(); + 8008e96: f000 f8b9 bl 800900c + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* definition and creation of defaultTask */ + osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128); + 8008e9a: 4b11 ldr r3, [pc, #68] ; (8008ee0 ) + 8008e9c: f107 0414 add.w r4, r7, #20 + 8008ea0: 461d mov r5, r3 + 8008ea2: cd0f ldmia r5!, {r0, r1, r2, r3} + 8008ea4: c40f stmia r4!, {r0, r1, r2, r3} + 8008ea6: 682b ldr r3, [r5, #0] + 8008ea8: 6023 str r3, [r4, #0] + defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL); + 8008eaa: f107 0314 add.w r3, r7, #20 + 8008eae: 2100 movs r1, #0 + 8008eb0: 4618 mov r0, r3 + 8008eb2: f7fe fedf bl 8007c74 + 8008eb6: 4602 mov r2, r0 + 8008eb8: 4b0a ldr r3, [pc, #40] ; (8008ee4 ) + 8008eba: 601a str r2, [r3, #0] + + /* definition and creation of myTask02 */ + osThreadDef(myTask02, StartTask02, osPriorityNormal, 0, 128); + 8008ebc: 4b0a ldr r3, [pc, #40] ; (8008ee8 ) + 8008ebe: 463c mov r4, r7 + 8008ec0: 461d mov r5, r3 + 8008ec2: cd0f ldmia r5!, {r0, r1, r2, r3} + 8008ec4: c40f stmia r4!, {r0, r1, r2, r3} + 8008ec6: 682b ldr r3, [r5, #0] + 8008ec8: 6023 str r3, [r4, #0] + myTask02Handle = osThreadCreate(osThread(myTask02), NULL); + 8008eca: 463b mov r3, r7 + 8008ecc: 2100 movs r1, #0 + 8008ece: 4618 mov r0, r3 + 8008ed0: f7fe fed0 bl 8007c74 + 8008ed4: 4602 mov r2, r0 + 8008ed6: 4b05 ldr r3, [pc, #20] ; (8008eec ) + 8008ed8: 601a str r2, [r3, #0] + /* USER CODE BEGIN RTOS_THREADS */ + /* add threads, ... */ + /* USER CODE END RTOS_THREADS */ + + /* Start scheduler */ + osKernelStart(); + 8008eda: f7fe fec4 bl 8007c66 + + /* We should never get here as control is now taken by the scheduler */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + 8008ede: e7fe b.n 8008ede + 8008ee0: 0800c6b8 .word 0x0800c6b8 + 8008ee4: 200011f8 .word 0x200011f8 + 8008ee8: 0800c6d8 .word 0x0800c6d8 + 8008eec: 200012a8 .word 0x200012a8 + +08008ef0 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8008ef0: b580 push {r7, lr} + 8008ef2: b094 sub sp, #80 ; 0x50 + 8008ef4: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8008ef6: f107 0328 add.w r3, r7, #40 ; 0x28 + 8008efa: 2228 movs r2, #40 ; 0x28 + 8008efc: 2100 movs r1, #0 + 8008efe: 4618 mov r0, r3 + 8008f00: f001 fee5 bl 800acce + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8008f04: f107 0314 add.w r3, r7, #20 + 8008f08: 2200 movs r2, #0 + 8008f0a: 601a str r2, [r3, #0] + 8008f0c: 605a str r2, [r3, #4] + 8008f0e: 609a str r2, [r3, #8] + 8008f10: 60da str r2, [r3, #12] + 8008f12: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 8008f14: 1d3b adds r3, r7, #4 + 8008f16: 2200 movs r2, #0 + 8008f18: 601a str r2, [r3, #0] + 8008f1a: 605a str r2, [r3, #4] + 8008f1c: 609a str r2, [r3, #8] + 8008f1e: 60da str r2, [r3, #12] + + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; + 8008f20: 2309 movs r3, #9 + 8008f22: 62bb str r3, [r7, #40] ; 0x28 + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 8008f24: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8008f28: 62fb str r3, [r7, #44] ; 0x2c + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; + 8008f2a: 2300 movs r3, #0 + 8008f2c: 633b str r3, [r7, #48] ; 0x30 + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8008f2e: 2301 movs r3, #1 + 8008f30: 63bb str r3, [r7, #56] ; 0x38 + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + 8008f32: 2301 movs r3, #1 + 8008f34: 643b str r3, [r7, #64] ; 0x40 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8008f36: 2302 movs r3, #2 + 8008f38: 647b str r3, [r7, #68] ; 0x44 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 8008f3a: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8008f3e: 64bb str r3, [r7, #72] ; 0x48 + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; + 8008f40: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 + 8008f44: 64fb str r3, [r7, #76] ; 0x4c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8008f46: f107 0328 add.w r3, r7, #40 ; 0x28 + 8008f4a: 4618 mov r0, r3 + 8008f4c: f7f9 fb84 bl 8002658 + 8008f50: 4603 mov r3, r0 + 8008f52: 2b00 cmp r3, #0 + 8008f54: d001 beq.n 8008f5a + { + Error_Handler(); + 8008f56: f000 fff3 bl 8009f40 + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8008f5a: 230f movs r3, #15 + 8008f5c: 617b str r3, [r7, #20] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8008f5e: 2302 movs r3, #2 + 8008f60: 61bb str r3, [r7, #24] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8008f62: 2300 movs r3, #0 + 8008f64: 61fb str r3, [r7, #28] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + 8008f66: f44f 6380 mov.w r3, #1024 ; 0x400 + 8008f6a: 623b str r3, [r7, #32] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8008f6c: 2300 movs r3, #0 + 8008f6e: 627b str r3, [r7, #36] ; 0x24 + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 8008f70: f107 0314 add.w r3, r7, #20 + 8008f74: 2102 movs r1, #2 + 8008f76: 4618 mov r0, r3 + 8008f78: f7f9 fdee bl 8002b58 + 8008f7c: 4603 mov r3, r0 + 8008f7e: 2b00 cmp r3, #0 + 8008f80: d001 beq.n 8008f86 + { + Error_Handler(); + 8008f82: f000 ffdd bl 8009f40 + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USB; + 8008f86: 2311 movs r3, #17 + 8008f88: 607b str r3, [r7, #4] + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + 8008f8a: f44f 7300 mov.w r3, #512 ; 0x200 + 8008f8e: 60bb str r3, [r7, #8] + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; + 8008f90: 2300 movs r3, #0 + 8008f92: 613b str r3, [r7, #16] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8008f94: 1d3b adds r3, r7, #4 + 8008f96: 4618 mov r0, r3 + 8008f98: f7f9 ff7a bl 8002e90 + 8008f9c: 4603 mov r3, r0 + 8008f9e: 2b00 cmp r3, #0 + 8008fa0: d001 beq.n 8008fa6 + { + Error_Handler(); + 8008fa2: f000 ffcd bl 8009f40 + } +} + 8008fa6: bf00 nop + 8008fa8: 3750 adds r7, #80 ; 0x50 + 8008faa: 46bd mov sp, r7 + 8008fac: bd80 pop {r7, pc} + ... + +08008fb0 : + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + 8008fb0: b580 push {r7, lr} + 8008fb2: af00 add r7, sp, #0 + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + 8008fb4: 4b12 ldr r3, [pc, #72] ; (8009000 ) + 8008fb6: 4a13 ldr r2, [pc, #76] ; (8009004 ) + 8008fb8: 601a str r2, [r3, #0] + hi2c1.Init.ClockSpeed = 100000; + 8008fba: 4b11 ldr r3, [pc, #68] ; (8009000 ) + 8008fbc: 4a12 ldr r2, [pc, #72] ; (8009008 ) + 8008fbe: 605a str r2, [r3, #4] + hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; + 8008fc0: 4b0f ldr r3, [pc, #60] ; (8009000 ) + 8008fc2: 2200 movs r2, #0 + 8008fc4: 609a str r2, [r3, #8] + hi2c1.Init.OwnAddress1 = 0; + 8008fc6: 4b0e ldr r3, [pc, #56] ; (8009000 ) + 8008fc8: 2200 movs r2, #0 + 8008fca: 60da str r2, [r3, #12] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8008fcc: 4b0c ldr r3, [pc, #48] ; (8009000 ) + 8008fce: f44f 4280 mov.w r2, #16384 ; 0x4000 + 8008fd2: 611a str r2, [r3, #16] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 8008fd4: 4b0a ldr r3, [pc, #40] ; (8009000 ) + 8008fd6: 2200 movs r2, #0 + 8008fd8: 615a str r2, [r3, #20] + hi2c1.Init.OwnAddress2 = 0; + 8008fda: 4b09 ldr r3, [pc, #36] ; (8009000 ) + 8008fdc: 2200 movs r2, #0 + 8008fde: 619a str r2, [r3, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8008fe0: 4b07 ldr r3, [pc, #28] ; (8009000 ) + 8008fe2: 2200 movs r2, #0 + 8008fe4: 61da str r2, [r3, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8008fe6: 4b06 ldr r3, [pc, #24] ; (8009000 ) + 8008fe8: 2200 movs r2, #0 + 8008fea: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 8008fec: 4804 ldr r0, [pc, #16] ; (8009000 ) + 8008fee: f7f8 fb1d bl 800162c + 8008ff2: 4603 mov r3, r0 + 8008ff4: 2b00 cmp r3, #0 + 8008ff6: d001 beq.n 8008ffc + { + Error_Handler(); + 8008ff8: f000 ffa2 bl 8009f40 + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + 8008ffc: bf00 nop + 8008ffe: bd80 pop {r7, pc} + 8009000: 20001254 .word 0x20001254 + 8009004: 40005400 .word 0x40005400 + 8009008: 000186a0 .word 0x000186a0 + +0800900c : + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + 800900c: b580 push {r7, lr} + 800900e: b082 sub sp, #8 + 8009010: af00 add r7, sp, #0 + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + RTC_TimeTypeDef sTime = {0}; + 8009012: 1d3b adds r3, r7, #4 + 8009014: 2100 movs r1, #0 + 8009016: 460a mov r2, r1 + 8009018: 801a strh r2, [r3, #0] + 800901a: 460a mov r2, r1 + 800901c: 709a strb r2, [r3, #2] + RTC_DateTypeDef DateToUpdate = {0}; + 800901e: 2300 movs r3, #0 + 8009020: 603b str r3, [r7, #0] + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + 8009022: 4b1d ldr r3, [pc, #116] ; (8009098 ) + 8009024: 4a1d ldr r2, [pc, #116] ; (800909c ) + 8009026: 601a str r2, [r3, #0] + hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; + 8009028: 4b1b ldr r3, [pc, #108] ; (8009098 ) + 800902a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800902e: 605a str r2, [r3, #4] + hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; + 8009030: 4b19 ldr r3, [pc, #100] ; (8009098 ) + 8009032: f44f 7280 mov.w r2, #256 ; 0x100 + 8009036: 609a str r2, [r3, #8] + if (HAL_RTC_Init(&hrtc) != HAL_OK) + 8009038: 4817 ldr r0, [pc, #92] ; (8009098 ) + 800903a: f7fa f89b bl 8003174 + 800903e: 4603 mov r3, r0 + 8009040: 2b00 cmp r3, #0 + 8009042: d001 beq.n 8009048 + { + Error_Handler(); + 8009044: f000 ff7c bl 8009f40 + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + sTime.Hours = 14; + 8009048: 230e movs r3, #14 + 800904a: 713b strb r3, [r7, #4] + sTime.Minutes = 54; + 800904c: 2336 movs r3, #54 ; 0x36 + 800904e: 717b strb r3, [r7, #5] + sTime.Seconds = 0; + 8009050: 2300 movs r3, #0 + 8009052: 71bb strb r3, [r7, #6] + + if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK) + 8009054: 1d3b adds r3, r7, #4 + 8009056: 2200 movs r2, #0 + 8009058: 4619 mov r1, r3 + 800905a: 480f ldr r0, [pc, #60] ; (8009098 ) + 800905c: f7fa f920 bl 80032a0 + 8009060: 4603 mov r3, r0 + 8009062: 2b00 cmp r3, #0 + 8009064: d001 beq.n 800906a + { + Error_Handler(); + 8009066: f000 ff6b bl 8009f40 + } + DateToUpdate.WeekDay = RTC_WEEKDAY_MONDAY; + 800906a: 2301 movs r3, #1 + 800906c: 703b strb r3, [r7, #0] + DateToUpdate.Month = RTC_MONTH_JANUARY; + 800906e: 2301 movs r3, #1 + 8009070: 707b strb r3, [r7, #1] + DateToUpdate.Date = 1; + 8009072: 2301 movs r3, #1 + 8009074: 70bb strb r3, [r7, #2] + DateToUpdate.Year = 0; + 8009076: 2300 movs r3, #0 + 8009078: 70fb strb r3, [r7, #3] + + if (HAL_RTC_SetDate(&hrtc, &DateToUpdate, RTC_FORMAT_BIN) != HAL_OK) + 800907a: 463b mov r3, r7 + 800907c: 2200 movs r2, #0 + 800907e: 4619 mov r1, r3 + 8009080: 4805 ldr r0, [pc, #20] ; (8009098 ) + 8009082: f7fa fa7d bl 8003580 + 8009086: 4603 mov r3, r0 + 8009088: 2b00 cmp r3, #0 + 800908a: d001 beq.n 8009090 + { + Error_Handler(); + 800908c: f000 ff58 bl 8009f40 + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + 8009090: bf00 nop + 8009092: 3708 adds r7, #8 + 8009094: 46bd mov sp, r7 + 8009096: bd80 pop {r7, pc} + 8009098: 200012ac .word 0x200012ac + 800909c: 40002800 .word 0x40002800 + +080090a0 : + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + 80090a0: b580 push {r7, lr} + 80090a2: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + 80090a4: 4b17 ldr r3, [pc, #92] ; (8009104 ) + 80090a6: 4a18 ldr r2, [pc, #96] ; (8009108 ) + 80090a8: 601a str r2, [r3, #0] + hspi2.Init.Mode = SPI_MODE_MASTER; + 80090aa: 4b16 ldr r3, [pc, #88] ; (8009104 ) + 80090ac: f44f 7282 mov.w r2, #260 ; 0x104 + 80090b0: 605a str r2, [r3, #4] + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + 80090b2: 4b14 ldr r3, [pc, #80] ; (8009104 ) + 80090b4: 2200 movs r2, #0 + 80090b6: 609a str r2, [r3, #8] + hspi2.Init.DataSize = SPI_DATASIZE_8BIT; + 80090b8: 4b12 ldr r3, [pc, #72] ; (8009104 ) + 80090ba: 2200 movs r2, #0 + 80090bc: 60da str r2, [r3, #12] + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + 80090be: 4b11 ldr r3, [pc, #68] ; (8009104 ) + 80090c0: 2200 movs r2, #0 + 80090c2: 611a str r2, [r3, #16] + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + 80090c4: 4b0f ldr r3, [pc, #60] ; (8009104 ) + 80090c6: 2200 movs r2, #0 + 80090c8: 615a str r2, [r3, #20] + hspi2.Init.NSS = SPI_NSS_SOFT; + 80090ca: 4b0e ldr r3, [pc, #56] ; (8009104 ) + 80090cc: f44f 7200 mov.w r2, #512 ; 0x200 + 80090d0: 619a str r2, [r3, #24] + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 80090d2: 4b0c ldr r3, [pc, #48] ; (8009104 ) + 80090d4: 2200 movs r2, #0 + 80090d6: 61da str r2, [r3, #28] + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + 80090d8: 4b0a ldr r3, [pc, #40] ; (8009104 ) + 80090da: 2200 movs r2, #0 + 80090dc: 621a str r2, [r3, #32] + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + 80090de: 4b09 ldr r3, [pc, #36] ; (8009104 ) + 80090e0: 2200 movs r2, #0 + 80090e2: 625a str r2, [r3, #36] ; 0x24 + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 80090e4: 4b07 ldr r3, [pc, #28] ; (8009104 ) + 80090e6: 2200 movs r2, #0 + 80090e8: 629a str r2, [r3, #40] ; 0x28 + hspi2.Init.CRCPolynomial = 10; + 80090ea: 4b06 ldr r3, [pc, #24] ; (8009104 ) + 80090ec: 220a movs r2, #10 + 80090ee: 62da str r2, [r3, #44] ; 0x2c + if (HAL_SPI_Init(&hspi2) != HAL_OK) + 80090f0: 4804 ldr r0, [pc, #16] ; (8009104 ) + 80090f2: f7fa fd9d bl 8003c30 + 80090f6: 4603 mov r3, r0 + 80090f8: 2b00 cmp r3, #0 + 80090fa: d001 beq.n 8009100 + { + Error_Handler(); + 80090fc: f000 ff20 bl 8009f40 + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + 8009100: bf00 nop + 8009102: bd80 pop {r7, pc} + 8009104: 200011fc .word 0x200011fc + 8009108: 40003800 .word 0x40003800 + +0800910c : + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + 800910c: b580 push {r7, lr} + 800910e: b08c sub sp, #48 ; 0x30 + 8009110: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_Encoder_InitTypeDef sConfig = {0}; + 8009112: f107 030c add.w r3, r7, #12 + 8009116: 2224 movs r2, #36 ; 0x24 + 8009118: 2100 movs r1, #0 + 800911a: 4618 mov r0, r3 + 800911c: f001 fdd7 bl 800acce + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8009120: 1d3b adds r3, r7, #4 + 8009122: 2200 movs r2, #0 + 8009124: 601a str r2, [r3, #0] + 8009126: 605a str r2, [r3, #4] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8009128: 4b21 ldr r3, [pc, #132] ; (80091b0 ) + 800912a: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 800912e: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 0; + 8009130: 4b1f ldr r3, [pc, #124] ; (80091b0 ) + 8009132: 2200 movs r2, #0 + 8009134: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8009136: 4b1e ldr r3, [pc, #120] ; (80091b0 ) + 8009138: 2200 movs r2, #0 + 800913a: 609a str r2, [r3, #8] + htim2.Init.Period = 65535; + 800913c: 4b1c ldr r3, [pc, #112] ; (80091b0 ) + 800913e: f64f 72ff movw r2, #65535 ; 0xffff + 8009142: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8009144: 4b1a ldr r3, [pc, #104] ; (80091b0 ) + 8009146: 2200 movs r2, #0 + 8009148: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 800914a: 4b19 ldr r3, [pc, #100] ; (80091b0 ) + 800914c: 2200 movs r2, #0 + 800914e: 619a str r2, [r3, #24] + sConfig.EncoderMode = TIM_ENCODERMODE_TI12; + 8009150: 2303 movs r3, #3 + 8009152: 60fb str r3, [r7, #12] + sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; + 8009154: 2300 movs r3, #0 + 8009156: 613b str r3, [r7, #16] + sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; + 8009158: 2301 movs r3, #1 + 800915a: 617b str r3, [r7, #20] + sConfig.IC1Prescaler = TIM_ICPSC_DIV1; + 800915c: 2300 movs r3, #0 + 800915e: 61bb str r3, [r7, #24] + sConfig.IC1Filter = 0; + 8009160: 2300 movs r3, #0 + 8009162: 61fb str r3, [r7, #28] + sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; + 8009164: 2300 movs r3, #0 + 8009166: 623b str r3, [r7, #32] + sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; + 8009168: 2301 movs r3, #1 + 800916a: 627b str r3, [r7, #36] ; 0x24 + sConfig.IC2Prescaler = TIM_ICPSC_DIV1; + 800916c: 2300 movs r3, #0 + 800916e: 62bb str r3, [r7, #40] ; 0x28 + sConfig.IC2Filter = 0; + 8009170: 2300 movs r3, #0 + 8009172: 62fb str r3, [r7, #44] ; 0x2c + if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) + 8009174: f107 030c add.w r3, r7, #12 + 8009178: 4619 mov r1, r3 + 800917a: 480d ldr r0, [pc, #52] ; (80091b0 ) + 800917c: f7fa ff75 bl 800406a + 8009180: 4603 mov r3, r0 + 8009182: 2b00 cmp r3, #0 + 8009184: d001 beq.n 800918a + { + Error_Handler(); + 8009186: f000 fedb bl 8009f40 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 800918a: 2300 movs r3, #0 + 800918c: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 800918e: 2300 movs r3, #0 + 8009190: 60bb str r3, [r7, #8] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 8009192: 1d3b adds r3, r7, #4 + 8009194: 4619 mov r1, r3 + 8009196: 4806 ldr r0, [pc, #24] ; (80091b0 ) + 8009198: f7fb f8b2 bl 8004300 + 800919c: 4603 mov r3, r0 + 800919e: 2b00 cmp r3, #0 + 80091a0: d001 beq.n 80091a6 + { + Error_Handler(); + 80091a2: f000 fecd bl 8009f40 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 80091a6: bf00 nop + 80091a8: 3730 adds r7, #48 ; 0x30 + 80091aa: 46bd mov sp, r7 + 80091ac: bd80 pop {r7, pc} + 80091ae: bf00 nop + 80091b0: 200012c0 .word 0x200012c0 + +080091b4 : + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + 80091b4: b580 push {r7, lr} + 80091b6: af00 add r7, sp, #0 + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + 80091b8: 4b11 ldr r3, [pc, #68] ; (8009200 ) + 80091ba: 4a12 ldr r2, [pc, #72] ; (8009204 ) + 80091bc: 601a str r2, [r3, #0] + huart2.Init.BaudRate = 115200; + 80091be: 4b10 ldr r3, [pc, #64] ; (8009200 ) + 80091c0: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 80091c4: 605a str r2, [r3, #4] + huart2.Init.WordLength = UART_WORDLENGTH_8B; + 80091c6: 4b0e ldr r3, [pc, #56] ; (8009200 ) + 80091c8: 2200 movs r2, #0 + 80091ca: 609a str r2, [r3, #8] + huart2.Init.StopBits = UART_STOPBITS_1; + 80091cc: 4b0c ldr r3, [pc, #48] ; (8009200 ) + 80091ce: 2200 movs r2, #0 + 80091d0: 60da str r2, [r3, #12] + huart2.Init.Parity = UART_PARITY_NONE; + 80091d2: 4b0b ldr r3, [pc, #44] ; (8009200 ) + 80091d4: 2200 movs r2, #0 + 80091d6: 611a str r2, [r3, #16] + huart2.Init.Mode = UART_MODE_TX_RX; + 80091d8: 4b09 ldr r3, [pc, #36] ; (8009200 ) + 80091da: 220c movs r2, #12 + 80091dc: 615a str r2, [r3, #20] + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 80091de: 4b08 ldr r3, [pc, #32] ; (8009200 ) + 80091e0: 2200 movs r2, #0 + 80091e2: 619a str r2, [r3, #24] + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + 80091e4: 4b06 ldr r3, [pc, #24] ; (8009200 ) + 80091e6: 2200 movs r2, #0 + 80091e8: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart2) != HAL_OK) + 80091ea: 4805 ldr r0, [pc, #20] ; (8009200 ) + 80091ec: f7fb f8cc bl 8004388 + 80091f0: 4603 mov r3, r0 + 80091f2: 2b00 cmp r3, #0 + 80091f4: d001 beq.n 80091fa + { + Error_Handler(); + 80091f6: f000 fea3 bl 8009f40 + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + 80091fa: bf00 nop + 80091fc: bd80 pop {r7, pc} + 80091fe: bf00 nop + 8009200: 20001300 .word 0x20001300 + 8009204: 40004400 .word 0x40004400 + +08009208 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8009208: b580 push {r7, lr} + 800920a: b088 sub sp, #32 + 800920c: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800920e: f107 0310 add.w r3, r7, #16 + 8009212: 2200 movs r2, #0 + 8009214: 601a str r2, [r3, #0] + 8009216: 605a str r2, [r3, #4] + 8009218: 609a str r2, [r3, #8] + 800921a: 60da str r2, [r3, #12] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800921c: 4b29 ldr r3, [pc, #164] ; (80092c4 ) + 800921e: 699b ldr r3, [r3, #24] + 8009220: 4a28 ldr r2, [pc, #160] ; (80092c4 ) + 8009222: f043 0310 orr.w r3, r3, #16 + 8009226: 6193 str r3, [r2, #24] + 8009228: 4b26 ldr r3, [pc, #152] ; (80092c4 ) + 800922a: 699b ldr r3, [r3, #24] + 800922c: f003 0310 and.w r3, r3, #16 + 8009230: 60fb str r3, [r7, #12] + 8009232: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8009234: 4b23 ldr r3, [pc, #140] ; (80092c4 ) + 8009236: 699b ldr r3, [r3, #24] + 8009238: 4a22 ldr r2, [pc, #136] ; (80092c4 ) + 800923a: f043 0320 orr.w r3, r3, #32 + 800923e: 6193 str r3, [r2, #24] + 8009240: 4b20 ldr r3, [pc, #128] ; (80092c4 ) + 8009242: 699b ldr r3, [r3, #24] + 8009244: f003 0320 and.w r3, r3, #32 + 8009248: 60bb str r3, [r7, #8] + 800924a: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800924c: 4b1d ldr r3, [pc, #116] ; (80092c4 ) + 800924e: 699b ldr r3, [r3, #24] + 8009250: 4a1c ldr r2, [pc, #112] ; (80092c4 ) + 8009252: f043 0304 orr.w r3, r3, #4 + 8009256: 6193 str r3, [r2, #24] + 8009258: 4b1a ldr r3, [pc, #104] ; (80092c4 ) + 800925a: 699b ldr r3, [r3, #24] + 800925c: f003 0304 and.w r3, r3, #4 + 8009260: 607b str r3, [r7, #4] + 8009262: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8009264: 4b17 ldr r3, [pc, #92] ; (80092c4 ) + 8009266: 699b ldr r3, [r3, #24] + 8009268: 4a16 ldr r2, [pc, #88] ; (80092c4 ) + 800926a: f043 0308 orr.w r3, r3, #8 + 800926e: 6193 str r3, [r2, #24] + 8009270: 4b14 ldr r3, [pc, #80] ; (80092c4 ) + 8009272: 699b ldr r3, [r3, #24] + 8009274: f003 0308 and.w r3, r3, #8 + 8009278: 603b str r3, [r7, #0] + 800927a: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); + 800927c: 2200 movs r2, #0 + 800927e: 21e0 movs r1, #224 ; 0xe0 + 8009280: 4811 ldr r0, [pc, #68] ; (80092c8 ) + 8009282: f7f8 f9ba bl 80015fa + + /*Configure GPIO pin : PA4 */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + 8009286: 2310 movs r3, #16 + 8009288: 613b str r3, [r7, #16] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800928a: 2300 movs r3, #0 + 800928c: 617b str r3, [r7, #20] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800928e: 2300 movs r3, #0 + 8009290: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8009292: f107 0310 add.w r3, r7, #16 + 8009296: 4619 mov r1, r3 + 8009298: 480b ldr r0, [pc, #44] ; (80092c8 ) + 800929a: f7f8 f83d bl 8001318 + + /*Configure GPIO pins : PA5 PA6 PA7 */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 800929e: 23e0 movs r3, #224 ; 0xe0 + 80092a0: 613b str r3, [r7, #16] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80092a2: 2301 movs r3, #1 + 80092a4: 617b str r3, [r7, #20] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80092a6: 2300 movs r3, #0 + 80092a8: 61bb str r3, [r7, #24] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80092aa: 2302 movs r3, #2 + 80092ac: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80092ae: f107 0310 add.w r3, r7, #16 + 80092b2: 4619 mov r1, r3 + 80092b4: 4804 ldr r0, [pc, #16] ; (80092c8 ) + 80092b6: f7f8 f82f bl 8001318 + +} + 80092ba: bf00 nop + 80092bc: 3720 adds r7, #32 + 80092be: 46bd mov sp, r7 + 80092c0: bd80 pop {r7, pc} + 80092c2: bf00 nop + 80092c4: 40021000 .word 0x40021000 + 80092c8: 40010800 .word 0x40010800 + +080092cc : + +/* USER CODE BEGIN 4 */ +void initDisplay() { + 80092cc: b580 push {r7, lr} + 80092ce: af00 add r7, sp, #0 + ILI9341_Unselect(); + 80092d0: f7fc fae8 bl 80058a4 + ILI9341_TouchUnselect(); + 80092d4: f7fd f978 bl 80065c8 + ILI9341_Init(); + 80092d8: f7fc fb92 bl 8005a00 +} + 80092dc: bf00 nop + 80092de: bd80 pop {r7, pc} + +080092e0 : + HAL_MAX_DELAY); + va_end(args); +} + +void drawLineCircle (int32_t centreX, int32_t centreY, int32_t diameter, uint16_t color) +{ + 80092e0: b5b0 push {r4, r5, r7, lr} + 80092e2: b08c sub sp, #48 ; 0x30 + 80092e4: af02 add r7, sp, #8 + 80092e6: 60f8 str r0, [r7, #12] + 80092e8: 60b9 str r1, [r7, #8] + 80092ea: 607a str r2, [r7, #4] + 80092ec: 807b strh r3, [r7, #2] + int32_t dxOuter, dyOuter, dxi, dyi; + for (float i = 0; i <360; i = i + 22.5) { + 80092ee: f04f 0300 mov.w r3, #0 + 80092f2: 627b str r3, [r7, #36] ; 0x24 + 80092f4: e0a5 b.n 8009442 + dxOuter = diameter * cos((i-90)*M_PI/180.0); + 80092f6: 6878 ldr r0, [r7, #4] + 80092f8: f7f7 f87c bl 80003f4 <__aeabi_i2d> + 80092fc: 4604 mov r4, r0 + 80092fe: 460d mov r5, r1 + 8009300: 495b ldr r1, [pc, #364] ; (8009470 ) + 8009302: 6a78 ldr r0, [r7, #36] ; 0x24 + 8009304: f7f7 fba6 bl 8000a54 <__aeabi_fsub> + 8009308: 4603 mov r3, r0 + 800930a: 4618 mov r0, r3 + 800930c: f7f7 f884 bl 8000418 <__aeabi_f2d> + 8009310: a353 add r3, pc, #332 ; (adr r3, 8009460 ) + 8009312: e9d3 2300 ldrd r2, r3, [r3] + 8009316: f7f7 f8d7 bl 80004c8 <__aeabi_dmul> + 800931a: 4602 mov r2, r0 + 800931c: 460b mov r3, r1 + 800931e: 4610 mov r0, r2 + 8009320: 4619 mov r1, r3 + 8009322: f04f 0200 mov.w r2, #0 + 8009326: 4b53 ldr r3, [pc, #332] ; (8009474 ) + 8009328: f7f7 f9f8 bl 800071c <__aeabi_ddiv> + 800932c: 4602 mov r2, r0 + 800932e: 460b mov r3, r1 + 8009330: 4610 mov r0, r2 + 8009332: 4619 mov r1, r3 + 8009334: f002 f910 bl 800b558 + 8009338: 4602 mov r2, r0 + 800933a: 460b mov r3, r1 + 800933c: 4620 mov r0, r4 + 800933e: 4629 mov r1, r5 + 8009340: f7f7 f8c2 bl 80004c8 <__aeabi_dmul> + 8009344: 4603 mov r3, r0 + 8009346: 460c mov r4, r1 + 8009348: 4618 mov r0, r3 + 800934a: 4621 mov r1, r4 + 800934c: f7f7 fb56 bl 80009fc <__aeabi_d2iz> + 8009350: 4603 mov r3, r0 + 8009352: 623b str r3, [r7, #32] + dyOuter = diameter * sin((i-90)*M_PI/180.0); + 8009354: 6878 ldr r0, [r7, #4] + 8009356: f7f7 f84d bl 80003f4 <__aeabi_i2d> + 800935a: 4604 mov r4, r0 + 800935c: 460d mov r5, r1 + 800935e: 4944 ldr r1, [pc, #272] ; (8009470 ) + 8009360: 6a78 ldr r0, [r7, #36] ; 0x24 + 8009362: f7f7 fb77 bl 8000a54 <__aeabi_fsub> + 8009366: 4603 mov r3, r0 + 8009368: 4618 mov r0, r3 + 800936a: f7f7 f855 bl 8000418 <__aeabi_f2d> + 800936e: a33c add r3, pc, #240 ; (adr r3, 8009460 ) + 8009370: e9d3 2300 ldrd r2, r3, [r3] + 8009374: f7f7 f8a8 bl 80004c8 <__aeabi_dmul> + 8009378: 4602 mov r2, r0 + 800937a: 460b mov r3, r1 + 800937c: 4610 mov r0, r2 + 800937e: 4619 mov r1, r3 + 8009380: f04f 0200 mov.w r2, #0 + 8009384: 4b3b ldr r3, [pc, #236] ; (8009474 ) + 8009386: f7f7 f9c9 bl 800071c <__aeabi_ddiv> + 800938a: 4602 mov r2, r0 + 800938c: 460b mov r3, r1 + 800938e: 4610 mov r0, r2 + 8009390: 4619 mov r1, r3 + 8009392: f002 f95d bl 800b650 + 8009396: 4602 mov r2, r0 + 8009398: 460b mov r3, r1 + 800939a: 4620 mov r0, r4 + 800939c: 4629 mov r1, r5 + 800939e: f7f7 f893 bl 80004c8 <__aeabi_dmul> + 80093a2: 4603 mov r3, r0 + 80093a4: 460c mov r4, r1 + 80093a6: 4618 mov r0, r3 + 80093a8: 4621 mov r1, r4 + 80093aa: f7f7 fb27 bl 80009fc <__aeabi_d2iz> + 80093ae: 4603 mov r3, r0 + 80093b0: 61fb str r3, [r7, #28] + dxi = dxOuter * 0.98; + 80093b2: 6a38 ldr r0, [r7, #32] + 80093b4: f7f7 f81e bl 80003f4 <__aeabi_i2d> + 80093b8: a32b add r3, pc, #172 ; (adr r3, 8009468 ) + 80093ba: e9d3 2300 ldrd r2, r3, [r3] + 80093be: f7f7 f883 bl 80004c8 <__aeabi_dmul> + 80093c2: 4603 mov r3, r0 + 80093c4: 460c mov r4, r1 + 80093c6: 4618 mov r0, r3 + 80093c8: 4621 mov r1, r4 + 80093ca: f7f7 fb17 bl 80009fc <__aeabi_d2iz> + 80093ce: 4603 mov r3, r0 + 80093d0: 61bb str r3, [r7, #24] + dyi = dyOuter * 0.98; + 80093d2: 69f8 ldr r0, [r7, #28] + 80093d4: f7f7 f80e bl 80003f4 <__aeabi_i2d> + 80093d8: a323 add r3, pc, #140 ; (adr r3, 8009468 ) + 80093da: e9d3 2300 ldrd r2, r3, [r3] + 80093de: f7f7 f873 bl 80004c8 <__aeabi_dmul> + 80093e2: 4603 mov r3, r0 + 80093e4: 460c mov r4, r1 + 80093e6: 4618 mov r0, r3 + 80093e8: 4621 mov r1, r4 + 80093ea: f7f7 fb07 bl 80009fc <__aeabi_d2iz> + 80093ee: 4603 mov r3, r0 + 80093f0: 617b str r3, [r7, #20] + ILI9341_writeLine(dxi+centreX,dyi+centreY,dxOuter+centreX,dyOuter+centreY,color); + 80093f2: 69bb ldr r3, [r7, #24] + 80093f4: b29a uxth r2, r3 + 80093f6: 68fb ldr r3, [r7, #12] + 80093f8: b29b uxth r3, r3 + 80093fa: 4413 add r3, r2 + 80093fc: b29b uxth r3, r3 + 80093fe: b218 sxth r0, r3 + 8009400: 697b ldr r3, [r7, #20] + 8009402: b29a uxth r2, r3 + 8009404: 68bb ldr r3, [r7, #8] + 8009406: b29b uxth r3, r3 + 8009408: 4413 add r3, r2 + 800940a: b29b uxth r3, r3 + 800940c: b219 sxth r1, r3 + 800940e: 6a3b ldr r3, [r7, #32] + 8009410: b29a uxth r2, r3 + 8009412: 68fb ldr r3, [r7, #12] + 8009414: b29b uxth r3, r3 + 8009416: 4413 add r3, r2 + 8009418: b29b uxth r3, r3 + 800941a: b21c sxth r4, r3 + 800941c: 69fb ldr r3, [r7, #28] + 800941e: b29a uxth r2, r3 + 8009420: 68bb ldr r3, [r7, #8] + 8009422: b29b uxth r3, r3 + 8009424: 4413 add r3, r2 + 8009426: b29b uxth r3, r3 + 8009428: b21a sxth r2, r3 + 800942a: 887b ldrh r3, [r7, #2] + 800942c: 9300 str r3, [sp, #0] + 800942e: 4613 mov r3, r2 + 8009430: 4622 mov r2, r4 + 8009432: f7fc fd7d bl 8005f30 + for (float i = 0; i <360; i = i + 22.5) { + 8009436: 4910 ldr r1, [pc, #64] ; (8009478 ) + 8009438: 6a78 ldr r0, [r7, #36] ; 0x24 + 800943a: f7f7 fb0d bl 8000a58 <__addsf3> + 800943e: 4603 mov r3, r0 + 8009440: 627b str r3, [r7, #36] ; 0x24 + 8009442: 490e ldr r1, [pc, #56] ; (800947c ) + 8009444: 6a78 ldr r0, [r7, #36] ; 0x24 + 8009446: f7f7 fdad bl 8000fa4 <__aeabi_fcmplt> + 800944a: 4603 mov r3, r0 + 800944c: 2b00 cmp r3, #0 + 800944e: f47f af52 bne.w 80092f6 +} +} + 8009452: bf00 nop + 8009454: 3728 adds r7, #40 ; 0x28 + 8009456: 46bd mov sp, r7 + 8009458: bdb0 pop {r4, r5, r7, pc} + 800945a: bf00 nop + 800945c: f3af 8000 nop.w + 8009460: 54442d18 .word 0x54442d18 + 8009464: 400921fb .word 0x400921fb + 8009468: f5c28f5c .word 0xf5c28f5c + 800946c: 3fef5c28 .word 0x3fef5c28 + 8009470: 42b40000 .word 0x42b40000 + 8009474: 40668000 .word 0x40668000 + 8009478: 41b40000 .word 0x41b40000 + 800947c: 43b40000 .word 0x43b40000 + +08009480 : + +void drawStatic (void) +{ + 8009480: b580 push {r7, lr} + 8009482: b084 sub sp, #16 + 8009484: af04 add r7, sp, #16 + ILI9341_FillScreen(ILI9341_BLACK); + 8009486: 2000 movs r0, #0 + 8009488: f7fd f88c bl 80065a4 + ILI9341_WriteString(0, 0, "ANTENNA ROTATOR", Font_11x18, ILI9341_RED, ILI9341_BLACK); + 800948c: 4b61 ldr r3, [pc, #388] ; (8009614 ) + 800948e: 2200 movs r2, #0 + 8009490: 9202 str r2, [sp, #8] + 8009492: f44f 4278 mov.w r2, #63488 ; 0xf800 + 8009496: 9201 str r2, [sp, #4] + 8009498: 685a ldr r2, [r3, #4] + 800949a: 9200 str r2, [sp, #0] + 800949c: 681b ldr r3, [r3, #0] + 800949e: 4a5e ldr r2, [pc, #376] ; (8009618 ) + 80094a0: 2100 movs r1, #0 + 80094a2: 2000 movs r0, #0 + 80094a4: f7fc fc89 bl 8005dba + ILI9341_WriteString(30, 18, "CONTROLLER", Font_11x18, ILI9341_RED, ILI9341_BLACK); + 80094a8: 4b5a ldr r3, [pc, #360] ; (8009614 ) + 80094aa: 2200 movs r2, #0 + 80094ac: 9202 str r2, [sp, #8] + 80094ae: f44f 4278 mov.w r2, #63488 ; 0xf800 + 80094b2: 9201 str r2, [sp, #4] + 80094b4: 685a ldr r2, [r3, #4] + 80094b6: 9200 str r2, [sp, #0] + 80094b8: 681b ldr r3, [r3, #0] + 80094ba: 4a58 ldr r2, [pc, #352] ; (800961c ) + 80094bc: 2112 movs r1, #18 + 80094be: 201e movs r0, #30 + 80094c0: f7fc fc7b bl 8005dba + ILI9341_WriteString(5, 80, "Cur pos:", Font_11x18, ILI9341_RED, ILI9341_BLACK); + 80094c4: 4b53 ldr r3, [pc, #332] ; (8009614 ) + 80094c6: 2200 movs r2, #0 + 80094c8: 9202 str r2, [sp, #8] + 80094ca: f44f 4278 mov.w r2, #63488 ; 0xf800 + 80094ce: 9201 str r2, [sp, #4] + 80094d0: 685a ldr r2, [r3, #4] + 80094d2: 9200 str r2, [sp, #0] + 80094d4: 681b ldr r3, [r3, #0] + 80094d6: 4a52 ldr r2, [pc, #328] ; (8009620 ) + 80094d8: 2150 movs r1, #80 ; 0x50 + 80094da: 2005 movs r0, #5 + 80094dc: f7fc fc6d bl 8005dba + ILI9341_WriteString(55, 100, "O", Font_7x10, ILI9341_RED, ILI9341_BLACK); + 80094e0: 4b50 ldr r3, [pc, #320] ; (8009624 ) + 80094e2: 2200 movs r2, #0 + 80094e4: 9202 str r2, [sp, #8] + 80094e6: f44f 4278 mov.w r2, #63488 ; 0xf800 + 80094ea: 9201 str r2, [sp, #4] + 80094ec: 685a ldr r2, [r3, #4] + 80094ee: 9200 str r2, [sp, #0] + 80094f0: 681b ldr r3, [r3, #0] + 80094f2: 4a4d ldr r2, [pc, #308] ; (8009628 ) + 80094f4: 2164 movs r1, #100 ; 0x64 + 80094f6: 2037 movs r0, #55 ; 0x37 + 80094f8: f7fc fc5f bl 8005dba + ILI9341_WriteString(5, 126, "Set pos:", Font_11x18, ILI9341_RED, ILI9341_BLACK); + 80094fc: 4b45 ldr r3, [pc, #276] ; (8009614 ) + 80094fe: 2200 movs r2, #0 + 8009500: 9202 str r2, [sp, #8] + 8009502: f44f 4278 mov.w r2, #63488 ; 0xf800 + 8009506: 9201 str r2, [sp, #4] + 8009508: 685a ldr r2, [r3, #4] + 800950a: 9200 str r2, [sp, #0] + 800950c: 681b ldr r3, [r3, #0] + 800950e: 4a47 ldr r2, [pc, #284] ; (800962c ) + 8009510: 217e movs r1, #126 ; 0x7e + 8009512: 2005 movs r0, #5 + 8009514: f7fc fc51 bl 8005dba + ILI9341_WriteString(55, 145, "O", Font_7x10, ILI9341_RED, ILI9341_BLACK); + 8009518: 4b42 ldr r3, [pc, #264] ; (8009624 ) + 800951a: 2200 movs r2, #0 + 800951c: 9202 str r2, [sp, #8] + 800951e: f44f 4278 mov.w r2, #63488 ; 0xf800 + 8009522: 9201 str r2, [sp, #4] + 8009524: 685a ldr r2, [r3, #4] + 8009526: 9200 str r2, [sp, #0] + 8009528: 681b ldr r3, [r3, #0] + 800952a: 4a3f ldr r2, [pc, #252] ; (8009628 ) + 800952c: 2191 movs r1, #145 ; 0x91 + 800952e: 2037 movs r0, #55 ; 0x37 + 8009530: f7fc fc43 bl 8005dba + ILI9341_WriteString(x_center+radius+7, y_center-5, "90", Font_7x10, ILI9341_GREEN, ILI9341_BLACK); + 8009534: 4b3e ldr r3, [pc, #248] ; (8009630 ) + 8009536: 681b ldr r3, [r3, #0] + 8009538: b29a uxth r2, r3 + 800953a: 4b3e ldr r3, [pc, #248] ; (8009634 ) + 800953c: 681b ldr r3, [r3, #0] + 800953e: b29b uxth r3, r3 + 8009540: 4413 add r3, r2 + 8009542: b29b uxth r3, r3 + 8009544: 3307 adds r3, #7 + 8009546: b298 uxth r0, r3 + 8009548: 4b3b ldr r3, [pc, #236] ; (8009638 ) + 800954a: 681b ldr r3, [r3, #0] + 800954c: b29b uxth r3, r3 + 800954e: 3b05 subs r3, #5 + 8009550: b299 uxth r1, r3 + 8009552: 4b34 ldr r3, [pc, #208] ; (8009624 ) + 8009554: 2200 movs r2, #0 + 8009556: 9202 str r2, [sp, #8] + 8009558: f44f 62fc mov.w r2, #2016 ; 0x7e0 + 800955c: 9201 str r2, [sp, #4] + 800955e: 685a ldr r2, [r3, #4] + 8009560: 9200 str r2, [sp, #0] + 8009562: 681b ldr r3, [r3, #0] + 8009564: 4a35 ldr r2, [pc, #212] ; (800963c ) + 8009566: f7fc fc28 bl 8005dba + ILI9341_WriteString(x_center-radius-28, y_center-5, "270", Font_7x10, ILI9341_GREEN, ILI9341_BLACK); + 800956a: 4b31 ldr r3, [pc, #196] ; (8009630 ) + 800956c: 681b ldr r3, [r3, #0] + 800956e: b29a uxth r2, r3 + 8009570: 4b30 ldr r3, [pc, #192] ; (8009634 ) + 8009572: 681b ldr r3, [r3, #0] + 8009574: b29b uxth r3, r3 + 8009576: 1ad3 subs r3, r2, r3 + 8009578: b29b uxth r3, r3 + 800957a: 3b1c subs r3, #28 + 800957c: b298 uxth r0, r3 + 800957e: 4b2e ldr r3, [pc, #184] ; (8009638 ) + 8009580: 681b ldr r3, [r3, #0] + 8009582: b29b uxth r3, r3 + 8009584: 3b05 subs r3, #5 + 8009586: b299 uxth r1, r3 + 8009588: 4b26 ldr r3, [pc, #152] ; (8009624 ) + 800958a: 2200 movs r2, #0 + 800958c: 9202 str r2, [sp, #8] + 800958e: f44f 62fc mov.w r2, #2016 ; 0x7e0 + 8009592: 9201 str r2, [sp, #4] + 8009594: 685a ldr r2, [r3, #4] + 8009596: 9200 str r2, [sp, #0] + 8009598: 681b ldr r3, [r3, #0] + 800959a: 4a29 ldr r2, [pc, #164] ; (8009640 ) + 800959c: f7fc fc0d bl 8005dba + ILI9341_WriteString(x_center-10, y_center+radius+7, "180", Font_7x10, ILI9341_GREEN, ILI9341_BLACK); + 80095a0: 4b23 ldr r3, [pc, #140] ; (8009630 ) + 80095a2: 681b ldr r3, [r3, #0] + 80095a4: b29b uxth r3, r3 + 80095a6: 3b0a subs r3, #10 + 80095a8: b298 uxth r0, r3 + 80095aa: 4b23 ldr r3, [pc, #140] ; (8009638 ) + 80095ac: 681b ldr r3, [r3, #0] + 80095ae: b29a uxth r2, r3 + 80095b0: 4b20 ldr r3, [pc, #128] ; (8009634 ) + 80095b2: 681b ldr r3, [r3, #0] + 80095b4: b29b uxth r3, r3 + 80095b6: 4413 add r3, r2 + 80095b8: b29b uxth r3, r3 + 80095ba: 3307 adds r3, #7 + 80095bc: b299 uxth r1, r3 + 80095be: 4b19 ldr r3, [pc, #100] ; (8009624 ) + 80095c0: 2200 movs r2, #0 + 80095c2: 9202 str r2, [sp, #8] + 80095c4: f44f 62fc mov.w r2, #2016 ; 0x7e0 + 80095c8: 9201 str r2, [sp, #4] + 80095ca: 685a ldr r2, [r3, #4] + 80095cc: 9200 str r2, [sp, #0] + 80095ce: 681b ldr r3, [r3, #0] + 80095d0: 4a1c ldr r2, [pc, #112] ; (8009644 ) + 80095d2: f7fc fbf2 bl 8005dba + ILI9341_WriteString(x_center-3, y_center-radius-17, "0", Font_7x10, ILI9341_GREEN, ILI9341_BLACK); + 80095d6: 4b16 ldr r3, [pc, #88] ; (8009630 ) + 80095d8: 681b ldr r3, [r3, #0] + 80095da: b29b uxth r3, r3 + 80095dc: 3b03 subs r3, #3 + 80095de: b298 uxth r0, r3 + 80095e0: 4b15 ldr r3, [pc, #84] ; (8009638 ) + 80095e2: 681b ldr r3, [r3, #0] + 80095e4: b29a uxth r2, r3 + 80095e6: 4b13 ldr r3, [pc, #76] ; (8009634 ) + 80095e8: 681b ldr r3, [r3, #0] + 80095ea: b29b uxth r3, r3 + 80095ec: 1ad3 subs r3, r2, r3 + 80095ee: b29b uxth r3, r3 + 80095f0: 3b11 subs r3, #17 + 80095f2: b299 uxth r1, r3 + 80095f4: 4b0b ldr r3, [pc, #44] ; (8009624 ) + 80095f6: 2200 movs r2, #0 + 80095f8: 9202 str r2, [sp, #8] + 80095fa: f44f 62fc mov.w r2, #2016 ; 0x7e0 + 80095fe: 9201 str r2, [sp, #4] + 8009600: 685a ldr r2, [r3, #4] + 8009602: 9200 str r2, [sp, #0] + 8009604: 681b ldr r3, [r3, #0] + 8009606: 4a10 ldr r2, [pc, #64] ; (8009648 ) + 8009608: f7fc fbd7 bl 8005dba +} + 800960c: bf00 nop + 800960e: 46bd mov sp, r7 + 8009610: bd80 pop {r7, pc} + 8009612: bf00 nop + 8009614: 20000010 .word 0x20000010 + 8009618: 0800c6ec .word 0x0800c6ec + 800961c: 0800c6fc .word 0x0800c6fc + 8009620: 0800c708 .word 0x0800c708 + 8009624: 20000008 .word 0x20000008 + 8009628: 0800c714 .word 0x0800c714 + 800962c: 0800c718 .word 0x0800c718 + 8009630: 20000138 .word 0x20000138 + 8009634: 20000134 .word 0x20000134 + 8009638: 2000013c .word 0x2000013c + 800963c: 0800c724 .word 0x0800c724 + 8009640: 0800c728 .word 0x0800c728 + 8009644: 0800c72c .word 0x0800c72c + 8009648: 0800c730 .word 0x0800c730 + 800964c: 00000000 .word 0x00000000 + +08009650 : + +void drawDirection (int32_t angle, int32_t x, int32_t y, uint16_t color) { + 8009650: b580 push {r7, lr} + 8009652: b088 sub sp, #32 + 8009654: af04 add r7, sp, #16 + 8009656: 60f8 str r0, [r7, #12] + 8009658: 60b9 str r1, [r7, #8] + 800965a: 607a str r2, [r7, #4] + 800965c: 807b strh r3, [r7, #2] + if((angle < 22.5) || (angle > 337.5 )) ILI9341_WriteString(x,y,"North ",Font_16x26,color, ILI9341_BLACK); + 800965e: 68f8 ldr r0, [r7, #12] + 8009660: f7f6 fec8 bl 80003f4 <__aeabi_i2d> + 8009664: f04f 0200 mov.w r2, #0 + 8009668: 4ba3 ldr r3, [pc, #652] ; (80098f8 ) + 800966a: f7f7 f99f bl 80009ac <__aeabi_dcmplt> + 800966e: 4603 mov r3, r0 + 8009670: 2b00 cmp r3, #0 + 8009672: d10a bne.n 800968a + 8009674: 68f8 ldr r0, [r7, #12] + 8009676: f7f6 febd bl 80003f4 <__aeabi_i2d> + 800967a: a391 add r3, pc, #580 ; (adr r3, 80098c0 ) + 800967c: e9d3 2300 ldrd r2, r3, [r3] + 8009680: f7f7 f9b2 bl 80009e8 <__aeabi_dcmpgt> + 8009684: 4603 mov r3, r0 + 8009686: 2b00 cmp r3, #0 + 8009688: d00e beq.n 80096a8 + 800968a: 68bb ldr r3, [r7, #8] + 800968c: b298 uxth r0, r3 + 800968e: 687b ldr r3, [r7, #4] + 8009690: b299 uxth r1, r3 + 8009692: 4b9a ldr r3, [pc, #616] ; (80098fc ) + 8009694: 2200 movs r2, #0 + 8009696: 9202 str r2, [sp, #8] + 8009698: 887a ldrh r2, [r7, #2] + 800969a: 9201 str r2, [sp, #4] + 800969c: 685a ldr r2, [r3, #4] + 800969e: 9200 str r2, [sp, #0] + 80096a0: 681b ldr r3, [r3, #0] + 80096a2: 4a97 ldr r2, [pc, #604] ; (8009900 ) + 80096a4: f7fc fb89 bl 8005dba + if((angle > 22.5) && (angle < 67.5 )) ILI9341_WriteString(x,y,"North-East",Font_16x26,color, ILI9341_BLACK); + 80096a8: 68f8 ldr r0, [r7, #12] + 80096aa: f7f6 fea3 bl 80003f4 <__aeabi_i2d> + 80096ae: f04f 0200 mov.w r2, #0 + 80096b2: 4b91 ldr r3, [pc, #580] ; (80098f8 ) + 80096b4: f7f7 f998 bl 80009e8 <__aeabi_dcmpgt> + 80096b8: 4603 mov r3, r0 + 80096ba: 2b00 cmp r3, #0 + 80096bc: d019 beq.n 80096f2 + 80096be: 68f8 ldr r0, [r7, #12] + 80096c0: f7f6 fe98 bl 80003f4 <__aeabi_i2d> + 80096c4: a380 add r3, pc, #512 ; (adr r3, 80098c8 ) + 80096c6: e9d3 2300 ldrd r2, r3, [r3] + 80096ca: f7f7 f96f bl 80009ac <__aeabi_dcmplt> + 80096ce: 4603 mov r3, r0 + 80096d0: 2b00 cmp r3, #0 + 80096d2: d00e beq.n 80096f2 + 80096d4: 68bb ldr r3, [r7, #8] + 80096d6: b298 uxth r0, r3 + 80096d8: 687b ldr r3, [r7, #4] + 80096da: b299 uxth r1, r3 + 80096dc: 4b87 ldr r3, [pc, #540] ; (80098fc ) + 80096de: 2200 movs r2, #0 + 80096e0: 9202 str r2, [sp, #8] + 80096e2: 887a ldrh r2, [r7, #2] + 80096e4: 9201 str r2, [sp, #4] + 80096e6: 685a ldr r2, [r3, #4] + 80096e8: 9200 str r2, [sp, #0] + 80096ea: 681b ldr r3, [r3, #0] + 80096ec: 4a85 ldr r2, [pc, #532] ; (8009904 ) + 80096ee: f7fc fb64 bl 8005dba + if((angle > 67.5) && (angle < 112.5 )) ILI9341_WriteString(x,y,"East ",Font_16x26,color, ILI9341_BLACK); + 80096f2: 68f8 ldr r0, [r7, #12] + 80096f4: f7f6 fe7e bl 80003f4 <__aeabi_i2d> + 80096f8: a373 add r3, pc, #460 ; (adr r3, 80098c8 ) + 80096fa: e9d3 2300 ldrd r2, r3, [r3] + 80096fe: f7f7 f973 bl 80009e8 <__aeabi_dcmpgt> + 8009702: 4603 mov r3, r0 + 8009704: 2b00 cmp r3, #0 + 8009706: d019 beq.n 800973c + 8009708: 68f8 ldr r0, [r7, #12] + 800970a: f7f6 fe73 bl 80003f4 <__aeabi_i2d> + 800970e: a370 add r3, pc, #448 ; (adr r3, 80098d0 ) + 8009710: e9d3 2300 ldrd r2, r3, [r3] + 8009714: f7f7 f94a bl 80009ac <__aeabi_dcmplt> + 8009718: 4603 mov r3, r0 + 800971a: 2b00 cmp r3, #0 + 800971c: d00e beq.n 800973c + 800971e: 68bb ldr r3, [r7, #8] + 8009720: b298 uxth r0, r3 + 8009722: 687b ldr r3, [r7, #4] + 8009724: b299 uxth r1, r3 + 8009726: 4b75 ldr r3, [pc, #468] ; (80098fc ) + 8009728: 2200 movs r2, #0 + 800972a: 9202 str r2, [sp, #8] + 800972c: 887a ldrh r2, [r7, #2] + 800972e: 9201 str r2, [sp, #4] + 8009730: 685a ldr r2, [r3, #4] + 8009732: 9200 str r2, [sp, #0] + 8009734: 681b ldr r3, [r3, #0] + 8009736: 4a74 ldr r2, [pc, #464] ; (8009908 ) + 8009738: f7fc fb3f bl 8005dba + if((angle > 112.5) && (angle < 157.5 )) ILI9341_WriteString(x,y,"South-East",Font_16x26,color, ILI9341_BLACK); + 800973c: 68f8 ldr r0, [r7, #12] + 800973e: f7f6 fe59 bl 80003f4 <__aeabi_i2d> + 8009742: a363 add r3, pc, #396 ; (adr r3, 80098d0 ) + 8009744: e9d3 2300 ldrd r2, r3, [r3] + 8009748: f7f7 f94e bl 80009e8 <__aeabi_dcmpgt> + 800974c: 4603 mov r3, r0 + 800974e: 2b00 cmp r3, #0 + 8009750: d019 beq.n 8009786 + 8009752: 68f8 ldr r0, [r7, #12] + 8009754: f7f6 fe4e bl 80003f4 <__aeabi_i2d> + 8009758: a35f add r3, pc, #380 ; (adr r3, 80098d8 ) + 800975a: e9d3 2300 ldrd r2, r3, [r3] + 800975e: f7f7 f925 bl 80009ac <__aeabi_dcmplt> + 8009762: 4603 mov r3, r0 + 8009764: 2b00 cmp r3, #0 + 8009766: d00e beq.n 8009786 + 8009768: 68bb ldr r3, [r7, #8] + 800976a: b298 uxth r0, r3 + 800976c: 687b ldr r3, [r7, #4] + 800976e: b299 uxth r1, r3 + 8009770: 4b62 ldr r3, [pc, #392] ; (80098fc ) + 8009772: 2200 movs r2, #0 + 8009774: 9202 str r2, [sp, #8] + 8009776: 887a ldrh r2, [r7, #2] + 8009778: 9201 str r2, [sp, #4] + 800977a: 685a ldr r2, [r3, #4] + 800977c: 9200 str r2, [sp, #0] + 800977e: 681b ldr r3, [r3, #0] + 8009780: 4a62 ldr r2, [pc, #392] ; (800990c ) + 8009782: f7fc fb1a bl 8005dba + if((angle > 157.5) && (angle < 202.5 )) ILI9341_WriteString(x,y,"South ",Font_16x26,color, ILI9341_BLACK); + 8009786: 68f8 ldr r0, [r7, #12] + 8009788: f7f6 fe34 bl 80003f4 <__aeabi_i2d> + 800978c: a352 add r3, pc, #328 ; (adr r3, 80098d8 ) + 800978e: e9d3 2300 ldrd r2, r3, [r3] + 8009792: f7f7 f929 bl 80009e8 <__aeabi_dcmpgt> + 8009796: 4603 mov r3, r0 + 8009798: 2b00 cmp r3, #0 + 800979a: d019 beq.n 80097d0 + 800979c: 68f8 ldr r0, [r7, #12] + 800979e: f7f6 fe29 bl 80003f4 <__aeabi_i2d> + 80097a2: a34f add r3, pc, #316 ; (adr r3, 80098e0 ) + 80097a4: e9d3 2300 ldrd r2, r3, [r3] + 80097a8: f7f7 f900 bl 80009ac <__aeabi_dcmplt> + 80097ac: 4603 mov r3, r0 + 80097ae: 2b00 cmp r3, #0 + 80097b0: d00e beq.n 80097d0 + 80097b2: 68bb ldr r3, [r7, #8] + 80097b4: b298 uxth r0, r3 + 80097b6: 687b ldr r3, [r7, #4] + 80097b8: b299 uxth r1, r3 + 80097ba: 4b50 ldr r3, [pc, #320] ; (80098fc ) + 80097bc: 2200 movs r2, #0 + 80097be: 9202 str r2, [sp, #8] + 80097c0: 887a ldrh r2, [r7, #2] + 80097c2: 9201 str r2, [sp, #4] + 80097c4: 685a ldr r2, [r3, #4] + 80097c6: 9200 str r2, [sp, #0] + 80097c8: 681b ldr r3, [r3, #0] + 80097ca: 4a51 ldr r2, [pc, #324] ; (8009910 ) + 80097cc: f7fc faf5 bl 8005dba + if((angle > 202.5) && (angle < 247.5 )) ILI9341_WriteString(x,y,"South-West",Font_16x26,color, ILI9341_BLACK); + 80097d0: 68f8 ldr r0, [r7, #12] + 80097d2: f7f6 fe0f bl 80003f4 <__aeabi_i2d> + 80097d6: a342 add r3, pc, #264 ; (adr r3, 80098e0 ) + 80097d8: e9d3 2300 ldrd r2, r3, [r3] + 80097dc: f7f7 f904 bl 80009e8 <__aeabi_dcmpgt> + 80097e0: 4603 mov r3, r0 + 80097e2: 2b00 cmp r3, #0 + 80097e4: d019 beq.n 800981a + 80097e6: 68f8 ldr r0, [r7, #12] + 80097e8: f7f6 fe04 bl 80003f4 <__aeabi_i2d> + 80097ec: a33e add r3, pc, #248 ; (adr r3, 80098e8 ) + 80097ee: e9d3 2300 ldrd r2, r3, [r3] + 80097f2: f7f7 f8db bl 80009ac <__aeabi_dcmplt> + 80097f6: 4603 mov r3, r0 + 80097f8: 2b00 cmp r3, #0 + 80097fa: d00e beq.n 800981a + 80097fc: 68bb ldr r3, [r7, #8] + 80097fe: b298 uxth r0, r3 + 8009800: 687b ldr r3, [r7, #4] + 8009802: b299 uxth r1, r3 + 8009804: 4b3d ldr r3, [pc, #244] ; (80098fc ) + 8009806: 2200 movs r2, #0 + 8009808: 9202 str r2, [sp, #8] + 800980a: 887a ldrh r2, [r7, #2] + 800980c: 9201 str r2, [sp, #4] + 800980e: 685a ldr r2, [r3, #4] + 8009810: 9200 str r2, [sp, #0] + 8009812: 681b ldr r3, [r3, #0] + 8009814: 4a3f ldr r2, [pc, #252] ; (8009914 ) + 8009816: f7fc fad0 bl 8005dba + if((angle > 247.5) && (angle < 292.5 )) ILI9341_WriteString(x,y,"West ",Font_16x26,color, ILI9341_BLACK); + 800981a: 68f8 ldr r0, [r7, #12] + 800981c: f7f6 fdea bl 80003f4 <__aeabi_i2d> + 8009820: a331 add r3, pc, #196 ; (adr r3, 80098e8 ) + 8009822: e9d3 2300 ldrd r2, r3, [r3] + 8009826: f7f7 f8df bl 80009e8 <__aeabi_dcmpgt> + 800982a: 4603 mov r3, r0 + 800982c: 2b00 cmp r3, #0 + 800982e: d019 beq.n 8009864 + 8009830: 68f8 ldr r0, [r7, #12] + 8009832: f7f6 fddf bl 80003f4 <__aeabi_i2d> + 8009836: a32e add r3, pc, #184 ; (adr r3, 80098f0 ) + 8009838: e9d3 2300 ldrd r2, r3, [r3] + 800983c: f7f7 f8b6 bl 80009ac <__aeabi_dcmplt> + 8009840: 4603 mov r3, r0 + 8009842: 2b00 cmp r3, #0 + 8009844: d00e beq.n 8009864 + 8009846: 68bb ldr r3, [r7, #8] + 8009848: b298 uxth r0, r3 + 800984a: 687b ldr r3, [r7, #4] + 800984c: b299 uxth r1, r3 + 800984e: 4b2b ldr r3, [pc, #172] ; (80098fc ) + 8009850: 2200 movs r2, #0 + 8009852: 9202 str r2, [sp, #8] + 8009854: 887a ldrh r2, [r7, #2] + 8009856: 9201 str r2, [sp, #4] + 8009858: 685a ldr r2, [r3, #4] + 800985a: 9200 str r2, [sp, #0] + 800985c: 681b ldr r3, [r3, #0] + 800985e: 4a2e ldr r2, [pc, #184] ; (8009918 ) + 8009860: f7fc faab bl 8005dba + if((angle > 292.5) && (angle < 337.5 )) ILI9341_WriteString(x,y,"North-West",Font_16x26,color, ILI9341_BLACK); + 8009864: 68f8 ldr r0, [r7, #12] + 8009866: f7f6 fdc5 bl 80003f4 <__aeabi_i2d> + 800986a: a321 add r3, pc, #132 ; (adr r3, 80098f0 ) + 800986c: e9d3 2300 ldrd r2, r3, [r3] + 8009870: f7f7 f8ba bl 80009e8 <__aeabi_dcmpgt> + 8009874: 4603 mov r3, r0 + 8009876: 2b00 cmp r3, #0 + 8009878: d100 bne.n 800987c +} + 800987a: e01a b.n 80098b2 + if((angle > 292.5) && (angle < 337.5 )) ILI9341_WriteString(x,y,"North-West",Font_16x26,color, ILI9341_BLACK); + 800987c: 68f8 ldr r0, [r7, #12] + 800987e: f7f6 fdb9 bl 80003f4 <__aeabi_i2d> + 8009882: a30f add r3, pc, #60 ; (adr r3, 80098c0 ) + 8009884: e9d3 2300 ldrd r2, r3, [r3] + 8009888: f7f7 f890 bl 80009ac <__aeabi_dcmplt> + 800988c: 4603 mov r3, r0 + 800988e: 2b00 cmp r3, #0 + 8009890: d100 bne.n 8009894 +} + 8009892: e00e b.n 80098b2 + if((angle > 292.5) && (angle < 337.5 )) ILI9341_WriteString(x,y,"North-West",Font_16x26,color, ILI9341_BLACK); + 8009894: 68bb ldr r3, [r7, #8] + 8009896: b298 uxth r0, r3 + 8009898: 687b ldr r3, [r7, #4] + 800989a: b299 uxth r1, r3 + 800989c: 4b17 ldr r3, [pc, #92] ; (80098fc ) + 800989e: 2200 movs r2, #0 + 80098a0: 9202 str r2, [sp, #8] + 80098a2: 887a ldrh r2, [r7, #2] + 80098a4: 9201 str r2, [sp, #4] + 80098a6: 685a ldr r2, [r3, #4] + 80098a8: 9200 str r2, [sp, #0] + 80098aa: 681b ldr r3, [r3, #0] + 80098ac: 4a1b ldr r2, [pc, #108] ; (800991c ) + 80098ae: f7fc fa84 bl 8005dba +} + 80098b2: bf00 nop + 80098b4: 3710 adds r7, #16 + 80098b6: 46bd mov sp, r7 + 80098b8: bd80 pop {r7, pc} + 80098ba: bf00 nop + 80098bc: f3af 8000 nop.w + 80098c0: 00000000 .word 0x00000000 + 80098c4: 40751800 .word 0x40751800 + 80098c8: 00000000 .word 0x00000000 + 80098cc: 4050e000 .word 0x4050e000 + 80098d0: 00000000 .word 0x00000000 + 80098d4: 405c2000 .word 0x405c2000 + 80098d8: 00000000 .word 0x00000000 + 80098dc: 4063b000 .word 0x4063b000 + 80098e0: 00000000 .word 0x00000000 + 80098e4: 40695000 .word 0x40695000 + 80098e8: 00000000 .word 0x00000000 + 80098ec: 406ef000 .word 0x406ef000 + 80098f0: 00000000 .word 0x00000000 + 80098f4: 40724800 .word 0x40724800 + 80098f8: 40368000 .word 0x40368000 + 80098fc: 20000018 .word 0x20000018 + 8009900: 0800c734 .word 0x0800c734 + 8009904: 0800c740 .word 0x0800c740 + 8009908: 0800c74c .word 0x0800c74c + 800990c: 0800c758 .word 0x0800c758 + 8009910: 0800c764 .word 0x0800c764 + 8009914: 0800c770 .word 0x0800c770 + 8009918: 0800c77c .word 0x0800c77c + 800991c: 0800c788 .word 0x0800c788 + +08009920 : + +void GetTime (void) +{ + 8009920: b580 push {r7, lr} + 8009922: b082 sub sp, #8 + 8009924: af02 add r7, sp, #8 + HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN); + 8009926: 2200 movs r2, #0 + 8009928: 490b ldr r1, [pc, #44] ; (8009958 ) + 800992a: 480c ldr r0, [pc, #48] ; (800995c ) + 800992c: f7f9 fd50 bl 80033d0 + snprintf(time_str, 63, "%02d:%02d:%02d", sTime.Hours, sTime.Minutes, sTime.Seconds); + 8009930: 4b09 ldr r3, [pc, #36] ; (8009958 ) + 8009932: 781b ldrb r3, [r3, #0] + 8009934: 4619 mov r1, r3 + 8009936: 4b08 ldr r3, [pc, #32] ; (8009958 ) + 8009938: 785b ldrb r3, [r3, #1] + 800993a: 461a mov r2, r3 + 800993c: 4b06 ldr r3, [pc, #24] ; (8009958 ) + 800993e: 789b ldrb r3, [r3, #2] + 8009940: 9301 str r3, [sp, #4] + 8009942: 9200 str r2, [sp, #0] + 8009944: 460b mov r3, r1 + 8009946: 4a06 ldr r2, [pc, #24] ; (8009960 ) + 8009948: 213f movs r1, #63 ; 0x3f + 800994a: 4806 ldr r0, [pc, #24] ; (8009964 ) + 800994c: f001 f9c8 bl 800ace0 +} + 8009950: bf00 nop + 8009952: 46bd mov sp, r7 + 8009954: bd80 pop {r7, pc} + 8009956: bf00 nop + 8009958: 20000f74 .word 0x20000f74 + 800995c: 200012ac .word 0x200012ac + 8009960: 0800c794 .word 0x0800c794 + 8009964: 20000f78 .word 0x20000f78 + +08009968 : + +void GetEncoder (void) +{ + 8009968: b480 push {r7} + 800996a: af00 add r7, sp, #0 + capture = TIM2->CNT / 4; + 800996c: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8009970: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009972: 089b lsrs r3, r3, #2 + 8009974: 461a mov r2, r3 + 8009976: 4b29 ldr r3, [pc, #164] ; (8009a1c ) + 8009978: 601a str r2, [r3, #0] + if (capture > 8000) { capture -= 65535 / 4; } + 800997a: 4b28 ldr r3, [pc, #160] ; (8009a1c ) + 800997c: 681b ldr r3, [r3, #0] + 800997e: f5b3 5ffa cmp.w r3, #8000 ; 0x1f40 + 8009982: dd06 ble.n 8009992 + 8009984: 4b25 ldr r3, [pc, #148] ; (8009a1c ) + 8009986: 681b ldr r3, [r3, #0] + 8009988: f5a3 537f sub.w r3, r3, #16320 ; 0x3fc0 + 800998c: 3b3f subs r3, #63 ; 0x3f + 800998e: 4a23 ldr r2, [pc, #140] ; (8009a1c ) + 8009990: 6013 str r3, [r2, #0] + if (capture != capture_prev) { + 8009992: 4b22 ldr r3, [pc, #136] ; (8009a1c ) + 8009994: 681a ldr r2, [r3, #0] + 8009996: 4b22 ldr r3, [pc, #136] ; (8009a20 ) + 8009998: 681b ldr r3, [r3, #0] + 800999a: 429a cmp r2, r3 + 800999c: d004 beq.n 80099a8 + encoder_prev = encoder; } + 800999e: 4b21 ldr r3, [pc, #132] ; (8009a24 ) + 80099a0: 681b ldr r3, [r3, #0] + 80099a2: 4a21 ldr r2, [pc, #132] ; (8009a28 ) + 80099a4: 6013 str r3, [r2, #0] + 80099a6: e003 b.n 80099b0 + else { encoder_prev = 10000; } + 80099a8: 4b1f ldr r3, [pc, #124] ; (8009a28 ) + 80099aa: f242 7210 movw r2, #10000 ; 0x2710 + 80099ae: 601a str r2, [r3, #0] + encoder += capture - capture_prev; + 80099b0: 4b1a ldr r3, [pc, #104] ; (8009a1c ) + 80099b2: 681a ldr r2, [r3, #0] + 80099b4: 4b1a ldr r3, [pc, #104] ; (8009a20 ) + 80099b6: 681b ldr r3, [r3, #0] + 80099b8: 1ad2 subs r2, r2, r3 + 80099ba: 4b1a ldr r3, [pc, #104] ; (8009a24 ) + 80099bc: 681b ldr r3, [r3, #0] + 80099be: 4413 add r3, r2 + 80099c0: 4a18 ldr r2, [pc, #96] ; (8009a24 ) + 80099c2: 6013 str r3, [r2, #0] + encoder = (encoder + 360) % 360; + 80099c4: 4b17 ldr r3, [pc, #92] ; (8009a24 ) + 80099c6: 681b ldr r3, [r3, #0] + 80099c8: f503 73b4 add.w r3, r3, #360 ; 0x168 + 80099cc: 4a17 ldr r2, [pc, #92] ; (8009a2c ) + 80099ce: fb82 1203 smull r1, r2, r2, r3 + 80099d2: 441a add r2, r3 + 80099d4: 1211 asrs r1, r2, #8 + 80099d6: 17da asrs r2, r3, #31 + 80099d8: 1a8a subs r2, r1, r2 + 80099da: f44f 71b4 mov.w r1, #360 ; 0x168 + 80099de: fb01 f202 mul.w r2, r1, r2 + 80099e2: 1a9a subs r2, r3, r2 + 80099e4: 4b0f ldr r3, [pc, #60] ; (8009a24 ) + 80099e6: 601a str r2, [r3, #0] + if (encoder == 0) { TIM2->CNT = 0; } + 80099e8: 4b0e ldr r3, [pc, #56] ; (8009a24 ) + 80099ea: 681b ldr r3, [r3, #0] + 80099ec: 2b00 cmp r3, #0 + 80099ee: d103 bne.n 80099f8 + 80099f0: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 80099f4: 2200 movs r2, #0 + 80099f6: 625a str r2, [r3, #36] ; 0x24 + if (encoder > 360) {TIM2->CNT = 0; } + 80099f8: 4b0a ldr r3, [pc, #40] ; (8009a24 ) + 80099fa: 681b ldr r3, [r3, #0] + 80099fc: f5b3 7fb4 cmp.w r3, #360 ; 0x168 + 8009a00: dd03 ble.n 8009a0a + 8009a02: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8009a06: 2200 movs r2, #0 + 8009a08: 625a str r2, [r3, #36] ; 0x24 + capture_prev = capture; + 8009a0a: 4b04 ldr r3, [pc, #16] ; (8009a1c ) + 8009a0c: 681b ldr r3, [r3, #0] + 8009a0e: 4a04 ldr r2, [pc, #16] ; (8009a20 ) + 8009a10: 6013 str r3, [r2, #0] +} + 8009a12: bf00 nop + 8009a14: 46bd mov sp, r7 + 8009a16: bc80 pop {r7} + 8009a18: 4770 bx lr + 8009a1a: bf00 nop + 8009a1c: 20000fc0 .word 0x20000fc0 + 8009a20: 20000fc4 .word 0x20000fc4 + 8009a24: 20000fb8 .word 0x20000fb8 + 8009a28: 20000fbc .word 0x20000fbc + 8009a2c: b60b60b7 .word 0xb60b60b7 + +08009a30 : + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void const * argument) +{ + 8009a30: b580 push {r7, lr} + 8009a32: b082 sub sp, #8 + 8009a34: af00 add r7, sp, #0 + 8009a36: 6078 str r0, [r7, #4] + /* init code for USB_DEVICE */ + MX_USB_DEVICE_Init(); + 8009a38: f000 fc84 bl 800a344 + + /* USER CODE BEGIN 5 */ + /* Infinite loop */ + for (;;) { + osDelay(1); + 8009a3c: 2001 movs r0, #1 + 8009a3e: f7fe f940 bl 8007cc2 + 8009a42: e7fb b.n 8009a3c + 8009a44: 0000 movs r0, r0 + ... + +08009a48 : + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartTask02 */ +void StartTask02(void const * argument) +{ + 8009a48: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8009a4c: b08f sub sp, #60 ; 0x3c + 8009a4e: af04 add r7, sp, #16 + 8009a50: 6078 str r0, [r7, #4] + /* USER CODE BEGIN StartTask02 */ + char buf[25]; + + initDisplay(); + 8009a52: f7ff fc3b bl 80092cc + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8009a56: 4bcc ldr r3, [pc, #816] ; (8009d88 ) + 8009a58: 2200 movs r2, #0 + 8009a5a: 61da str r2, [r3, #28] + HAL_TIM_Encoder_Start(&htim2, TIM_CHANNEL_ALL); + 8009a5c: 213c movs r1, #60 ; 0x3c + 8009a5e: 48cb ldr r0, [pc, #812] ; (8009d8c ) + 8009a60: f7fa fb91 bl 8004186 + drawStatic(); + 8009a64: f7ff fd0c bl 8009480 + + /* Infinite loop */ + for (;;) { + GetTime(); + 8009a68: f7ff ff5a bl 8009920 + GetEncoder(); + 8009a6c: f7ff ff7c bl 8009968 + + if (HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_4) == 0) { + 8009a70: 2110 movs r1, #16 + 8009a72: 48c7 ldr r0, [pc, #796] ; (8009d90 ) + 8009a74: f7f7 fdaa bl 80015cc + + } + + sprintf(buf, "%03ld", encoder); + 8009a78: 4bc6 ldr r3, [pc, #792] ; (8009d94 ) + 8009a7a: 681a ldr r2, [r3, #0] + 8009a7c: f107 030c add.w r3, r7, #12 + 8009a80: 49c5 ldr r1, [pc, #788] ; (8009d98 ) + 8009a82: 4618 mov r0, r3 + 8009a84: f001 f960 bl 800ad48 + drawDirection(encoder,0,210, ILI9341_CYAN); + 8009a88: 4bc2 ldr r3, [pc, #776] ; (8009d94 ) + 8009a8a: 6818 ldr r0, [r3, #0] + 8009a8c: f240 73ff movw r3, #2047 ; 0x7ff + 8009a90: 22d2 movs r2, #210 ; 0xd2 + 8009a92: 2100 movs r1, #0 + 8009a94: f7ff fddc bl 8009650 + ILI9341_WriteString(5, 100, buf, Font_16x26, ILI9341_RED, ILI9341_BLACK); + 8009a98: 4bc0 ldr r3, [pc, #768] ; (8009d9c ) + 8009a9a: f107 010c add.w r1, r7, #12 + 8009a9e: 2200 movs r2, #0 + 8009aa0: 9202 str r2, [sp, #8] + 8009aa2: f44f 4278 mov.w r2, #63488 ; 0xf800 + 8009aa6: 9201 str r2, [sp, #4] + 8009aa8: 685a ldr r2, [r3, #4] + 8009aaa: 9200 str r2, [sp, #0] + 8009aac: 681b ldr r3, [r3, #0] + 8009aae: 460a mov r2, r1 + 8009ab0: 2164 movs r1, #100 ; 0x64 + 8009ab2: 2005 movs r0, #5 + 8009ab4: f7fc f981 bl 8005dba + ILI9341_WriteString(5, 145, buf, Font_16x26, ILI9341_RED, ILI9341_BLACK); + 8009ab8: 4bb8 ldr r3, [pc, #736] ; (8009d9c ) + 8009aba: f107 010c add.w r1, r7, #12 + 8009abe: 2200 movs r2, #0 + 8009ac0: 9202 str r2, [sp, #8] + 8009ac2: f44f 4278 mov.w r2, #63488 ; 0xf800 + 8009ac6: 9201 str r2, [sp, #4] + 8009ac8: 685a ldr r2, [r3, #4] + 8009aca: 9200 str r2, [sp, #0] + 8009acc: 681b ldr r3, [r3, #0] + 8009ace: 460a mov r2, r1 + 8009ad0: 2191 movs r1, #145 ; 0x91 + 8009ad2: 2005 movs r0, #5 + 8009ad4: f7fc f971 bl 8005dba + ILI9341_WriteString(229, 0, time_str, Font_11x18, ILI9341_GREEN, ILI9341_BLACK); + 8009ad8: 4bb1 ldr r3, [pc, #708] ; (8009da0 ) + 8009ada: 2200 movs r2, #0 + 8009adc: 9202 str r2, [sp, #8] + 8009ade: f44f 62fc mov.w r2, #2016 ; 0x7e0 + 8009ae2: 9201 str r2, [sp, #4] + 8009ae4: 685a ldr r2, [r3, #4] + 8009ae6: 9200 str r2, [sp, #0] + 8009ae8: 681b ldr r3, [r3, #0] + 8009aea: 4aae ldr r2, [pc, #696] ; (8009da4 ) + 8009aec: 2100 movs r1, #0 + 8009aee: 20e5 movs r0, #229 ; 0xe5 + 8009af0: f7fc f963 bl 8005dba + ILI9341_DrawArrow(x_center, y_center, x_center+radius*cos((encoder/180.0*M_PI)-(90/180.0*M_PI)), y_center+radius*sin((encoder/180.0*M_PI)-(90/180.0 * M_PI)), 0.23, ILI9341_RED); + 8009af4: 4bac ldr r3, [pc, #688] ; (8009da8 ) + 8009af6: 681b ldr r3, [r3, #0] + 8009af8: b21c sxth r4, r3 + 8009afa: 4bac ldr r3, [pc, #688] ; (8009dac ) + 8009afc: 681b ldr r3, [r3, #0] + 8009afe: b21d sxth r5, r3 + 8009b00: 4ba9 ldr r3, [pc, #676] ; (8009da8 ) + 8009b02: 681b ldr r3, [r3, #0] + 8009b04: 4618 mov r0, r3 + 8009b06: f7f6 fc75 bl 80003f4 <__aeabi_i2d> + 8009b0a: 4680 mov r8, r0 + 8009b0c: 4689 mov r9, r1 + 8009b0e: 4ba8 ldr r3, [pc, #672] ; (8009db0 ) + 8009b10: 681b ldr r3, [r3, #0] + 8009b12: 4618 mov r0, r3 + 8009b14: f7f6 fc6e bl 80003f4 <__aeabi_i2d> + 8009b18: 4682 mov sl, r0 + 8009b1a: 468b mov fp, r1 + 8009b1c: 4b9d ldr r3, [pc, #628] ; (8009d94 ) + 8009b1e: 681b ldr r3, [r3, #0] + 8009b20: 4618 mov r0, r3 + 8009b22: f7f6 fc67 bl 80003f4 <__aeabi_i2d> + 8009b26: f04f 0200 mov.w r2, #0 + 8009b2a: 4ba2 ldr r3, [pc, #648] ; (8009db4 ) + 8009b2c: f7f6 fdf6 bl 800071c <__aeabi_ddiv> + 8009b30: 4602 mov r2, r0 + 8009b32: 460b mov r3, r1 + 8009b34: 4610 mov r0, r2 + 8009b36: 4619 mov r1, r3 + 8009b38: a38f add r3, pc, #572 ; (adr r3, 8009d78 ) + 8009b3a: e9d3 2300 ldrd r2, r3, [r3] + 8009b3e: f7f6 fcc3 bl 80004c8 <__aeabi_dmul> + 8009b42: 4602 mov r2, r0 + 8009b44: 460b mov r3, r1 + 8009b46: 4610 mov r0, r2 + 8009b48: 4619 mov r1, r3 + 8009b4a: a38d add r3, pc, #564 ; (adr r3, 8009d80 ) + 8009b4c: e9d3 2300 ldrd r2, r3, [r3] + 8009b50: f7f6 fb02 bl 8000158 <__aeabi_dsub> + 8009b54: 4602 mov r2, r0 + 8009b56: 460b mov r3, r1 + 8009b58: 4610 mov r0, r2 + 8009b5a: 4619 mov r1, r3 + 8009b5c: f001 fcfc bl 800b558 + 8009b60: 4602 mov r2, r0 + 8009b62: 460b mov r3, r1 + 8009b64: 4650 mov r0, sl + 8009b66: 4659 mov r1, fp + 8009b68: f7f6 fcae bl 80004c8 <__aeabi_dmul> + 8009b6c: 4602 mov r2, r0 + 8009b6e: 460b mov r3, r1 + 8009b70: 4640 mov r0, r8 + 8009b72: 4649 mov r1, r9 + 8009b74: f7f6 faf2 bl 800015c <__adddf3> + 8009b78: 4602 mov r2, r0 + 8009b7a: 460b mov r3, r1 + 8009b7c: 4610 mov r0, r2 + 8009b7e: 4619 mov r1, r3 + 8009b80: f7f6 ff3c bl 80009fc <__aeabi_d2iz> + 8009b84: 4603 mov r3, r0 + 8009b86: b21e sxth r6, r3 + 8009b88: 4b88 ldr r3, [pc, #544] ; (8009dac ) + 8009b8a: 681b ldr r3, [r3, #0] + 8009b8c: 4618 mov r0, r3 + 8009b8e: f7f6 fc31 bl 80003f4 <__aeabi_i2d> + 8009b92: 4680 mov r8, r0 + 8009b94: 4689 mov r9, r1 + 8009b96: 4b86 ldr r3, [pc, #536] ; (8009db0 ) + 8009b98: 681b ldr r3, [r3, #0] + 8009b9a: 4618 mov r0, r3 + 8009b9c: f7f6 fc2a bl 80003f4 <__aeabi_i2d> + 8009ba0: 4682 mov sl, r0 + 8009ba2: 468b mov fp, r1 + 8009ba4: 4b7b ldr r3, [pc, #492] ; (8009d94 ) + 8009ba6: 681b ldr r3, [r3, #0] + 8009ba8: 4618 mov r0, r3 + 8009baa: f7f6 fc23 bl 80003f4 <__aeabi_i2d> + 8009bae: f04f 0200 mov.w r2, #0 + 8009bb2: 4b80 ldr r3, [pc, #512] ; (8009db4 ) + 8009bb4: f7f6 fdb2 bl 800071c <__aeabi_ddiv> + 8009bb8: 4602 mov r2, r0 + 8009bba: 460b mov r3, r1 + 8009bbc: 4610 mov r0, r2 + 8009bbe: 4619 mov r1, r3 + 8009bc0: a36d add r3, pc, #436 ; (adr r3, 8009d78 ) + 8009bc2: e9d3 2300 ldrd r2, r3, [r3] + 8009bc6: f7f6 fc7f bl 80004c8 <__aeabi_dmul> + 8009bca: 4602 mov r2, r0 + 8009bcc: 460b mov r3, r1 + 8009bce: 4610 mov r0, r2 + 8009bd0: 4619 mov r1, r3 + 8009bd2: a36b add r3, pc, #428 ; (adr r3, 8009d80 ) + 8009bd4: e9d3 2300 ldrd r2, r3, [r3] + 8009bd8: f7f6 fabe bl 8000158 <__aeabi_dsub> + 8009bdc: 4602 mov r2, r0 + 8009bde: 460b mov r3, r1 + 8009be0: 4610 mov r0, r2 + 8009be2: 4619 mov r1, r3 + 8009be4: f001 fd34 bl 800b650 + 8009be8: 4602 mov r2, r0 + 8009bea: 460b mov r3, r1 + 8009bec: 4650 mov r0, sl + 8009bee: 4659 mov r1, fp + 8009bf0: f7f6 fc6a bl 80004c8 <__aeabi_dmul> + 8009bf4: 4602 mov r2, r0 + 8009bf6: 460b mov r3, r1 + 8009bf8: 4640 mov r0, r8 + 8009bfa: 4649 mov r1, r9 + 8009bfc: f7f6 faae bl 800015c <__adddf3> + 8009c00: 4602 mov r2, r0 + 8009c02: 460b mov r3, r1 + 8009c04: 4610 mov r0, r2 + 8009c06: 4619 mov r1, r3 + 8009c08: f7f6 fef8 bl 80009fc <__aeabi_d2iz> + 8009c0c: 4603 mov r3, r0 + 8009c0e: b21a sxth r2, r3 + 8009c10: f44f 4378 mov.w r3, #63488 ; 0xf800 + 8009c14: 9301 str r3, [sp, #4] + 8009c16: 4b68 ldr r3, [pc, #416] ; (8009db8 ) + 8009c18: 9300 str r3, [sp, #0] + 8009c1a: 4613 mov r3, r2 + 8009c1c: 4632 mov r2, r6 + 8009c1e: 4629 mov r1, r5 + 8009c20: 4620 mov r0, r4 + 8009c22: f7fc fa26 bl 8006072 + ILI9341_drawCircle(x_center, y_center, radius, ILI9341_RED); + 8009c26: 4b60 ldr r3, [pc, #384] ; (8009da8 ) + 8009c28: 681b ldr r3, [r3, #0] + 8009c2a: b218 sxth r0, r3 + 8009c2c: 4b5f ldr r3, [pc, #380] ; (8009dac ) + 8009c2e: 681b ldr r3, [r3, #0] + 8009c30: b219 sxth r1, r3 + 8009c32: 4b5f ldr r3, [pc, #380] ; (8009db0 ) + 8009c34: 681b ldr r3, [r3, #0] + 8009c36: b21a sxth r2, r3 + 8009c38: f44f 4378 mov.w r3, #63488 ; 0xf800 + 8009c3c: f7fc fbc3 bl 80063c6 + drawLineCircle(x_center,y_center,radius,ILI9341_YELLOW); + 8009c40: 4b59 ldr r3, [pc, #356] ; (8009da8 ) + 8009c42: 6818 ldr r0, [r3, #0] + 8009c44: 4b59 ldr r3, [pc, #356] ; (8009dac ) + 8009c46: 6819 ldr r1, [r3, #0] + 8009c48: 4b59 ldr r3, [pc, #356] ; (8009db0 ) + 8009c4a: 681a ldr r2, [r3, #0] + 8009c4c: f64f 73e0 movw r3, #65504 ; 0xffe0 + 8009c50: f7ff fb46 bl 80092e0 + if (encoder_prev != 10000) { + 8009c54: 4b59 ldr r3, [pc, #356] ; (8009dbc ) + 8009c56: 681b ldr r3, [r3, #0] + 8009c58: f242 7210 movw r2, #10000 ; 0x2710 + 8009c5c: 4293 cmp r3, r2 + 8009c5e: f000 8157 beq.w 8009f10 + ILI9341_DrawArrow(x_center, y_center, x_center+radius*cos((encoder_prev/180.0*M_PI)-(90/180.0*M_PI)), y_center+radius*sin((encoder_prev/180.0*M_PI)-(90/180.0 * M_PI)), 0.23, ILI9341_BLACK); + 8009c62: 4b51 ldr r3, [pc, #324] ; (8009da8 ) + 8009c64: 681b ldr r3, [r3, #0] + 8009c66: b21c sxth r4, r3 + 8009c68: 4b50 ldr r3, [pc, #320] ; (8009dac ) + 8009c6a: 681b ldr r3, [r3, #0] + 8009c6c: b21d sxth r5, r3 + 8009c6e: 4b4e ldr r3, [pc, #312] ; (8009da8 ) + 8009c70: 681b ldr r3, [r3, #0] + 8009c72: 4618 mov r0, r3 + 8009c74: f7f6 fbbe bl 80003f4 <__aeabi_i2d> + 8009c78: 4680 mov r8, r0 + 8009c7a: 4689 mov r9, r1 + 8009c7c: 4b4c ldr r3, [pc, #304] ; (8009db0 ) + 8009c7e: 681b ldr r3, [r3, #0] + 8009c80: 4618 mov r0, r3 + 8009c82: f7f6 fbb7 bl 80003f4 <__aeabi_i2d> + 8009c86: 4682 mov sl, r0 + 8009c88: 468b mov fp, r1 + 8009c8a: 4b4c ldr r3, [pc, #304] ; (8009dbc ) + 8009c8c: 681b ldr r3, [r3, #0] + 8009c8e: 4618 mov r0, r3 + 8009c90: f7f6 fbb0 bl 80003f4 <__aeabi_i2d> + 8009c94: f04f 0200 mov.w r2, #0 + 8009c98: 4b46 ldr r3, [pc, #280] ; (8009db4 ) + 8009c9a: f7f6 fd3f bl 800071c <__aeabi_ddiv> + 8009c9e: 4602 mov r2, r0 + 8009ca0: 460b mov r3, r1 + 8009ca2: 4610 mov r0, r2 + 8009ca4: 4619 mov r1, r3 + 8009ca6: a334 add r3, pc, #208 ; (adr r3, 8009d78 ) + 8009ca8: e9d3 2300 ldrd r2, r3, [r3] + 8009cac: f7f6 fc0c bl 80004c8 <__aeabi_dmul> + 8009cb0: 4602 mov r2, r0 + 8009cb2: 460b mov r3, r1 + 8009cb4: 4610 mov r0, r2 + 8009cb6: 4619 mov r1, r3 + 8009cb8: a331 add r3, pc, #196 ; (adr r3, 8009d80 ) + 8009cba: e9d3 2300 ldrd r2, r3, [r3] + 8009cbe: f7f6 fa4b bl 8000158 <__aeabi_dsub> + 8009cc2: 4602 mov r2, r0 + 8009cc4: 460b mov r3, r1 + 8009cc6: 4610 mov r0, r2 + 8009cc8: 4619 mov r1, r3 + 8009cca: f001 fc45 bl 800b558 + 8009cce: 4602 mov r2, r0 + 8009cd0: 460b mov r3, r1 + 8009cd2: 4650 mov r0, sl + 8009cd4: 4659 mov r1, fp + 8009cd6: f7f6 fbf7 bl 80004c8 <__aeabi_dmul> + 8009cda: 4602 mov r2, r0 + 8009cdc: 460b mov r3, r1 + 8009cde: 4640 mov r0, r8 + 8009ce0: 4649 mov r1, r9 + 8009ce2: f7f6 fa3b bl 800015c <__adddf3> + 8009ce6: 4602 mov r2, r0 + 8009ce8: 460b mov r3, r1 + 8009cea: 4610 mov r0, r2 + 8009cec: 4619 mov r1, r3 + 8009cee: f7f6 fe85 bl 80009fc <__aeabi_d2iz> + 8009cf2: 4603 mov r3, r0 + 8009cf4: b21e sxth r6, r3 + 8009cf6: 4b2d ldr r3, [pc, #180] ; (8009dac ) + 8009cf8: 681b ldr r3, [r3, #0] + 8009cfa: 4618 mov r0, r3 + 8009cfc: f7f6 fb7a bl 80003f4 <__aeabi_i2d> + 8009d00: 4680 mov r8, r0 + 8009d02: 4689 mov r9, r1 + 8009d04: 4b2a ldr r3, [pc, #168] ; (8009db0 ) + 8009d06: 681b ldr r3, [r3, #0] + 8009d08: 4618 mov r0, r3 + 8009d0a: f7f6 fb73 bl 80003f4 <__aeabi_i2d> + 8009d0e: 4682 mov sl, r0 + 8009d10: 468b mov fp, r1 + 8009d12: 4b2a ldr r3, [pc, #168] ; (8009dbc ) + 8009d14: 681b ldr r3, [r3, #0] + 8009d16: 4618 mov r0, r3 + 8009d18: f7f6 fb6c bl 80003f4 <__aeabi_i2d> + 8009d1c: f04f 0200 mov.w r2, #0 + 8009d20: 4b24 ldr r3, [pc, #144] ; (8009db4 ) + 8009d22: f7f6 fcfb bl 800071c <__aeabi_ddiv> + 8009d26: 4602 mov r2, r0 + 8009d28: 460b mov r3, r1 + 8009d2a: 4610 mov r0, r2 + 8009d2c: 4619 mov r1, r3 + 8009d2e: a312 add r3, pc, #72 ; (adr r3, 8009d78 ) + 8009d30: e9d3 2300 ldrd r2, r3, [r3] + 8009d34: f7f6 fbc8 bl 80004c8 <__aeabi_dmul> + 8009d38: 4602 mov r2, r0 + 8009d3a: 460b mov r3, r1 + 8009d3c: 4610 mov r0, r2 + 8009d3e: 4619 mov r1, r3 + 8009d40: a30f add r3, pc, #60 ; (adr r3, 8009d80 ) + 8009d42: e9d3 2300 ldrd r2, r3, [r3] + 8009d46: f7f6 fa07 bl 8000158 <__aeabi_dsub> + 8009d4a: 4602 mov r2, r0 + 8009d4c: 460b mov r3, r1 + 8009d4e: 4610 mov r0, r2 + 8009d50: 4619 mov r1, r3 + 8009d52: f001 fc7d bl 800b650 + 8009d56: 4602 mov r2, r0 + 8009d58: 460b mov r3, r1 + 8009d5a: 4650 mov r0, sl + 8009d5c: 4659 mov r1, fp + 8009d5e: f7f6 fbb3 bl 80004c8 <__aeabi_dmul> + 8009d62: 4602 mov r2, r0 + 8009d64: 460b mov r3, r1 + 8009d66: 4640 mov r0, r8 + 8009d68: 4649 mov r1, r9 + 8009d6a: f7f6 f9f7 bl 800015c <__adddf3> + 8009d6e: 4602 mov r2, r0 + 8009d70: 460b mov r3, r1 + 8009d72: 4610 mov r0, r2 + 8009d74: e024 b.n 8009dc0 + 8009d76: bf00 nop + 8009d78: 54442d18 .word 0x54442d18 + 8009d7c: 400921fb .word 0x400921fb + 8009d80: 54442d18 .word 0x54442d18 + 8009d84: 3ff921fb .word 0x3ff921fb + 8009d88: 200011fc .word 0x200011fc + 8009d8c: 200012c0 .word 0x200012c0 + 8009d90: 40010800 .word 0x40010800 + 8009d94: 20000fb8 .word 0x20000fb8 + 8009d98: 0800c7a4 .word 0x0800c7a4 + 8009d9c: 20000018 .word 0x20000018 + 8009da0: 20000010 .word 0x20000010 + 8009da4: 20000f78 .word 0x20000f78 + 8009da8: 20000138 .word 0x20000138 + 8009dac: 2000013c .word 0x2000013c + 8009db0: 20000134 .word 0x20000134 + 8009db4: 40668000 .word 0x40668000 + 8009db8: 3e6b851f .word 0x3e6b851f + 8009dbc: 20000fbc .word 0x20000fbc + 8009dc0: 4619 mov r1, r3 + 8009dc2: f7f6 fe1b bl 80009fc <__aeabi_d2iz> + 8009dc6: 4603 mov r3, r0 + 8009dc8: b21a sxth r2, r3 + 8009dca: 2300 movs r3, #0 + 8009dcc: 9301 str r3, [sp, #4] + 8009dce: 4b56 ldr r3, [pc, #344] ; (8009f28 ) + 8009dd0: 9300 str r3, [sp, #0] + 8009dd2: 4613 mov r3, r2 + 8009dd4: 4632 mov r2, r6 + 8009dd6: 4629 mov r1, r5 + 8009dd8: 4620 mov r0, r4 + 8009dda: f7fc f94a bl 8006072 + ILI9341_DrawArrow(x_center, y_center, x_center+radius*cos((encoder/180.0*M_PI)-(90/180.0*M_PI)), y_center+radius*sin((encoder/180.0*M_PI)-(90/180.0 * M_PI)), 0.23, ILI9341_RED); + 8009dde: 4b53 ldr r3, [pc, #332] ; (8009f2c ) + 8009de0: 681b ldr r3, [r3, #0] + 8009de2: b21c sxth r4, r3 + 8009de4: 4b52 ldr r3, [pc, #328] ; (8009f30 ) + 8009de6: 681b ldr r3, [r3, #0] + 8009de8: b21d sxth r5, r3 + 8009dea: 4b50 ldr r3, [pc, #320] ; (8009f2c ) + 8009dec: 681b ldr r3, [r3, #0] + 8009dee: 4618 mov r0, r3 + 8009df0: f7f6 fb00 bl 80003f4 <__aeabi_i2d> + 8009df4: 4680 mov r8, r0 + 8009df6: 4689 mov r9, r1 + 8009df8: 4b4e ldr r3, [pc, #312] ; (8009f34 ) + 8009dfa: 681b ldr r3, [r3, #0] + 8009dfc: 4618 mov r0, r3 + 8009dfe: f7f6 faf9 bl 80003f4 <__aeabi_i2d> + 8009e02: 4682 mov sl, r0 + 8009e04: 468b mov fp, r1 + 8009e06: 4b4c ldr r3, [pc, #304] ; (8009f38 ) + 8009e08: 681b ldr r3, [r3, #0] + 8009e0a: 4618 mov r0, r3 + 8009e0c: f7f6 faf2 bl 80003f4 <__aeabi_i2d> + 8009e10: f04f 0200 mov.w r2, #0 + 8009e14: 4b49 ldr r3, [pc, #292] ; (8009f3c ) + 8009e16: f7f6 fc81 bl 800071c <__aeabi_ddiv> + 8009e1a: 4602 mov r2, r0 + 8009e1c: 460b mov r3, r1 + 8009e1e: 4610 mov r0, r2 + 8009e20: 4619 mov r1, r3 + 8009e22: a33d add r3, pc, #244 ; (adr r3, 8009f18 ) + 8009e24: e9d3 2300 ldrd r2, r3, [r3] + 8009e28: f7f6 fb4e bl 80004c8 <__aeabi_dmul> + 8009e2c: 4602 mov r2, r0 + 8009e2e: 460b mov r3, r1 + 8009e30: 4610 mov r0, r2 + 8009e32: 4619 mov r1, r3 + 8009e34: a33a add r3, pc, #232 ; (adr r3, 8009f20 ) + 8009e36: e9d3 2300 ldrd r2, r3, [r3] + 8009e3a: f7f6 f98d bl 8000158 <__aeabi_dsub> + 8009e3e: 4602 mov r2, r0 + 8009e40: 460b mov r3, r1 + 8009e42: 4610 mov r0, r2 + 8009e44: 4619 mov r1, r3 + 8009e46: f001 fb87 bl 800b558 + 8009e4a: 4602 mov r2, r0 + 8009e4c: 460b mov r3, r1 + 8009e4e: 4650 mov r0, sl + 8009e50: 4659 mov r1, fp + 8009e52: f7f6 fb39 bl 80004c8 <__aeabi_dmul> + 8009e56: 4602 mov r2, r0 + 8009e58: 460b mov r3, r1 + 8009e5a: 4640 mov r0, r8 + 8009e5c: 4649 mov r1, r9 + 8009e5e: f7f6 f97d bl 800015c <__adddf3> + 8009e62: 4602 mov r2, r0 + 8009e64: 460b mov r3, r1 + 8009e66: 4610 mov r0, r2 + 8009e68: 4619 mov r1, r3 + 8009e6a: f7f6 fdc7 bl 80009fc <__aeabi_d2iz> + 8009e6e: 4603 mov r3, r0 + 8009e70: b21e sxth r6, r3 + 8009e72: 4b2f ldr r3, [pc, #188] ; (8009f30 ) + 8009e74: 681b ldr r3, [r3, #0] + 8009e76: 4618 mov r0, r3 + 8009e78: f7f6 fabc bl 80003f4 <__aeabi_i2d> + 8009e7c: 4680 mov r8, r0 + 8009e7e: 4689 mov r9, r1 + 8009e80: 4b2c ldr r3, [pc, #176] ; (8009f34 ) + 8009e82: 681b ldr r3, [r3, #0] + 8009e84: 4618 mov r0, r3 + 8009e86: f7f6 fab5 bl 80003f4 <__aeabi_i2d> + 8009e8a: 4682 mov sl, r0 + 8009e8c: 468b mov fp, r1 + 8009e8e: 4b2a ldr r3, [pc, #168] ; (8009f38 ) + 8009e90: 681b ldr r3, [r3, #0] + 8009e92: 4618 mov r0, r3 + 8009e94: f7f6 faae bl 80003f4 <__aeabi_i2d> + 8009e98: f04f 0200 mov.w r2, #0 + 8009e9c: 4b27 ldr r3, [pc, #156] ; (8009f3c ) + 8009e9e: f7f6 fc3d bl 800071c <__aeabi_ddiv> + 8009ea2: 4602 mov r2, r0 + 8009ea4: 460b mov r3, r1 + 8009ea6: 4610 mov r0, r2 + 8009ea8: 4619 mov r1, r3 + 8009eaa: a31b add r3, pc, #108 ; (adr r3, 8009f18 ) + 8009eac: e9d3 2300 ldrd r2, r3, [r3] + 8009eb0: f7f6 fb0a bl 80004c8 <__aeabi_dmul> + 8009eb4: 4602 mov r2, r0 + 8009eb6: 460b mov r3, r1 + 8009eb8: 4610 mov r0, r2 + 8009eba: 4619 mov r1, r3 + 8009ebc: a318 add r3, pc, #96 ; (adr r3, 8009f20 ) + 8009ebe: e9d3 2300 ldrd r2, r3, [r3] + 8009ec2: f7f6 f949 bl 8000158 <__aeabi_dsub> + 8009ec6: 4602 mov r2, r0 + 8009ec8: 460b mov r3, r1 + 8009eca: 4610 mov r0, r2 + 8009ecc: 4619 mov r1, r3 + 8009ece: f001 fbbf bl 800b650 + 8009ed2: 4602 mov r2, r0 + 8009ed4: 460b mov r3, r1 + 8009ed6: 4650 mov r0, sl + 8009ed8: 4659 mov r1, fp + 8009eda: f7f6 faf5 bl 80004c8 <__aeabi_dmul> + 8009ede: 4602 mov r2, r0 + 8009ee0: 460b mov r3, r1 + 8009ee2: 4640 mov r0, r8 + 8009ee4: 4649 mov r1, r9 + 8009ee6: f7f6 f939 bl 800015c <__adddf3> + 8009eea: 4602 mov r2, r0 + 8009eec: 460b mov r3, r1 + 8009eee: 4610 mov r0, r2 + 8009ef0: 4619 mov r1, r3 + 8009ef2: f7f6 fd83 bl 80009fc <__aeabi_d2iz> + 8009ef6: 4603 mov r3, r0 + 8009ef8: b21a sxth r2, r3 + 8009efa: f44f 4378 mov.w r3, #63488 ; 0xf800 + 8009efe: 9301 str r3, [sp, #4] + 8009f00: 4b09 ldr r3, [pc, #36] ; (8009f28 ) + 8009f02: 9300 str r3, [sp, #0] + 8009f04: 4613 mov r3, r2 + 8009f06: 4632 mov r2, r6 + 8009f08: 4629 mov r1, r5 + 8009f0a: 4620 mov r0, r4 + 8009f0c: f7fc f8b1 bl 8006072 + } + osDelay(1); + 8009f10: 2001 movs r0, #1 + 8009f12: f7fd fed6 bl 8007cc2 + GetTime(); + 8009f16: e5a7 b.n 8009a68 + 8009f18: 54442d18 .word 0x54442d18 + 8009f1c: 400921fb .word 0x400921fb + 8009f20: 54442d18 .word 0x54442d18 + 8009f24: 3ff921fb .word 0x3ff921fb + 8009f28: 3e6b851f .word 0x3e6b851f + 8009f2c: 20000138 .word 0x20000138 + 8009f30: 2000013c .word 0x2000013c + 8009f34: 20000134 .word 0x20000134 + 8009f38: 20000fb8 .word 0x20000fb8 + 8009f3c: 40668000 .word 0x40668000 + +08009f40 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8009f40: b480 push {r7} + 8009f42: af00 add r7, sp, #0 + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + 8009f44: bf00 nop + 8009f46: 46bd mov sp, r7 + 8009f48: bc80 pop {r7} + 8009f4a: 4770 bx lr + +08009f4c : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8009f4c: b580 push {r7, lr} + 8009f4e: b084 sub sp, #16 + 8009f50: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_AFIO_CLK_ENABLE(); + 8009f52: 4b18 ldr r3, [pc, #96] ; (8009fb4 ) + 8009f54: 699b ldr r3, [r3, #24] + 8009f56: 4a17 ldr r2, [pc, #92] ; (8009fb4 ) + 8009f58: f043 0301 orr.w r3, r3, #1 + 8009f5c: 6193 str r3, [r2, #24] + 8009f5e: 4b15 ldr r3, [pc, #84] ; (8009fb4 ) + 8009f60: 699b ldr r3, [r3, #24] + 8009f62: f003 0301 and.w r3, r3, #1 + 8009f66: 60bb str r3, [r7, #8] + 8009f68: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 8009f6a: 4b12 ldr r3, [pc, #72] ; (8009fb4 ) + 8009f6c: 69db ldr r3, [r3, #28] + 8009f6e: 4a11 ldr r2, [pc, #68] ; (8009fb4 ) + 8009f70: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8009f74: 61d3 str r3, [r2, #28] + 8009f76: 4b0f ldr r3, [pc, #60] ; (8009fb4 ) + 8009f78: 69db ldr r3, [r3, #28] + 8009f7a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8009f7e: 607b str r3, [r7, #4] + 8009f80: 687b ldr r3, [r7, #4] + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + 8009f82: 2200 movs r2, #0 + 8009f84: 210f movs r1, #15 + 8009f86: f06f 0001 mvn.w r0, #1 + 8009f8a: f7f7 f98e bl 80012aa + + /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled + */ + __HAL_AFIO_REMAP_SWJ_NOJTAG(); + 8009f8e: 4b0a ldr r3, [pc, #40] ; (8009fb8 ) + 8009f90: 685b ldr r3, [r3, #4] + 8009f92: 60fb str r3, [r7, #12] + 8009f94: 68fb ldr r3, [r7, #12] + 8009f96: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 + 8009f9a: 60fb str r3, [r7, #12] + 8009f9c: 68fb ldr r3, [r7, #12] + 8009f9e: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 + 8009fa2: 60fb str r3, [r7, #12] + 8009fa4: 4a04 ldr r2, [pc, #16] ; (8009fb8 ) + 8009fa6: 68fb ldr r3, [r7, #12] + 8009fa8: 6053 str r3, [r2, #4] + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8009faa: bf00 nop + 8009fac: 3710 adds r7, #16 + 8009fae: 46bd mov sp, r7 + 8009fb0: bd80 pop {r7, pc} + 8009fb2: bf00 nop + 8009fb4: 40021000 .word 0x40021000 + 8009fb8: 40010000 .word 0x40010000 + +08009fbc : +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + 8009fbc: b580 push {r7, lr} + 8009fbe: b088 sub sp, #32 + 8009fc0: af00 add r7, sp, #0 + 8009fc2: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8009fc4: f107 0310 add.w r3, r7, #16 + 8009fc8: 2200 movs r2, #0 + 8009fca: 601a str r2, [r3, #0] + 8009fcc: 605a str r2, [r3, #4] + 8009fce: 609a str r2, [r3, #8] + 8009fd0: 60da str r2, [r3, #12] + if(hi2c->Instance==I2C1) + 8009fd2: 687b ldr r3, [r7, #4] + 8009fd4: 681b ldr r3, [r3, #0] + 8009fd6: 4a15 ldr r2, [pc, #84] ; (800a02c ) + 8009fd8: 4293 cmp r3, r2 + 8009fda: d123 bne.n 800a024 + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8009fdc: 4b14 ldr r3, [pc, #80] ; (800a030 ) + 8009fde: 699b ldr r3, [r3, #24] + 8009fe0: 4a13 ldr r2, [pc, #76] ; (800a030 ) + 8009fe2: f043 0308 orr.w r3, r3, #8 + 8009fe6: 6193 str r3, [r2, #24] + 8009fe8: 4b11 ldr r3, [pc, #68] ; (800a030 ) + 8009fea: 699b ldr r3, [r3, #24] + 8009fec: f003 0308 and.w r3, r3, #8 + 8009ff0: 60fb str r3, [r7, #12] + 8009ff2: 68fb ldr r3, [r7, #12] + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + 8009ff4: 23c0 movs r3, #192 ; 0xc0 + 8009ff6: 613b str r3, [r7, #16] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8009ff8: 2312 movs r3, #18 + 8009ffa: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8009ffc: 2303 movs r3, #3 + 8009ffe: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800a000: f107 0310 add.w r3, r7, #16 + 800a004: 4619 mov r1, r3 + 800a006: 480b ldr r0, [pc, #44] ; (800a034 ) + 800a008: f7f7 f986 bl 8001318 + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 800a00c: 4b08 ldr r3, [pc, #32] ; (800a030 ) + 800a00e: 69db ldr r3, [r3, #28] + 800a010: 4a07 ldr r2, [pc, #28] ; (800a030 ) + 800a012: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 800a016: 61d3 str r3, [r2, #28] + 800a018: 4b05 ldr r3, [pc, #20] ; (800a030 ) + 800a01a: 69db ldr r3, [r3, #28] + 800a01c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800a020: 60bb str r3, [r7, #8] + 800a022: 68bb ldr r3, [r7, #8] + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } + +} + 800a024: bf00 nop + 800a026: 3720 adds r7, #32 + 800a028: 46bd mov sp, r7 + 800a02a: bd80 pop {r7, pc} + 800a02c: 40005400 .word 0x40005400 + 800a030: 40021000 .word 0x40021000 + 800a034: 40010c00 .word 0x40010c00 + +0800a038 : +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + 800a038: b580 push {r7, lr} + 800a03a: b084 sub sp, #16 + 800a03c: af00 add r7, sp, #0 + 800a03e: 6078 str r0, [r7, #4] + if(hrtc->Instance==RTC) + 800a040: 687b ldr r3, [r7, #4] + 800a042: 681b ldr r3, [r3, #0] + 800a044: 4a0b ldr r2, [pc, #44] ; (800a074 ) + 800a046: 4293 cmp r3, r2 + 800a048: d110 bne.n 800a06c + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + HAL_PWR_EnableBkUpAccess(); + 800a04a: f7f8 faf9 bl 8002640 + /* Enable BKP CLK enable for backup registers */ + __HAL_RCC_BKP_CLK_ENABLE(); + 800a04e: 4b0a ldr r3, [pc, #40] ; (800a078 ) + 800a050: 69db ldr r3, [r3, #28] + 800a052: 4a09 ldr r2, [pc, #36] ; (800a078 ) + 800a054: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 + 800a058: 61d3 str r3, [r2, #28] + 800a05a: 4b07 ldr r3, [pc, #28] ; (800a078 ) + 800a05c: 69db ldr r3, [r3, #28] + 800a05e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 800a062: 60fb str r3, [r7, #12] + 800a064: 68fb ldr r3, [r7, #12] + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + 800a066: 4b05 ldr r3, [pc, #20] ; (800a07c ) + 800a068: 2201 movs r2, #1 + 800a06a: 601a str r2, [r3, #0] + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + 800a06c: bf00 nop + 800a06e: 3710 adds r7, #16 + 800a070: 46bd mov sp, r7 + 800a072: bd80 pop {r7, pc} + 800a074: 40002800 .word 0x40002800 + 800a078: 40021000 .word 0x40021000 + 800a07c: 4242043c .word 0x4242043c + +0800a080 : +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 800a080: b580 push {r7, lr} + 800a082: b088 sub sp, #32 + 800a084: af00 add r7, sp, #0 + 800a086: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800a088: f107 0310 add.w r3, r7, #16 + 800a08c: 2200 movs r2, #0 + 800a08e: 601a str r2, [r3, #0] + 800a090: 605a str r2, [r3, #4] + 800a092: 609a str r2, [r3, #8] + 800a094: 60da str r2, [r3, #12] + if(hspi->Instance==SPI2) + 800a096: 687b ldr r3, [r7, #4] + 800a098: 681b ldr r3, [r3, #0] + 800a09a: 4a1c ldr r2, [pc, #112] ; (800a10c ) + 800a09c: 4293 cmp r3, r2 + 800a09e: d131 bne.n 800a104 + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + 800a0a0: 4b1b ldr r3, [pc, #108] ; (800a110 ) + 800a0a2: 69db ldr r3, [r3, #28] + 800a0a4: 4a1a ldr r2, [pc, #104] ; (800a110 ) + 800a0a6: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 800a0aa: 61d3 str r3, [r2, #28] + 800a0ac: 4b18 ldr r3, [pc, #96] ; (800a110 ) + 800a0ae: 69db ldr r3, [r3, #28] + 800a0b0: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800a0b4: 60fb str r3, [r7, #12] + 800a0b6: 68fb ldr r3, [r7, #12] + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800a0b8: 4b15 ldr r3, [pc, #84] ; (800a110 ) + 800a0ba: 699b ldr r3, [r3, #24] + 800a0bc: 4a14 ldr r2, [pc, #80] ; (800a110 ) + 800a0be: f043 0308 orr.w r3, r3, #8 + 800a0c2: 6193 str r3, [r2, #24] + 800a0c4: 4b12 ldr r3, [pc, #72] ; (800a110 ) + 800a0c6: 699b ldr r3, [r3, #24] + 800a0c8: f003 0308 and.w r3, r3, #8 + 800a0cc: 60bb str r3, [r7, #8] + 800a0ce: 68bb ldr r3, [r7, #8] + /**SPI2 GPIO Configuration + PB13 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; + 800a0d0: f44f 4320 mov.w r3, #40960 ; 0xa000 + 800a0d4: 613b str r3, [r7, #16] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800a0d6: 2302 movs r3, #2 + 800a0d8: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 800a0da: 2303 movs r3, #3 + 800a0dc: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800a0de: f107 0310 add.w r3, r7, #16 + 800a0e2: 4619 mov r1, r3 + 800a0e4: 480b ldr r0, [pc, #44] ; (800a114 ) + 800a0e6: f7f7 f917 bl 8001318 + + GPIO_InitStruct.Pin = GPIO_PIN_14; + 800a0ea: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800a0ee: 613b str r3, [r7, #16] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800a0f0: 2300 movs r3, #0 + 800a0f2: 617b str r3, [r7, #20] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800a0f4: 2300 movs r3, #0 + 800a0f6: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800a0f8: f107 0310 add.w r3, r7, #16 + 800a0fc: 4619 mov r1, r3 + 800a0fe: 4805 ldr r0, [pc, #20] ; (800a114 ) + 800a100: f7f7 f90a bl 8001318 + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + 800a104: bf00 nop + 800a106: 3720 adds r7, #32 + 800a108: 46bd mov sp, r7 + 800a10a: bd80 pop {r7, pc} + 800a10c: 40003800 .word 0x40003800 + 800a110: 40021000 .word 0x40021000 + 800a114: 40010c00 .word 0x40010c00 + +0800a118 : +* This function configures the hardware resources used in this example +* @param htim_encoder: TIM_Encoder handle pointer +* @retval None +*/ +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) +{ + 800a118: b580 push {r7, lr} + 800a11a: b088 sub sp, #32 + 800a11c: af00 add r7, sp, #0 + 800a11e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800a120: f107 0310 add.w r3, r7, #16 + 800a124: 2200 movs r2, #0 + 800a126: 601a str r2, [r3, #0] + 800a128: 605a str r2, [r3, #4] + 800a12a: 609a str r2, [r3, #8] + 800a12c: 60da str r2, [r3, #12] + if(htim_encoder->Instance==TIM2) + 800a12e: 687b ldr r3, [r7, #4] + 800a130: 681b ldr r3, [r3, #0] + 800a132: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800a136: d123 bne.n 800a180 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 800a138: 4b13 ldr r3, [pc, #76] ; (800a188 ) + 800a13a: 69db ldr r3, [r3, #28] + 800a13c: 4a12 ldr r2, [pc, #72] ; (800a188 ) + 800a13e: f043 0301 orr.w r3, r3, #1 + 800a142: 61d3 str r3, [r2, #28] + 800a144: 4b10 ldr r3, [pc, #64] ; (800a188 ) + 800a146: 69db ldr r3, [r3, #28] + 800a148: f003 0301 and.w r3, r3, #1 + 800a14c: 60fb str r3, [r7, #12] + 800a14e: 68fb ldr r3, [r7, #12] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800a150: 4b0d ldr r3, [pc, #52] ; (800a188 ) + 800a152: 699b ldr r3, [r3, #24] + 800a154: 4a0c ldr r2, [pc, #48] ; (800a188 ) + 800a156: f043 0304 orr.w r3, r3, #4 + 800a15a: 6193 str r3, [r2, #24] + 800a15c: 4b0a ldr r3, [pc, #40] ; (800a188 ) + 800a15e: 699b ldr r3, [r3, #24] + 800a160: f003 0304 and.w r3, r3, #4 + 800a164: 60bb str r3, [r7, #8] + 800a166: 68bb ldr r3, [r7, #8] + /**TIM2 GPIO Configuration + PA0-WKUP ------> TIM2_CH1 + PA1 ------> TIM2_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + 800a168: 2303 movs r3, #3 + 800a16a: 613b str r3, [r7, #16] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800a16c: 2300 movs r3, #0 + 800a16e: 617b str r3, [r7, #20] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 800a170: 2301 movs r3, #1 + 800a172: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800a174: f107 0310 add.w r3, r7, #16 + 800a178: 4619 mov r1, r3 + 800a17a: 4804 ldr r0, [pc, #16] ; (800a18c ) + 800a17c: f7f7 f8cc bl 8001318 + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + +} + 800a180: bf00 nop + 800a182: 3720 adds r7, #32 + 800a184: 46bd mov sp, r7 + 800a186: bd80 pop {r7, pc} + 800a188: 40021000 .word 0x40021000 + 800a18c: 40010800 .word 0x40010800 + +0800a190 : +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + 800a190: b580 push {r7, lr} + 800a192: b088 sub sp, #32 + 800a194: af00 add r7, sp, #0 + 800a196: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800a198: f107 0310 add.w r3, r7, #16 + 800a19c: 2200 movs r2, #0 + 800a19e: 601a str r2, [r3, #0] + 800a1a0: 605a str r2, [r3, #4] + 800a1a2: 609a str r2, [r3, #8] + 800a1a4: 60da str r2, [r3, #12] + if(huart->Instance==USART2) + 800a1a6: 687b ldr r3, [r7, #4] + 800a1a8: 681b ldr r3, [r3, #0] + 800a1aa: 4a1b ldr r2, [pc, #108] ; (800a218 ) + 800a1ac: 4293 cmp r3, r2 + 800a1ae: d12f bne.n 800a210 + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + 800a1b0: 4b1a ldr r3, [pc, #104] ; (800a21c ) + 800a1b2: 69db ldr r3, [r3, #28] + 800a1b4: 4a19 ldr r2, [pc, #100] ; (800a21c ) + 800a1b6: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 800a1ba: 61d3 str r3, [r2, #28] + 800a1bc: 4b17 ldr r3, [pc, #92] ; (800a21c ) + 800a1be: 69db ldr r3, [r3, #28] + 800a1c0: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800a1c4: 60fb str r3, [r7, #12] + 800a1c6: 68fb ldr r3, [r7, #12] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800a1c8: 4b14 ldr r3, [pc, #80] ; (800a21c ) + 800a1ca: 699b ldr r3, [r3, #24] + 800a1cc: 4a13 ldr r2, [pc, #76] ; (800a21c ) + 800a1ce: f043 0304 orr.w r3, r3, #4 + 800a1d2: 6193 str r3, [r2, #24] + 800a1d4: 4b11 ldr r3, [pc, #68] ; (800a21c ) + 800a1d6: 699b ldr r3, [r3, #24] + 800a1d8: f003 0304 and.w r3, r3, #4 + 800a1dc: 60bb str r3, [r7, #8] + 800a1de: 68bb ldr r3, [r7, #8] + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + 800a1e0: 2304 movs r3, #4 + 800a1e2: 613b str r3, [r7, #16] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800a1e4: 2302 movs r3, #2 + 800a1e6: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 800a1e8: 2303 movs r3, #3 + 800a1ea: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800a1ec: f107 0310 add.w r3, r7, #16 + 800a1f0: 4619 mov r1, r3 + 800a1f2: 480b ldr r0, [pc, #44] ; (800a220 ) + 800a1f4: f7f7 f890 bl 8001318 + + GPIO_InitStruct.Pin = GPIO_PIN_3; + 800a1f8: 2308 movs r3, #8 + 800a1fa: 613b str r3, [r7, #16] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 800a1fc: 2300 movs r3, #0 + 800a1fe: 617b str r3, [r7, #20] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800a200: 2300 movs r3, #0 + 800a202: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800a204: f107 0310 add.w r3, r7, #16 + 800a208: 4619 mov r1, r3 + 800a20a: 4805 ldr r0, [pc, #20] ; (800a220 ) + 800a20c: f7f7 f884 bl 8001318 + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + 800a210: bf00 nop + 800a212: 3720 adds r7, #32 + 800a214: 46bd mov sp, r7 + 800a216: bd80 pop {r7, pc} + 800a218: 40004400 .word 0x40004400 + 800a21c: 40021000 .word 0x40021000 + 800a220: 40010800 .word 0x40010800 + +0800a224 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 800a224: b480 push {r7} + 800a226: af00 add r7, sp, #0 + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + 800a228: bf00 nop + 800a22a: 46bd mov sp, r7 + 800a22c: bc80 pop {r7} + 800a22e: 4770 bx lr + +0800a230 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 800a230: b480 push {r7} + 800a232: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 800a234: e7fe b.n 800a234 + +0800a236 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 800a236: b480 push {r7} + 800a238: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 800a23a: e7fe b.n 800a23a + +0800a23c : + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 800a23c: b480 push {r7} + 800a23e: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 800a240: e7fe b.n 800a240 + +0800a242 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 800a242: b480 push {r7} + 800a244: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 800a246: e7fe b.n 800a246 + +0800a248 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 800a248: b480 push {r7} + 800a24a: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 800a24c: bf00 nop + 800a24e: 46bd mov sp, r7 + 800a250: bc80 pop {r7} + 800a252: 4770 bx lr + +0800a254 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 800a254: b580 push {r7, lr} + 800a256: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 800a258: f7f6 ff12 bl 8001080 +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + 800a25c: f7fe fa10 bl 8008680 + 800a260: 4603 mov r3, r0 + 800a262: 2b01 cmp r3, #1 + 800a264: d001 beq.n 800a26a + { +#endif /* INCLUDE_xTaskGetSchedulerState */ + xPortSysTickHandler(); + 800a266: f7fe fbef bl 8008a48 + } +#endif /* INCLUDE_xTaskGetSchedulerState */ + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 800a26a: bf00 nop + 800a26c: bd80 pop {r7, pc} + ... + +0800a270 : + +/** + * @brief This function handles USB low priority or CAN RX0 interrupts. + */ +void USB_LP_CAN1_RX0_IRQHandler(void) +{ + 800a270: b580 push {r7, lr} + 800a272: af00 add r7, sp, #0 + /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */ + + /* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_FS); + 800a274: 4802 ldr r0, [pc, #8] ; (800a280 ) + 800a276: f7f7 fc08 bl 8001a8a + /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */ + + /* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */ +} + 800a27a: bf00 nop + 800a27c: bd80 pop {r7, pc} + 800a27e: bf00 nop + 800a280: 20001dd4 .word 0x20001dd4 + +0800a284 <_sbrk>: +/** + _sbrk + Increase program data space. Malloc and related functions depend on this +**/ +caddr_t _sbrk(int incr) +{ + 800a284: b580 push {r7, lr} + 800a286: b084 sub sp, #16 + 800a288: af00 add r7, sp, #0 + 800a28a: 6078 str r0, [r7, #4] + extern char end asm("end"); + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) + 800a28c: 4b11 ldr r3, [pc, #68] ; (800a2d4 <_sbrk+0x50>) + 800a28e: 681b ldr r3, [r3, #0] + 800a290: 2b00 cmp r3, #0 + 800a292: d102 bne.n 800a29a <_sbrk+0x16> + heap_end = &end; + 800a294: 4b0f ldr r3, [pc, #60] ; (800a2d4 <_sbrk+0x50>) + 800a296: 4a10 ldr r2, [pc, #64] ; (800a2d8 <_sbrk+0x54>) + 800a298: 601a str r2, [r3, #0] + + prev_heap_end = heap_end; + 800a29a: 4b0e ldr r3, [pc, #56] ; (800a2d4 <_sbrk+0x50>) + 800a29c: 681b ldr r3, [r3, #0] + 800a29e: 60fb str r3, [r7, #12] + if (heap_end + incr > stack_ptr) + 800a2a0: 4b0c ldr r3, [pc, #48] ; (800a2d4 <_sbrk+0x50>) + 800a2a2: 681a ldr r2, [r3, #0] + 800a2a4: 687b ldr r3, [r7, #4] + 800a2a6: 4413 add r3, r2 + 800a2a8: 466a mov r2, sp + 800a2aa: 4293 cmp r3, r2 + 800a2ac: d907 bls.n 800a2be <_sbrk+0x3a> + { + errno = ENOMEM; + 800a2ae: f000 fcd9 bl 800ac64 <__errno> + 800a2b2: 4602 mov r2, r0 + 800a2b4: 230c movs r3, #12 + 800a2b6: 6013 str r3, [r2, #0] + return (caddr_t) -1; + 800a2b8: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800a2bc: e006 b.n 800a2cc <_sbrk+0x48> + } + + heap_end += incr; + 800a2be: 4b05 ldr r3, [pc, #20] ; (800a2d4 <_sbrk+0x50>) + 800a2c0: 681a ldr r2, [r3, #0] + 800a2c2: 687b ldr r3, [r7, #4] + 800a2c4: 4413 add r3, r2 + 800a2c6: 4a03 ldr r2, [pc, #12] ; (800a2d4 <_sbrk+0x50>) + 800a2c8: 6013 str r3, [r2, #0] + + return (caddr_t) prev_heap_end; + 800a2ca: 68fb ldr r3, [r7, #12] +} + 800a2cc: 4618 mov r0, r3 + 800a2ce: 3710 adds r7, #16 + 800a2d0: 46bd mov sp, r7 + 800a2d2: bd80 pop {r7, pc} + 800a2d4: 20000fc8 .word 0x20000fc8 + 800a2d8: 20002248 .word 0x20002248 + +0800a2dc : + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 800a2dc: b480 push {r7} + 800a2de: af00 add r7, sp, #0 + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= 0x00000001U; + 800a2e0: 4b15 ldr r3, [pc, #84] ; (800a338 ) + 800a2e2: 681b ldr r3, [r3, #0] + 800a2e4: 4a14 ldr r2, [pc, #80] ; (800a338 ) + 800a2e6: f043 0301 orr.w r3, r3, #1 + 800a2ea: 6013 str r3, [r2, #0] + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#if !defined(STM32F105xC) && !defined(STM32F107xC) + RCC->CFGR &= 0xF8FF0000U; + 800a2ec: 4b12 ldr r3, [pc, #72] ; (800a338 ) + 800a2ee: 685a ldr r2, [r3, #4] + 800a2f0: 4911 ldr r1, [pc, #68] ; (800a338 ) + 800a2f2: 4b12 ldr r3, [pc, #72] ; (800a33c ) + 800a2f4: 4013 ands r3, r2 + 800a2f6: 604b str r3, [r1, #4] +#else + RCC->CFGR &= 0xF0FF0000U; +#endif /* STM32F105xC */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= 0xFEF6FFFFU; + 800a2f8: 4b0f ldr r3, [pc, #60] ; (800a338 ) + 800a2fa: 681b ldr r3, [r3, #0] + 800a2fc: 4a0e ldr r2, [pc, #56] ; (800a338 ) + 800a2fe: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 + 800a302: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 800a306: 6013 str r3, [r2, #0] + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + 800a308: 4b0b ldr r3, [pc, #44] ; (800a338 ) + 800a30a: 681b ldr r3, [r3, #0] + 800a30c: 4a0a ldr r2, [pc, #40] ; (800a338 ) + 800a30e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 800a312: 6013 str r3, [r2, #0] + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= 0xFF80FFFFU; + 800a314: 4b08 ldr r3, [pc, #32] ; (800a338 ) + 800a316: 685b ldr r3, [r3, #4] + 800a318: 4a07 ldr r2, [pc, #28] ; (800a338 ) + 800a31a: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 + 800a31e: 6053 str r3, [r2, #4] + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000U; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000U; + 800a320: 4b05 ldr r3, [pc, #20] ; (800a338 ) + 800a322: f44f 021f mov.w r2, #10420224 ; 0x9f0000 + 800a326: 609a str r2, [r3, #8] +#endif + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ + 800a328: 4b05 ldr r3, [pc, #20] ; (800a340 ) + 800a32a: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 800a32e: 609a str r2, [r3, #8] +#endif +} + 800a330: bf00 nop + 800a332: 46bd mov sp, r7 + 800a334: bc80 pop {r7} + 800a336: 4770 bx lr + 800a338: 40021000 .word 0x40021000 + 800a33c: f8ff0000 .word 0xf8ff0000 + 800a340: e000ed00 .word 0xe000ed00 + +0800a344 : +/** + * Init USB device Library, add supported class and start the library + * @retval None + */ +void MX_USB_DEVICE_Init(void) +{ + 800a344: b580 push {r7, lr} + 800a346: af00 add r7, sp, #0 + /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ + + /* USER CODE END USB_DEVICE_Init_PreTreatment */ + + /* Init Device Library, add supported class and start the library. */ + if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) + 800a348: 2200 movs r2, #0 + 800a34a: 4912 ldr r1, [pc, #72] ; (800a394 ) + 800a34c: 4812 ldr r0, [pc, #72] ; (800a398 ) + 800a34e: f7fc fbe7 bl 8006b20 + 800a352: 4603 mov r3, r0 + 800a354: 2b00 cmp r3, #0 + 800a356: d001 beq.n 800a35c + { + Error_Handler(); + 800a358: f7ff fdf2 bl 8009f40 + } + if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) + 800a35c: 490f ldr r1, [pc, #60] ; (800a39c ) + 800a35e: 480e ldr r0, [pc, #56] ; (800a398 ) + 800a360: f7fc fc09 bl 8006b76 + 800a364: 4603 mov r3, r0 + 800a366: 2b00 cmp r3, #0 + 800a368: d001 beq.n 800a36e + { + Error_Handler(); + 800a36a: f7ff fde9 bl 8009f40 + } + if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) + 800a36e: 490c ldr r1, [pc, #48] ; (800a3a0 ) + 800a370: 4809 ldr r0, [pc, #36] ; (800a398 ) + 800a372: f7fc fb69 bl 8006a48 + 800a376: 4603 mov r3, r0 + 800a378: 2b00 cmp r3, #0 + 800a37a: d001 beq.n 800a380 + { + Error_Handler(); + 800a37c: f7ff fde0 bl 8009f40 + } + if (USBD_Start(&hUsbDeviceFS) != USBD_OK) + 800a380: 4805 ldr r0, [pc, #20] ; (800a398 ) + 800a382: f7fc fc11 bl 8006ba8 + 800a386: 4603 mov r3, r0 + 800a388: 2b00 cmp r3, #0 + 800a38a: d001 beq.n 800a390 + { + Error_Handler(); + 800a38c: f7ff fdd8 bl 8009f40 + } + + /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ + + /* USER CODE END USB_DEVICE_Init_PostTreatment */ +} + 800a390: bf00 nop + 800a392: bd80 pop {r7, pc} + 800a394: 20000154 .word 0x20000154 + 800a398: 20001340 .word 0x20001340 + 800a39c: 2000002c .word 0x2000002c + 800a3a0: 20000144 .word 0x20000144 + +0800a3a4 : +/** + * @brief Initializes the CDC media low layer over the FS USB IP + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Init_FS(void) +{ + 800a3a4: b580 push {r7, lr} + 800a3a6: af00 add r7, sp, #0 + /* USER CODE BEGIN 3 */ + /* Set Application Buffers */ + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); + 800a3a8: 2200 movs r2, #0 + 800a3aa: 4905 ldr r1, [pc, #20] ; (800a3c0 ) + 800a3ac: 4805 ldr r0, [pc, #20] ; (800a3c4 ) + 800a3ae: f7fc fb61 bl 8006a74 + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); + 800a3b2: 4905 ldr r1, [pc, #20] ; (800a3c8 ) + 800a3b4: 4803 ldr r0, [pc, #12] ; (800a3c4 ) + 800a3b6: f7fc fb76 bl 8006aa6 + return (USBD_OK); + 800a3ba: 2300 movs r3, #0 + /* USER CODE END 3 */ +} + 800a3bc: 4618 mov r0, r3 + 800a3be: bd80 pop {r7, pc} + 800a3c0: 200019ec .word 0x200019ec + 800a3c4: 20001340 .word 0x20001340 + 800a3c8: 20001604 .word 0x20001604 + +0800a3cc : +/** + * @brief DeInitializes the CDC media low layer + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_DeInit_FS(void) +{ + 800a3cc: b480 push {r7} + 800a3ce: af00 add r7, sp, #0 + /* USER CODE BEGIN 4 */ + return (USBD_OK); + 800a3d0: 2300 movs r3, #0 + /* USER CODE END 4 */ +} + 800a3d2: 4618 mov r0, r3 + 800a3d4: 46bd mov sp, r7 + 800a3d6: bc80 pop {r7} + 800a3d8: 4770 bx lr + ... + +0800a3dc : + * @param pbuf: Buffer containing command data (request parameters) + * @param length: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) +{ + 800a3dc: b480 push {r7} + 800a3de: b083 sub sp, #12 + 800a3e0: af00 add r7, sp, #0 + 800a3e2: 4603 mov r3, r0 + 800a3e4: 6039 str r1, [r7, #0] + 800a3e6: 71fb strb r3, [r7, #7] + 800a3e8: 4613 mov r3, r2 + 800a3ea: 80bb strh r3, [r7, #4] + /* USER CODE BEGIN 5 */ + switch(cmd) + 800a3ec: 79fb ldrb r3, [r7, #7] + 800a3ee: 2b23 cmp r3, #35 ; 0x23 + 800a3f0: d84a bhi.n 800a488 + 800a3f2: a201 add r2, pc, #4 ; (adr r2, 800a3f8 ) + 800a3f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a3f8: 0800a489 .word 0x0800a489 + 800a3fc: 0800a489 .word 0x0800a489 + 800a400: 0800a489 .word 0x0800a489 + 800a404: 0800a489 .word 0x0800a489 + 800a408: 0800a489 .word 0x0800a489 + 800a40c: 0800a489 .word 0x0800a489 + 800a410: 0800a489 .word 0x0800a489 + 800a414: 0800a489 .word 0x0800a489 + 800a418: 0800a489 .word 0x0800a489 + 800a41c: 0800a489 .word 0x0800a489 + 800a420: 0800a489 .word 0x0800a489 + 800a424: 0800a489 .word 0x0800a489 + 800a428: 0800a489 .word 0x0800a489 + 800a42c: 0800a489 .word 0x0800a489 + 800a430: 0800a489 .word 0x0800a489 + 800a434: 0800a489 .word 0x0800a489 + 800a438: 0800a489 .word 0x0800a489 + 800a43c: 0800a489 .word 0x0800a489 + 800a440: 0800a489 .word 0x0800a489 + 800a444: 0800a489 .word 0x0800a489 + 800a448: 0800a489 .word 0x0800a489 + 800a44c: 0800a489 .word 0x0800a489 + 800a450: 0800a489 .word 0x0800a489 + 800a454: 0800a489 .word 0x0800a489 + 800a458: 0800a489 .word 0x0800a489 + 800a45c: 0800a489 .word 0x0800a489 + 800a460: 0800a489 .word 0x0800a489 + 800a464: 0800a489 .word 0x0800a489 + 800a468: 0800a489 .word 0x0800a489 + 800a46c: 0800a489 .word 0x0800a489 + 800a470: 0800a489 .word 0x0800a489 + 800a474: 0800a489 .word 0x0800a489 + 800a478: 0800a489 .word 0x0800a489 + 800a47c: 0800a489 .word 0x0800a489 + 800a480: 0800a489 .word 0x0800a489 + 800a484: 0800a489 .word 0x0800a489 + case CDC_SEND_BREAK: + + break; + + default: + break; + 800a488: bf00 nop + } + + return (USBD_OK); + 800a48a: 2300 movs r3, #0 + /* USER CODE END 5 */ +} + 800a48c: 4618 mov r0, r3 + 800a48e: 370c adds r7, #12 + 800a490: 46bd mov sp, r7 + 800a492: bc80 pop {r7} + 800a494: 4770 bx lr + 800a496: bf00 nop + +0800a498 : + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) +{ + 800a498: b580 push {r7, lr} + 800a49a: b082 sub sp, #8 + 800a49c: af00 add r7, sp, #0 + 800a49e: 6078 str r0, [r7, #4] + 800a4a0: 6039 str r1, [r7, #0] + /* USER CODE BEGIN 6 */ + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); + 800a4a2: 6879 ldr r1, [r7, #4] + 800a4a4: 4805 ldr r0, [pc, #20] ; (800a4bc ) + 800a4a6: f7fc fafe bl 8006aa6 + USBD_CDC_ReceivePacket(&hUsbDeviceFS); + 800a4aa: 4804 ldr r0, [pc, #16] ; (800a4bc ) + 800a4ac: f7fc fb0e bl 8006acc + return (USBD_OK); + 800a4b0: 2300 movs r3, #0 + /* USER CODE END 6 */ +} + 800a4b2: 4618 mov r0, r3 + 800a4b4: 3708 adds r7, #8 + 800a4b6: 46bd mov sp, r7 + 800a4b8: bd80 pop {r7, pc} + 800a4ba: bf00 nop + 800a4bc: 20001340 .word 0x20001340 + +0800a4c0 : + LL Driver Callbacks (PCD -> USB Device Library) +*******************************************************************************/ +/* MSP Init */ + +void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) +{ + 800a4c0: b580 push {r7, lr} + 800a4c2: b084 sub sp, #16 + 800a4c4: af00 add r7, sp, #0 + 800a4c6: 6078 str r0, [r7, #4] + if(pcdHandle->Instance==USB) + 800a4c8: 687b ldr r3, [r7, #4] + 800a4ca: 681b ldr r3, [r3, #0] + 800a4cc: 4a0d ldr r2, [pc, #52] ; (800a504 ) + 800a4ce: 4293 cmp r3, r2 + 800a4d0: d113 bne.n 800a4fa + { + /* USER CODE BEGIN USB_MspInit 0 */ + + /* USER CODE END USB_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USB_CLK_ENABLE(); + 800a4d2: 4b0d ldr r3, [pc, #52] ; (800a508 ) + 800a4d4: 69db ldr r3, [r3, #28] + 800a4d6: 4a0c ldr r2, [pc, #48] ; (800a508 ) + 800a4d8: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 800a4dc: 61d3 str r3, [r2, #28] + 800a4de: 4b0a ldr r3, [pc, #40] ; (800a508 ) + 800a4e0: 69db ldr r3, [r3, #28] + 800a4e2: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 800a4e6: 60fb str r3, [r7, #12] + 800a4e8: 68fb ldr r3, [r7, #12] + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 5, 0); + 800a4ea: 2200 movs r2, #0 + 800a4ec: 2105 movs r1, #5 + 800a4ee: 2014 movs r0, #20 + 800a4f0: f7f6 fedb bl 80012aa + HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn); + 800a4f4: 2014 movs r0, #20 + 800a4f6: f7f6 fef4 bl 80012e2 + /* USER CODE BEGIN USB_MspInit 1 */ + + /* USER CODE END USB_MspInit 1 */ + } +} + 800a4fa: bf00 nop + 800a4fc: 3710 adds r7, #16 + 800a4fe: 46bd mov sp, r7 + 800a500: bd80 pop {r7, pc} + 800a502: bf00 nop + 800a504: 40005c00 .word 0x40005c00 + 800a508: 40021000 .word 0x40021000 + +0800a50c : +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + 800a50c: b580 push {r7, lr} + 800a50e: b082 sub sp, #8 + 800a510: af00 add r7, sp, #0 + 800a512: 6078 str r0, [r7, #4] + USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); + 800a514: 687b ldr r3, [r7, #4] + 800a516: f8d3 2268 ldr.w r2, [r3, #616] ; 0x268 + 800a51a: 687b ldr r3, [r7, #4] + 800a51c: f503 730c add.w r3, r3, #560 ; 0x230 + 800a520: 4619 mov r1, r3 + 800a522: 4610 mov r0, r2 + 800a524: f7fc fb88 bl 8006c38 +} + 800a528: bf00 nop + 800a52a: 3708 adds r7, #8 + 800a52c: 46bd mov sp, r7 + 800a52e: bd80 pop {r7, pc} + +0800a530 : +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + 800a530: b580 push {r7, lr} + 800a532: b082 sub sp, #8 + 800a534: af00 add r7, sp, #0 + 800a536: 6078 str r0, [r7, #4] + 800a538: 460b mov r3, r1 + 800a53a: 70fb strb r3, [r7, #3] + USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); + 800a53c: 687b ldr r3, [r7, #4] + 800a53e: f8d3 0268 ldr.w r0, [r3, #616] ; 0x268 + 800a542: 78fb ldrb r3, [r7, #3] + 800a544: 687a ldr r2, [r7, #4] + 800a546: 015b lsls r3, r3, #5 + 800a548: 4413 add r3, r2 + 800a54a: f503 739e add.w r3, r3, #316 ; 0x13c + 800a54e: 681a ldr r2, [r3, #0] + 800a550: 78fb ldrb r3, [r7, #3] + 800a552: 4619 mov r1, r3 + 800a554: f7fc fbbb bl 8006cce +} + 800a558: bf00 nop + 800a55a: 3708 adds r7, #8 + 800a55c: 46bd mov sp, r7 + 800a55e: bd80 pop {r7, pc} + +0800a560 : +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#else +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + 800a560: b580 push {r7, lr} + 800a562: b082 sub sp, #8 + 800a564: af00 add r7, sp, #0 + 800a566: 6078 str r0, [r7, #4] + 800a568: 460b mov r3, r1 + 800a56a: 70fb strb r3, [r7, #3] + USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); + 800a56c: 687b ldr r3, [r7, #4] + 800a56e: f8d3 0268 ldr.w r0, [r3, #616] ; 0x268 + 800a572: 78fb ldrb r3, [r7, #3] + 800a574: 687a ldr r2, [r7, #4] + 800a576: 015b lsls r3, r3, #5 + 800a578: 4413 add r3, r2 + 800a57a: 333c adds r3, #60 ; 0x3c + 800a57c: 681a ldr r2, [r3, #0] + 800a57e: 78fb ldrb r3, [r7, #3] + 800a580: 4619 mov r1, r3 + 800a582: f7fc fc15 bl 8006db0 +} + 800a586: bf00 nop + 800a588: 3708 adds r7, #8 + 800a58a: 46bd mov sp, r7 + 800a58c: bd80 pop {r7, pc} + +0800a58e : +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + 800a58e: b580 push {r7, lr} + 800a590: b082 sub sp, #8 + 800a592: af00 add r7, sp, #0 + 800a594: 6078 str r0, [r7, #4] + USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); + 800a596: 687b ldr r3, [r7, #4] + 800a598: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268 + 800a59c: 4618 mov r0, r3 + 800a59e: f7fc fd25 bl 8006fec +} + 800a5a2: bf00 nop + 800a5a4: 3708 adds r7, #8 + 800a5a6: 46bd mov sp, r7 + 800a5a8: bd80 pop {r7, pc} + +0800a5aa : +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + 800a5aa: b580 push {r7, lr} + 800a5ac: b084 sub sp, #16 + 800a5ae: af00 add r7, sp, #0 + 800a5b0: 6078 str r0, [r7, #4] + USBD_SpeedTypeDef speed = USBD_SPEED_FULL; + 800a5b2: 2301 movs r3, #1 + 800a5b4: 73fb strb r3, [r7, #15] + + if ( hpcd->Init.speed != PCD_SPEED_FULL) + 800a5b6: 687b ldr r3, [r7, #4] + 800a5b8: 689b ldr r3, [r3, #8] + 800a5ba: 2b02 cmp r3, #2 + 800a5bc: d001 beq.n 800a5c2 + { + Error_Handler(); + 800a5be: f7ff fcbf bl 8009f40 + } + /* Set Speed. */ + USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); + 800a5c2: 687b ldr r3, [r7, #4] + 800a5c4: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268 + 800a5c8: 7bfa ldrb r2, [r7, #15] + 800a5ca: 4611 mov r1, r2 + 800a5cc: 4618 mov r0, r3 + 800a5ce: f7fc fcd5 bl 8006f7c + + /* Reset Device. */ + USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); + 800a5d2: 687b ldr r3, [r7, #4] + 800a5d4: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268 + 800a5d8: 4618 mov r0, r3 + 800a5da: f7fc fc8e bl 8006efa +} + 800a5de: bf00 nop + 800a5e0: 3710 adds r7, #16 + 800a5e2: 46bd mov sp, r7 + 800a5e4: bd80 pop {r7, pc} + ... + +0800a5e8 : +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + 800a5e8: b580 push {r7, lr} + 800a5ea: b082 sub sp, #8 + 800a5ec: af00 add r7, sp, #0 + 800a5ee: 6078 str r0, [r7, #4] + /* Inform USB library that core enters in suspend Mode. */ + USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); + 800a5f0: 687b ldr r3, [r7, #4] + 800a5f2: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268 + 800a5f6: 4618 mov r0, r3 + 800a5f8: f7fc fccf bl 8006f9a + /* Enter in STOP mode. */ + /* USER CODE BEGIN 2 */ + if (hpcd->Init.low_power_enable) + 800a5fc: 687b ldr r3, [r7, #4] + 800a5fe: 699b ldr r3, [r3, #24] + 800a600: 2b00 cmp r3, #0 + 800a602: d005 beq.n 800a610 + { + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ + SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + 800a604: 4b04 ldr r3, [pc, #16] ; (800a618 ) + 800a606: 691b ldr r3, [r3, #16] + 800a608: 4a03 ldr r2, [pc, #12] ; (800a618 ) + 800a60a: f043 0306 orr.w r3, r3, #6 + 800a60e: 6113 str r3, [r2, #16] + } + /* USER CODE END 2 */ +} + 800a610: bf00 nop + 800a612: 3708 adds r7, #8 + 800a614: 46bd mov sp, r7 + 800a616: bd80 pop {r7, pc} + 800a618: e000ed00 .word 0xe000ed00 + +0800a61c : +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +#else +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + 800a61c: b580 push {r7, lr} + 800a61e: b082 sub sp, #8 + 800a620: af00 add r7, sp, #0 + 800a622: 6078 str r0, [r7, #4] + /* USER CODE BEGIN 3 */ + + /* USER CODE END 3 */ + USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); + 800a624: 687b ldr r3, [r7, #4] + 800a626: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268 + 800a62a: 4618 mov r0, r3 + 800a62c: f7fc fcc9 bl 8006fc2 +} + 800a630: bf00 nop + 800a632: 3708 adds r7, #8 + 800a634: 46bd mov sp, r7 + 800a636: bd80 pop {r7, pc} + +0800a638 : + * @brief Initializes the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) +{ + 800a638: b580 push {r7, lr} + 800a63a: b082 sub sp, #8 + 800a63c: af00 add r7, sp, #0 + 800a63e: 6078 str r0, [r7, #4] + /* Init USB Ip. */ + /* Link the driver to the stack. */ + hpcd_USB_FS.pData = pdev; + 800a640: 4a28 ldr r2, [pc, #160] ; (800a6e4 ) + 800a642: 687b ldr r3, [r7, #4] + 800a644: f8c2 3268 str.w r3, [r2, #616] ; 0x268 + pdev->pData = &hpcd_USB_FS; + 800a648: 687b ldr r3, [r7, #4] + 800a64a: 4a26 ldr r2, [pc, #152] ; (800a6e4 ) + 800a64c: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0 + + hpcd_USB_FS.Instance = USB; + 800a650: 4b24 ldr r3, [pc, #144] ; (800a6e4 ) + 800a652: 4a25 ldr r2, [pc, #148] ; (800a6e8 ) + 800a654: 601a str r2, [r3, #0] + hpcd_USB_FS.Init.dev_endpoints = 8; + 800a656: 4b23 ldr r3, [pc, #140] ; (800a6e4 ) + 800a658: 2208 movs r2, #8 + 800a65a: 605a str r2, [r3, #4] + hpcd_USB_FS.Init.speed = PCD_SPEED_FULL; + 800a65c: 4b21 ldr r3, [pc, #132] ; (800a6e4 ) + 800a65e: 2202 movs r2, #2 + 800a660: 609a str r2, [r3, #8] + hpcd_USB_FS.Init.low_power_enable = DISABLE; + 800a662: 4b20 ldr r3, [pc, #128] ; (800a6e4 ) + 800a664: 2200 movs r2, #0 + 800a666: 619a str r2, [r3, #24] + hpcd_USB_FS.Init.lpm_enable = DISABLE; + 800a668: 4b1e ldr r3, [pc, #120] ; (800a6e4 ) + 800a66a: 2200 movs r2, #0 + 800a66c: 61da str r2, [r3, #28] + hpcd_USB_FS.Init.battery_charging_enable = DISABLE; + 800a66e: 4b1d ldr r3, [pc, #116] ; (800a6e4 ) + 800a670: 2200 movs r2, #0 + 800a672: 621a str r2, [r3, #32] + if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK) + 800a674: 481b ldr r0, [pc, #108] ; (800a6e4 ) + 800a676: f7f7 f901 bl 800187c + 800a67a: 4603 mov r3, r0 + 800a67c: 2b00 cmp r3, #0 + 800a67e: d001 beq.n 800a684 + { + Error_Handler( ); + 800a680: f7ff fc5e bl 8009f40 + HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback); + HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback); + HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + /* USER CODE BEGIN EndPoint_Configuration */ + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); + 800a684: 687b ldr r3, [r7, #4] + 800a686: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0 + 800a68a: 2318 movs r3, #24 + 800a68c: 2200 movs r2, #0 + 800a68e: 2100 movs r1, #0 + 800a690: f7f7 ff9a bl 80025c8 + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); + 800a694: 687b ldr r3, [r7, #4] + 800a696: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0 + 800a69a: 2358 movs r3, #88 ; 0x58 + 800a69c: 2200 movs r2, #0 + 800a69e: 2180 movs r1, #128 ; 0x80 + 800a6a0: f7f7 ff92 bl 80025c8 + /* USER CODE END EndPoint_Configuration */ + /* USER CODE BEGIN EndPoint_Configuration_CDC */ + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); + 800a6a4: 687b ldr r3, [r7, #4] + 800a6a6: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0 + 800a6aa: 23c0 movs r3, #192 ; 0xc0 + 800a6ac: 2200 movs r2, #0 + 800a6ae: 2181 movs r1, #129 ; 0x81 + 800a6b0: f7f7 ff8a bl 80025c8 + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); + 800a6b4: 687b ldr r3, [r7, #4] + 800a6b6: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0 + 800a6ba: f44f 7388 mov.w r3, #272 ; 0x110 + 800a6be: 2200 movs r2, #0 + 800a6c0: 2101 movs r1, #1 + 800a6c2: f7f7 ff81 bl 80025c8 + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); + 800a6c6: 687b ldr r3, [r7, #4] + 800a6c8: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0 + 800a6cc: f44f 7380 mov.w r3, #256 ; 0x100 + 800a6d0: 2200 movs r2, #0 + 800a6d2: 2182 movs r1, #130 ; 0x82 + 800a6d4: f7f7 ff78 bl 80025c8 + /* USER CODE END EndPoint_Configuration_CDC */ + return USBD_OK; + 800a6d8: 2300 movs r3, #0 +} + 800a6da: 4618 mov r0, r3 + 800a6dc: 3708 adds r7, #8 + 800a6de: 46bd mov sp, r7 + 800a6e0: bd80 pop {r7, pc} + 800a6e2: bf00 nop + 800a6e4: 20001dd4 .word 0x20001dd4 + 800a6e8: 40005c00 .word 0x40005c00 + +0800a6ec : + * @brief Starts the low level portion of the device driver. + * @param pdev: Device handle + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) +{ + 800a6ec: b580 push {r7, lr} + 800a6ee: b084 sub sp, #16 + 800a6f0: af00 add r7, sp, #0 + 800a6f2: 6078 str r0, [r7, #4] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a6f4: 2300 movs r3, #0 + 800a6f6: 73fb strb r3, [r7, #15] + USBD_StatusTypeDef usb_status = USBD_OK; + 800a6f8: 2300 movs r3, #0 + 800a6fa: 73bb strb r3, [r7, #14] + + hal_status = HAL_PCD_Start(pdev->pData); + 800a6fc: 687b ldr r3, [r7, #4] + 800a6fe: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 800a702: 4618 mov r0, r3 + 800a704: f7f7 f99b bl 8001a3e + 800a708: 4603 mov r3, r0 + 800a70a: 73fb strb r3, [r7, #15] + + usb_status = USBD_Get_USB_Status(hal_status); + 800a70c: 7bfb ldrb r3, [r7, #15] + 800a70e: 4618 mov r0, r3 + 800a710: f000 f948 bl 800a9a4 + 800a714: 4603 mov r3, r0 + 800a716: 73bb strb r3, [r7, #14] + + return usb_status; + 800a718: 7bbb ldrb r3, [r7, #14] +} + 800a71a: 4618 mov r0, r3 + 800a71c: 3710 adds r7, #16 + 800a71e: 46bd mov sp, r7 + 800a720: bd80 pop {r7, pc} + +0800a722 : + * @param ep_type: Endpoint type + * @param ep_mps: Endpoint max packet size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) +{ + 800a722: b580 push {r7, lr} + 800a724: b084 sub sp, #16 + 800a726: af00 add r7, sp, #0 + 800a728: 6078 str r0, [r7, #4] + 800a72a: 4608 mov r0, r1 + 800a72c: 4611 mov r1, r2 + 800a72e: 461a mov r2, r3 + 800a730: 4603 mov r3, r0 + 800a732: 70fb strb r3, [r7, #3] + 800a734: 460b mov r3, r1 + 800a736: 70bb strb r3, [r7, #2] + 800a738: 4613 mov r3, r2 + 800a73a: 803b strh r3, [r7, #0] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a73c: 2300 movs r3, #0 + 800a73e: 73fb strb r3, [r7, #15] + USBD_StatusTypeDef usb_status = USBD_OK; + 800a740: 2300 movs r3, #0 + 800a742: 73bb strb r3, [r7, #14] + + hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); + 800a744: 687b ldr r3, [r7, #4] + 800a746: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0 + 800a74a: 78bb ldrb r3, [r7, #2] + 800a74c: 883a ldrh r2, [r7, #0] + 800a74e: 78f9 ldrb r1, [r7, #3] + 800a750: f7f7 face bl 8001cf0 + 800a754: 4603 mov r3, r0 + 800a756: 73fb strb r3, [r7, #15] + + usb_status = USBD_Get_USB_Status(hal_status); + 800a758: 7bfb ldrb r3, [r7, #15] + 800a75a: 4618 mov r0, r3 + 800a75c: f000 f922 bl 800a9a4 + 800a760: 4603 mov r3, r0 + 800a762: 73bb strb r3, [r7, #14] + + return usb_status; + 800a764: 7bbb ldrb r3, [r7, #14] +} + 800a766: 4618 mov r0, r3 + 800a768: 3710 adds r7, #16 + 800a76a: 46bd mov sp, r7 + 800a76c: bd80 pop {r7, pc} + +0800a76e : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 800a76e: b580 push {r7, lr} + 800a770: b084 sub sp, #16 + 800a772: af00 add r7, sp, #0 + 800a774: 6078 str r0, [r7, #4] + 800a776: 460b mov r3, r1 + 800a778: 70fb strb r3, [r7, #3] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a77a: 2300 movs r3, #0 + 800a77c: 73fb strb r3, [r7, #15] + USBD_StatusTypeDef usb_status = USBD_OK; + 800a77e: 2300 movs r3, #0 + 800a780: 73bb strb r3, [r7, #14] + + hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); + 800a782: 687b ldr r3, [r7, #4] + 800a784: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 800a788: 78fa ldrb r2, [r7, #3] + 800a78a: 4611 mov r1, r2 + 800a78c: 4618 mov r0, r3 + 800a78e: f7f7 fb0f bl 8001db0 + 800a792: 4603 mov r3, r0 + 800a794: 73fb strb r3, [r7, #15] + + usb_status = USBD_Get_USB_Status(hal_status); + 800a796: 7bfb ldrb r3, [r7, #15] + 800a798: 4618 mov r0, r3 + 800a79a: f000 f903 bl 800a9a4 + 800a79e: 4603 mov r3, r0 + 800a7a0: 73bb strb r3, [r7, #14] + + return usb_status; + 800a7a2: 7bbb ldrb r3, [r7, #14] +} + 800a7a4: 4618 mov r0, r3 + 800a7a6: 3710 adds r7, #16 + 800a7a8: 46bd mov sp, r7 + 800a7aa: bd80 pop {r7, pc} + +0800a7ac : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 800a7ac: b580 push {r7, lr} + 800a7ae: b084 sub sp, #16 + 800a7b0: af00 add r7, sp, #0 + 800a7b2: 6078 str r0, [r7, #4] + 800a7b4: 460b mov r3, r1 + 800a7b6: 70fb strb r3, [r7, #3] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a7b8: 2300 movs r3, #0 + 800a7ba: 73fb strb r3, [r7, #15] + USBD_StatusTypeDef usb_status = USBD_OK; + 800a7bc: 2300 movs r3, #0 + 800a7be: 73bb strb r3, [r7, #14] + + hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); + 800a7c0: 687b ldr r3, [r7, #4] + 800a7c2: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 800a7c6: 78fa ldrb r2, [r7, #3] + 800a7c8: 4611 mov r1, r2 + 800a7ca: 4618 mov r0, r3 + 800a7cc: f7f7 fbb9 bl 8001f42 + 800a7d0: 4603 mov r3, r0 + 800a7d2: 73fb strb r3, [r7, #15] + + usb_status = USBD_Get_USB_Status(hal_status); + 800a7d4: 7bfb ldrb r3, [r7, #15] + 800a7d6: 4618 mov r0, r3 + 800a7d8: f000 f8e4 bl 800a9a4 + 800a7dc: 4603 mov r3, r0 + 800a7de: 73bb strb r3, [r7, #14] + + return usb_status; + 800a7e0: 7bbb ldrb r3, [r7, #14] +} + 800a7e2: 4618 mov r0, r3 + 800a7e4: 3710 adds r7, #16 + 800a7e6: 46bd mov sp, r7 + 800a7e8: bd80 pop {r7, pc} + +0800a7ea : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 800a7ea: b580 push {r7, lr} + 800a7ec: b084 sub sp, #16 + 800a7ee: af00 add r7, sp, #0 + 800a7f0: 6078 str r0, [r7, #4] + 800a7f2: 460b mov r3, r1 + 800a7f4: 70fb strb r3, [r7, #3] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a7f6: 2300 movs r3, #0 + 800a7f8: 73fb strb r3, [r7, #15] + USBD_StatusTypeDef usb_status = USBD_OK; + 800a7fa: 2300 movs r3, #0 + 800a7fc: 73bb strb r3, [r7, #14] + + hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); + 800a7fe: 687b ldr r3, [r7, #4] + 800a800: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 800a804: 78fa ldrb r2, [r7, #3] + 800a806: 4611 mov r1, r2 + 800a808: 4618 mov r0, r3 + 800a80a: f7f7 fbf4 bl 8001ff6 + 800a80e: 4603 mov r3, r0 + 800a810: 73fb strb r3, [r7, #15] + + usb_status = USBD_Get_USB_Status(hal_status); + 800a812: 7bfb ldrb r3, [r7, #15] + 800a814: 4618 mov r0, r3 + 800a816: f000 f8c5 bl 800a9a4 + 800a81a: 4603 mov r3, r0 + 800a81c: 73bb strb r3, [r7, #14] + + return usb_status; + 800a81e: 7bbb ldrb r3, [r7, #14] +} + 800a820: 4618 mov r0, r3 + 800a822: 3710 adds r7, #16 + 800a824: 46bd mov sp, r7 + 800a826: bd80 pop {r7, pc} + +0800a828 : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Stall (1: Yes, 0: No) + */ +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 800a828: b480 push {r7} + 800a82a: b085 sub sp, #20 + 800a82c: af00 add r7, sp, #0 + 800a82e: 6078 str r0, [r7, #4] + 800a830: 460b mov r3, r1 + 800a832: 70fb strb r3, [r7, #3] + PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; + 800a834: 687b ldr r3, [r7, #4] + 800a836: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 800a83a: 60fb str r3, [r7, #12] + + if((ep_addr & 0x80) == 0x80) + 800a83c: f997 3003 ldrsb.w r3, [r7, #3] + 800a840: 2b00 cmp r3, #0 + 800a842: da08 bge.n 800a856 + { + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + 800a844: 78fb ldrb r3, [r7, #3] + 800a846: f003 037f and.w r3, r3, #127 ; 0x7f + 800a84a: 68fa ldr r2, [r7, #12] + 800a84c: 015b lsls r3, r3, #5 + 800a84e: 4413 add r3, r2 + 800a850: 332a adds r3, #42 ; 0x2a + 800a852: 781b ldrb r3, [r3, #0] + 800a854: e008 b.n 800a868 + } + else + { + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + 800a856: 78fb ldrb r3, [r7, #3] + 800a858: f003 037f and.w r3, r3, #127 ; 0x7f + 800a85c: 68fa ldr r2, [r7, #12] + 800a85e: 015b lsls r3, r3, #5 + 800a860: 4413 add r3, r2 + 800a862: f503 7395 add.w r3, r3, #298 ; 0x12a + 800a866: 781b ldrb r3, [r3, #0] + } +} + 800a868: 4618 mov r0, r3 + 800a86a: 3714 adds r7, #20 + 800a86c: 46bd mov sp, r7 + 800a86e: bc80 pop {r7} + 800a870: 4770 bx lr + +0800a872 : + * @param pdev: Device handle + * @param dev_addr: Device address + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) +{ + 800a872: b580 push {r7, lr} + 800a874: b084 sub sp, #16 + 800a876: af00 add r7, sp, #0 + 800a878: 6078 str r0, [r7, #4] + 800a87a: 460b mov r3, r1 + 800a87c: 70fb strb r3, [r7, #3] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a87e: 2300 movs r3, #0 + 800a880: 73fb strb r3, [r7, #15] + USBD_StatusTypeDef usb_status = USBD_OK; + 800a882: 2300 movs r3, #0 + 800a884: 73bb strb r3, [r7, #14] + + hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); + 800a886: 687b ldr r3, [r7, #4] + 800a888: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 800a88c: 78fa ldrb r2, [r7, #3] + 800a88e: 4611 mov r1, r2 + 800a890: 4618 mov r0, r3 + 800a892: f7f7 fa08 bl 8001ca6 + 800a896: 4603 mov r3, r0 + 800a898: 73fb strb r3, [r7, #15] + + usb_status = USBD_Get_USB_Status(hal_status); + 800a89a: 7bfb ldrb r3, [r7, #15] + 800a89c: 4618 mov r0, r3 + 800a89e: f000 f881 bl 800a9a4 + 800a8a2: 4603 mov r3, r0 + 800a8a4: 73bb strb r3, [r7, #14] + + return usb_status; + 800a8a6: 7bbb ldrb r3, [r7, #14] +} + 800a8a8: 4618 mov r0, r3 + 800a8aa: 3710 adds r7, #16 + 800a8ac: 46bd mov sp, r7 + 800a8ae: bd80 pop {r7, pc} + +0800a8b0 : + * @param pbuf: Pointer to data to be sent + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +{ + 800a8b0: b580 push {r7, lr} + 800a8b2: b086 sub sp, #24 + 800a8b4: af00 add r7, sp, #0 + 800a8b6: 60f8 str r0, [r7, #12] + 800a8b8: 607a str r2, [r7, #4] + 800a8ba: 461a mov r2, r3 + 800a8bc: 460b mov r3, r1 + 800a8be: 72fb strb r3, [r7, #11] + 800a8c0: 4613 mov r3, r2 + 800a8c2: 813b strh r3, [r7, #8] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a8c4: 2300 movs r3, #0 + 800a8c6: 75fb strb r3, [r7, #23] + USBD_StatusTypeDef usb_status = USBD_OK; + 800a8c8: 2300 movs r3, #0 + 800a8ca: 75bb strb r3, [r7, #22] + + hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); + 800a8cc: 68fb ldr r3, [r7, #12] + 800a8ce: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0 + 800a8d2: 893b ldrh r3, [r7, #8] + 800a8d4: 7af9 ldrb r1, [r7, #11] + 800a8d6: 687a ldr r2, [r7, #4] + 800a8d8: f7f7 fafa bl 8001ed0 + 800a8dc: 4603 mov r3, r0 + 800a8de: 75fb strb r3, [r7, #23] + + usb_status = USBD_Get_USB_Status(hal_status); + 800a8e0: 7dfb ldrb r3, [r7, #23] + 800a8e2: 4618 mov r0, r3 + 800a8e4: f000 f85e bl 800a9a4 + 800a8e8: 4603 mov r3, r0 + 800a8ea: 75bb strb r3, [r7, #22] + + return usb_status; + 800a8ec: 7dbb ldrb r3, [r7, #22] +} + 800a8ee: 4618 mov r0, r3 + 800a8f0: 3718 adds r7, #24 + 800a8f2: 46bd mov sp, r7 + 800a8f4: bd80 pop {r7, pc} + +0800a8f6 : + * @param pbuf: Pointer to data to be received + * @param size: Data size + * @retval USBD status + */ +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +{ + 800a8f6: b580 push {r7, lr} + 800a8f8: b086 sub sp, #24 + 800a8fa: af00 add r7, sp, #0 + 800a8fc: 60f8 str r0, [r7, #12] + 800a8fe: 607a str r2, [r7, #4] + 800a900: 461a mov r2, r3 + 800a902: 460b mov r3, r1 + 800a904: 72fb strb r3, [r7, #11] + 800a906: 4613 mov r3, r2 + 800a908: 813b strh r3, [r7, #8] + HAL_StatusTypeDef hal_status = HAL_OK; + 800a90a: 2300 movs r3, #0 + 800a90c: 75fb strb r3, [r7, #23] + USBD_StatusTypeDef usb_status = USBD_OK; + 800a90e: 2300 movs r3, #0 + 800a910: 75bb strb r3, [r7, #22] + + hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); + 800a912: 68fb ldr r3, [r7, #12] + 800a914: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0 + 800a918: 893b ldrh r3, [r7, #8] + 800a91a: 7af9 ldrb r1, [r7, #11] + 800a91c: 687a ldr r2, [r7, #4] + 800a91e: f7f7 fa89 bl 8001e34 + 800a922: 4603 mov r3, r0 + 800a924: 75fb strb r3, [r7, #23] + + usb_status = USBD_Get_USB_Status(hal_status); + 800a926: 7dfb ldrb r3, [r7, #23] + 800a928: 4618 mov r0, r3 + 800a92a: f000 f83b bl 800a9a4 + 800a92e: 4603 mov r3, r0 + 800a930: 75bb strb r3, [r7, #22] + + return usb_status; + 800a932: 7dbb ldrb r3, [r7, #22] +} + 800a934: 4618 mov r0, r3 + 800a936: 3718 adds r7, #24 + 800a938: 46bd mov sp, r7 + 800a93a: bd80 pop {r7, pc} + +0800a93c : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Recived Data Size + */ +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 800a93c: b580 push {r7, lr} + 800a93e: b082 sub sp, #8 + 800a940: af00 add r7, sp, #0 + 800a942: 6078 str r0, [r7, #4] + 800a944: 460b mov r3, r1 + 800a946: 70fb strb r3, [r7, #3] + return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); + 800a948: 687b ldr r3, [r7, #4] + 800a94a: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0 + 800a94e: 78fa ldrb r2, [r7, #3] + 800a950: 4611 mov r1, r2 + 800a952: 4618 mov r0, r3 + 800a954: f7f7 faa8 bl 8001ea8 + 800a958: 4603 mov r3, r0 +} + 800a95a: 4618 mov r0, r3 + 800a95c: 3708 adds r7, #8 + 800a95e: 46bd mov sp, r7 + 800a960: bd80 pop {r7, pc} + ... + +0800a964 : + * @brief Static single allocation. + * @param size: Size of allocated memory + * @retval None + */ +void *USBD_static_malloc(uint32_t size) +{ + 800a964: b480 push {r7} + 800a966: b083 sub sp, #12 + 800a968: af00 add r7, sp, #0 + 800a96a: 6078 str r0, [r7, #4] + static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ + return mem; + 800a96c: 4b02 ldr r3, [pc, #8] ; (800a978 ) +} + 800a96e: 4618 mov r0, r3 + 800a970: 370c adds r7, #12 + 800a972: 46bd mov sp, r7 + 800a974: bc80 pop {r7} + 800a976: 4770 bx lr + 800a978: 20000fcc .word 0x20000fcc + +0800a97c : + * @brief Dummy memory free + * @param p: Pointer to allocated memory address + * @retval None + */ +void USBD_static_free(void *p) +{ + 800a97c: b480 push {r7} + 800a97e: b083 sub sp, #12 + 800a980: af00 add r7, sp, #0 + 800a982: 6078 str r0, [r7, #4] + +} + 800a984: bf00 nop + 800a986: 370c adds r7, #12 + 800a988: 46bd mov sp, r7 + 800a98a: bc80 pop {r7} + 800a98c: 4770 bx lr + +0800a98e : +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) +#else +void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + 800a98e: b480 push {r7} + 800a990: b083 sub sp, #12 + 800a992: af00 add r7, sp, #0 + 800a994: 6078 str r0, [r7, #4] + 800a996: 460b mov r3, r1 + 800a998: 70fb strb r3, [r7, #3] + { + /* Configure High connection state. */ + + } + /* USER CODE END 6 */ +} + 800a99a: bf00 nop + 800a99c: 370c adds r7, #12 + 800a99e: 46bd mov sp, r7 + 800a9a0: bc80 pop {r7} + 800a9a2: 4770 bx lr + +0800a9a4 : + * @brief Retuns the USB status depending on the HAL status: + * @param hal_status: HAL status + * @retval USB status + */ +USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) +{ + 800a9a4: b480 push {r7} + 800a9a6: b085 sub sp, #20 + 800a9a8: af00 add r7, sp, #0 + 800a9aa: 4603 mov r3, r0 + 800a9ac: 71fb strb r3, [r7, #7] + USBD_StatusTypeDef usb_status = USBD_OK; + 800a9ae: 2300 movs r3, #0 + 800a9b0: 73fb strb r3, [r7, #15] + + switch (hal_status) + 800a9b2: 79fb ldrb r3, [r7, #7] + 800a9b4: 2b03 cmp r3, #3 + 800a9b6: d817 bhi.n 800a9e8 + 800a9b8: a201 add r2, pc, #4 ; (adr r2, 800a9c0 ) + 800a9ba: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a9be: bf00 nop + 800a9c0: 0800a9d1 .word 0x0800a9d1 + 800a9c4: 0800a9d7 .word 0x0800a9d7 + 800a9c8: 0800a9dd .word 0x0800a9dd + 800a9cc: 0800a9e3 .word 0x0800a9e3 + { + case HAL_OK : + usb_status = USBD_OK; + 800a9d0: 2300 movs r3, #0 + 800a9d2: 73fb strb r3, [r7, #15] + break; + 800a9d4: e00b b.n 800a9ee + case HAL_ERROR : + usb_status = USBD_FAIL; + 800a9d6: 2302 movs r3, #2 + 800a9d8: 73fb strb r3, [r7, #15] + break; + 800a9da: e008 b.n 800a9ee + case HAL_BUSY : + usb_status = USBD_BUSY; + 800a9dc: 2301 movs r3, #1 + 800a9de: 73fb strb r3, [r7, #15] + break; + 800a9e0: e005 b.n 800a9ee + case HAL_TIMEOUT : + usb_status = USBD_FAIL; + 800a9e2: 2302 movs r3, #2 + 800a9e4: 73fb strb r3, [r7, #15] + break; + 800a9e6: e002 b.n 800a9ee + default : + usb_status = USBD_FAIL; + 800a9e8: 2302 movs r3, #2 + 800a9ea: 73fb strb r3, [r7, #15] + break; + 800a9ec: bf00 nop + } + return usb_status; + 800a9ee: 7bfb ldrb r3, [r7, #15] +} + 800a9f0: 4618 mov r0, r3 + 800a9f2: 3714 adds r7, #20 + 800a9f4: 46bd mov sp, r7 + 800a9f6: bc80 pop {r7} + 800a9f8: 4770 bx lr + 800a9fa: bf00 nop + +0800a9fc : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 800a9fc: b480 push {r7} + 800a9fe: b083 sub sp, #12 + 800aa00: af00 add r7, sp, #0 + 800aa02: 4603 mov r3, r0 + 800aa04: 6039 str r1, [r7, #0] + 800aa06: 71fb strb r3, [r7, #7] + UNUSED(speed); + *length = sizeof(USBD_FS_DeviceDesc); + 800aa08: 683b ldr r3, [r7, #0] + 800aa0a: 2212 movs r2, #18 + 800aa0c: 801a strh r2, [r3, #0] + return USBD_FS_DeviceDesc; + 800aa0e: 4b03 ldr r3, [pc, #12] ; (800aa1c ) +} + 800aa10: 4618 mov r0, r3 + 800aa12: 370c adds r7, #12 + 800aa14: 46bd mov sp, r7 + 800aa16: bc80 pop {r7} + 800aa18: 4770 bx lr + 800aa1a: bf00 nop + 800aa1c: 20000170 .word 0x20000170 + +0800aa20 : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 800aa20: b480 push {r7} + 800aa22: b083 sub sp, #12 + 800aa24: af00 add r7, sp, #0 + 800aa26: 4603 mov r3, r0 + 800aa28: 6039 str r1, [r7, #0] + 800aa2a: 71fb strb r3, [r7, #7] + UNUSED(speed); + *length = sizeof(USBD_LangIDDesc); + 800aa2c: 683b ldr r3, [r7, #0] + 800aa2e: 2204 movs r2, #4 + 800aa30: 801a strh r2, [r3, #0] + return USBD_LangIDDesc; + 800aa32: 4b03 ldr r3, [pc, #12] ; (800aa40 ) +} + 800aa34: 4618 mov r0, r3 + 800aa36: 370c adds r7, #12 + 800aa38: 46bd mov sp, r7 + 800aa3a: bc80 pop {r7} + 800aa3c: 4770 bx lr + 800aa3e: bf00 nop + 800aa40: 20000184 .word 0x20000184 + +0800aa44 : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 800aa44: b580 push {r7, lr} + 800aa46: b082 sub sp, #8 + 800aa48: af00 add r7, sp, #0 + 800aa4a: 4603 mov r3, r0 + 800aa4c: 6039 str r1, [r7, #0] + 800aa4e: 71fb strb r3, [r7, #7] + if(speed == 0) + 800aa50: 79fb ldrb r3, [r7, #7] + 800aa52: 2b00 cmp r3, #0 + 800aa54: d105 bne.n 800aa62 + { + USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + 800aa56: 683a ldr r2, [r7, #0] + 800aa58: 4907 ldr r1, [pc, #28] ; (800aa78 ) + 800aa5a: 4808 ldr r0, [pc, #32] ; (800aa7c ) + 800aa5c: f7fd f80f bl 8007a7e + 800aa60: e004 b.n 800aa6c + } + else + { + USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + 800aa62: 683a ldr r2, [r7, #0] + 800aa64: 4904 ldr r1, [pc, #16] ; (800aa78 ) + 800aa66: 4805 ldr r0, [pc, #20] ; (800aa7c ) + 800aa68: f7fd f809 bl 8007a7e + } + return USBD_StrDesc; + 800aa6c: 4b02 ldr r3, [pc, #8] ; (800aa78 ) +} + 800aa6e: 4618 mov r0, r3 + 800aa70: 3708 adds r7, #8 + 800aa72: 46bd mov sp, r7 + 800aa74: bd80 pop {r7, pc} + 800aa76: bf00 nop + 800aa78: 20002040 .word 0x20002040 + 800aa7c: 0800c7ac .word 0x0800c7ac + +0800aa80 : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 800aa80: b580 push {r7, lr} + 800aa82: b082 sub sp, #8 + 800aa84: af00 add r7, sp, #0 + 800aa86: 4603 mov r3, r0 + 800aa88: 6039 str r1, [r7, #0] + 800aa8a: 71fb strb r3, [r7, #7] + UNUSED(speed); + USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + 800aa8c: 683a ldr r2, [r7, #0] + 800aa8e: 4904 ldr r1, [pc, #16] ; (800aaa0 ) + 800aa90: 4804 ldr r0, [pc, #16] ; (800aaa4 ) + 800aa92: f7fc fff4 bl 8007a7e + return USBD_StrDesc; + 800aa96: 4b02 ldr r3, [pc, #8] ; (800aaa0 ) +} + 800aa98: 4618 mov r0, r3 + 800aa9a: 3708 adds r7, #8 + 800aa9c: 46bd mov sp, r7 + 800aa9e: bd80 pop {r7, pc} + 800aaa0: 20002040 .word 0x20002040 + 800aaa4: 0800c7c4 .word 0x0800c7c4 + +0800aaa8 : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 800aaa8: b580 push {r7, lr} + 800aaaa: b082 sub sp, #8 + 800aaac: af00 add r7, sp, #0 + 800aaae: 4603 mov r3, r0 + 800aab0: 6039 str r1, [r7, #0] + 800aab2: 71fb strb r3, [r7, #7] + UNUSED(speed); + *length = USB_SIZ_STRING_SERIAL; + 800aab4: 683b ldr r3, [r7, #0] + 800aab6: 221a movs r2, #26 + 800aab8: 801a strh r2, [r3, #0] + + /* Update the serial number string descriptor with the data from the unique + * ID */ + Get_SerialNum(); + 800aaba: f000 f843 bl 800ab44 + /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ + + /* USER CODE END USBD_FS_SerialStrDescriptor */ + return (uint8_t *) USBD_StringSerial; + 800aabe: 4b02 ldr r3, [pc, #8] ; (800aac8 ) +} + 800aac0: 4618 mov r0, r3 + 800aac2: 3708 adds r7, #8 + 800aac4: 46bd mov sp, r7 + 800aac6: bd80 pop {r7, pc} + 800aac8: 20000188 .word 0x20000188 + +0800aacc : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 800aacc: b580 push {r7, lr} + 800aace: b082 sub sp, #8 + 800aad0: af00 add r7, sp, #0 + 800aad2: 4603 mov r3, r0 + 800aad4: 6039 str r1, [r7, #0] + 800aad6: 71fb strb r3, [r7, #7] + if(speed == USBD_SPEED_HIGH) + 800aad8: 79fb ldrb r3, [r7, #7] + 800aada: 2b00 cmp r3, #0 + 800aadc: d105 bne.n 800aaea + { + USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + 800aade: 683a ldr r2, [r7, #0] + 800aae0: 4907 ldr r1, [pc, #28] ; (800ab00 ) + 800aae2: 4808 ldr r0, [pc, #32] ; (800ab04 ) + 800aae4: f7fc ffcb bl 8007a7e + 800aae8: e004 b.n 800aaf4 + } + else + { + USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + 800aaea: 683a ldr r2, [r7, #0] + 800aaec: 4904 ldr r1, [pc, #16] ; (800ab00 ) + 800aaee: 4805 ldr r0, [pc, #20] ; (800ab04 ) + 800aaf0: f7fc ffc5 bl 8007a7e + } + return USBD_StrDesc; + 800aaf4: 4b02 ldr r3, [pc, #8] ; (800ab00 ) +} + 800aaf6: 4618 mov r0, r3 + 800aaf8: 3708 adds r7, #8 + 800aafa: 46bd mov sp, r7 + 800aafc: bd80 pop {r7, pc} + 800aafe: bf00 nop + 800ab00: 20002040 .word 0x20002040 + 800ab04: 0800c7d8 .word 0x0800c7d8 + +0800ab08 : + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + 800ab08: b580 push {r7, lr} + 800ab0a: b082 sub sp, #8 + 800ab0c: af00 add r7, sp, #0 + 800ab0e: 4603 mov r3, r0 + 800ab10: 6039 str r1, [r7, #0] + 800ab12: 71fb strb r3, [r7, #7] + if(speed == 0) + 800ab14: 79fb ldrb r3, [r7, #7] + 800ab16: 2b00 cmp r3, #0 + 800ab18: d105 bne.n 800ab26 + { + USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + 800ab1a: 683a ldr r2, [r7, #0] + 800ab1c: 4907 ldr r1, [pc, #28] ; (800ab3c ) + 800ab1e: 4808 ldr r0, [pc, #32] ; (800ab40 ) + 800ab20: f7fc ffad bl 8007a7e + 800ab24: e004 b.n 800ab30 + } + else + { + USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + 800ab26: 683a ldr r2, [r7, #0] + 800ab28: 4904 ldr r1, [pc, #16] ; (800ab3c ) + 800ab2a: 4805 ldr r0, [pc, #20] ; (800ab40 ) + 800ab2c: f7fc ffa7 bl 8007a7e + } + return USBD_StrDesc; + 800ab30: 4b02 ldr r3, [pc, #8] ; (800ab3c ) +} + 800ab32: 4618 mov r0, r3 + 800ab34: 3708 adds r7, #8 + 800ab36: 46bd mov sp, r7 + 800ab38: bd80 pop {r7, pc} + 800ab3a: bf00 nop + 800ab3c: 20002040 .word 0x20002040 + 800ab40: 0800c7e4 .word 0x0800c7e4 + +0800ab44 : + * @brief Create the serial number string descriptor + * @param None + * @retval None + */ +static void Get_SerialNum(void) +{ + 800ab44: b580 push {r7, lr} + 800ab46: b084 sub sp, #16 + 800ab48: af00 add r7, sp, #0 + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t *) DEVICE_ID1; + 800ab4a: 4b0f ldr r3, [pc, #60] ; (800ab88 ) + 800ab4c: 681b ldr r3, [r3, #0] + 800ab4e: 60fb str r3, [r7, #12] + deviceserial1 = *(uint32_t *) DEVICE_ID2; + 800ab50: 4b0e ldr r3, [pc, #56] ; (800ab8c ) + 800ab52: 681b ldr r3, [r3, #0] + 800ab54: 60bb str r3, [r7, #8] + deviceserial2 = *(uint32_t *) DEVICE_ID3; + 800ab56: 4b0e ldr r3, [pc, #56] ; (800ab90 ) + 800ab58: 681b ldr r3, [r3, #0] + 800ab5a: 607b str r3, [r7, #4] + + deviceserial0 += deviceserial2; + 800ab5c: 68fa ldr r2, [r7, #12] + 800ab5e: 687b ldr r3, [r7, #4] + 800ab60: 4413 add r3, r2 + 800ab62: 60fb str r3, [r7, #12] + + if (deviceserial0 != 0) + 800ab64: 68fb ldr r3, [r7, #12] + 800ab66: 2b00 cmp r3, #0 + 800ab68: d009 beq.n 800ab7e + { + IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); + 800ab6a: 2208 movs r2, #8 + 800ab6c: 4909 ldr r1, [pc, #36] ; (800ab94 ) + 800ab6e: 68f8 ldr r0, [r7, #12] + 800ab70: f000 f814 bl 800ab9c + IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); + 800ab74: 2204 movs r2, #4 + 800ab76: 4908 ldr r1, [pc, #32] ; (800ab98 ) + 800ab78: 68b8 ldr r0, [r7, #8] + 800ab7a: f000 f80f bl 800ab9c + } +} + 800ab7e: bf00 nop + 800ab80: 3710 adds r7, #16 + 800ab82: 46bd mov sp, r7 + 800ab84: bd80 pop {r7, pc} + 800ab86: bf00 nop + 800ab88: 1ffff7e8 .word 0x1ffff7e8 + 800ab8c: 1ffff7ec .word 0x1ffff7ec + 800ab90: 1ffff7f0 .word 0x1ffff7f0 + 800ab94: 2000018a .word 0x2000018a + 800ab98: 2000019a .word 0x2000019a + +0800ab9c : + * @param pbuf: pointer to the buffer + * @param len: buffer length + * @retval None + */ +static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) +{ + 800ab9c: b480 push {r7} + 800ab9e: b087 sub sp, #28 + 800aba0: af00 add r7, sp, #0 + 800aba2: 60f8 str r0, [r7, #12] + 800aba4: 60b9 str r1, [r7, #8] + 800aba6: 4613 mov r3, r2 + 800aba8: 71fb strb r3, [r7, #7] + uint8_t idx = 0; + 800abaa: 2300 movs r3, #0 + 800abac: 75fb strb r3, [r7, #23] + + for (idx = 0; idx < len; idx++) + 800abae: 2300 movs r3, #0 + 800abb0: 75fb strb r3, [r7, #23] + 800abb2: e027 b.n 800ac04 + { + if (((value >> 28)) < 0xA) + 800abb4: 68fb ldr r3, [r7, #12] + 800abb6: 0f1b lsrs r3, r3, #28 + 800abb8: 2b09 cmp r3, #9 + 800abba: d80b bhi.n 800abd4 + { + pbuf[2 * idx] = (value >> 28) + '0'; + 800abbc: 68fb ldr r3, [r7, #12] + 800abbe: 0f1b lsrs r3, r3, #28 + 800abc0: b2da uxtb r2, r3 + 800abc2: 7dfb ldrb r3, [r7, #23] + 800abc4: 005b lsls r3, r3, #1 + 800abc6: 4619 mov r1, r3 + 800abc8: 68bb ldr r3, [r7, #8] + 800abca: 440b add r3, r1 + 800abcc: 3230 adds r2, #48 ; 0x30 + 800abce: b2d2 uxtb r2, r2 + 800abd0: 701a strb r2, [r3, #0] + 800abd2: e00a b.n 800abea + } + else + { + pbuf[2 * idx] = (value >> 28) + 'A' - 10; + 800abd4: 68fb ldr r3, [r7, #12] + 800abd6: 0f1b lsrs r3, r3, #28 + 800abd8: b2da uxtb r2, r3 + 800abda: 7dfb ldrb r3, [r7, #23] + 800abdc: 005b lsls r3, r3, #1 + 800abde: 4619 mov r1, r3 + 800abe0: 68bb ldr r3, [r7, #8] + 800abe2: 440b add r3, r1 + 800abe4: 3237 adds r2, #55 ; 0x37 + 800abe6: b2d2 uxtb r2, r2 + 800abe8: 701a strb r2, [r3, #0] + } + + value = value << 4; + 800abea: 68fb ldr r3, [r7, #12] + 800abec: 011b lsls r3, r3, #4 + 800abee: 60fb str r3, [r7, #12] + + pbuf[2 * idx + 1] = 0; + 800abf0: 7dfb ldrb r3, [r7, #23] + 800abf2: 005b lsls r3, r3, #1 + 800abf4: 3301 adds r3, #1 + 800abf6: 68ba ldr r2, [r7, #8] + 800abf8: 4413 add r3, r2 + 800abfa: 2200 movs r2, #0 + 800abfc: 701a strb r2, [r3, #0] + for (idx = 0; idx < len; idx++) + 800abfe: 7dfb ldrb r3, [r7, #23] + 800ac00: 3301 adds r3, #1 + 800ac02: 75fb strb r3, [r7, #23] + 800ac04: 7dfa ldrb r2, [r7, #23] + 800ac06: 79fb ldrb r3, [r7, #7] + 800ac08: 429a cmp r2, r3 + 800ac0a: d3d3 bcc.n 800abb4 + } +} + 800ac0c: bf00 nop + 800ac0e: 371c adds r7, #28 + 800ac10: 46bd mov sp, r7 + 800ac12: bc80 pop {r7} + 800ac14: 4770 bx lr + ... + +0800ac18 : + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 800ac18: 2100 movs r1, #0 + b LoopCopyDataInit + 800ac1a: e003 b.n 800ac24 + +0800ac1c : + +CopyDataInit: + ldr r3, =_sidata + 800ac1c: 4b0b ldr r3, [pc, #44] ; (800ac4c ) + ldr r3, [r3, r1] + 800ac1e: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 800ac20: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 800ac22: 3104 adds r1, #4 + +0800ac24 : + +LoopCopyDataInit: + ldr r0, =_sdata + 800ac24: 480a ldr r0, [pc, #40] ; (800ac50 ) + ldr r3, =_edata + 800ac26: 4b0b ldr r3, [pc, #44] ; (800ac54 ) + adds r2, r0, r1 + 800ac28: 1842 adds r2, r0, r1 + cmp r2, r3 + 800ac2a: 429a cmp r2, r3 + bcc CopyDataInit + 800ac2c: d3f6 bcc.n 800ac1c + ldr r2, =_sbss + 800ac2e: 4a0a ldr r2, [pc, #40] ; (800ac58 ) + b LoopFillZerobss + 800ac30: e002 b.n 800ac38 + +0800ac32 : +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 800ac32: 2300 movs r3, #0 + str r3, [r2], #4 + 800ac34: f842 3b04 str.w r3, [r2], #4 + +0800ac38 : + +LoopFillZerobss: + ldr r3, = _ebss + 800ac38: 4b08 ldr r3, [pc, #32] ; (800ac5c ) + cmp r2, r3 + 800ac3a: 429a cmp r2, r3 + bcc FillZerobss + 800ac3c: d3f9 bcc.n 800ac32 + +/* Call the clock system intitialization function.*/ + bl SystemInit + 800ac3e: f7ff fb4d bl 800a2dc +/* Call static constructors */ + bl __libc_init_array + 800ac42: f000 f815 bl 800ac70 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 800ac46: f7fe f915 bl 8008e74
+ bx lr + 800ac4a: 4770 bx lr + ldr r3, =_sidata + 800ac4c: 0800f238 .word 0x0800f238 + ldr r0, =_sdata + 800ac50: 20000000 .word 0x20000000 + ldr r3, =_edata + 800ac54: 20000208 .word 0x20000208 + ldr r2, =_sbss + 800ac58: 20000208 .word 0x20000208 + ldr r3, = _ebss + 800ac5c: 20002244 .word 0x20002244 + +0800ac60 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 800ac60: e7fe b.n 800ac60 + ... + +0800ac64 <__errno>: + 800ac64: 4b01 ldr r3, [pc, #4] ; (800ac6c <__errno+0x8>) + 800ac66: 6818 ldr r0, [r3, #0] + 800ac68: 4770 bx lr + 800ac6a: bf00 nop + 800ac6c: 200001a4 .word 0x200001a4 + +0800ac70 <__libc_init_array>: + 800ac70: b570 push {r4, r5, r6, lr} + 800ac72: 2500 movs r5, #0 + 800ac74: 4e0c ldr r6, [pc, #48] ; (800aca8 <__libc_init_array+0x38>) + 800ac76: 4c0d ldr r4, [pc, #52] ; (800acac <__libc_init_array+0x3c>) + 800ac78: 1ba4 subs r4, r4, r6 + 800ac7a: 10a4 asrs r4, r4, #2 + 800ac7c: 42a5 cmp r5, r4 + 800ac7e: d109 bne.n 800ac94 <__libc_init_array+0x24> + 800ac80: f001 fcd2 bl 800c628 <_init> + 800ac84: 2500 movs r5, #0 + 800ac86: 4e0a ldr r6, [pc, #40] ; (800acb0 <__libc_init_array+0x40>) + 800ac88: 4c0a ldr r4, [pc, #40] ; (800acb4 <__libc_init_array+0x44>) + 800ac8a: 1ba4 subs r4, r4, r6 + 800ac8c: 10a4 asrs r4, r4, #2 + 800ac8e: 42a5 cmp r5, r4 + 800ac90: d105 bne.n 800ac9e <__libc_init_array+0x2e> + 800ac92: bd70 pop {r4, r5, r6, pc} + 800ac94: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800ac98: 4798 blx r3 + 800ac9a: 3501 adds r5, #1 + 800ac9c: e7ee b.n 800ac7c <__libc_init_array+0xc> + 800ac9e: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800aca2: 4798 blx r3 + 800aca4: 3501 adds r5, #1 + 800aca6: e7f2 b.n 800ac8e <__libc_init_array+0x1e> + 800aca8: 0800f230 .word 0x0800f230 + 800acac: 0800f230 .word 0x0800f230 + 800acb0: 0800f230 .word 0x0800f230 + 800acb4: 0800f234 .word 0x0800f234 + +0800acb8 : + 800acb8: b510 push {r4, lr} + 800acba: 1e43 subs r3, r0, #1 + 800acbc: 440a add r2, r1 + 800acbe: 4291 cmp r1, r2 + 800acc0: d100 bne.n 800acc4 + 800acc2: bd10 pop {r4, pc} + 800acc4: f811 4b01 ldrb.w r4, [r1], #1 + 800acc8: f803 4f01 strb.w r4, [r3, #1]! + 800accc: e7f7 b.n 800acbe + +0800acce : + 800acce: 4603 mov r3, r0 + 800acd0: 4402 add r2, r0 + 800acd2: 4293 cmp r3, r2 + 800acd4: d100 bne.n 800acd8 + 800acd6: 4770 bx lr + 800acd8: f803 1b01 strb.w r1, [r3], #1 + 800acdc: e7f9 b.n 800acd2 + ... + +0800ace0 : + 800ace0: b40c push {r2, r3} + 800ace2: b530 push {r4, r5, lr} + 800ace4: 4b17 ldr r3, [pc, #92] ; (800ad44 ) + 800ace6: 1e0c subs r4, r1, #0 + 800ace8: b09d sub sp, #116 ; 0x74 + 800acea: 681d ldr r5, [r3, #0] + 800acec: da08 bge.n 800ad00 + 800acee: 238b movs r3, #139 ; 0x8b + 800acf0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800acf4: 602b str r3, [r5, #0] + 800acf6: b01d add sp, #116 ; 0x74 + 800acf8: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + 800acfc: b002 add sp, #8 + 800acfe: 4770 bx lr + 800ad00: f44f 7302 mov.w r3, #520 ; 0x208 + 800ad04: f8ad 3014 strh.w r3, [sp, #20] + 800ad08: bf0c ite eq + 800ad0a: 4623 moveq r3, r4 + 800ad0c: f104 33ff addne.w r3, r4, #4294967295 ; 0xffffffff + 800ad10: 9304 str r3, [sp, #16] + 800ad12: 9307 str r3, [sp, #28] + 800ad14: f64f 73ff movw r3, #65535 ; 0xffff + 800ad18: 9002 str r0, [sp, #8] + 800ad1a: 9006 str r0, [sp, #24] + 800ad1c: f8ad 3016 strh.w r3, [sp, #22] + 800ad20: 9a20 ldr r2, [sp, #128] ; 0x80 + 800ad22: ab21 add r3, sp, #132 ; 0x84 + 800ad24: a902 add r1, sp, #8 + 800ad26: 4628 mov r0, r5 + 800ad28: 9301 str r3, [sp, #4] + 800ad2a: f000 f887 bl 800ae3c <_svfiprintf_r> + 800ad2e: 1c43 adds r3, r0, #1 + 800ad30: bfbc itt lt + 800ad32: 238b movlt r3, #139 ; 0x8b + 800ad34: 602b strlt r3, [r5, #0] + 800ad36: 2c00 cmp r4, #0 + 800ad38: d0dd beq.n 800acf6 + 800ad3a: 2200 movs r2, #0 + 800ad3c: 9b02 ldr r3, [sp, #8] + 800ad3e: 701a strb r2, [r3, #0] + 800ad40: e7d9 b.n 800acf6 + 800ad42: bf00 nop + 800ad44: 200001a4 .word 0x200001a4 + +0800ad48 : + 800ad48: b40e push {r1, r2, r3} + 800ad4a: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 + 800ad4e: b500 push {lr} + 800ad50: b09c sub sp, #112 ; 0x70 + 800ad52: ab1d add r3, sp, #116 ; 0x74 + 800ad54: 9002 str r0, [sp, #8] + 800ad56: 9006 str r0, [sp, #24] + 800ad58: 9107 str r1, [sp, #28] + 800ad5a: 9104 str r1, [sp, #16] + 800ad5c: 4808 ldr r0, [pc, #32] ; (800ad80 ) + 800ad5e: 4909 ldr r1, [pc, #36] ; (800ad84 ) + 800ad60: f853 2b04 ldr.w r2, [r3], #4 + 800ad64: 9105 str r1, [sp, #20] + 800ad66: 6800 ldr r0, [r0, #0] + 800ad68: a902 add r1, sp, #8 + 800ad6a: 9301 str r3, [sp, #4] + 800ad6c: f000 f866 bl 800ae3c <_svfiprintf_r> + 800ad70: 2200 movs r2, #0 + 800ad72: 9b02 ldr r3, [sp, #8] + 800ad74: 701a strb r2, [r3, #0] + 800ad76: b01c add sp, #112 ; 0x70 + 800ad78: f85d eb04 ldr.w lr, [sp], #4 + 800ad7c: b003 add sp, #12 + 800ad7e: 4770 bx lr + 800ad80: 200001a4 .word 0x200001a4 + 800ad84: ffff0208 .word 0xffff0208 + +0800ad88 <__ssputs_r>: + 800ad88: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800ad8c: 688e ldr r6, [r1, #8] + 800ad8e: 4682 mov sl, r0 + 800ad90: 429e cmp r6, r3 + 800ad92: 460c mov r4, r1 + 800ad94: 4690 mov r8, r2 + 800ad96: 4699 mov r9, r3 + 800ad98: d837 bhi.n 800ae0a <__ssputs_r+0x82> + 800ad9a: 898a ldrh r2, [r1, #12] + 800ad9c: f412 6f90 tst.w r2, #1152 ; 0x480 + 800ada0: d031 beq.n 800ae06 <__ssputs_r+0x7e> + 800ada2: 2302 movs r3, #2 + 800ada4: 6825 ldr r5, [r4, #0] + 800ada6: 6909 ldr r1, [r1, #16] + 800ada8: 1a6f subs r7, r5, r1 + 800adaa: 6965 ldr r5, [r4, #20] + 800adac: eb05 0545 add.w r5, r5, r5, lsl #1 + 800adb0: fb95 f5f3 sdiv r5, r5, r3 + 800adb4: f109 0301 add.w r3, r9, #1 + 800adb8: 443b add r3, r7 + 800adba: 429d cmp r5, r3 + 800adbc: bf38 it cc + 800adbe: 461d movcc r5, r3 + 800adc0: 0553 lsls r3, r2, #21 + 800adc2: d530 bpl.n 800ae26 <__ssputs_r+0x9e> + 800adc4: 4629 mov r1, r5 + 800adc6: f000 fb2d bl 800b424 <_malloc_r> + 800adca: 4606 mov r6, r0 + 800adcc: b950 cbnz r0, 800ade4 <__ssputs_r+0x5c> + 800adce: 230c movs r3, #12 + 800add0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800add4: f8ca 3000 str.w r3, [sl] + 800add8: 89a3 ldrh r3, [r4, #12] + 800adda: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800adde: 81a3 strh r3, [r4, #12] + 800ade0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800ade4: 463a mov r2, r7 + 800ade6: 6921 ldr r1, [r4, #16] + 800ade8: f7ff ff66 bl 800acb8 + 800adec: 89a3 ldrh r3, [r4, #12] + 800adee: f423 6390 bic.w r3, r3, #1152 ; 0x480 + 800adf2: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800adf6: 81a3 strh r3, [r4, #12] + 800adf8: 6126 str r6, [r4, #16] + 800adfa: 443e add r6, r7 + 800adfc: 6026 str r6, [r4, #0] + 800adfe: 464e mov r6, r9 + 800ae00: 6165 str r5, [r4, #20] + 800ae02: 1bed subs r5, r5, r7 + 800ae04: 60a5 str r5, [r4, #8] + 800ae06: 454e cmp r6, r9 + 800ae08: d900 bls.n 800ae0c <__ssputs_r+0x84> + 800ae0a: 464e mov r6, r9 + 800ae0c: 4632 mov r2, r6 + 800ae0e: 4641 mov r1, r8 + 800ae10: 6820 ldr r0, [r4, #0] + 800ae12: f000 faa1 bl 800b358 + 800ae16: 68a3 ldr r3, [r4, #8] + 800ae18: 2000 movs r0, #0 + 800ae1a: 1b9b subs r3, r3, r6 + 800ae1c: 60a3 str r3, [r4, #8] + 800ae1e: 6823 ldr r3, [r4, #0] + 800ae20: 441e add r6, r3 + 800ae22: 6026 str r6, [r4, #0] + 800ae24: e7dc b.n 800ade0 <__ssputs_r+0x58> + 800ae26: 462a mov r2, r5 + 800ae28: f000 fb56 bl 800b4d8 <_realloc_r> + 800ae2c: 4606 mov r6, r0 + 800ae2e: 2800 cmp r0, #0 + 800ae30: d1e2 bne.n 800adf8 <__ssputs_r+0x70> + 800ae32: 6921 ldr r1, [r4, #16] + 800ae34: 4650 mov r0, sl + 800ae36: f000 faa9 bl 800b38c <_free_r> + 800ae3a: e7c8 b.n 800adce <__ssputs_r+0x46> + +0800ae3c <_svfiprintf_r>: + 800ae3c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800ae40: 461d mov r5, r3 + 800ae42: 898b ldrh r3, [r1, #12] + 800ae44: b09d sub sp, #116 ; 0x74 + 800ae46: 061f lsls r7, r3, #24 + 800ae48: 4680 mov r8, r0 + 800ae4a: 460c mov r4, r1 + 800ae4c: 4616 mov r6, r2 + 800ae4e: d50f bpl.n 800ae70 <_svfiprintf_r+0x34> + 800ae50: 690b ldr r3, [r1, #16] + 800ae52: b96b cbnz r3, 800ae70 <_svfiprintf_r+0x34> + 800ae54: 2140 movs r1, #64 ; 0x40 + 800ae56: f000 fae5 bl 800b424 <_malloc_r> + 800ae5a: 6020 str r0, [r4, #0] + 800ae5c: 6120 str r0, [r4, #16] + 800ae5e: b928 cbnz r0, 800ae6c <_svfiprintf_r+0x30> + 800ae60: 230c movs r3, #12 + 800ae62: f8c8 3000 str.w r3, [r8] + 800ae66: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800ae6a: e0c8 b.n 800affe <_svfiprintf_r+0x1c2> + 800ae6c: 2340 movs r3, #64 ; 0x40 + 800ae6e: 6163 str r3, [r4, #20] + 800ae70: 2300 movs r3, #0 + 800ae72: 9309 str r3, [sp, #36] ; 0x24 + 800ae74: 2320 movs r3, #32 + 800ae76: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 800ae7a: 2330 movs r3, #48 ; 0x30 + 800ae7c: f04f 0b01 mov.w fp, #1 + 800ae80: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 800ae84: 9503 str r5, [sp, #12] + 800ae86: 4637 mov r7, r6 + 800ae88: 463d mov r5, r7 + 800ae8a: f815 3b01 ldrb.w r3, [r5], #1 + 800ae8e: b10b cbz r3, 800ae94 <_svfiprintf_r+0x58> + 800ae90: 2b25 cmp r3, #37 ; 0x25 + 800ae92: d13e bne.n 800af12 <_svfiprintf_r+0xd6> + 800ae94: ebb7 0a06 subs.w sl, r7, r6 + 800ae98: d00b beq.n 800aeb2 <_svfiprintf_r+0x76> + 800ae9a: 4653 mov r3, sl + 800ae9c: 4632 mov r2, r6 + 800ae9e: 4621 mov r1, r4 + 800aea0: 4640 mov r0, r8 + 800aea2: f7ff ff71 bl 800ad88 <__ssputs_r> + 800aea6: 3001 adds r0, #1 + 800aea8: f000 80a4 beq.w 800aff4 <_svfiprintf_r+0x1b8> + 800aeac: 9b09 ldr r3, [sp, #36] ; 0x24 + 800aeae: 4453 add r3, sl + 800aeb0: 9309 str r3, [sp, #36] ; 0x24 + 800aeb2: 783b ldrb r3, [r7, #0] + 800aeb4: 2b00 cmp r3, #0 + 800aeb6: f000 809d beq.w 800aff4 <_svfiprintf_r+0x1b8> + 800aeba: 2300 movs r3, #0 + 800aebc: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800aec0: e9cd 2305 strd r2, r3, [sp, #20] + 800aec4: 9304 str r3, [sp, #16] + 800aec6: 9307 str r3, [sp, #28] + 800aec8: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 800aecc: 931a str r3, [sp, #104] ; 0x68 + 800aece: 462f mov r7, r5 + 800aed0: 2205 movs r2, #5 + 800aed2: f817 1b01 ldrb.w r1, [r7], #1 + 800aed6: 4850 ldr r0, [pc, #320] ; (800b018 <_svfiprintf_r+0x1dc>) + 800aed8: f000 fa30 bl 800b33c + 800aedc: 9b04 ldr r3, [sp, #16] + 800aede: b9d0 cbnz r0, 800af16 <_svfiprintf_r+0xda> + 800aee0: 06d9 lsls r1, r3, #27 + 800aee2: bf44 itt mi + 800aee4: 2220 movmi r2, #32 + 800aee6: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800aeea: 071a lsls r2, r3, #28 + 800aeec: bf44 itt mi + 800aeee: 222b movmi r2, #43 ; 0x2b + 800aef0: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800aef4: 782a ldrb r2, [r5, #0] + 800aef6: 2a2a cmp r2, #42 ; 0x2a + 800aef8: d015 beq.n 800af26 <_svfiprintf_r+0xea> + 800aefa: 462f mov r7, r5 + 800aefc: 2000 movs r0, #0 + 800aefe: 250a movs r5, #10 + 800af00: 9a07 ldr r2, [sp, #28] + 800af02: 4639 mov r1, r7 + 800af04: f811 3b01 ldrb.w r3, [r1], #1 + 800af08: 3b30 subs r3, #48 ; 0x30 + 800af0a: 2b09 cmp r3, #9 + 800af0c: d94d bls.n 800afaa <_svfiprintf_r+0x16e> + 800af0e: b1b8 cbz r0, 800af40 <_svfiprintf_r+0x104> + 800af10: e00f b.n 800af32 <_svfiprintf_r+0xf6> + 800af12: 462f mov r7, r5 + 800af14: e7b8 b.n 800ae88 <_svfiprintf_r+0x4c> + 800af16: 4a40 ldr r2, [pc, #256] ; (800b018 <_svfiprintf_r+0x1dc>) + 800af18: 463d mov r5, r7 + 800af1a: 1a80 subs r0, r0, r2 + 800af1c: fa0b f000 lsl.w r0, fp, r0 + 800af20: 4318 orrs r0, r3 + 800af22: 9004 str r0, [sp, #16] + 800af24: e7d3 b.n 800aece <_svfiprintf_r+0x92> + 800af26: 9a03 ldr r2, [sp, #12] + 800af28: 1d11 adds r1, r2, #4 + 800af2a: 6812 ldr r2, [r2, #0] + 800af2c: 9103 str r1, [sp, #12] + 800af2e: 2a00 cmp r2, #0 + 800af30: db01 blt.n 800af36 <_svfiprintf_r+0xfa> + 800af32: 9207 str r2, [sp, #28] + 800af34: e004 b.n 800af40 <_svfiprintf_r+0x104> + 800af36: 4252 negs r2, r2 + 800af38: f043 0302 orr.w r3, r3, #2 + 800af3c: 9207 str r2, [sp, #28] + 800af3e: 9304 str r3, [sp, #16] + 800af40: 783b ldrb r3, [r7, #0] + 800af42: 2b2e cmp r3, #46 ; 0x2e + 800af44: d10c bne.n 800af60 <_svfiprintf_r+0x124> + 800af46: 787b ldrb r3, [r7, #1] + 800af48: 2b2a cmp r3, #42 ; 0x2a + 800af4a: d133 bne.n 800afb4 <_svfiprintf_r+0x178> + 800af4c: 9b03 ldr r3, [sp, #12] + 800af4e: 3702 adds r7, #2 + 800af50: 1d1a adds r2, r3, #4 + 800af52: 681b ldr r3, [r3, #0] + 800af54: 9203 str r2, [sp, #12] + 800af56: 2b00 cmp r3, #0 + 800af58: bfb8 it lt + 800af5a: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff + 800af5e: 9305 str r3, [sp, #20] + 800af60: 4d2e ldr r5, [pc, #184] ; (800b01c <_svfiprintf_r+0x1e0>) + 800af62: 2203 movs r2, #3 + 800af64: 7839 ldrb r1, [r7, #0] + 800af66: 4628 mov r0, r5 + 800af68: f000 f9e8 bl 800b33c + 800af6c: b138 cbz r0, 800af7e <_svfiprintf_r+0x142> + 800af6e: 2340 movs r3, #64 ; 0x40 + 800af70: 1b40 subs r0, r0, r5 + 800af72: fa03 f000 lsl.w r0, r3, r0 + 800af76: 9b04 ldr r3, [sp, #16] + 800af78: 3701 adds r7, #1 + 800af7a: 4303 orrs r3, r0 + 800af7c: 9304 str r3, [sp, #16] + 800af7e: 7839 ldrb r1, [r7, #0] + 800af80: 2206 movs r2, #6 + 800af82: 4827 ldr r0, [pc, #156] ; (800b020 <_svfiprintf_r+0x1e4>) + 800af84: 1c7e adds r6, r7, #1 + 800af86: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 800af8a: f000 f9d7 bl 800b33c + 800af8e: 2800 cmp r0, #0 + 800af90: d038 beq.n 800b004 <_svfiprintf_r+0x1c8> + 800af92: 4b24 ldr r3, [pc, #144] ; (800b024 <_svfiprintf_r+0x1e8>) + 800af94: bb13 cbnz r3, 800afdc <_svfiprintf_r+0x1a0> + 800af96: 9b03 ldr r3, [sp, #12] + 800af98: 3307 adds r3, #7 + 800af9a: f023 0307 bic.w r3, r3, #7 + 800af9e: 3308 adds r3, #8 + 800afa0: 9303 str r3, [sp, #12] + 800afa2: 9b09 ldr r3, [sp, #36] ; 0x24 + 800afa4: 444b add r3, r9 + 800afa6: 9309 str r3, [sp, #36] ; 0x24 + 800afa8: e76d b.n 800ae86 <_svfiprintf_r+0x4a> + 800afaa: fb05 3202 mla r2, r5, r2, r3 + 800afae: 2001 movs r0, #1 + 800afb0: 460f mov r7, r1 + 800afb2: e7a6 b.n 800af02 <_svfiprintf_r+0xc6> + 800afb4: 2300 movs r3, #0 + 800afb6: 250a movs r5, #10 + 800afb8: 4619 mov r1, r3 + 800afba: 3701 adds r7, #1 + 800afbc: 9305 str r3, [sp, #20] + 800afbe: 4638 mov r0, r7 + 800afc0: f810 2b01 ldrb.w r2, [r0], #1 + 800afc4: 3a30 subs r2, #48 ; 0x30 + 800afc6: 2a09 cmp r2, #9 + 800afc8: d903 bls.n 800afd2 <_svfiprintf_r+0x196> + 800afca: 2b00 cmp r3, #0 + 800afcc: d0c8 beq.n 800af60 <_svfiprintf_r+0x124> + 800afce: 9105 str r1, [sp, #20] + 800afd0: e7c6 b.n 800af60 <_svfiprintf_r+0x124> + 800afd2: fb05 2101 mla r1, r5, r1, r2 + 800afd6: 2301 movs r3, #1 + 800afd8: 4607 mov r7, r0 + 800afda: e7f0 b.n 800afbe <_svfiprintf_r+0x182> + 800afdc: ab03 add r3, sp, #12 + 800afde: 9300 str r3, [sp, #0] + 800afe0: 4622 mov r2, r4 + 800afe2: 4b11 ldr r3, [pc, #68] ; (800b028 <_svfiprintf_r+0x1ec>) + 800afe4: a904 add r1, sp, #16 + 800afe6: 4640 mov r0, r8 + 800afe8: f3af 8000 nop.w + 800afec: f1b0 3fff cmp.w r0, #4294967295 ; 0xffffffff + 800aff0: 4681 mov r9, r0 + 800aff2: d1d6 bne.n 800afa2 <_svfiprintf_r+0x166> + 800aff4: 89a3 ldrh r3, [r4, #12] + 800aff6: 065b lsls r3, r3, #25 + 800aff8: f53f af35 bmi.w 800ae66 <_svfiprintf_r+0x2a> + 800affc: 9809 ldr r0, [sp, #36] ; 0x24 + 800affe: b01d add sp, #116 ; 0x74 + 800b000: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800b004: ab03 add r3, sp, #12 + 800b006: 9300 str r3, [sp, #0] + 800b008: 4622 mov r2, r4 + 800b00a: 4b07 ldr r3, [pc, #28] ; (800b028 <_svfiprintf_r+0x1ec>) + 800b00c: a904 add r1, sp, #16 + 800b00e: 4640 mov r0, r8 + 800b010: f000 f882 bl 800b118 <_printf_i> + 800b014: e7ea b.n 800afec <_svfiprintf_r+0x1b0> + 800b016: bf00 nop + 800b018: 0800f020 .word 0x0800f020 + 800b01c: 0800f026 .word 0x0800f026 + 800b020: 0800f02a .word 0x0800f02a + 800b024: 00000000 .word 0x00000000 + 800b028: 0800ad89 .word 0x0800ad89 + +0800b02c <_printf_common>: + 800b02c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800b030: 4691 mov r9, r2 + 800b032: 461f mov r7, r3 + 800b034: 688a ldr r2, [r1, #8] + 800b036: 690b ldr r3, [r1, #16] + 800b038: 4606 mov r6, r0 + 800b03a: 4293 cmp r3, r2 + 800b03c: bfb8 it lt + 800b03e: 4613 movlt r3, r2 + 800b040: f8c9 3000 str.w r3, [r9] + 800b044: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 800b048: 460c mov r4, r1 + 800b04a: f8dd 8020 ldr.w r8, [sp, #32] + 800b04e: b112 cbz r2, 800b056 <_printf_common+0x2a> + 800b050: 3301 adds r3, #1 + 800b052: f8c9 3000 str.w r3, [r9] + 800b056: 6823 ldr r3, [r4, #0] + 800b058: 0699 lsls r1, r3, #26 + 800b05a: bf42 ittt mi + 800b05c: f8d9 3000 ldrmi.w r3, [r9] + 800b060: 3302 addmi r3, #2 + 800b062: f8c9 3000 strmi.w r3, [r9] + 800b066: 6825 ldr r5, [r4, #0] + 800b068: f015 0506 ands.w r5, r5, #6 + 800b06c: d107 bne.n 800b07e <_printf_common+0x52> + 800b06e: f104 0a19 add.w sl, r4, #25 + 800b072: 68e3 ldr r3, [r4, #12] + 800b074: f8d9 2000 ldr.w r2, [r9] + 800b078: 1a9b subs r3, r3, r2 + 800b07a: 42ab cmp r3, r5 + 800b07c: dc29 bgt.n 800b0d2 <_printf_common+0xa6> + 800b07e: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 + 800b082: 6822 ldr r2, [r4, #0] + 800b084: 3300 adds r3, #0 + 800b086: bf18 it ne + 800b088: 2301 movne r3, #1 + 800b08a: 0692 lsls r2, r2, #26 + 800b08c: d42e bmi.n 800b0ec <_printf_common+0xc0> + 800b08e: f104 0243 add.w r2, r4, #67 ; 0x43 + 800b092: 4639 mov r1, r7 + 800b094: 4630 mov r0, r6 + 800b096: 47c0 blx r8 + 800b098: 3001 adds r0, #1 + 800b09a: d021 beq.n 800b0e0 <_printf_common+0xb4> + 800b09c: 6823 ldr r3, [r4, #0] + 800b09e: 68e5 ldr r5, [r4, #12] + 800b0a0: f003 0306 and.w r3, r3, #6 + 800b0a4: 2b04 cmp r3, #4 + 800b0a6: bf18 it ne + 800b0a8: 2500 movne r5, #0 + 800b0aa: f8d9 2000 ldr.w r2, [r9] + 800b0ae: f04f 0900 mov.w r9, #0 + 800b0b2: bf08 it eq + 800b0b4: 1aad subeq r5, r5, r2 + 800b0b6: 68a3 ldr r3, [r4, #8] + 800b0b8: 6922 ldr r2, [r4, #16] + 800b0ba: bf08 it eq + 800b0bc: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 800b0c0: 4293 cmp r3, r2 + 800b0c2: bfc4 itt gt + 800b0c4: 1a9b subgt r3, r3, r2 + 800b0c6: 18ed addgt r5, r5, r3 + 800b0c8: 341a adds r4, #26 + 800b0ca: 454d cmp r5, r9 + 800b0cc: d11a bne.n 800b104 <_printf_common+0xd8> + 800b0ce: 2000 movs r0, #0 + 800b0d0: e008 b.n 800b0e4 <_printf_common+0xb8> + 800b0d2: 2301 movs r3, #1 + 800b0d4: 4652 mov r2, sl + 800b0d6: 4639 mov r1, r7 + 800b0d8: 4630 mov r0, r6 + 800b0da: 47c0 blx r8 + 800b0dc: 3001 adds r0, #1 + 800b0de: d103 bne.n 800b0e8 <_printf_common+0xbc> + 800b0e0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800b0e4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800b0e8: 3501 adds r5, #1 + 800b0ea: e7c2 b.n 800b072 <_printf_common+0x46> + 800b0ec: 2030 movs r0, #48 ; 0x30 + 800b0ee: 18e1 adds r1, r4, r3 + 800b0f0: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 800b0f4: 1c5a adds r2, r3, #1 + 800b0f6: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 800b0fa: 4422 add r2, r4 + 800b0fc: 3302 adds r3, #2 + 800b0fe: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 800b102: e7c4 b.n 800b08e <_printf_common+0x62> + 800b104: 2301 movs r3, #1 + 800b106: 4622 mov r2, r4 + 800b108: 4639 mov r1, r7 + 800b10a: 4630 mov r0, r6 + 800b10c: 47c0 blx r8 + 800b10e: 3001 adds r0, #1 + 800b110: d0e6 beq.n 800b0e0 <_printf_common+0xb4> + 800b112: f109 0901 add.w r9, r9, #1 + 800b116: e7d8 b.n 800b0ca <_printf_common+0x9e> + +0800b118 <_printf_i>: + 800b118: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 800b11c: f101 0c43 add.w ip, r1, #67 ; 0x43 + 800b120: 460c mov r4, r1 + 800b122: 7e09 ldrb r1, [r1, #24] + 800b124: b085 sub sp, #20 + 800b126: 296e cmp r1, #110 ; 0x6e + 800b128: 4617 mov r7, r2 + 800b12a: 4606 mov r6, r0 + 800b12c: 4698 mov r8, r3 + 800b12e: 9a0c ldr r2, [sp, #48] ; 0x30 + 800b130: f000 80b3 beq.w 800b29a <_printf_i+0x182> + 800b134: d822 bhi.n 800b17c <_printf_i+0x64> + 800b136: 2963 cmp r1, #99 ; 0x63 + 800b138: d036 beq.n 800b1a8 <_printf_i+0x90> + 800b13a: d80a bhi.n 800b152 <_printf_i+0x3a> + 800b13c: 2900 cmp r1, #0 + 800b13e: f000 80b9 beq.w 800b2b4 <_printf_i+0x19c> + 800b142: 2958 cmp r1, #88 ; 0x58 + 800b144: f000 8083 beq.w 800b24e <_printf_i+0x136> + 800b148: f104 0542 add.w r5, r4, #66 ; 0x42 + 800b14c: f884 1042 strb.w r1, [r4, #66] ; 0x42 + 800b150: e032 b.n 800b1b8 <_printf_i+0xa0> + 800b152: 2964 cmp r1, #100 ; 0x64 + 800b154: d001 beq.n 800b15a <_printf_i+0x42> + 800b156: 2969 cmp r1, #105 ; 0x69 + 800b158: d1f6 bne.n 800b148 <_printf_i+0x30> + 800b15a: 6820 ldr r0, [r4, #0] + 800b15c: 6813 ldr r3, [r2, #0] + 800b15e: 0605 lsls r5, r0, #24 + 800b160: f103 0104 add.w r1, r3, #4 + 800b164: d52a bpl.n 800b1bc <_printf_i+0xa4> + 800b166: 681b ldr r3, [r3, #0] + 800b168: 6011 str r1, [r2, #0] + 800b16a: 2b00 cmp r3, #0 + 800b16c: da03 bge.n 800b176 <_printf_i+0x5e> + 800b16e: 222d movs r2, #45 ; 0x2d + 800b170: 425b negs r3, r3 + 800b172: f884 2043 strb.w r2, [r4, #67] ; 0x43 + 800b176: 486f ldr r0, [pc, #444] ; (800b334 <_printf_i+0x21c>) + 800b178: 220a movs r2, #10 + 800b17a: e039 b.n 800b1f0 <_printf_i+0xd8> + 800b17c: 2973 cmp r1, #115 ; 0x73 + 800b17e: f000 809d beq.w 800b2bc <_printf_i+0x1a4> + 800b182: d808 bhi.n 800b196 <_printf_i+0x7e> + 800b184: 296f cmp r1, #111 ; 0x6f + 800b186: d020 beq.n 800b1ca <_printf_i+0xb2> + 800b188: 2970 cmp r1, #112 ; 0x70 + 800b18a: d1dd bne.n 800b148 <_printf_i+0x30> + 800b18c: 6823 ldr r3, [r4, #0] + 800b18e: f043 0320 orr.w r3, r3, #32 + 800b192: 6023 str r3, [r4, #0] + 800b194: e003 b.n 800b19e <_printf_i+0x86> + 800b196: 2975 cmp r1, #117 ; 0x75 + 800b198: d017 beq.n 800b1ca <_printf_i+0xb2> + 800b19a: 2978 cmp r1, #120 ; 0x78 + 800b19c: d1d4 bne.n 800b148 <_printf_i+0x30> + 800b19e: 2378 movs r3, #120 ; 0x78 + 800b1a0: 4865 ldr r0, [pc, #404] ; (800b338 <_printf_i+0x220>) + 800b1a2: f884 3045 strb.w r3, [r4, #69] ; 0x45 + 800b1a6: e055 b.n 800b254 <_printf_i+0x13c> + 800b1a8: 6813 ldr r3, [r2, #0] + 800b1aa: f104 0542 add.w r5, r4, #66 ; 0x42 + 800b1ae: 1d19 adds r1, r3, #4 + 800b1b0: 681b ldr r3, [r3, #0] + 800b1b2: 6011 str r1, [r2, #0] + 800b1b4: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 800b1b8: 2301 movs r3, #1 + 800b1ba: e08c b.n 800b2d6 <_printf_i+0x1be> + 800b1bc: 681b ldr r3, [r3, #0] + 800b1be: f010 0f40 tst.w r0, #64 ; 0x40 + 800b1c2: 6011 str r1, [r2, #0] + 800b1c4: bf18 it ne + 800b1c6: b21b sxthne r3, r3 + 800b1c8: e7cf b.n 800b16a <_printf_i+0x52> + 800b1ca: 6813 ldr r3, [r2, #0] + 800b1cc: 6825 ldr r5, [r4, #0] + 800b1ce: 1d18 adds r0, r3, #4 + 800b1d0: 6010 str r0, [r2, #0] + 800b1d2: 0628 lsls r0, r5, #24 + 800b1d4: d501 bpl.n 800b1da <_printf_i+0xc2> + 800b1d6: 681b ldr r3, [r3, #0] + 800b1d8: e002 b.n 800b1e0 <_printf_i+0xc8> + 800b1da: 0668 lsls r0, r5, #25 + 800b1dc: d5fb bpl.n 800b1d6 <_printf_i+0xbe> + 800b1de: 881b ldrh r3, [r3, #0] + 800b1e0: 296f cmp r1, #111 ; 0x6f + 800b1e2: bf14 ite ne + 800b1e4: 220a movne r2, #10 + 800b1e6: 2208 moveq r2, #8 + 800b1e8: 4852 ldr r0, [pc, #328] ; (800b334 <_printf_i+0x21c>) + 800b1ea: 2100 movs r1, #0 + 800b1ec: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 800b1f0: 6865 ldr r5, [r4, #4] + 800b1f2: 2d00 cmp r5, #0 + 800b1f4: 60a5 str r5, [r4, #8] + 800b1f6: f2c0 8095 blt.w 800b324 <_printf_i+0x20c> + 800b1fa: 6821 ldr r1, [r4, #0] + 800b1fc: f021 0104 bic.w r1, r1, #4 + 800b200: 6021 str r1, [r4, #0] + 800b202: 2b00 cmp r3, #0 + 800b204: d13d bne.n 800b282 <_printf_i+0x16a> + 800b206: 2d00 cmp r5, #0 + 800b208: f040 808e bne.w 800b328 <_printf_i+0x210> + 800b20c: 4665 mov r5, ip + 800b20e: 2a08 cmp r2, #8 + 800b210: d10b bne.n 800b22a <_printf_i+0x112> + 800b212: 6823 ldr r3, [r4, #0] + 800b214: 07db lsls r3, r3, #31 + 800b216: d508 bpl.n 800b22a <_printf_i+0x112> + 800b218: 6923 ldr r3, [r4, #16] + 800b21a: 6862 ldr r2, [r4, #4] + 800b21c: 429a cmp r2, r3 + 800b21e: bfde ittt le + 800b220: 2330 movle r3, #48 ; 0x30 + 800b222: f805 3c01 strble.w r3, [r5, #-1] + 800b226: f105 35ff addle.w r5, r5, #4294967295 ; 0xffffffff + 800b22a: ebac 0305 sub.w r3, ip, r5 + 800b22e: 6123 str r3, [r4, #16] + 800b230: f8cd 8000 str.w r8, [sp] + 800b234: 463b mov r3, r7 + 800b236: aa03 add r2, sp, #12 + 800b238: 4621 mov r1, r4 + 800b23a: 4630 mov r0, r6 + 800b23c: f7ff fef6 bl 800b02c <_printf_common> + 800b240: 3001 adds r0, #1 + 800b242: d14d bne.n 800b2e0 <_printf_i+0x1c8> + 800b244: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800b248: b005 add sp, #20 + 800b24a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 800b24e: 4839 ldr r0, [pc, #228] ; (800b334 <_printf_i+0x21c>) + 800b250: f884 1045 strb.w r1, [r4, #69] ; 0x45 + 800b254: 6813 ldr r3, [r2, #0] + 800b256: 6821 ldr r1, [r4, #0] + 800b258: 1d1d adds r5, r3, #4 + 800b25a: 681b ldr r3, [r3, #0] + 800b25c: 6015 str r5, [r2, #0] + 800b25e: 060a lsls r2, r1, #24 + 800b260: d50b bpl.n 800b27a <_printf_i+0x162> + 800b262: 07ca lsls r2, r1, #31 + 800b264: bf44 itt mi + 800b266: f041 0120 orrmi.w r1, r1, #32 + 800b26a: 6021 strmi r1, [r4, #0] + 800b26c: b91b cbnz r3, 800b276 <_printf_i+0x15e> + 800b26e: 6822 ldr r2, [r4, #0] + 800b270: f022 0220 bic.w r2, r2, #32 + 800b274: 6022 str r2, [r4, #0] + 800b276: 2210 movs r2, #16 + 800b278: e7b7 b.n 800b1ea <_printf_i+0xd2> + 800b27a: 064d lsls r5, r1, #25 + 800b27c: bf48 it mi + 800b27e: b29b uxthmi r3, r3 + 800b280: e7ef b.n 800b262 <_printf_i+0x14a> + 800b282: 4665 mov r5, ip + 800b284: fbb3 f1f2 udiv r1, r3, r2 + 800b288: fb02 3311 mls r3, r2, r1, r3 + 800b28c: 5cc3 ldrb r3, [r0, r3] + 800b28e: f805 3d01 strb.w r3, [r5, #-1]! + 800b292: 460b mov r3, r1 + 800b294: 2900 cmp r1, #0 + 800b296: d1f5 bne.n 800b284 <_printf_i+0x16c> + 800b298: e7b9 b.n 800b20e <_printf_i+0xf6> + 800b29a: 6813 ldr r3, [r2, #0] + 800b29c: 6825 ldr r5, [r4, #0] + 800b29e: 1d18 adds r0, r3, #4 + 800b2a0: 6961 ldr r1, [r4, #20] + 800b2a2: 6010 str r0, [r2, #0] + 800b2a4: 0628 lsls r0, r5, #24 + 800b2a6: 681b ldr r3, [r3, #0] + 800b2a8: d501 bpl.n 800b2ae <_printf_i+0x196> + 800b2aa: 6019 str r1, [r3, #0] + 800b2ac: e002 b.n 800b2b4 <_printf_i+0x19c> + 800b2ae: 066a lsls r2, r5, #25 + 800b2b0: d5fb bpl.n 800b2aa <_printf_i+0x192> + 800b2b2: 8019 strh r1, [r3, #0] + 800b2b4: 2300 movs r3, #0 + 800b2b6: 4665 mov r5, ip + 800b2b8: 6123 str r3, [r4, #16] + 800b2ba: e7b9 b.n 800b230 <_printf_i+0x118> + 800b2bc: 6813 ldr r3, [r2, #0] + 800b2be: 1d19 adds r1, r3, #4 + 800b2c0: 6011 str r1, [r2, #0] + 800b2c2: 681d ldr r5, [r3, #0] + 800b2c4: 6862 ldr r2, [r4, #4] + 800b2c6: 2100 movs r1, #0 + 800b2c8: 4628 mov r0, r5 + 800b2ca: f000 f837 bl 800b33c + 800b2ce: b108 cbz r0, 800b2d4 <_printf_i+0x1bc> + 800b2d0: 1b40 subs r0, r0, r5 + 800b2d2: 6060 str r0, [r4, #4] + 800b2d4: 6863 ldr r3, [r4, #4] + 800b2d6: 6123 str r3, [r4, #16] + 800b2d8: 2300 movs r3, #0 + 800b2da: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 800b2de: e7a7 b.n 800b230 <_printf_i+0x118> + 800b2e0: 6923 ldr r3, [r4, #16] + 800b2e2: 462a mov r2, r5 + 800b2e4: 4639 mov r1, r7 + 800b2e6: 4630 mov r0, r6 + 800b2e8: 47c0 blx r8 + 800b2ea: 3001 adds r0, #1 + 800b2ec: d0aa beq.n 800b244 <_printf_i+0x12c> + 800b2ee: 6823 ldr r3, [r4, #0] + 800b2f0: 079b lsls r3, r3, #30 + 800b2f2: d413 bmi.n 800b31c <_printf_i+0x204> + 800b2f4: 68e0 ldr r0, [r4, #12] + 800b2f6: 9b03 ldr r3, [sp, #12] + 800b2f8: 4298 cmp r0, r3 + 800b2fa: bfb8 it lt + 800b2fc: 4618 movlt r0, r3 + 800b2fe: e7a3 b.n 800b248 <_printf_i+0x130> + 800b300: 2301 movs r3, #1 + 800b302: 464a mov r2, r9 + 800b304: 4639 mov r1, r7 + 800b306: 4630 mov r0, r6 + 800b308: 47c0 blx r8 + 800b30a: 3001 adds r0, #1 + 800b30c: d09a beq.n 800b244 <_printf_i+0x12c> + 800b30e: 3501 adds r5, #1 + 800b310: 68e3 ldr r3, [r4, #12] + 800b312: 9a03 ldr r2, [sp, #12] + 800b314: 1a9b subs r3, r3, r2 + 800b316: 42ab cmp r3, r5 + 800b318: dcf2 bgt.n 800b300 <_printf_i+0x1e8> + 800b31a: e7eb b.n 800b2f4 <_printf_i+0x1dc> + 800b31c: 2500 movs r5, #0 + 800b31e: f104 0919 add.w r9, r4, #25 + 800b322: e7f5 b.n 800b310 <_printf_i+0x1f8> + 800b324: 2b00 cmp r3, #0 + 800b326: d1ac bne.n 800b282 <_printf_i+0x16a> + 800b328: 7803 ldrb r3, [r0, #0] + 800b32a: f104 0542 add.w r5, r4, #66 ; 0x42 + 800b32e: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 800b332: e76c b.n 800b20e <_printf_i+0xf6> + 800b334: 0800f031 .word 0x0800f031 + 800b338: 0800f042 .word 0x0800f042 + +0800b33c : + 800b33c: b510 push {r4, lr} + 800b33e: b2c9 uxtb r1, r1 + 800b340: 4402 add r2, r0 + 800b342: 4290 cmp r0, r2 + 800b344: 4603 mov r3, r0 + 800b346: d101 bne.n 800b34c + 800b348: 2300 movs r3, #0 + 800b34a: e003 b.n 800b354 + 800b34c: 781c ldrb r4, [r3, #0] + 800b34e: 3001 adds r0, #1 + 800b350: 428c cmp r4, r1 + 800b352: d1f6 bne.n 800b342 + 800b354: 4618 mov r0, r3 + 800b356: bd10 pop {r4, pc} + +0800b358 : + 800b358: 4288 cmp r0, r1 + 800b35a: b510 push {r4, lr} + 800b35c: eb01 0302 add.w r3, r1, r2 + 800b360: d807 bhi.n 800b372 + 800b362: 1e42 subs r2, r0, #1 + 800b364: 4299 cmp r1, r3 + 800b366: d00a beq.n 800b37e + 800b368: f811 4b01 ldrb.w r4, [r1], #1 + 800b36c: f802 4f01 strb.w r4, [r2, #1]! + 800b370: e7f8 b.n 800b364 + 800b372: 4283 cmp r3, r0 + 800b374: d9f5 bls.n 800b362 + 800b376: 1881 adds r1, r0, r2 + 800b378: 1ad2 subs r2, r2, r3 + 800b37a: 42d3 cmn r3, r2 + 800b37c: d100 bne.n 800b380 + 800b37e: bd10 pop {r4, pc} + 800b380: f813 4d01 ldrb.w r4, [r3, #-1]! + 800b384: f801 4d01 strb.w r4, [r1, #-1]! + 800b388: e7f7 b.n 800b37a + ... + +0800b38c <_free_r>: + 800b38c: b538 push {r3, r4, r5, lr} + 800b38e: 4605 mov r5, r0 + 800b390: 2900 cmp r1, #0 + 800b392: d043 beq.n 800b41c <_free_r+0x90> + 800b394: f851 3c04 ldr.w r3, [r1, #-4] + 800b398: 1f0c subs r4, r1, #4 + 800b39a: 2b00 cmp r3, #0 + 800b39c: bfb8 it lt + 800b39e: 18e4 addlt r4, r4, r3 + 800b3a0: f000 f8d0 bl 800b544 <__malloc_lock> + 800b3a4: 4a1e ldr r2, [pc, #120] ; (800b420 <_free_r+0x94>) + 800b3a6: 6813 ldr r3, [r2, #0] + 800b3a8: 4610 mov r0, r2 + 800b3aa: b933 cbnz r3, 800b3ba <_free_r+0x2e> + 800b3ac: 6063 str r3, [r4, #4] + 800b3ae: 6014 str r4, [r2, #0] + 800b3b0: 4628 mov r0, r5 + 800b3b2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800b3b6: f000 b8c6 b.w 800b546 <__malloc_unlock> + 800b3ba: 42a3 cmp r3, r4 + 800b3bc: d90b bls.n 800b3d6 <_free_r+0x4a> + 800b3be: 6821 ldr r1, [r4, #0] + 800b3c0: 1862 adds r2, r4, r1 + 800b3c2: 4293 cmp r3, r2 + 800b3c4: bf01 itttt eq + 800b3c6: 681a ldreq r2, [r3, #0] + 800b3c8: 685b ldreq r3, [r3, #4] + 800b3ca: 1852 addeq r2, r2, r1 + 800b3cc: 6022 streq r2, [r4, #0] + 800b3ce: 6063 str r3, [r4, #4] + 800b3d0: 6004 str r4, [r0, #0] + 800b3d2: e7ed b.n 800b3b0 <_free_r+0x24> + 800b3d4: 4613 mov r3, r2 + 800b3d6: 685a ldr r2, [r3, #4] + 800b3d8: b10a cbz r2, 800b3de <_free_r+0x52> + 800b3da: 42a2 cmp r2, r4 + 800b3dc: d9fa bls.n 800b3d4 <_free_r+0x48> + 800b3de: 6819 ldr r1, [r3, #0] + 800b3e0: 1858 adds r0, r3, r1 + 800b3e2: 42a0 cmp r0, r4 + 800b3e4: d10b bne.n 800b3fe <_free_r+0x72> + 800b3e6: 6820 ldr r0, [r4, #0] + 800b3e8: 4401 add r1, r0 + 800b3ea: 1858 adds r0, r3, r1 + 800b3ec: 4282 cmp r2, r0 + 800b3ee: 6019 str r1, [r3, #0] + 800b3f0: d1de bne.n 800b3b0 <_free_r+0x24> + 800b3f2: 6810 ldr r0, [r2, #0] + 800b3f4: 6852 ldr r2, [r2, #4] + 800b3f6: 4401 add r1, r0 + 800b3f8: 6019 str r1, [r3, #0] + 800b3fa: 605a str r2, [r3, #4] + 800b3fc: e7d8 b.n 800b3b0 <_free_r+0x24> + 800b3fe: d902 bls.n 800b406 <_free_r+0x7a> + 800b400: 230c movs r3, #12 + 800b402: 602b str r3, [r5, #0] + 800b404: e7d4 b.n 800b3b0 <_free_r+0x24> + 800b406: 6820 ldr r0, [r4, #0] + 800b408: 1821 adds r1, r4, r0 + 800b40a: 428a cmp r2, r1 + 800b40c: bf01 itttt eq + 800b40e: 6811 ldreq r1, [r2, #0] + 800b410: 6852 ldreq r2, [r2, #4] + 800b412: 1809 addeq r1, r1, r0 + 800b414: 6021 streq r1, [r4, #0] + 800b416: 6062 str r2, [r4, #4] + 800b418: 605c str r4, [r3, #4] + 800b41a: e7c9 b.n 800b3b0 <_free_r+0x24> + 800b41c: bd38 pop {r3, r4, r5, pc} + 800b41e: bf00 nop + 800b420: 200011ec .word 0x200011ec + +0800b424 <_malloc_r>: + 800b424: b570 push {r4, r5, r6, lr} + 800b426: 1ccd adds r5, r1, #3 + 800b428: f025 0503 bic.w r5, r5, #3 + 800b42c: 3508 adds r5, #8 + 800b42e: 2d0c cmp r5, #12 + 800b430: bf38 it cc + 800b432: 250c movcc r5, #12 + 800b434: 2d00 cmp r5, #0 + 800b436: 4606 mov r6, r0 + 800b438: db01 blt.n 800b43e <_malloc_r+0x1a> + 800b43a: 42a9 cmp r1, r5 + 800b43c: d903 bls.n 800b446 <_malloc_r+0x22> + 800b43e: 230c movs r3, #12 + 800b440: 6033 str r3, [r6, #0] + 800b442: 2000 movs r0, #0 + 800b444: bd70 pop {r4, r5, r6, pc} + 800b446: f000 f87d bl 800b544 <__malloc_lock> + 800b44a: 4a21 ldr r2, [pc, #132] ; (800b4d0 <_malloc_r+0xac>) + 800b44c: 6814 ldr r4, [r2, #0] + 800b44e: 4621 mov r1, r4 + 800b450: b991 cbnz r1, 800b478 <_malloc_r+0x54> + 800b452: 4c20 ldr r4, [pc, #128] ; (800b4d4 <_malloc_r+0xb0>) + 800b454: 6823 ldr r3, [r4, #0] + 800b456: b91b cbnz r3, 800b460 <_malloc_r+0x3c> + 800b458: 4630 mov r0, r6 + 800b45a: f000 f863 bl 800b524 <_sbrk_r> + 800b45e: 6020 str r0, [r4, #0] + 800b460: 4629 mov r1, r5 + 800b462: 4630 mov r0, r6 + 800b464: f000 f85e bl 800b524 <_sbrk_r> + 800b468: 1c43 adds r3, r0, #1 + 800b46a: d124 bne.n 800b4b6 <_malloc_r+0x92> + 800b46c: 230c movs r3, #12 + 800b46e: 4630 mov r0, r6 + 800b470: 6033 str r3, [r6, #0] + 800b472: f000 f868 bl 800b546 <__malloc_unlock> + 800b476: e7e4 b.n 800b442 <_malloc_r+0x1e> + 800b478: 680b ldr r3, [r1, #0] + 800b47a: 1b5b subs r3, r3, r5 + 800b47c: d418 bmi.n 800b4b0 <_malloc_r+0x8c> + 800b47e: 2b0b cmp r3, #11 + 800b480: d90f bls.n 800b4a2 <_malloc_r+0x7e> + 800b482: 600b str r3, [r1, #0] + 800b484: 18cc adds r4, r1, r3 + 800b486: 50cd str r5, [r1, r3] + 800b488: 4630 mov r0, r6 + 800b48a: f000 f85c bl 800b546 <__malloc_unlock> + 800b48e: f104 000b add.w r0, r4, #11 + 800b492: 1d23 adds r3, r4, #4 + 800b494: f020 0007 bic.w r0, r0, #7 + 800b498: 1ac3 subs r3, r0, r3 + 800b49a: d0d3 beq.n 800b444 <_malloc_r+0x20> + 800b49c: 425a negs r2, r3 + 800b49e: 50e2 str r2, [r4, r3] + 800b4a0: e7d0 b.n 800b444 <_malloc_r+0x20> + 800b4a2: 684b ldr r3, [r1, #4] + 800b4a4: 428c cmp r4, r1 + 800b4a6: bf16 itet ne + 800b4a8: 6063 strne r3, [r4, #4] + 800b4aa: 6013 streq r3, [r2, #0] + 800b4ac: 460c movne r4, r1 + 800b4ae: e7eb b.n 800b488 <_malloc_r+0x64> + 800b4b0: 460c mov r4, r1 + 800b4b2: 6849 ldr r1, [r1, #4] + 800b4b4: e7cc b.n 800b450 <_malloc_r+0x2c> + 800b4b6: 1cc4 adds r4, r0, #3 + 800b4b8: f024 0403 bic.w r4, r4, #3 + 800b4bc: 42a0 cmp r0, r4 + 800b4be: d005 beq.n 800b4cc <_malloc_r+0xa8> + 800b4c0: 1a21 subs r1, r4, r0 + 800b4c2: 4630 mov r0, r6 + 800b4c4: f000 f82e bl 800b524 <_sbrk_r> + 800b4c8: 3001 adds r0, #1 + 800b4ca: d0cf beq.n 800b46c <_malloc_r+0x48> + 800b4cc: 6025 str r5, [r4, #0] + 800b4ce: e7db b.n 800b488 <_malloc_r+0x64> + 800b4d0: 200011ec .word 0x200011ec + 800b4d4: 200011f0 .word 0x200011f0 + +0800b4d8 <_realloc_r>: + 800b4d8: b5f8 push {r3, r4, r5, r6, r7, lr} + 800b4da: 4607 mov r7, r0 + 800b4dc: 4614 mov r4, r2 + 800b4de: 460e mov r6, r1 + 800b4e0: b921 cbnz r1, 800b4ec <_realloc_r+0x14> + 800b4e2: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} + 800b4e6: 4611 mov r1, r2 + 800b4e8: f7ff bf9c b.w 800b424 <_malloc_r> + 800b4ec: b922 cbnz r2, 800b4f8 <_realloc_r+0x20> + 800b4ee: f7ff ff4d bl 800b38c <_free_r> + 800b4f2: 4625 mov r5, r4 + 800b4f4: 4628 mov r0, r5 + 800b4f6: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800b4f8: f000 f826 bl 800b548 <_malloc_usable_size_r> + 800b4fc: 42a0 cmp r0, r4 + 800b4fe: d20f bcs.n 800b520 <_realloc_r+0x48> + 800b500: 4621 mov r1, r4 + 800b502: 4638 mov r0, r7 + 800b504: f7ff ff8e bl 800b424 <_malloc_r> + 800b508: 4605 mov r5, r0 + 800b50a: 2800 cmp r0, #0 + 800b50c: d0f2 beq.n 800b4f4 <_realloc_r+0x1c> + 800b50e: 4631 mov r1, r6 + 800b510: 4622 mov r2, r4 + 800b512: f7ff fbd1 bl 800acb8 + 800b516: 4631 mov r1, r6 + 800b518: 4638 mov r0, r7 + 800b51a: f7ff ff37 bl 800b38c <_free_r> + 800b51e: e7e9 b.n 800b4f4 <_realloc_r+0x1c> + 800b520: 4635 mov r5, r6 + 800b522: e7e7 b.n 800b4f4 <_realloc_r+0x1c> + +0800b524 <_sbrk_r>: + 800b524: b538 push {r3, r4, r5, lr} + 800b526: 2300 movs r3, #0 + 800b528: 4c05 ldr r4, [pc, #20] ; (800b540 <_sbrk_r+0x1c>) + 800b52a: 4605 mov r5, r0 + 800b52c: 4608 mov r0, r1 + 800b52e: 6023 str r3, [r4, #0] + 800b530: f7fe fea8 bl 800a284 <_sbrk> + 800b534: 1c43 adds r3, r0, #1 + 800b536: d102 bne.n 800b53e <_sbrk_r+0x1a> + 800b538: 6823 ldr r3, [r4, #0] + 800b53a: b103 cbz r3, 800b53e <_sbrk_r+0x1a> + 800b53c: 602b str r3, [r5, #0] + 800b53e: bd38 pop {r3, r4, r5, pc} + 800b540: 20002240 .word 0x20002240 + +0800b544 <__malloc_lock>: + 800b544: 4770 bx lr + +0800b546 <__malloc_unlock>: + 800b546: 4770 bx lr + +0800b548 <_malloc_usable_size_r>: + 800b548: f851 3c04 ldr.w r3, [r1, #-4] + 800b54c: 1f18 subs r0, r3, #4 + 800b54e: 2b00 cmp r3, #0 + 800b550: bfbc itt lt + 800b552: 580b ldrlt r3, [r1, r0] + 800b554: 18c0 addlt r0, r0, r3 + 800b556: 4770 bx lr + +0800b558 : + 800b558: b530 push {r4, r5, lr} + 800b55a: 4a18 ldr r2, [pc, #96] ; (800b5bc ) + 800b55c: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800b560: 4293 cmp r3, r2 + 800b562: b087 sub sp, #28 + 800b564: dc04 bgt.n 800b570 + 800b566: 2200 movs r2, #0 + 800b568: 2300 movs r3, #0 + 800b56a: f000 fa9d bl 800baa8 <__kernel_cos> + 800b56e: e006 b.n 800b57e + 800b570: 4a13 ldr r2, [pc, #76] ; (800b5c0 ) + 800b572: 4293 cmp r3, r2 + 800b574: dd05 ble.n 800b582 + 800b576: 4602 mov r2, r0 + 800b578: 460b mov r3, r1 + 800b57a: f7f4 fded bl 8000158 <__aeabi_dsub> + 800b57e: b007 add sp, #28 + 800b580: bd30 pop {r4, r5, pc} + 800b582: aa02 add r2, sp, #8 + 800b584: f000 f8a0 bl 800b6c8 <__ieee754_rem_pio2> + 800b588: e9dd 2304 ldrd r2, r3, [sp, #16] + 800b58c: f000 0403 and.w r4, r0, #3 + 800b590: 2c01 cmp r4, #1 + 800b592: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b596: d008 beq.n 800b5aa + 800b598: 2c02 cmp r4, #2 + 800b59a: d00c beq.n 800b5b6 + 800b59c: 2c00 cmp r4, #0 + 800b59e: d0e4 beq.n 800b56a + 800b5a0: 2401 movs r4, #1 + 800b5a2: 9400 str r4, [sp, #0] + 800b5a4: f000 fe88 bl 800c2b8 <__kernel_sin> + 800b5a8: e7e9 b.n 800b57e + 800b5aa: 9400 str r4, [sp, #0] + 800b5ac: f000 fe84 bl 800c2b8 <__kernel_sin> + 800b5b0: f101 4100 add.w r1, r1, #2147483648 ; 0x80000000 + 800b5b4: e7e3 b.n 800b57e + 800b5b6: f000 fa77 bl 800baa8 <__kernel_cos> + 800b5ba: e7f9 b.n 800b5b0 + 800b5bc: 3fe921fb .word 0x3fe921fb + 800b5c0: 7fefffff .word 0x7fefffff + +0800b5c4 : + 800b5c4: b5f8 push {r3, r4, r5, r6, r7, lr} + 800b5c6: f3c1 570a ubfx r7, r1, #20, #11 + 800b5ca: f2a7 34ff subw r4, r7, #1023 ; 0x3ff + 800b5ce: 2c13 cmp r4, #19 + 800b5d0: 4606 mov r6, r0 + 800b5d2: 460d mov r5, r1 + 800b5d4: 460b mov r3, r1 + 800b5d6: 468c mov ip, r1 + 800b5d8: 4602 mov r2, r0 + 800b5da: dc17 bgt.n 800b60c + 800b5dc: 2c00 cmp r4, #0 + 800b5de: da09 bge.n 800b5f4 + 800b5e0: 3401 adds r4, #1 + 800b5e2: f001 4300 and.w r3, r1, #2147483648 ; 0x80000000 + 800b5e6: d103 bne.n 800b5f0 + 800b5e8: f043 537f orr.w r3, r3, #1069547520 ; 0x3fc00000 + 800b5ec: f443 1340 orr.w r3, r3, #3145728 ; 0x300000 + 800b5f0: 2200 movs r2, #0 + 800b5f2: e028 b.n 800b646 + 800b5f4: 4915 ldr r1, [pc, #84] ; (800b64c ) + 800b5f6: 4121 asrs r1, r4 + 800b5f8: 420d tst r5, r1 + 800b5fa: d100 bne.n 800b5fe + 800b5fc: b178 cbz r0, 800b61e + 800b5fe: f44f 2300 mov.w r3, #524288 ; 0x80000 + 800b602: 4123 asrs r3, r4 + 800b604: 4463 add r3, ip + 800b606: ea23 0301 bic.w r3, r3, r1 + 800b60a: e7f1 b.n 800b5f0 + 800b60c: 2c33 cmp r4, #51 ; 0x33 + 800b60e: dd09 ble.n 800b624 + 800b610: f5b4 6f80 cmp.w r4, #1024 ; 0x400 + 800b614: d103 bne.n 800b61e + 800b616: f7f4 fda1 bl 800015c <__adddf3> + 800b61a: 4606 mov r6, r0 + 800b61c: 460d mov r5, r1 + 800b61e: 4630 mov r0, r6 + 800b620: 4629 mov r1, r5 + 800b622: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800b624: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800b628: f2a7 4713 subw r7, r7, #1043 ; 0x413 + 800b62c: 40f8 lsrs r0, r7 + 800b62e: 4206 tst r6, r0 + 800b630: d0f5 beq.n 800b61e + 800b632: 2101 movs r1, #1 + 800b634: f1c4 0433 rsb r4, r4, #51 ; 0x33 + 800b638: fa01 f404 lsl.w r4, r1, r4 + 800b63c: 1932 adds r2, r6, r4 + 800b63e: bf28 it cs + 800b640: 185b addcs r3, r3, r1 + 800b642: ea22 0200 bic.w r2, r2, r0 + 800b646: 4619 mov r1, r3 + 800b648: 4610 mov r0, r2 + 800b64a: e7e6 b.n 800b61a + 800b64c: 000fffff .word 0x000fffff + +0800b650 : + 800b650: b530 push {r4, r5, lr} + 800b652: 4a1a ldr r2, [pc, #104] ; (800b6bc ) + 800b654: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800b658: 4293 cmp r3, r2 + 800b65a: b087 sub sp, #28 + 800b65c: dc06 bgt.n 800b66c + 800b65e: 2300 movs r3, #0 + 800b660: 2200 movs r2, #0 + 800b662: 9300 str r3, [sp, #0] + 800b664: 2300 movs r3, #0 + 800b666: f000 fe27 bl 800c2b8 <__kernel_sin> + 800b66a: e006 b.n 800b67a + 800b66c: 4a14 ldr r2, [pc, #80] ; (800b6c0 ) + 800b66e: 4293 cmp r3, r2 + 800b670: dd05 ble.n 800b67e + 800b672: 4602 mov r2, r0 + 800b674: 460b mov r3, r1 + 800b676: f7f4 fd6f bl 8000158 <__aeabi_dsub> + 800b67a: b007 add sp, #28 + 800b67c: bd30 pop {r4, r5, pc} + 800b67e: aa02 add r2, sp, #8 + 800b680: f000 f822 bl 800b6c8 <__ieee754_rem_pio2> + 800b684: e9dd 2304 ldrd r2, r3, [sp, #16] + 800b688: f000 0403 and.w r4, r0, #3 + 800b68c: 2c01 cmp r4, #1 + 800b68e: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b692: d005 beq.n 800b6a0 + 800b694: 2c02 cmp r4, #2 + 800b696: d006 beq.n 800b6a6 + 800b698: b964 cbnz r4, 800b6b4 + 800b69a: 2401 movs r4, #1 + 800b69c: 9400 str r4, [sp, #0] + 800b69e: e7e2 b.n 800b666 + 800b6a0: f000 fa02 bl 800baa8 <__kernel_cos> + 800b6a4: e7e9 b.n 800b67a + 800b6a6: 2401 movs r4, #1 + 800b6a8: 9400 str r4, [sp, #0] + 800b6aa: f000 fe05 bl 800c2b8 <__kernel_sin> + 800b6ae: f101 4100 add.w r1, r1, #2147483648 ; 0x80000000 + 800b6b2: e7e2 b.n 800b67a + 800b6b4: f000 f9f8 bl 800baa8 <__kernel_cos> + 800b6b8: e7f9 b.n 800b6ae + 800b6ba: bf00 nop + 800b6bc: 3fe921fb .word 0x3fe921fb + 800b6c0: 7fefffff .word 0x7fefffff + 800b6c4: 00000000 .word 0x00000000 + +0800b6c8 <__ieee754_rem_pio2>: + 800b6c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800b6cc: 4614 mov r4, r2 + 800b6ce: 4ac2 ldr r2, [pc, #776] ; (800b9d8 <__ieee754_rem_pio2+0x310>) + 800b6d0: f021 4a00 bic.w sl, r1, #2147483648 ; 0x80000000 + 800b6d4: 4592 cmp sl, r2 + 800b6d6: b08d sub sp, #52 ; 0x34 + 800b6d8: 468b mov fp, r1 + 800b6da: dc07 bgt.n 800b6ec <__ieee754_rem_pio2+0x24> + 800b6dc: 2200 movs r2, #0 + 800b6de: 2300 movs r3, #0 + 800b6e0: e9c4 0100 strd r0, r1, [r4] + 800b6e4: e9c4 2302 strd r2, r3, [r4, #8] + 800b6e8: 2500 movs r5, #0 + 800b6ea: e023 b.n 800b734 <__ieee754_rem_pio2+0x6c> + 800b6ec: 4abb ldr r2, [pc, #748] ; (800b9dc <__ieee754_rem_pio2+0x314>) + 800b6ee: 4592 cmp sl, r2 + 800b6f0: dc71 bgt.n 800b7d6 <__ieee754_rem_pio2+0x10e> + 800b6f2: a3ab add r3, pc, #684 ; (adr r3, 800b9a0 <__ieee754_rem_pio2+0x2d8>) + 800b6f4: e9d3 2300 ldrd r2, r3, [r3] + 800b6f8: 2900 cmp r1, #0 + 800b6fa: 4db9 ldr r5, [pc, #740] ; (800b9e0 <__ieee754_rem_pio2+0x318>) + 800b6fc: dd36 ble.n 800b76c <__ieee754_rem_pio2+0xa4> + 800b6fe: f7f4 fd2b bl 8000158 <__aeabi_dsub> + 800b702: 45aa cmp sl, r5 + 800b704: 4606 mov r6, r0 + 800b706: 460f mov r7, r1 + 800b708: d018 beq.n 800b73c <__ieee754_rem_pio2+0x74> + 800b70a: a3a7 add r3, pc, #668 ; (adr r3, 800b9a8 <__ieee754_rem_pio2+0x2e0>) + 800b70c: e9d3 2300 ldrd r2, r3, [r3] + 800b710: f7f4 fd22 bl 8000158 <__aeabi_dsub> + 800b714: 4602 mov r2, r0 + 800b716: 460b mov r3, r1 + 800b718: 4630 mov r0, r6 + 800b71a: e9c4 2300 strd r2, r3, [r4] + 800b71e: 4639 mov r1, r7 + 800b720: f7f4 fd1a bl 8000158 <__aeabi_dsub> + 800b724: a3a0 add r3, pc, #640 ; (adr r3, 800b9a8 <__ieee754_rem_pio2+0x2e0>) + 800b726: e9d3 2300 ldrd r2, r3, [r3] + 800b72a: f7f4 fd15 bl 8000158 <__aeabi_dsub> + 800b72e: 2501 movs r5, #1 + 800b730: e9c4 0102 strd r0, r1, [r4, #8] + 800b734: 4628 mov r0, r5 + 800b736: b00d add sp, #52 ; 0x34 + 800b738: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800b73c: a39c add r3, pc, #624 ; (adr r3, 800b9b0 <__ieee754_rem_pio2+0x2e8>) + 800b73e: e9d3 2300 ldrd r2, r3, [r3] + 800b742: f7f4 fd09 bl 8000158 <__aeabi_dsub> + 800b746: a39c add r3, pc, #624 ; (adr r3, 800b9b8 <__ieee754_rem_pio2+0x2f0>) + 800b748: e9d3 2300 ldrd r2, r3, [r3] + 800b74c: 4606 mov r6, r0 + 800b74e: 460f mov r7, r1 + 800b750: f7f4 fd02 bl 8000158 <__aeabi_dsub> + 800b754: 4602 mov r2, r0 + 800b756: 460b mov r3, r1 + 800b758: 4630 mov r0, r6 + 800b75a: e9c4 2300 strd r2, r3, [r4] + 800b75e: 4639 mov r1, r7 + 800b760: f7f4 fcfa bl 8000158 <__aeabi_dsub> + 800b764: a394 add r3, pc, #592 ; (adr r3, 800b9b8 <__ieee754_rem_pio2+0x2f0>) + 800b766: e9d3 2300 ldrd r2, r3, [r3] + 800b76a: e7de b.n 800b72a <__ieee754_rem_pio2+0x62> + 800b76c: f7f4 fcf6 bl 800015c <__adddf3> + 800b770: 45aa cmp sl, r5 + 800b772: 4606 mov r6, r0 + 800b774: 460f mov r7, r1 + 800b776: d016 beq.n 800b7a6 <__ieee754_rem_pio2+0xde> + 800b778: a38b add r3, pc, #556 ; (adr r3, 800b9a8 <__ieee754_rem_pio2+0x2e0>) + 800b77a: e9d3 2300 ldrd r2, r3, [r3] + 800b77e: f7f4 fced bl 800015c <__adddf3> + 800b782: 4602 mov r2, r0 + 800b784: 460b mov r3, r1 + 800b786: 4630 mov r0, r6 + 800b788: e9c4 2300 strd r2, r3, [r4] + 800b78c: 4639 mov r1, r7 + 800b78e: f7f4 fce3 bl 8000158 <__aeabi_dsub> + 800b792: a385 add r3, pc, #532 ; (adr r3, 800b9a8 <__ieee754_rem_pio2+0x2e0>) + 800b794: e9d3 2300 ldrd r2, r3, [r3] + 800b798: f7f4 fce0 bl 800015c <__adddf3> + 800b79c: f04f 35ff mov.w r5, #4294967295 ; 0xffffffff + 800b7a0: e9c4 0102 strd r0, r1, [r4, #8] + 800b7a4: e7c6 b.n 800b734 <__ieee754_rem_pio2+0x6c> + 800b7a6: a382 add r3, pc, #520 ; (adr r3, 800b9b0 <__ieee754_rem_pio2+0x2e8>) + 800b7a8: e9d3 2300 ldrd r2, r3, [r3] + 800b7ac: f7f4 fcd6 bl 800015c <__adddf3> + 800b7b0: a381 add r3, pc, #516 ; (adr r3, 800b9b8 <__ieee754_rem_pio2+0x2f0>) + 800b7b2: e9d3 2300 ldrd r2, r3, [r3] + 800b7b6: 4606 mov r6, r0 + 800b7b8: 460f mov r7, r1 + 800b7ba: f7f4 fccf bl 800015c <__adddf3> + 800b7be: 4602 mov r2, r0 + 800b7c0: 460b mov r3, r1 + 800b7c2: 4630 mov r0, r6 + 800b7c4: e9c4 2300 strd r2, r3, [r4] + 800b7c8: 4639 mov r1, r7 + 800b7ca: f7f4 fcc5 bl 8000158 <__aeabi_dsub> + 800b7ce: a37a add r3, pc, #488 ; (adr r3, 800b9b8 <__ieee754_rem_pio2+0x2f0>) + 800b7d0: e9d3 2300 ldrd r2, r3, [r3] + 800b7d4: e7e0 b.n 800b798 <__ieee754_rem_pio2+0xd0> + 800b7d6: 4a83 ldr r2, [pc, #524] ; (800b9e4 <__ieee754_rem_pio2+0x31c>) + 800b7d8: 4592 cmp sl, r2 + 800b7da: f300 80d2 bgt.w 800b982 <__ieee754_rem_pio2+0x2ba> + 800b7de: f000 fe21 bl 800c424 + 800b7e2: a377 add r3, pc, #476 ; (adr r3, 800b9c0 <__ieee754_rem_pio2+0x2f8>) + 800b7e4: e9d3 2300 ldrd r2, r3, [r3] + 800b7e8: 4606 mov r6, r0 + 800b7ea: 460f mov r7, r1 + 800b7ec: f7f4 fe6c bl 80004c8 <__aeabi_dmul> + 800b7f0: 2200 movs r2, #0 + 800b7f2: 4b7d ldr r3, [pc, #500] ; (800b9e8 <__ieee754_rem_pio2+0x320>) + 800b7f4: f7f4 fcb2 bl 800015c <__adddf3> + 800b7f8: f7f5 f900 bl 80009fc <__aeabi_d2iz> + 800b7fc: 4605 mov r5, r0 + 800b7fe: f7f4 fdf9 bl 80003f4 <__aeabi_i2d> + 800b802: a367 add r3, pc, #412 ; (adr r3, 800b9a0 <__ieee754_rem_pio2+0x2d8>) + 800b804: e9d3 2300 ldrd r2, r3, [r3] + 800b808: e9cd 0102 strd r0, r1, [sp, #8] + 800b80c: f7f4 fe5c bl 80004c8 <__aeabi_dmul> + 800b810: 4602 mov r2, r0 + 800b812: 460b mov r3, r1 + 800b814: 4630 mov r0, r6 + 800b816: 4639 mov r1, r7 + 800b818: f7f4 fc9e bl 8000158 <__aeabi_dsub> + 800b81c: a362 add r3, pc, #392 ; (adr r3, 800b9a8 <__ieee754_rem_pio2+0x2e0>) + 800b81e: e9d3 2300 ldrd r2, r3, [r3] + 800b822: 4606 mov r6, r0 + 800b824: 460f mov r7, r1 + 800b826: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b82a: f7f4 fe4d bl 80004c8 <__aeabi_dmul> + 800b82e: 2d1f cmp r5, #31 + 800b830: 4680 mov r8, r0 + 800b832: 4689 mov r9, r1 + 800b834: dc0e bgt.n 800b854 <__ieee754_rem_pio2+0x18c> + 800b836: 4b6d ldr r3, [pc, #436] ; (800b9ec <__ieee754_rem_pio2+0x324>) + 800b838: 1e6a subs r2, r5, #1 + 800b83a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800b83e: 4553 cmp r3, sl + 800b840: d008 beq.n 800b854 <__ieee754_rem_pio2+0x18c> + 800b842: 4642 mov r2, r8 + 800b844: 464b mov r3, r9 + 800b846: 4630 mov r0, r6 + 800b848: 4639 mov r1, r7 + 800b84a: f7f4 fc85 bl 8000158 <__aeabi_dsub> + 800b84e: e9c4 0100 strd r0, r1, [r4] + 800b852: e011 b.n 800b878 <__ieee754_rem_pio2+0x1b0> + 800b854: 464b mov r3, r9 + 800b856: 4642 mov r2, r8 + 800b858: 4630 mov r0, r6 + 800b85a: 4639 mov r1, r7 + 800b85c: f7f4 fc7c bl 8000158 <__aeabi_dsub> + 800b860: ea4f 5a2a mov.w sl, sl, asr #20 + 800b864: f3c1 530a ubfx r3, r1, #20, #11 + 800b868: ebaa 0303 sub.w r3, sl, r3 + 800b86c: 2b10 cmp r3, #16 + 800b86e: dc1f bgt.n 800b8b0 <__ieee754_rem_pio2+0x1e8> + 800b870: 4602 mov r2, r0 + 800b872: 460b mov r3, r1 + 800b874: e9c4 2300 strd r2, r3, [r4] + 800b878: e9d4 2a00 ldrd r2, sl, [r4] + 800b87c: 4630 mov r0, r6 + 800b87e: 4653 mov r3, sl + 800b880: 4639 mov r1, r7 + 800b882: f7f4 fc69 bl 8000158 <__aeabi_dsub> + 800b886: 4642 mov r2, r8 + 800b888: 464b mov r3, r9 + 800b88a: f7f4 fc65 bl 8000158 <__aeabi_dsub> + 800b88e: 4602 mov r2, r0 + 800b890: 460b mov r3, r1 + 800b892: f1bb 0f00 cmp.w fp, #0 + 800b896: e9c4 2302 strd r2, r3, [r4, #8] + 800b89a: f6bf af4b bge.w 800b734 <__ieee754_rem_pio2+0x6c> + 800b89e: f10a 4300 add.w r3, sl, #2147483648 ; 0x80000000 + 800b8a2: e9c4 3001 strd r3, r0, [r4, #4] + 800b8a6: f101 4100 add.w r1, r1, #2147483648 ; 0x80000000 + 800b8aa: 60e1 str r1, [r4, #12] + 800b8ac: 426d negs r5, r5 + 800b8ae: e741 b.n 800b734 <__ieee754_rem_pio2+0x6c> + 800b8b0: a33f add r3, pc, #252 ; (adr r3, 800b9b0 <__ieee754_rem_pio2+0x2e8>) + 800b8b2: e9d3 2300 ldrd r2, r3, [r3] + 800b8b6: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b8ba: f7f4 fe05 bl 80004c8 <__aeabi_dmul> + 800b8be: 4680 mov r8, r0 + 800b8c0: 4689 mov r9, r1 + 800b8c2: 4602 mov r2, r0 + 800b8c4: 460b mov r3, r1 + 800b8c6: 4630 mov r0, r6 + 800b8c8: 4639 mov r1, r7 + 800b8ca: f7f4 fc45 bl 8000158 <__aeabi_dsub> + 800b8ce: e9cd 0104 strd r0, r1, [sp, #16] + 800b8d2: 4602 mov r2, r0 + 800b8d4: 460b mov r3, r1 + 800b8d6: 4630 mov r0, r6 + 800b8d8: 4639 mov r1, r7 + 800b8da: f7f4 fc3d bl 8000158 <__aeabi_dsub> + 800b8de: 4642 mov r2, r8 + 800b8e0: 464b mov r3, r9 + 800b8e2: f7f4 fc39 bl 8000158 <__aeabi_dsub> + 800b8e6: a334 add r3, pc, #208 ; (adr r3, 800b9b8 <__ieee754_rem_pio2+0x2f0>) + 800b8e8: e9d3 2300 ldrd r2, r3, [r3] + 800b8ec: 4606 mov r6, r0 + 800b8ee: 460f mov r7, r1 + 800b8f0: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b8f4: f7f4 fde8 bl 80004c8 <__aeabi_dmul> + 800b8f8: 4632 mov r2, r6 + 800b8fa: 463b mov r3, r7 + 800b8fc: f7f4 fc2c bl 8000158 <__aeabi_dsub> + 800b900: 460b mov r3, r1 + 800b902: 4602 mov r2, r0 + 800b904: 4680 mov r8, r0 + 800b906: 4689 mov r9, r1 + 800b908: e9dd 0104 ldrd r0, r1, [sp, #16] + 800b90c: f7f4 fc24 bl 8000158 <__aeabi_dsub> + 800b910: f3c1 530a ubfx r3, r1, #20, #11 + 800b914: ebaa 0a03 sub.w sl, sl, r3 + 800b918: f1ba 0f31 cmp.w sl, #49 ; 0x31 + 800b91c: dc06 bgt.n 800b92c <__ieee754_rem_pio2+0x264> + 800b91e: e9dd 6704 ldrd r6, r7, [sp, #16] + 800b922: 4602 mov r2, r0 + 800b924: 460b mov r3, r1 + 800b926: e9c4 2300 strd r2, r3, [r4] + 800b92a: e7a5 b.n 800b878 <__ieee754_rem_pio2+0x1b0> + 800b92c: a326 add r3, pc, #152 ; (adr r3, 800b9c8 <__ieee754_rem_pio2+0x300>) + 800b92e: e9d3 2300 ldrd r2, r3, [r3] + 800b932: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b936: f7f4 fdc7 bl 80004c8 <__aeabi_dmul> + 800b93a: 4680 mov r8, r0 + 800b93c: 4689 mov r9, r1 + 800b93e: 4602 mov r2, r0 + 800b940: 460b mov r3, r1 + 800b942: e9dd 0104 ldrd r0, r1, [sp, #16] + 800b946: f7f4 fc07 bl 8000158 <__aeabi_dsub> + 800b94a: 4602 mov r2, r0 + 800b94c: 460b mov r3, r1 + 800b94e: 4606 mov r6, r0 + 800b950: 460f mov r7, r1 + 800b952: e9dd 0104 ldrd r0, r1, [sp, #16] + 800b956: f7f4 fbff bl 8000158 <__aeabi_dsub> + 800b95a: 4642 mov r2, r8 + 800b95c: 464b mov r3, r9 + 800b95e: f7f4 fbfb bl 8000158 <__aeabi_dsub> + 800b962: a31b add r3, pc, #108 ; (adr r3, 800b9d0 <__ieee754_rem_pio2+0x308>) + 800b964: e9d3 2300 ldrd r2, r3, [r3] + 800b968: 4680 mov r8, r0 + 800b96a: 4689 mov r9, r1 + 800b96c: e9dd 0102 ldrd r0, r1, [sp, #8] + 800b970: f7f4 fdaa bl 80004c8 <__aeabi_dmul> + 800b974: 4642 mov r2, r8 + 800b976: 464b mov r3, r9 + 800b978: f7f4 fbee bl 8000158 <__aeabi_dsub> + 800b97c: 4680 mov r8, r0 + 800b97e: 4689 mov r9, r1 + 800b980: e75f b.n 800b842 <__ieee754_rem_pio2+0x17a> + 800b982: 4a1b ldr r2, [pc, #108] ; (800b9f0 <__ieee754_rem_pio2+0x328>) + 800b984: 4592 cmp sl, r2 + 800b986: dd35 ble.n 800b9f4 <__ieee754_rem_pio2+0x32c> + 800b988: 4602 mov r2, r0 + 800b98a: 460b mov r3, r1 + 800b98c: f7f4 fbe4 bl 8000158 <__aeabi_dsub> + 800b990: e9c4 0102 strd r0, r1, [r4, #8] + 800b994: e9c4 0100 strd r0, r1, [r4] + 800b998: e6a6 b.n 800b6e8 <__ieee754_rem_pio2+0x20> + 800b99a: bf00 nop + 800b99c: f3af 8000 nop.w + 800b9a0: 54400000 .word 0x54400000 + 800b9a4: 3ff921fb .word 0x3ff921fb + 800b9a8: 1a626331 .word 0x1a626331 + 800b9ac: 3dd0b461 .word 0x3dd0b461 + 800b9b0: 1a600000 .word 0x1a600000 + 800b9b4: 3dd0b461 .word 0x3dd0b461 + 800b9b8: 2e037073 .word 0x2e037073 + 800b9bc: 3ba3198a .word 0x3ba3198a + 800b9c0: 6dc9c883 .word 0x6dc9c883 + 800b9c4: 3fe45f30 .word 0x3fe45f30 + 800b9c8: 2e000000 .word 0x2e000000 + 800b9cc: 3ba3198a .word 0x3ba3198a + 800b9d0: 252049c1 .word 0x252049c1 + 800b9d4: 397b839a .word 0x397b839a + 800b9d8: 3fe921fb .word 0x3fe921fb + 800b9dc: 4002d97b .word 0x4002d97b + 800b9e0: 3ff921fb .word 0x3ff921fb + 800b9e4: 413921fb .word 0x413921fb + 800b9e8: 3fe00000 .word 0x3fe00000 + 800b9ec: 0800f054 .word 0x0800f054 + 800b9f0: 7fefffff .word 0x7fefffff + 800b9f4: ea4f 552a mov.w r5, sl, asr #20 + 800b9f8: f2a5 4516 subw r5, r5, #1046 ; 0x416 + 800b9fc: ebaa 5105 sub.w r1, sl, r5, lsl #20 + 800ba00: 460f mov r7, r1 + 800ba02: 4606 mov r6, r0 + 800ba04: f7f4 fffa bl 80009fc <__aeabi_d2iz> + 800ba08: f7f4 fcf4 bl 80003f4 <__aeabi_i2d> + 800ba0c: 4602 mov r2, r0 + 800ba0e: 460b mov r3, r1 + 800ba10: 4630 mov r0, r6 + 800ba12: 4639 mov r1, r7 + 800ba14: e9cd 2306 strd r2, r3, [sp, #24] + 800ba18: f7f4 fb9e bl 8000158 <__aeabi_dsub> + 800ba1c: 2200 movs r2, #0 + 800ba1e: 4b20 ldr r3, [pc, #128] ; (800baa0 <__ieee754_rem_pio2+0x3d8>) + 800ba20: f7f4 fd52 bl 80004c8 <__aeabi_dmul> + 800ba24: 460f mov r7, r1 + 800ba26: 4606 mov r6, r0 + 800ba28: f7f4 ffe8 bl 80009fc <__aeabi_d2iz> + 800ba2c: f7f4 fce2 bl 80003f4 <__aeabi_i2d> + 800ba30: 4602 mov r2, r0 + 800ba32: 460b mov r3, r1 + 800ba34: 4630 mov r0, r6 + 800ba36: 4639 mov r1, r7 + 800ba38: e9cd 2308 strd r2, r3, [sp, #32] + 800ba3c: f7f4 fb8c bl 8000158 <__aeabi_dsub> + 800ba40: 2200 movs r2, #0 + 800ba42: 4b17 ldr r3, [pc, #92] ; (800baa0 <__ieee754_rem_pio2+0x3d8>) + 800ba44: f7f4 fd40 bl 80004c8 <__aeabi_dmul> + 800ba48: f04f 0803 mov.w r8, #3 + 800ba4c: 2600 movs r6, #0 + 800ba4e: 2700 movs r7, #0 + 800ba50: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 + 800ba54: f10d 0930 add.w r9, sp, #48 ; 0x30 + 800ba58: 4632 mov r2, r6 + 800ba5a: e979 0102 ldrd r0, r1, [r9, #-8]! + 800ba5e: 463b mov r3, r7 + 800ba60: f108 3aff add.w sl, r8, #4294967295 ; 0xffffffff + 800ba64: f7f4 ff98 bl 8000998 <__aeabi_dcmpeq> + 800ba68: b9b8 cbnz r0, 800ba9a <__ieee754_rem_pio2+0x3d2> + 800ba6a: 4b0e ldr r3, [pc, #56] ; (800baa4 <__ieee754_rem_pio2+0x3dc>) + 800ba6c: 462a mov r2, r5 + 800ba6e: 9301 str r3, [sp, #4] + 800ba70: 2302 movs r3, #2 + 800ba72: 4621 mov r1, r4 + 800ba74: 9300 str r3, [sp, #0] + 800ba76: a806 add r0, sp, #24 + 800ba78: 4643 mov r3, r8 + 800ba7a: f000 f8d3 bl 800bc24 <__kernel_rem_pio2> + 800ba7e: f1bb 0f00 cmp.w fp, #0 + 800ba82: 4605 mov r5, r0 + 800ba84: f6bf ae56 bge.w 800b734 <__ieee754_rem_pio2+0x6c> + 800ba88: 6863 ldr r3, [r4, #4] + 800ba8a: f103 4300 add.w r3, r3, #2147483648 ; 0x80000000 + 800ba8e: 6063 str r3, [r4, #4] + 800ba90: 68e3 ldr r3, [r4, #12] + 800ba92: f103 4300 add.w r3, r3, #2147483648 ; 0x80000000 + 800ba96: 60e3 str r3, [r4, #12] + 800ba98: e708 b.n 800b8ac <__ieee754_rem_pio2+0x1e4> + 800ba9a: 46d0 mov r8, sl + 800ba9c: e7dc b.n 800ba58 <__ieee754_rem_pio2+0x390> + 800ba9e: bf00 nop + 800baa0: 41700000 .word 0x41700000 + 800baa4: 0800f0d4 .word 0x0800f0d4 + +0800baa8 <__kernel_cos>: + 800baa8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800baac: f021 4600 bic.w r6, r1, #2147483648 ; 0x80000000 + 800bab0: f1b6 5f79 cmp.w r6, #1044381696 ; 0x3e400000 + 800bab4: 4680 mov r8, r0 + 800bab6: 460f mov r7, r1 + 800bab8: e9cd 2300 strd r2, r3, [sp] + 800babc: da04 bge.n 800bac8 <__kernel_cos+0x20> + 800babe: f7f4 ff9d bl 80009fc <__aeabi_d2iz> + 800bac2: 2800 cmp r0, #0 + 800bac4: f000 8086 beq.w 800bbd4 <__kernel_cos+0x12c> + 800bac8: 4642 mov r2, r8 + 800baca: 463b mov r3, r7 + 800bacc: 4640 mov r0, r8 + 800bace: 4639 mov r1, r7 + 800bad0: f7f4 fcfa bl 80004c8 <__aeabi_dmul> + 800bad4: 2200 movs r2, #0 + 800bad6: 4b4e ldr r3, [pc, #312] ; (800bc10 <__kernel_cos+0x168>) + 800bad8: 4604 mov r4, r0 + 800bada: 460d mov r5, r1 + 800badc: f7f4 fcf4 bl 80004c8 <__aeabi_dmul> + 800bae0: a33f add r3, pc, #252 ; (adr r3, 800bbe0 <__kernel_cos+0x138>) + 800bae2: e9d3 2300 ldrd r2, r3, [r3] + 800bae6: 4682 mov sl, r0 + 800bae8: 468b mov fp, r1 + 800baea: 4620 mov r0, r4 + 800baec: 4629 mov r1, r5 + 800baee: f7f4 fceb bl 80004c8 <__aeabi_dmul> + 800baf2: a33d add r3, pc, #244 ; (adr r3, 800bbe8 <__kernel_cos+0x140>) + 800baf4: e9d3 2300 ldrd r2, r3, [r3] + 800baf8: f7f4 fb30 bl 800015c <__adddf3> + 800bafc: 4622 mov r2, r4 + 800bafe: 462b mov r3, r5 + 800bb00: f7f4 fce2 bl 80004c8 <__aeabi_dmul> + 800bb04: a33a add r3, pc, #232 ; (adr r3, 800bbf0 <__kernel_cos+0x148>) + 800bb06: e9d3 2300 ldrd r2, r3, [r3] + 800bb0a: f7f4 fb25 bl 8000158 <__aeabi_dsub> + 800bb0e: 4622 mov r2, r4 + 800bb10: 462b mov r3, r5 + 800bb12: f7f4 fcd9 bl 80004c8 <__aeabi_dmul> + 800bb16: a338 add r3, pc, #224 ; (adr r3, 800bbf8 <__kernel_cos+0x150>) + 800bb18: e9d3 2300 ldrd r2, r3, [r3] + 800bb1c: f7f4 fb1e bl 800015c <__adddf3> + 800bb20: 4622 mov r2, r4 + 800bb22: 462b mov r3, r5 + 800bb24: f7f4 fcd0 bl 80004c8 <__aeabi_dmul> + 800bb28: a335 add r3, pc, #212 ; (adr r3, 800bc00 <__kernel_cos+0x158>) + 800bb2a: e9d3 2300 ldrd r2, r3, [r3] + 800bb2e: f7f4 fb13 bl 8000158 <__aeabi_dsub> + 800bb32: 4622 mov r2, r4 + 800bb34: 462b mov r3, r5 + 800bb36: f7f4 fcc7 bl 80004c8 <__aeabi_dmul> + 800bb3a: a333 add r3, pc, #204 ; (adr r3, 800bc08 <__kernel_cos+0x160>) + 800bb3c: e9d3 2300 ldrd r2, r3, [r3] + 800bb40: f7f4 fb0c bl 800015c <__adddf3> + 800bb44: 4622 mov r2, r4 + 800bb46: 462b mov r3, r5 + 800bb48: f7f4 fcbe bl 80004c8 <__aeabi_dmul> + 800bb4c: 4622 mov r2, r4 + 800bb4e: 462b mov r3, r5 + 800bb50: f7f4 fcba bl 80004c8 <__aeabi_dmul> + 800bb54: e9dd 2300 ldrd r2, r3, [sp] + 800bb58: 4604 mov r4, r0 + 800bb5a: 460d mov r5, r1 + 800bb5c: 4640 mov r0, r8 + 800bb5e: 4639 mov r1, r7 + 800bb60: f7f4 fcb2 bl 80004c8 <__aeabi_dmul> + 800bb64: 460b mov r3, r1 + 800bb66: 4602 mov r2, r0 + 800bb68: 4629 mov r1, r5 + 800bb6a: 4620 mov r0, r4 + 800bb6c: f7f4 faf4 bl 8000158 <__aeabi_dsub> + 800bb70: 4b28 ldr r3, [pc, #160] ; (800bc14 <__kernel_cos+0x16c>) + 800bb72: 4680 mov r8, r0 + 800bb74: 429e cmp r6, r3 + 800bb76: 4689 mov r9, r1 + 800bb78: dc0e bgt.n 800bb98 <__kernel_cos+0xf0> + 800bb7a: 4602 mov r2, r0 + 800bb7c: 460b mov r3, r1 + 800bb7e: 4650 mov r0, sl + 800bb80: 4659 mov r1, fp + 800bb82: f7f4 fae9 bl 8000158 <__aeabi_dsub> + 800bb86: 4602 mov r2, r0 + 800bb88: 2000 movs r0, #0 + 800bb8a: 460b mov r3, r1 + 800bb8c: 4922 ldr r1, [pc, #136] ; (800bc18 <__kernel_cos+0x170>) + 800bb8e: f7f4 fae3 bl 8000158 <__aeabi_dsub> + 800bb92: b003 add sp, #12 + 800bb94: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800bb98: 2400 movs r4, #0 + 800bb9a: 4b20 ldr r3, [pc, #128] ; (800bc1c <__kernel_cos+0x174>) + 800bb9c: 4622 mov r2, r4 + 800bb9e: 429e cmp r6, r3 + 800bba0: bfcc ite gt + 800bba2: 4d1f ldrgt r5, [pc, #124] ; (800bc20 <__kernel_cos+0x178>) + 800bba4: f5a6 1500 suble.w r5, r6, #2097152 ; 0x200000 + 800bba8: 462b mov r3, r5 + 800bbaa: 2000 movs r0, #0 + 800bbac: 491a ldr r1, [pc, #104] ; (800bc18 <__kernel_cos+0x170>) + 800bbae: f7f4 fad3 bl 8000158 <__aeabi_dsub> + 800bbb2: 4622 mov r2, r4 + 800bbb4: 4606 mov r6, r0 + 800bbb6: 460f mov r7, r1 + 800bbb8: 462b mov r3, r5 + 800bbba: 4650 mov r0, sl + 800bbbc: 4659 mov r1, fp + 800bbbe: f7f4 facb bl 8000158 <__aeabi_dsub> + 800bbc2: 4642 mov r2, r8 + 800bbc4: 464b mov r3, r9 + 800bbc6: f7f4 fac7 bl 8000158 <__aeabi_dsub> + 800bbca: 4602 mov r2, r0 + 800bbcc: 460b mov r3, r1 + 800bbce: 4630 mov r0, r6 + 800bbd0: 4639 mov r1, r7 + 800bbd2: e7dc b.n 800bb8e <__kernel_cos+0xe6> + 800bbd4: 2000 movs r0, #0 + 800bbd6: 4910 ldr r1, [pc, #64] ; (800bc18 <__kernel_cos+0x170>) + 800bbd8: e7db b.n 800bb92 <__kernel_cos+0xea> + 800bbda: bf00 nop + 800bbdc: f3af 8000 nop.w + 800bbe0: be8838d4 .word 0xbe8838d4 + 800bbe4: bda8fae9 .word 0xbda8fae9 + 800bbe8: bdb4b1c4 .word 0xbdb4b1c4 + 800bbec: 3e21ee9e .word 0x3e21ee9e + 800bbf0: 809c52ad .word 0x809c52ad + 800bbf4: 3e927e4f .word 0x3e927e4f + 800bbf8: 19cb1590 .word 0x19cb1590 + 800bbfc: 3efa01a0 .word 0x3efa01a0 + 800bc00: 16c15177 .word 0x16c15177 + 800bc04: 3f56c16c .word 0x3f56c16c + 800bc08: 5555554c .word 0x5555554c + 800bc0c: 3fa55555 .word 0x3fa55555 + 800bc10: 3fe00000 .word 0x3fe00000 + 800bc14: 3fd33332 .word 0x3fd33332 + 800bc18: 3ff00000 .word 0x3ff00000 + 800bc1c: 3fe90000 .word 0x3fe90000 + 800bc20: 3fd20000 .word 0x3fd20000 + +0800bc24 <__kernel_rem_pio2>: + 800bc24: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800bc28: f5ad 7d19 sub.w sp, sp, #612 ; 0x264 + 800bc2c: 9307 str r3, [sp, #28] + 800bc2e: 9104 str r1, [sp, #16] + 800bc30: 4bbf ldr r3, [pc, #764] ; (800bf30 <__kernel_rem_pio2+0x30c>) + 800bc32: 99a2 ldr r1, [sp, #648] ; 0x288 + 800bc34: 1ed4 subs r4, r2, #3 + 800bc36: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 800bc3a: 2500 movs r5, #0 + 800bc3c: 9302 str r3, [sp, #8] + 800bc3e: 9b07 ldr r3, [sp, #28] + 800bc40: 9008 str r0, [sp, #32] + 800bc42: 3b01 subs r3, #1 + 800bc44: 9306 str r3, [sp, #24] + 800bc46: 2318 movs r3, #24 + 800bc48: fb94 f4f3 sdiv r4, r4, r3 + 800bc4c: f06f 0317 mvn.w r3, #23 + 800bc50: ea24 74e4 bic.w r4, r4, r4, asr #31 + 800bc54: fb04 3303 mla r3, r4, r3, r3 + 800bc58: eb03 0a02 add.w sl, r3, r2 + 800bc5c: 9a06 ldr r2, [sp, #24] + 800bc5e: 9b02 ldr r3, [sp, #8] + 800bc60: 1aa7 subs r7, r4, r2 + 800bc62: eb03 0802 add.w r8, r3, r2 + 800bc66: 9ba3 ldr r3, [sp, #652] ; 0x28c + 800bc68: 2200 movs r2, #0 + 800bc6a: eb03 0987 add.w r9, r3, r7, lsl #2 + 800bc6e: 2300 movs r3, #0 + 800bc70: ae1e add r6, sp, #120 ; 0x78 + 800bc72: 4545 cmp r5, r8 + 800bc74: dd14 ble.n 800bca0 <__kernel_rem_pio2+0x7c> + 800bc76: 2600 movs r6, #0 + 800bc78: f50d 7bdc add.w fp, sp, #440 ; 0x1b8 + 800bc7c: 9b02 ldr r3, [sp, #8] + 800bc7e: 429e cmp r6, r3 + 800bc80: dc39 bgt.n 800bcf6 <__kernel_rem_pio2+0xd2> + 800bc82: 9b08 ldr r3, [sp, #32] + 800bc84: f04f 0800 mov.w r8, #0 + 800bc88: 3b08 subs r3, #8 + 800bc8a: 9300 str r3, [sp, #0] + 800bc8c: 9b07 ldr r3, [sp, #28] + 800bc8e: f04f 0900 mov.w r9, #0 + 800bc92: 199d adds r5, r3, r6 + 800bc94: ab20 add r3, sp, #128 ; 0x80 + 800bc96: eb03 03c5 add.w r3, r3, r5, lsl #3 + 800bc9a: 9305 str r3, [sp, #20] + 800bc9c: 2700 movs r7, #0 + 800bc9e: e023 b.n 800bce8 <__kernel_rem_pio2+0xc4> + 800bca0: 42ef cmn r7, r5 + 800bca2: d40b bmi.n 800bcbc <__kernel_rem_pio2+0x98> + 800bca4: f859 0025 ldr.w r0, [r9, r5, lsl #2] + 800bca8: e9cd 2300 strd r2, r3, [sp] + 800bcac: f7f4 fba2 bl 80003f4 <__aeabi_i2d> + 800bcb0: e9dd 2300 ldrd r2, r3, [sp] + 800bcb4: e9e6 0102 strd r0, r1, [r6, #8]! + 800bcb8: 3501 adds r5, #1 + 800bcba: e7da b.n 800bc72 <__kernel_rem_pio2+0x4e> + 800bcbc: 4610 mov r0, r2 + 800bcbe: 4619 mov r1, r3 + 800bcc0: e7f8 b.n 800bcb4 <__kernel_rem_pio2+0x90> + 800bcc2: 9905 ldr r1, [sp, #20] + 800bcc4: 9d00 ldr r5, [sp, #0] + 800bcc6: e971 2302 ldrd r2, r3, [r1, #-8]! + 800bcca: 9105 str r1, [sp, #20] + 800bccc: e9f5 0102 ldrd r0, r1, [r5, #8]! + 800bcd0: 9500 str r5, [sp, #0] + 800bcd2: f7f4 fbf9 bl 80004c8 <__aeabi_dmul> + 800bcd6: 4602 mov r2, r0 + 800bcd8: 460b mov r3, r1 + 800bcda: 4640 mov r0, r8 + 800bcdc: 4649 mov r1, r9 + 800bcde: f7f4 fa3d bl 800015c <__adddf3> + 800bce2: 4680 mov r8, r0 + 800bce4: 4689 mov r9, r1 + 800bce6: 3701 adds r7, #1 + 800bce8: 9b06 ldr r3, [sp, #24] + 800bcea: 429f cmp r7, r3 + 800bcec: dde9 ble.n 800bcc2 <__kernel_rem_pio2+0x9e> + 800bcee: e9eb 8902 strd r8, r9, [fp, #8]! + 800bcf2: 3601 adds r6, #1 + 800bcf4: e7c2 b.n 800bc7c <__kernel_rem_pio2+0x58> + 800bcf6: 9b02 ldr r3, [sp, #8] + 800bcf8: aa0c add r2, sp, #48 ; 0x30 + 800bcfa: eb02 0383 add.w r3, r2, r3, lsl #2 + 800bcfe: 930b str r3, [sp, #44] ; 0x2c + 800bd00: 9ba3 ldr r3, [sp, #652] ; 0x28c + 800bd02: 9f02 ldr r7, [sp, #8] + 800bd04: eb03 0384 add.w r3, r3, r4, lsl #2 + 800bd08: 930a str r3, [sp, #40] ; 0x28 + 800bd0a: 2600 movs r6, #0 + 800bd0c: ab98 add r3, sp, #608 ; 0x260 + 800bd0e: f107 5b00 add.w fp, r7, #536870912 ; 0x20000000 + 800bd12: eb03 03c7 add.w r3, r3, r7, lsl #3 + 800bd16: f10b 3bff add.w fp, fp, #4294967295 ; 0xffffffff + 800bd1a: e953 8928 ldrd r8, r9, [r3, #-160] ; 0xa0 + 800bd1e: ea4f 0bcb mov.w fp, fp, lsl #3 + 800bd22: ab98 add r3, sp, #608 ; 0x260 + 800bd24: 445b add r3, fp + 800bd26: f1a3 0498 sub.w r4, r3, #152 ; 0x98 + 800bd2a: 1bbb subs r3, r7, r6 + 800bd2c: 2b00 cmp r3, #0 + 800bd2e: dc71 bgt.n 800be14 <__kernel_rem_pio2+0x1f0> + 800bd30: 4652 mov r2, sl + 800bd32: 4640 mov r0, r8 + 800bd34: 4649 mov r1, r9 + 800bd36: f000 fbff bl 800c538 + 800bd3a: 2200 movs r2, #0 + 800bd3c: f04f 537f mov.w r3, #1069547520 ; 0x3fc00000 + 800bd40: 4604 mov r4, r0 + 800bd42: 460d mov r5, r1 + 800bd44: f7f4 fbc0 bl 80004c8 <__aeabi_dmul> + 800bd48: f000 fb72 bl 800c430 + 800bd4c: 2200 movs r2, #0 + 800bd4e: 4b79 ldr r3, [pc, #484] ; (800bf34 <__kernel_rem_pio2+0x310>) + 800bd50: f7f4 fbba bl 80004c8 <__aeabi_dmul> + 800bd54: 4602 mov r2, r0 + 800bd56: 460b mov r3, r1 + 800bd58: 4620 mov r0, r4 + 800bd5a: 4629 mov r1, r5 + 800bd5c: f7f4 f9fc bl 8000158 <__aeabi_dsub> + 800bd60: 460d mov r5, r1 + 800bd62: 4604 mov r4, r0 + 800bd64: f7f4 fe4a bl 80009fc <__aeabi_d2iz> + 800bd68: 9005 str r0, [sp, #20] + 800bd6a: f7f4 fb43 bl 80003f4 <__aeabi_i2d> + 800bd6e: 4602 mov r2, r0 + 800bd70: 460b mov r3, r1 + 800bd72: 4620 mov r0, r4 + 800bd74: 4629 mov r1, r5 + 800bd76: f7f4 f9ef bl 8000158 <__aeabi_dsub> + 800bd7a: f1ba 0f00 cmp.w sl, #0 + 800bd7e: 4680 mov r8, r0 + 800bd80: 4689 mov r9, r1 + 800bd82: dd6c ble.n 800be5e <__kernel_rem_pio2+0x23a> + 800bd84: 1e7a subs r2, r7, #1 + 800bd86: ab0c add r3, sp, #48 ; 0x30 + 800bd88: f853 0022 ldr.w r0, [r3, r2, lsl #2] + 800bd8c: f1ca 0118 rsb r1, sl, #24 + 800bd90: 9c05 ldr r4, [sp, #20] + 800bd92: fa40 f301 asr.w r3, r0, r1 + 800bd96: 441c add r4, r3 + 800bd98: 408b lsls r3, r1 + 800bd9a: 1ac0 subs r0, r0, r3 + 800bd9c: ab0c add r3, sp, #48 ; 0x30 + 800bd9e: f843 0022 str.w r0, [r3, r2, lsl #2] + 800bda2: f1ca 0317 rsb r3, sl, #23 + 800bda6: 9405 str r4, [sp, #20] + 800bda8: fa40 f303 asr.w r3, r0, r3 + 800bdac: 9300 str r3, [sp, #0] + 800bdae: 9b00 ldr r3, [sp, #0] + 800bdb0: 2b00 cmp r3, #0 + 800bdb2: dd62 ble.n 800be7a <__kernel_rem_pio2+0x256> + 800bdb4: 2200 movs r2, #0 + 800bdb6: f06f 417f mvn.w r1, #4278190080 ; 0xff000000 + 800bdba: 4614 mov r4, r2 + 800bdbc: 9b05 ldr r3, [sp, #20] + 800bdbe: 3301 adds r3, #1 + 800bdc0: 9305 str r3, [sp, #20] + 800bdc2: 4297 cmp r7, r2 + 800bdc4: f300 809f bgt.w 800bf06 <__kernel_rem_pio2+0x2e2> + 800bdc8: f1ba 0f00 cmp.w sl, #0 + 800bdcc: dd07 ble.n 800bdde <__kernel_rem_pio2+0x1ba> + 800bdce: f1ba 0f01 cmp.w sl, #1 + 800bdd2: f000 80bb beq.w 800bf4c <__kernel_rem_pio2+0x328> + 800bdd6: f1ba 0f02 cmp.w sl, #2 + 800bdda: f000 80c1 beq.w 800bf60 <__kernel_rem_pio2+0x33c> + 800bdde: 9b00 ldr r3, [sp, #0] + 800bde0: 2b02 cmp r3, #2 + 800bde2: d14a bne.n 800be7a <__kernel_rem_pio2+0x256> + 800bde4: 4642 mov r2, r8 + 800bde6: 464b mov r3, r9 + 800bde8: 2000 movs r0, #0 + 800bdea: 4953 ldr r1, [pc, #332] ; (800bf38 <__kernel_rem_pio2+0x314>) + 800bdec: f7f4 f9b4 bl 8000158 <__aeabi_dsub> + 800bdf0: 4680 mov r8, r0 + 800bdf2: 4689 mov r9, r1 + 800bdf4: 2c00 cmp r4, #0 + 800bdf6: d040 beq.n 800be7a <__kernel_rem_pio2+0x256> + 800bdf8: 4652 mov r2, sl + 800bdfa: 2000 movs r0, #0 + 800bdfc: 494e ldr r1, [pc, #312] ; (800bf38 <__kernel_rem_pio2+0x314>) + 800bdfe: f000 fb9b bl 800c538 + 800be02: 4602 mov r2, r0 + 800be04: 460b mov r3, r1 + 800be06: 4640 mov r0, r8 + 800be08: 4649 mov r1, r9 + 800be0a: f7f4 f9a5 bl 8000158 <__aeabi_dsub> + 800be0e: 4680 mov r8, r0 + 800be10: 4689 mov r9, r1 + 800be12: e032 b.n 800be7a <__kernel_rem_pio2+0x256> + 800be14: 2200 movs r2, #0 + 800be16: 4b49 ldr r3, [pc, #292] ; (800bf3c <__kernel_rem_pio2+0x318>) + 800be18: 4640 mov r0, r8 + 800be1a: 4649 mov r1, r9 + 800be1c: f7f4 fb54 bl 80004c8 <__aeabi_dmul> + 800be20: f7f4 fdec bl 80009fc <__aeabi_d2iz> + 800be24: f7f4 fae6 bl 80003f4 <__aeabi_i2d> + 800be28: 2200 movs r2, #0 + 800be2a: 4b45 ldr r3, [pc, #276] ; (800bf40 <__kernel_rem_pio2+0x31c>) + 800be2c: e9cd 0100 strd r0, r1, [sp] + 800be30: f7f4 fb4a bl 80004c8 <__aeabi_dmul> + 800be34: 4602 mov r2, r0 + 800be36: 460b mov r3, r1 + 800be38: 4640 mov r0, r8 + 800be3a: 4649 mov r1, r9 + 800be3c: f7f4 f98c bl 8000158 <__aeabi_dsub> + 800be40: f7f4 fddc bl 80009fc <__aeabi_d2iz> + 800be44: ab0c add r3, sp, #48 ; 0x30 + 800be46: f843 0026 str.w r0, [r3, r6, lsl #2] + 800be4a: e974 2302 ldrd r2, r3, [r4, #-8]! + 800be4e: e9dd 0100 ldrd r0, r1, [sp] + 800be52: f7f4 f983 bl 800015c <__adddf3> + 800be56: 3601 adds r6, #1 + 800be58: 4680 mov r8, r0 + 800be5a: 4689 mov r9, r1 + 800be5c: e765 b.n 800bd2a <__kernel_rem_pio2+0x106> + 800be5e: d105 bne.n 800be6c <__kernel_rem_pio2+0x248> + 800be60: 1e7b subs r3, r7, #1 + 800be62: aa0c add r2, sp, #48 ; 0x30 + 800be64: f852 0023 ldr.w r0, [r2, r3, lsl #2] + 800be68: 15c3 asrs r3, r0, #23 + 800be6a: e79f b.n 800bdac <__kernel_rem_pio2+0x188> + 800be6c: 2200 movs r2, #0 + 800be6e: 4b35 ldr r3, [pc, #212] ; (800bf44 <__kernel_rem_pio2+0x320>) + 800be70: f7f4 fdb0 bl 80009d4 <__aeabi_dcmpge> + 800be74: 2800 cmp r0, #0 + 800be76: d143 bne.n 800bf00 <__kernel_rem_pio2+0x2dc> + 800be78: 9000 str r0, [sp, #0] + 800be7a: 2200 movs r2, #0 + 800be7c: 2300 movs r3, #0 + 800be7e: 4640 mov r0, r8 + 800be80: 4649 mov r1, r9 + 800be82: f7f4 fd89 bl 8000998 <__aeabi_dcmpeq> + 800be86: 2800 cmp r0, #0 + 800be88: f000 80c3 beq.w 800c012 <__kernel_rem_pio2+0x3ee> + 800be8c: 1e7c subs r4, r7, #1 + 800be8e: 4623 mov r3, r4 + 800be90: 2200 movs r2, #0 + 800be92: 9902 ldr r1, [sp, #8] + 800be94: 428b cmp r3, r1 + 800be96: da6a bge.n 800bf6e <__kernel_rem_pio2+0x34a> + 800be98: 2a00 cmp r2, #0 + 800be9a: f000 8084 beq.w 800bfa6 <__kernel_rem_pio2+0x382> + 800be9e: ab0c add r3, sp, #48 ; 0x30 + 800bea0: f853 3024 ldr.w r3, [r3, r4, lsl #2] + 800bea4: f1aa 0a18 sub.w sl, sl, #24 + 800bea8: 2b00 cmp r3, #0 + 800beaa: f000 80b0 beq.w 800c00e <__kernel_rem_pio2+0x3ea> + 800beae: 4652 mov r2, sl + 800beb0: 2000 movs r0, #0 + 800beb2: 4921 ldr r1, [pc, #132] ; (800bf38 <__kernel_rem_pio2+0x314>) + 800beb4: f000 fb40 bl 800c538 + 800beb8: 4625 mov r5, r4 + 800beba: 4606 mov r6, r0 + 800bebc: 460f mov r7, r1 + 800bebe: f04f 0a00 mov.w sl, #0 + 800bec2: 00e3 lsls r3, r4, #3 + 800bec4: aa98 add r2, sp, #608 ; 0x260 + 800bec6: eb02 0803 add.w r8, r2, r3 + 800beca: f8df b070 ldr.w fp, [pc, #112] ; 800bf3c <__kernel_rem_pio2+0x318> + 800bece: 9306 str r3, [sp, #24] + 800bed0: f1a8 0898 sub.w r8, r8, #152 ; 0x98 + 800bed4: 2d00 cmp r5, #0 + 800bed6: f280 80d2 bge.w 800c07e <__kernel_rem_pio2+0x45a> + 800beda: 2500 movs r5, #0 + 800bedc: 9a06 ldr r2, [sp, #24] + 800bede: ab98 add r3, sp, #608 ; 0x260 + 800bee0: 189e adds r6, r3, r2 + 800bee2: 3ea8 subs r6, #168 ; 0xa8 + 800bee4: 1b63 subs r3, r4, r5 + 800bee6: 2b00 cmp r3, #0 + 800bee8: f2c0 80f9 blt.w 800c0de <__kernel_rem_pio2+0x4ba> + 800beec: f8df 9058 ldr.w r9, [pc, #88] ; 800bf48 <__kernel_rem_pio2+0x324> + 800bef0: eba6 08c5 sub.w r8, r6, r5, lsl #3 + 800bef4: f04f 0a00 mov.w sl, #0 + 800bef8: f04f 0b00 mov.w fp, #0 + 800befc: 2700 movs r7, #0 + 800befe: e0e2 b.n 800c0c6 <__kernel_rem_pio2+0x4a2> + 800bf00: 2302 movs r3, #2 + 800bf02: 9300 str r3, [sp, #0] + 800bf04: e756 b.n 800bdb4 <__kernel_rem_pio2+0x190> + 800bf06: ab0c add r3, sp, #48 ; 0x30 + 800bf08: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800bf0c: b94c cbnz r4, 800bf22 <__kernel_rem_pio2+0x2fe> + 800bf0e: b12b cbz r3, 800bf1c <__kernel_rem_pio2+0x2f8> + 800bf10: f1c3 7380 rsb r3, r3, #16777216 ; 0x1000000 + 800bf14: a80c add r0, sp, #48 ; 0x30 + 800bf16: f840 3022 str.w r3, [r0, r2, lsl #2] + 800bf1a: 2301 movs r3, #1 + 800bf1c: 3201 adds r2, #1 + 800bf1e: 461c mov r4, r3 + 800bf20: e74f b.n 800bdc2 <__kernel_rem_pio2+0x19e> + 800bf22: 1acb subs r3, r1, r3 + 800bf24: a80c add r0, sp, #48 ; 0x30 + 800bf26: f840 3022 str.w r3, [r0, r2, lsl #2] + 800bf2a: 4623 mov r3, r4 + 800bf2c: e7f6 b.n 800bf1c <__kernel_rem_pio2+0x2f8> + 800bf2e: bf00 nop + 800bf30: 0800f220 .word 0x0800f220 + 800bf34: 40200000 .word 0x40200000 + 800bf38: 3ff00000 .word 0x3ff00000 + 800bf3c: 3e700000 .word 0x3e700000 + 800bf40: 41700000 .word 0x41700000 + 800bf44: 3fe00000 .word 0x3fe00000 + 800bf48: 0800f1d8 .word 0x0800f1d8 + 800bf4c: 1e7a subs r2, r7, #1 + 800bf4e: ab0c add r3, sp, #48 ; 0x30 + 800bf50: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800bf54: f3c3 0316 ubfx r3, r3, #0, #23 + 800bf58: a90c add r1, sp, #48 ; 0x30 + 800bf5a: f841 3022 str.w r3, [r1, r2, lsl #2] + 800bf5e: e73e b.n 800bdde <__kernel_rem_pio2+0x1ba> + 800bf60: 1e7a subs r2, r7, #1 + 800bf62: ab0c add r3, sp, #48 ; 0x30 + 800bf64: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800bf68: f3c3 0315 ubfx r3, r3, #0, #22 + 800bf6c: e7f4 b.n 800bf58 <__kernel_rem_pio2+0x334> + 800bf6e: a90c add r1, sp, #48 ; 0x30 + 800bf70: f851 1023 ldr.w r1, [r1, r3, lsl #2] + 800bf74: 3b01 subs r3, #1 + 800bf76: 430a orrs r2, r1 + 800bf78: e78b b.n 800be92 <__kernel_rem_pio2+0x26e> + 800bf7a: 3401 adds r4, #1 + 800bf7c: f853 2d04 ldr.w r2, [r3, #-4]! + 800bf80: 2a00 cmp r2, #0 + 800bf82: d0fa beq.n 800bf7a <__kernel_rem_pio2+0x356> + 800bf84: ab98 add r3, sp, #608 ; 0x260 + 800bf86: 449b add fp, r3 + 800bf88: 9b07 ldr r3, [sp, #28] + 800bf8a: 1c7e adds r6, r7, #1 + 800bf8c: 19dd adds r5, r3, r7 + 800bf8e: ab98 add r3, sp, #608 ; 0x260 + 800bf90: eb03 05c5 add.w r5, r3, r5, lsl #3 + 800bf94: f1ab 0b98 sub.w fp, fp, #152 ; 0x98 + 800bf98: f5a5 75f4 sub.w r5, r5, #488 ; 0x1e8 + 800bf9c: 443c add r4, r7 + 800bf9e: 42b4 cmp r4, r6 + 800bfa0: da04 bge.n 800bfac <__kernel_rem_pio2+0x388> + 800bfa2: 4627 mov r7, r4 + 800bfa4: e6b1 b.n 800bd0a <__kernel_rem_pio2+0xe6> + 800bfa6: 9b0b ldr r3, [sp, #44] ; 0x2c + 800bfa8: 2401 movs r4, #1 + 800bfaa: e7e7 b.n 800bf7c <__kernel_rem_pio2+0x358> + 800bfac: f105 0308 add.w r3, r5, #8 + 800bfb0: 9309 str r3, [sp, #36] ; 0x24 + 800bfb2: 9b0a ldr r3, [sp, #40] ; 0x28 + 800bfb4: 2700 movs r7, #0 + 800bfb6: f853 0026 ldr.w r0, [r3, r6, lsl #2] + 800bfba: f7f4 fa1b bl 80003f4 <__aeabi_i2d> + 800bfbe: f04f 0800 mov.w r8, #0 + 800bfc2: f04f 0900 mov.w r9, #0 + 800bfc6: 9b08 ldr r3, [sp, #32] + 800bfc8: e9c5 0102 strd r0, r1, [r5, #8] + 800bfcc: 3b08 subs r3, #8 + 800bfce: 9300 str r3, [sp, #0] + 800bfd0: f105 0310 add.w r3, r5, #16 + 800bfd4: 9305 str r3, [sp, #20] + 800bfd6: 9b06 ldr r3, [sp, #24] + 800bfd8: 429f cmp r7, r3 + 800bfda: dd04 ble.n 800bfe6 <__kernel_rem_pio2+0x3c2> + 800bfdc: e9eb 8902 strd r8, r9, [fp, #8]! + 800bfe0: 3601 adds r6, #1 + 800bfe2: 9d09 ldr r5, [sp, #36] ; 0x24 + 800bfe4: e7db b.n 800bf9e <__kernel_rem_pio2+0x37a> + 800bfe6: 9905 ldr r1, [sp, #20] + 800bfe8: 9d00 ldr r5, [sp, #0] + 800bfea: e971 2302 ldrd r2, r3, [r1, #-8]! + 800bfee: 9105 str r1, [sp, #20] + 800bff0: e9f5 0102 ldrd r0, r1, [r5, #8]! + 800bff4: 9500 str r5, [sp, #0] + 800bff6: f7f4 fa67 bl 80004c8 <__aeabi_dmul> + 800bffa: 4602 mov r2, r0 + 800bffc: 460b mov r3, r1 + 800bffe: 4640 mov r0, r8 + 800c000: 4649 mov r1, r9 + 800c002: f7f4 f8ab bl 800015c <__adddf3> + 800c006: 3701 adds r7, #1 + 800c008: 4680 mov r8, r0 + 800c00a: 4689 mov r9, r1 + 800c00c: e7e3 b.n 800bfd6 <__kernel_rem_pio2+0x3b2> + 800c00e: 3c01 subs r4, #1 + 800c010: e745 b.n 800be9e <__kernel_rem_pio2+0x27a> + 800c012: f1ca 0200 rsb r2, sl, #0 + 800c016: 4640 mov r0, r8 + 800c018: 4649 mov r1, r9 + 800c01a: f000 fa8d bl 800c538 + 800c01e: 2200 movs r2, #0 + 800c020: 4ba3 ldr r3, [pc, #652] ; (800c2b0 <__kernel_rem_pio2+0x68c>) + 800c022: 4604 mov r4, r0 + 800c024: 460d mov r5, r1 + 800c026: f7f4 fcd5 bl 80009d4 <__aeabi_dcmpge> + 800c02a: b1f8 cbz r0, 800c06c <__kernel_rem_pio2+0x448> + 800c02c: 2200 movs r2, #0 + 800c02e: 4ba1 ldr r3, [pc, #644] ; (800c2b4 <__kernel_rem_pio2+0x690>) + 800c030: 4620 mov r0, r4 + 800c032: 4629 mov r1, r5 + 800c034: f7f4 fa48 bl 80004c8 <__aeabi_dmul> + 800c038: f7f4 fce0 bl 80009fc <__aeabi_d2iz> + 800c03c: 4606 mov r6, r0 + 800c03e: f7f4 f9d9 bl 80003f4 <__aeabi_i2d> + 800c042: 2200 movs r2, #0 + 800c044: 4b9a ldr r3, [pc, #616] ; (800c2b0 <__kernel_rem_pio2+0x68c>) + 800c046: f7f4 fa3f bl 80004c8 <__aeabi_dmul> + 800c04a: 460b mov r3, r1 + 800c04c: 4602 mov r2, r0 + 800c04e: 4629 mov r1, r5 + 800c050: 4620 mov r0, r4 + 800c052: f7f4 f881 bl 8000158 <__aeabi_dsub> + 800c056: f7f4 fcd1 bl 80009fc <__aeabi_d2iz> + 800c05a: 1c7c adds r4, r7, #1 + 800c05c: ab0c add r3, sp, #48 ; 0x30 + 800c05e: f843 0027 str.w r0, [r3, r7, lsl #2] + 800c062: f10a 0a18 add.w sl, sl, #24 + 800c066: f843 6024 str.w r6, [r3, r4, lsl #2] + 800c06a: e720 b.n 800beae <__kernel_rem_pio2+0x28a> + 800c06c: 4620 mov r0, r4 + 800c06e: 4629 mov r1, r5 + 800c070: f7f4 fcc4 bl 80009fc <__aeabi_d2iz> + 800c074: ab0c add r3, sp, #48 ; 0x30 + 800c076: f843 0027 str.w r0, [r3, r7, lsl #2] + 800c07a: 463c mov r4, r7 + 800c07c: e717 b.n 800beae <__kernel_rem_pio2+0x28a> + 800c07e: ab0c add r3, sp, #48 ; 0x30 + 800c080: f853 0025 ldr.w r0, [r3, r5, lsl #2] + 800c084: f7f4 f9b6 bl 80003f4 <__aeabi_i2d> + 800c088: 4632 mov r2, r6 + 800c08a: 463b mov r3, r7 + 800c08c: f7f4 fa1c bl 80004c8 <__aeabi_dmul> + 800c090: 4652 mov r2, sl + 800c092: e968 0102 strd r0, r1, [r8, #-8]! + 800c096: 465b mov r3, fp + 800c098: 4630 mov r0, r6 + 800c09a: 4639 mov r1, r7 + 800c09c: f7f4 fa14 bl 80004c8 <__aeabi_dmul> + 800c0a0: 3d01 subs r5, #1 + 800c0a2: 4606 mov r6, r0 + 800c0a4: 460f mov r7, r1 + 800c0a6: e715 b.n 800bed4 <__kernel_rem_pio2+0x2b0> + 800c0a8: e9f8 2302 ldrd r2, r3, [r8, #8]! + 800c0ac: e9f9 0102 ldrd r0, r1, [r9, #8]! + 800c0b0: f7f4 fa0a bl 80004c8 <__aeabi_dmul> + 800c0b4: 4602 mov r2, r0 + 800c0b6: 460b mov r3, r1 + 800c0b8: 4650 mov r0, sl + 800c0ba: 4659 mov r1, fp + 800c0bc: f7f4 f84e bl 800015c <__adddf3> + 800c0c0: 4682 mov sl, r0 + 800c0c2: 468b mov fp, r1 + 800c0c4: 3701 adds r7, #1 + 800c0c6: 9b02 ldr r3, [sp, #8] + 800c0c8: 429f cmp r7, r3 + 800c0ca: dc01 bgt.n 800c0d0 <__kernel_rem_pio2+0x4ac> + 800c0cc: 42bd cmp r5, r7 + 800c0ce: daeb bge.n 800c0a8 <__kernel_rem_pio2+0x484> + 800c0d0: ab48 add r3, sp, #288 ; 0x120 + 800c0d2: eb03 03c5 add.w r3, r3, r5, lsl #3 + 800c0d6: e9c3 ab00 strd sl, fp, [r3] + 800c0da: 3501 adds r5, #1 + 800c0dc: e702 b.n 800bee4 <__kernel_rem_pio2+0x2c0> + 800c0de: 9ba2 ldr r3, [sp, #648] ; 0x288 + 800c0e0: 2b03 cmp r3, #3 + 800c0e2: d86c bhi.n 800c1be <__kernel_rem_pio2+0x59a> + 800c0e4: e8df f003 tbb [pc, r3] + 800c0e8: 022f2f59 .word 0x022f2f59 + 800c0ec: 9a06 ldr r2, [sp, #24] + 800c0ee: ab48 add r3, sp, #288 ; 0x120 + 800c0f0: 189d adds r5, r3, r2 + 800c0f2: 46aa mov sl, r5 + 800c0f4: 46a3 mov fp, r4 + 800c0f6: f1bb 0f00 cmp.w fp, #0 + 800c0fa: f300 8087 bgt.w 800c20c <__kernel_rem_pio2+0x5e8> + 800c0fe: 46a2 mov sl, r4 + 800c100: f1ba 0f01 cmp.w sl, #1 + 800c104: f300 809f bgt.w 800c246 <__kernel_rem_pio2+0x622> + 800c108: 2700 movs r7, #0 + 800c10a: 463e mov r6, r7 + 800c10c: 9d06 ldr r5, [sp, #24] + 800c10e: ab48 add r3, sp, #288 ; 0x120 + 800c110: 3508 adds r5, #8 + 800c112: 441d add r5, r3 + 800c114: 2c01 cmp r4, #1 + 800c116: f300 80b3 bgt.w 800c280 <__kernel_rem_pio2+0x65c> + 800c11a: 9b00 ldr r3, [sp, #0] + 800c11c: 9d48 ldr r5, [sp, #288] ; 0x120 + 800c11e: 9849 ldr r0, [sp, #292] ; 0x124 + 800c120: 9c4a ldr r4, [sp, #296] ; 0x128 + 800c122: 994b ldr r1, [sp, #300] ; 0x12c + 800c124: 2b00 cmp r3, #0 + 800c126: f040 80b5 bne.w 800c294 <__kernel_rem_pio2+0x670> + 800c12a: 4603 mov r3, r0 + 800c12c: 462a mov r2, r5 + 800c12e: 9804 ldr r0, [sp, #16] + 800c130: e9c0 2300 strd r2, r3, [r0] + 800c134: 4622 mov r2, r4 + 800c136: 460b mov r3, r1 + 800c138: e9c0 2302 strd r2, r3, [r0, #8] + 800c13c: 463a mov r2, r7 + 800c13e: 4633 mov r3, r6 + 800c140: e9c0 2304 strd r2, r3, [r0, #16] + 800c144: e03b b.n 800c1be <__kernel_rem_pio2+0x59a> + 800c146: f04f 0c00 mov.w ip, #0 + 800c14a: 4626 mov r6, r4 + 800c14c: 4667 mov r7, ip + 800c14e: 9d06 ldr r5, [sp, #24] + 800c150: ab48 add r3, sp, #288 ; 0x120 + 800c152: 3508 adds r5, #8 + 800c154: 441d add r5, r3 + 800c156: 2e00 cmp r6, #0 + 800c158: da42 bge.n 800c1e0 <__kernel_rem_pio2+0x5bc> + 800c15a: 9b00 ldr r3, [sp, #0] + 800c15c: 2b00 cmp r3, #0 + 800c15e: d049 beq.n 800c1f4 <__kernel_rem_pio2+0x5d0> + 800c160: f107 4100 add.w r1, r7, #2147483648 ; 0x80000000 + 800c164: 4662 mov r2, ip + 800c166: 460b mov r3, r1 + 800c168: 9904 ldr r1, [sp, #16] + 800c16a: 2601 movs r6, #1 + 800c16c: e9c1 2300 strd r2, r3, [r1] + 800c170: a948 add r1, sp, #288 ; 0x120 + 800c172: 463b mov r3, r7 + 800c174: e9d1 0100 ldrd r0, r1, [r1] + 800c178: f7f3 ffee bl 8000158 <__aeabi_dsub> + 800c17c: 4684 mov ip, r0 + 800c17e: 460f mov r7, r1 + 800c180: ad48 add r5, sp, #288 ; 0x120 + 800c182: 42b4 cmp r4, r6 + 800c184: da38 bge.n 800c1f8 <__kernel_rem_pio2+0x5d4> + 800c186: 9b00 ldr r3, [sp, #0] + 800c188: b10b cbz r3, 800c18e <__kernel_rem_pio2+0x56a> + 800c18a: f107 4700 add.w r7, r7, #2147483648 ; 0x80000000 + 800c18e: 4662 mov r2, ip + 800c190: 463b mov r3, r7 + 800c192: 9904 ldr r1, [sp, #16] + 800c194: e9c1 2302 strd r2, r3, [r1, #8] + 800c198: e011 b.n 800c1be <__kernel_rem_pio2+0x59a> + 800c19a: 2700 movs r7, #0 + 800c19c: 463d mov r5, r7 + 800c19e: 9b06 ldr r3, [sp, #24] + 800c1a0: aa98 add r2, sp, #608 ; 0x260 + 800c1a2: 4413 add r3, r2 + 800c1a4: f5a3 769c sub.w r6, r3, #312 ; 0x138 + 800c1a8: 2c00 cmp r4, #0 + 800c1aa: da0f bge.n 800c1cc <__kernel_rem_pio2+0x5a8> + 800c1ac: 9b00 ldr r3, [sp, #0] + 800c1ae: b10b cbz r3, 800c1b4 <__kernel_rem_pio2+0x590> + 800c1b0: f105 4500 add.w r5, r5, #2147483648 ; 0x80000000 + 800c1b4: 463a mov r2, r7 + 800c1b6: 462b mov r3, r5 + 800c1b8: 9904 ldr r1, [sp, #16] + 800c1ba: e9c1 2300 strd r2, r3, [r1] + 800c1be: 9b05 ldr r3, [sp, #20] + 800c1c0: f003 0007 and.w r0, r3, #7 + 800c1c4: f50d 7d19 add.w sp, sp, #612 ; 0x264 + 800c1c8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800c1cc: 4638 mov r0, r7 + 800c1ce: e976 2302 ldrd r2, r3, [r6, #-8]! + 800c1d2: 4629 mov r1, r5 + 800c1d4: f7f3 ffc2 bl 800015c <__adddf3> + 800c1d8: 3c01 subs r4, #1 + 800c1da: 4607 mov r7, r0 + 800c1dc: 460d mov r5, r1 + 800c1de: e7e3 b.n 800c1a8 <__kernel_rem_pio2+0x584> + 800c1e0: 4660 mov r0, ip + 800c1e2: e975 2302 ldrd r2, r3, [r5, #-8]! + 800c1e6: 4639 mov r1, r7 + 800c1e8: f7f3 ffb8 bl 800015c <__adddf3> + 800c1ec: 3e01 subs r6, #1 + 800c1ee: 4684 mov ip, r0 + 800c1f0: 460f mov r7, r1 + 800c1f2: e7b0 b.n 800c156 <__kernel_rem_pio2+0x532> + 800c1f4: 4639 mov r1, r7 + 800c1f6: e7b5 b.n 800c164 <__kernel_rem_pio2+0x540> + 800c1f8: 4660 mov r0, ip + 800c1fa: e9f5 2302 ldrd r2, r3, [r5, #8]! + 800c1fe: 4639 mov r1, r7 + 800c200: f7f3 ffac bl 800015c <__adddf3> + 800c204: 3601 adds r6, #1 + 800c206: 4684 mov ip, r0 + 800c208: 460f mov r7, r1 + 800c20a: e7ba b.n 800c182 <__kernel_rem_pio2+0x55e> + 800c20c: e97a 8902 ldrd r8, r9, [sl, #-8]! + 800c210: e9da 2302 ldrd r2, r3, [sl, #8] + 800c214: 4640 mov r0, r8 + 800c216: 4649 mov r1, r9 + 800c218: e9cd 2302 strd r2, r3, [sp, #8] + 800c21c: f7f3 ff9e bl 800015c <__adddf3> + 800c220: 4602 mov r2, r0 + 800c222: 460b mov r3, r1 + 800c224: 4606 mov r6, r0 + 800c226: 460f mov r7, r1 + 800c228: 4640 mov r0, r8 + 800c22a: 4649 mov r1, r9 + 800c22c: f7f3 ff94 bl 8000158 <__aeabi_dsub> + 800c230: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c234: f7f3 ff92 bl 800015c <__adddf3> + 800c238: f10b 3bff add.w fp, fp, #4294967295 ; 0xffffffff + 800c23c: e9ca 0102 strd r0, r1, [sl, #8] + 800c240: e9ca 6700 strd r6, r7, [sl] + 800c244: e757 b.n 800c0f6 <__kernel_rem_pio2+0x4d2> + 800c246: e975 6702 ldrd r6, r7, [r5, #-8]! + 800c24a: e9d5 2302 ldrd r2, r3, [r5, #8] + 800c24e: 4630 mov r0, r6 + 800c250: 4639 mov r1, r7 + 800c252: e9cd 2302 strd r2, r3, [sp, #8] + 800c256: f7f3 ff81 bl 800015c <__adddf3> + 800c25a: 4602 mov r2, r0 + 800c25c: 460b mov r3, r1 + 800c25e: 4680 mov r8, r0 + 800c260: 4689 mov r9, r1 + 800c262: 4630 mov r0, r6 + 800c264: 4639 mov r1, r7 + 800c266: f7f3 ff77 bl 8000158 <__aeabi_dsub> + 800c26a: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c26e: f7f3 ff75 bl 800015c <__adddf3> + 800c272: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff + 800c276: e9c5 0102 strd r0, r1, [r5, #8] + 800c27a: e9c5 8900 strd r8, r9, [r5] + 800c27e: e73f b.n 800c100 <__kernel_rem_pio2+0x4dc> + 800c280: 4638 mov r0, r7 + 800c282: e975 2302 ldrd r2, r3, [r5, #-8]! + 800c286: 4631 mov r1, r6 + 800c288: f7f3 ff68 bl 800015c <__adddf3> + 800c28c: 3c01 subs r4, #1 + 800c28e: 4607 mov r7, r0 + 800c290: 460e mov r6, r1 + 800c292: e73f b.n 800c114 <__kernel_rem_pio2+0x4f0> + 800c294: 9b04 ldr r3, [sp, #16] + 800c296: f100 4000 add.w r0, r0, #2147483648 ; 0x80000000 + 800c29a: f101 4100 add.w r1, r1, #2147483648 ; 0x80000000 + 800c29e: f106 4600 add.w r6, r6, #2147483648 ; 0x80000000 + 800c2a2: 601d str r5, [r3, #0] + 800c2a4: e9c3 0401 strd r0, r4, [r3, #4] + 800c2a8: e9c3 1703 strd r1, r7, [r3, #12] + 800c2ac: 615e str r6, [r3, #20] + 800c2ae: e786 b.n 800c1be <__kernel_rem_pio2+0x59a> + 800c2b0: 41700000 .word 0x41700000 + 800c2b4: 3e700000 .word 0x3e700000 + +0800c2b8 <__kernel_sin>: + 800c2b8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800c2bc: b086 sub sp, #24 + 800c2be: e9cd 2300 strd r2, r3, [sp] + 800c2c2: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800c2c6: f1b3 5f79 cmp.w r3, #1044381696 ; 0x3e400000 + 800c2ca: 4682 mov sl, r0 + 800c2cc: 460c mov r4, r1 + 800c2ce: 9d0e ldr r5, [sp, #56] ; 0x38 + 800c2d0: da03 bge.n 800c2da <__kernel_sin+0x22> + 800c2d2: f7f4 fb93 bl 80009fc <__aeabi_d2iz> + 800c2d6: 2800 cmp r0, #0 + 800c2d8: d050 beq.n 800c37c <__kernel_sin+0xc4> + 800c2da: 4652 mov r2, sl + 800c2dc: 4623 mov r3, r4 + 800c2de: 4650 mov r0, sl + 800c2e0: 4621 mov r1, r4 + 800c2e2: f7f4 f8f1 bl 80004c8 <__aeabi_dmul> + 800c2e6: 4606 mov r6, r0 + 800c2e8: 460f mov r7, r1 + 800c2ea: 4602 mov r2, r0 + 800c2ec: 460b mov r3, r1 + 800c2ee: 4650 mov r0, sl + 800c2f0: 4621 mov r1, r4 + 800c2f2: f7f4 f8e9 bl 80004c8 <__aeabi_dmul> + 800c2f6: a33e add r3, pc, #248 ; (adr r3, 800c3f0 <__kernel_sin+0x138>) + 800c2f8: e9d3 2300 ldrd r2, r3, [r3] + 800c2fc: 4680 mov r8, r0 + 800c2fe: 4689 mov r9, r1 + 800c300: 4630 mov r0, r6 + 800c302: 4639 mov r1, r7 + 800c304: f7f4 f8e0 bl 80004c8 <__aeabi_dmul> + 800c308: a33b add r3, pc, #236 ; (adr r3, 800c3f8 <__kernel_sin+0x140>) + 800c30a: e9d3 2300 ldrd r2, r3, [r3] + 800c30e: f7f3 ff23 bl 8000158 <__aeabi_dsub> + 800c312: 4632 mov r2, r6 + 800c314: 463b mov r3, r7 + 800c316: f7f4 f8d7 bl 80004c8 <__aeabi_dmul> + 800c31a: a339 add r3, pc, #228 ; (adr r3, 800c400 <__kernel_sin+0x148>) + 800c31c: e9d3 2300 ldrd r2, r3, [r3] + 800c320: f7f3 ff1c bl 800015c <__adddf3> + 800c324: 4632 mov r2, r6 + 800c326: 463b mov r3, r7 + 800c328: f7f4 f8ce bl 80004c8 <__aeabi_dmul> + 800c32c: a336 add r3, pc, #216 ; (adr r3, 800c408 <__kernel_sin+0x150>) + 800c32e: e9d3 2300 ldrd r2, r3, [r3] + 800c332: f7f3 ff11 bl 8000158 <__aeabi_dsub> + 800c336: 4632 mov r2, r6 + 800c338: 463b mov r3, r7 + 800c33a: f7f4 f8c5 bl 80004c8 <__aeabi_dmul> + 800c33e: a334 add r3, pc, #208 ; (adr r3, 800c410 <__kernel_sin+0x158>) + 800c340: e9d3 2300 ldrd r2, r3, [r3] + 800c344: f7f3 ff0a bl 800015c <__adddf3> + 800c348: e9cd 0102 strd r0, r1, [sp, #8] + 800c34c: b9dd cbnz r5, 800c386 <__kernel_sin+0xce> + 800c34e: 4602 mov r2, r0 + 800c350: 460b mov r3, r1 + 800c352: 4630 mov r0, r6 + 800c354: 4639 mov r1, r7 + 800c356: f7f4 f8b7 bl 80004c8 <__aeabi_dmul> + 800c35a: a32f add r3, pc, #188 ; (adr r3, 800c418 <__kernel_sin+0x160>) + 800c35c: e9d3 2300 ldrd r2, r3, [r3] + 800c360: f7f3 fefa bl 8000158 <__aeabi_dsub> + 800c364: 4642 mov r2, r8 + 800c366: 464b mov r3, r9 + 800c368: f7f4 f8ae bl 80004c8 <__aeabi_dmul> + 800c36c: 4602 mov r2, r0 + 800c36e: 460b mov r3, r1 + 800c370: 4650 mov r0, sl + 800c372: 4621 mov r1, r4 + 800c374: f7f3 fef2 bl 800015c <__adddf3> + 800c378: 4682 mov sl, r0 + 800c37a: 460c mov r4, r1 + 800c37c: 4650 mov r0, sl + 800c37e: 4621 mov r1, r4 + 800c380: b006 add sp, #24 + 800c382: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800c386: 2200 movs r2, #0 + 800c388: e9dd 0100 ldrd r0, r1, [sp] + 800c38c: 4b24 ldr r3, [pc, #144] ; (800c420 <__kernel_sin+0x168>) + 800c38e: f7f4 f89b bl 80004c8 <__aeabi_dmul> + 800c392: e9dd 2302 ldrd r2, r3, [sp, #8] + 800c396: e9cd 0104 strd r0, r1, [sp, #16] + 800c39a: 4640 mov r0, r8 + 800c39c: 4649 mov r1, r9 + 800c39e: f7f4 f893 bl 80004c8 <__aeabi_dmul> + 800c3a2: 4602 mov r2, r0 + 800c3a4: 460b mov r3, r1 + 800c3a6: e9dd 0104 ldrd r0, r1, [sp, #16] + 800c3aa: f7f3 fed5 bl 8000158 <__aeabi_dsub> + 800c3ae: 4632 mov r2, r6 + 800c3b0: 463b mov r3, r7 + 800c3b2: f7f4 f889 bl 80004c8 <__aeabi_dmul> + 800c3b6: e9dd 2300 ldrd r2, r3, [sp] + 800c3ba: f7f3 fecd bl 8000158 <__aeabi_dsub> + 800c3be: a316 add r3, pc, #88 ; (adr r3, 800c418 <__kernel_sin+0x160>) + 800c3c0: e9d3 2300 ldrd r2, r3, [r3] + 800c3c4: 4606 mov r6, r0 + 800c3c6: 460f mov r7, r1 + 800c3c8: 4640 mov r0, r8 + 800c3ca: 4649 mov r1, r9 + 800c3cc: f7f4 f87c bl 80004c8 <__aeabi_dmul> + 800c3d0: 4602 mov r2, r0 + 800c3d2: 460b mov r3, r1 + 800c3d4: 4630 mov r0, r6 + 800c3d6: 4639 mov r1, r7 + 800c3d8: f7f3 fec0 bl 800015c <__adddf3> + 800c3dc: 4602 mov r2, r0 + 800c3de: 460b mov r3, r1 + 800c3e0: 4650 mov r0, sl + 800c3e2: 4621 mov r1, r4 + 800c3e4: f7f3 feb8 bl 8000158 <__aeabi_dsub> + 800c3e8: e7c6 b.n 800c378 <__kernel_sin+0xc0> + 800c3ea: bf00 nop + 800c3ec: f3af 8000 nop.w + 800c3f0: 5acfd57c .word 0x5acfd57c + 800c3f4: 3de5d93a .word 0x3de5d93a + 800c3f8: 8a2b9ceb .word 0x8a2b9ceb + 800c3fc: 3e5ae5e6 .word 0x3e5ae5e6 + 800c400: 57b1fe7d .word 0x57b1fe7d + 800c404: 3ec71de3 .word 0x3ec71de3 + 800c408: 19c161d5 .word 0x19c161d5 + 800c40c: 3f2a01a0 .word 0x3f2a01a0 + 800c410: 1110f8a6 .word 0x1110f8a6 + 800c414: 3f811111 .word 0x3f811111 + 800c418: 55555549 .word 0x55555549 + 800c41c: 3fc55555 .word 0x3fc55555 + 800c420: 3fe00000 .word 0x3fe00000 + +0800c424 : + 800c424: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800c428: 4619 mov r1, r3 + 800c42a: 4770 bx lr + 800c42c: 0000 movs r0, r0 + ... + +0800c430 : + 800c430: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 800c434: f3c1 580a ubfx r8, r1, #20, #11 + 800c438: f2a8 36ff subw r6, r8, #1023 ; 0x3ff + 800c43c: 2e13 cmp r6, #19 + 800c43e: 4607 mov r7, r0 + 800c440: 460b mov r3, r1 + 800c442: 460c mov r4, r1 + 800c444: 4605 mov r5, r0 + 800c446: dc35 bgt.n 800c4b4 + 800c448: 2e00 cmp r6, #0 + 800c44a: da16 bge.n 800c47a + 800c44c: a336 add r3, pc, #216 ; (adr r3, 800c528 ) + 800c44e: e9d3 2300 ldrd r2, r3, [r3] + 800c452: f7f3 fe83 bl 800015c <__adddf3> + 800c456: 2200 movs r2, #0 + 800c458: 2300 movs r3, #0 + 800c45a: f7f4 fac5 bl 80009e8 <__aeabi_dcmpgt> + 800c45e: b148 cbz r0, 800c474 + 800c460: 2c00 cmp r4, #0 + 800c462: da5b bge.n 800c51c + 800c464: 2500 movs r5, #0 + 800c466: f024 4300 bic.w r3, r4, #2147483648 ; 0x80000000 + 800c46a: 4a31 ldr r2, [pc, #196] ; (800c530 ) + 800c46c: 433b orrs r3, r7 + 800c46e: 42ab cmp r3, r5 + 800c470: bf18 it ne + 800c472: 4614 movne r4, r2 + 800c474: 4623 mov r3, r4 + 800c476: 462f mov r7, r5 + 800c478: e026 b.n 800c4c8 + 800c47a: 4a2e ldr r2, [pc, #184] ; (800c534 ) + 800c47c: fa42 f806 asr.w r8, r2, r6 + 800c480: ea01 0208 and.w r2, r1, r8 + 800c484: 4302 orrs r2, r0 + 800c486: d01f beq.n 800c4c8 + 800c488: a327 add r3, pc, #156 ; (adr r3, 800c528 ) + 800c48a: e9d3 2300 ldrd r2, r3, [r3] + 800c48e: f7f3 fe65 bl 800015c <__adddf3> + 800c492: 2200 movs r2, #0 + 800c494: 2300 movs r3, #0 + 800c496: f7f4 faa7 bl 80009e8 <__aeabi_dcmpgt> + 800c49a: 2800 cmp r0, #0 + 800c49c: d0ea beq.n 800c474 + 800c49e: 2c00 cmp r4, #0 + 800c4a0: bfbe ittt lt + 800c4a2: f44f 1380 movlt.w r3, #1048576 ; 0x100000 + 800c4a6: fa43 f606 asrlt.w r6, r3, r6 + 800c4aa: 19a4 addlt r4, r4, r6 + 800c4ac: ea24 0408 bic.w r4, r4, r8 + 800c4b0: 2500 movs r5, #0 + 800c4b2: e7df b.n 800c474 + 800c4b4: 2e33 cmp r6, #51 ; 0x33 + 800c4b6: dd0b ble.n 800c4d0 + 800c4b8: f5b6 6f80 cmp.w r6, #1024 ; 0x400 + 800c4bc: d104 bne.n 800c4c8 + 800c4be: 4602 mov r2, r0 + 800c4c0: f7f3 fe4c bl 800015c <__adddf3> + 800c4c4: 4607 mov r7, r0 + 800c4c6: 460b mov r3, r1 + 800c4c8: 4638 mov r0, r7 + 800c4ca: 4619 mov r1, r3 + 800c4cc: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 800c4d0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800c4d4: f2a8 4813 subw r8, r8, #1043 ; 0x413 + 800c4d8: fa22 f808 lsr.w r8, r2, r8 + 800c4dc: ea18 0f00 tst.w r8, r0 + 800c4e0: d0f2 beq.n 800c4c8 + 800c4e2: a311 add r3, pc, #68 ; (adr r3, 800c528 ) + 800c4e4: e9d3 2300 ldrd r2, r3, [r3] + 800c4e8: f7f3 fe38 bl 800015c <__adddf3> + 800c4ec: 2200 movs r2, #0 + 800c4ee: 2300 movs r3, #0 + 800c4f0: f7f4 fa7a bl 80009e8 <__aeabi_dcmpgt> + 800c4f4: 2800 cmp r0, #0 + 800c4f6: d0bd beq.n 800c474 + 800c4f8: 2c00 cmp r4, #0 + 800c4fa: da02 bge.n 800c502 + 800c4fc: 2e14 cmp r6, #20 + 800c4fe: d103 bne.n 800c508 + 800c500: 3401 adds r4, #1 + 800c502: ea25 0508 bic.w r5, r5, r8 + 800c506: e7b5 b.n 800c474 + 800c508: 2301 movs r3, #1 + 800c50a: f1c6 0634 rsb r6, r6, #52 ; 0x34 + 800c50e: fa03 f606 lsl.w r6, r3, r6 + 800c512: 4435 add r5, r6 + 800c514: 42bd cmp r5, r7 + 800c516: bf38 it cc + 800c518: 18e4 addcc r4, r4, r3 + 800c51a: e7f2 b.n 800c502 + 800c51c: 2500 movs r5, #0 + 800c51e: 462c mov r4, r5 + 800c520: e7a8 b.n 800c474 + 800c522: bf00 nop + 800c524: f3af 8000 nop.w + 800c528: 8800759c .word 0x8800759c + 800c52c: 7e37e43c .word 0x7e37e43c + 800c530: bff00000 .word 0xbff00000 + 800c534: 000fffff .word 0x000fffff + +0800c538 : + 800c538: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c53a: 4616 mov r6, r2 + 800c53c: f3c1 520a ubfx r2, r1, #20, #11 + 800c540: 4604 mov r4, r0 + 800c542: 460d mov r5, r1 + 800c544: 460b mov r3, r1 + 800c546: b982 cbnz r2, 800c56a + 800c548: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800c54c: 4303 orrs r3, r0 + 800c54e: d034 beq.n 800c5ba + 800c550: 4b2d ldr r3, [pc, #180] ; (800c608 ) + 800c552: 2200 movs r2, #0 + 800c554: f7f3 ffb8 bl 80004c8 <__aeabi_dmul> + 800c558: 4b2c ldr r3, [pc, #176] ; (800c60c ) + 800c55a: 4604 mov r4, r0 + 800c55c: 429e cmp r6, r3 + 800c55e: 460d mov r5, r1 + 800c560: da0d bge.n 800c57e + 800c562: a325 add r3, pc, #148 ; (adr r3, 800c5f8 ) + 800c564: e9d3 2300 ldrd r2, r3, [r3] + 800c568: e01c b.n 800c5a4 + 800c56a: f240 77ff movw r7, #2047 ; 0x7ff + 800c56e: 42ba cmp r2, r7 + 800c570: d109 bne.n 800c586 + 800c572: 4602 mov r2, r0 + 800c574: f7f3 fdf2 bl 800015c <__adddf3> + 800c578: 4604 mov r4, r0 + 800c57a: 460d mov r5, r1 + 800c57c: e01d b.n 800c5ba + 800c57e: 460b mov r3, r1 + 800c580: f3c1 520a ubfx r2, r1, #20, #11 + 800c584: 3a36 subs r2, #54 ; 0x36 + 800c586: f240 71fe movw r1, #2046 ; 0x7fe + 800c58a: 4432 add r2, r6 + 800c58c: 428a cmp r2, r1 + 800c58e: dd0c ble.n 800c5aa + 800c590: 4622 mov r2, r4 + 800c592: 462b mov r3, r5 + 800c594: a11a add r1, pc, #104 ; (adr r1, 800c600 ) + 800c596: e9d1 0100 ldrd r0, r1, [r1] + 800c59a: f000 f83b bl 800c614 + 800c59e: a318 add r3, pc, #96 ; (adr r3, 800c600 ) + 800c5a0: e9d3 2300 ldrd r2, r3, [r3] + 800c5a4: f7f3 ff90 bl 80004c8 <__aeabi_dmul> + 800c5a8: e7e6 b.n 800c578 + 800c5aa: 2a00 cmp r2, #0 + 800c5ac: dd08 ble.n 800c5c0 + 800c5ae: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 800c5b2: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 800c5b6: ea43 5502 orr.w r5, r3, r2, lsl #20 + 800c5ba: 4620 mov r0, r4 + 800c5bc: 4629 mov r1, r5 + 800c5be: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800c5c0: f112 0f35 cmn.w r2, #53 ; 0x35 + 800c5c4: da0b bge.n 800c5de + 800c5c6: f24c 3350 movw r3, #50000 ; 0xc350 + 800c5ca: 429e cmp r6, r3 + 800c5cc: 4622 mov r2, r4 + 800c5ce: 462b mov r3, r5 + 800c5d0: dce0 bgt.n 800c594 + 800c5d2: a109 add r1, pc, #36 ; (adr r1, 800c5f8 ) + 800c5d4: e9d1 0100 ldrd r0, r1, [r1] + 800c5d8: f000 f81c bl 800c614 + 800c5dc: e7c1 b.n 800c562 + 800c5de: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 800c5e2: 3236 adds r2, #54 ; 0x36 + 800c5e4: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 800c5e8: ea43 5502 orr.w r5, r3, r2, lsl #20 + 800c5ec: 4620 mov r0, r4 + 800c5ee: 4629 mov r1, r5 + 800c5f0: 2200 movs r2, #0 + 800c5f2: 4b07 ldr r3, [pc, #28] ; (800c610 ) + 800c5f4: e7d6 b.n 800c5a4 + 800c5f6: bf00 nop + 800c5f8: c2f8f359 .word 0xc2f8f359 + 800c5fc: 01a56e1f .word 0x01a56e1f + 800c600: 8800759c .word 0x8800759c + 800c604: 7e37e43c .word 0x7e37e43c + 800c608: 43500000 .word 0x43500000 + 800c60c: ffff3cb0 .word 0xffff3cb0 + 800c610: 3c900000 .word 0x3c900000 + +0800c614 : + 800c614: b530 push {r4, r5, lr} + 800c616: f021 4200 bic.w r2, r1, #2147483648 ; 0x80000000 + 800c61a: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 800c61e: ea42 0503 orr.w r5, r2, r3 + 800c622: 4629 mov r1, r5 + 800c624: bd30 pop {r4, r5, pc} + ... + +0800c628 <_init>: + 800c628: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c62a: bf00 nop + 800c62c: bcf8 pop {r3, r4, r5, r6, r7} + 800c62e: bc08 pop {r3} + 800c630: 469e mov lr, r3 + 800c632: 4770 bx lr + +0800c634 <_fini>: + 800c634: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c636: bf00 nop + 800c638: bcf8 pop {r3, r4, r5, r6, r7} + 800c63a: bc08 pop {r3} + 800c63c: 469e mov lr, r3 + 800c63e: 4770 bx lr diff --git a/Debug/Src/subdir.mk b/Debug/Src/subdir.mk new file mode 100644 index 0000000..7518edc --- /dev/null +++ b/Debug/Src/subdir.mk @@ -0,0 +1,69 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Src/freertos.c \ +../Src/main.c \ +../Src/stm32f1xx_hal_msp.c \ +../Src/stm32f1xx_it.c \ +../Src/syscalls.c \ +../Src/sysmem.c \ +../Src/system_stm32f1xx.c \ +../Src/usb_device.c \ +../Src/usbd_cdc_if.c \ +../Src/usbd_conf.c \ +../Src/usbd_desc.c + +OBJS += \ +./Src/freertos.o \ +./Src/main.o \ +./Src/stm32f1xx_hal_msp.o \ +./Src/stm32f1xx_it.o \ +./Src/syscalls.o \ +./Src/sysmem.o \ +./Src/system_stm32f1xx.o \ +./Src/usb_device.o \ +./Src/usbd_cdc_if.o \ +./Src/usbd_conf.o \ +./Src/usbd_desc.o + +C_DEPS += \ +./Src/freertos.d \ +./Src/main.d \ +./Src/stm32f1xx_hal_msp.d \ +./Src/stm32f1xx_it.d \ +./Src/syscalls.d \ +./Src/sysmem.d \ +./Src/system_stm32f1xx.d \ +./Src/usb_device.d \ +./Src/usbd_cdc_if.d \ +./Src/usbd_conf.d \ +./Src/usbd_desc.d + + +# Each subdirectory must supply rules for building sources it contributes +Src/freertos.o: ../Src/freertos.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/freertos.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/main.o: ../Src/main.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/main.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/stm32f1xx_hal_msp.o: ../Src/stm32f1xx_hal_msp.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/stm32f1xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/stm32f1xx_it.o: ../Src/stm32f1xx_it.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/stm32f1xx_it.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/syscalls.o: ../Src/syscalls.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/syscalls.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/sysmem.o: ../Src/sysmem.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/sysmem.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/system_stm32f1xx.o: ../Src/system_stm32f1xx.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/system_stm32f1xx.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/usb_device.o: ../Src/usb_device.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/usb_device.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/usbd_cdc_if.o: ../Src/usbd_cdc_if.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/usbd_cdc_if.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/usbd_conf.o: ../Src/usbd_conf.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/usbd_conf.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Src/usbd_desc.o: ../Src/usbd_desc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F103xB -DDEBUG -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Drivers/ili9341 -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/usbd_desc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/Debug/Startup/subdir.mk b/Debug/Startup/subdir.mk new file mode 100644 index 0000000..4991e4f --- /dev/null +++ b/Debug/Startup/subdir.mk @@ -0,0 +1,16 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Startup/startup_stm32f103c8tx.s + +OBJS += \ +./Startup/startup_stm32f103c8tx.o + + +# Each subdirectory must supply rules for building sources it contributes +Startup/%.o: ../Startup/%.s + arm-none-eabi-gcc -mcpu=cortex-m3 -g3 -c -x assembler-with-cpp --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + diff --git a/Debug/makefile b/Debug/makefile new file mode 100644 index 0000000..7574965 --- /dev/null +++ b/Debug/makefile @@ -0,0 +1,72 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Startup/subdir.mk +-include Src/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk +-include Drivers/ili9341/subdir.mk +-include Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +STM32Display.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +STM32Display.list \ + + +# All Target +all: STM32Display.elf secondary-outputs + +# Tool invocations +STM32Display.elf: $(OBJS) $(USER_OBJS) /home/vladimir/Desktop/STM32Display/STM32F103C8TX_FLASH.ld + arm-none-eabi-gcc -o "STM32Display.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m3 -T"/home/vladimir/Desktop/STM32Display/STM32F103C8TX_FLASH.ld" --specs=nosys.specs -Wl,-Map="STM32Display.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +STM32Display.list: $(EXECUTABLES) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "STM32Display.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets diff --git a/Debug/objects.list b/Debug/objects.list new file mode 100644 index 0000000..d9beea1 --- /dev/null +++ b/Debug/objects.list @@ -0,0 +1,50 @@ +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o" +"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.o" +"Drivers/ili9341/fonts.o" +"Drivers/ili9341/ili9341.o" +"Drivers/ili9341/ili9341_touch.o" +"Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o" +"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o" +"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o" +"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o" +"Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o" +"Middlewares/Third_Party/FreeRTOS/Source/croutine.o" +"Middlewares/Third_Party/FreeRTOS/Source/event_groups.o" +"Middlewares/Third_Party/FreeRTOS/Source/list.o" +"Middlewares/Third_Party/FreeRTOS/Source/queue.o" +"Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o" +"Middlewares/Third_Party/FreeRTOS/Source/tasks.o" +"Middlewares/Third_Party/FreeRTOS/Source/timers.o" +"Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.o" +"Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o" +"Src/freertos.o" +"Src/main.o" +"Src/stm32f1xx_hal_msp.o" +"Src/stm32f1xx_it.o" +"Src/syscalls.o" +"Src/sysmem.o" +"Src/system_stm32f1xx.o" +"Src/usb_device.o" +"Src/usbd_cdc_if.o" +"Src/usbd_conf.o" +"Src/usbd_desc.o" +"Startup/startup_stm32f103c8tx.o" diff --git a/Debug/objects.mk b/Debug/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Debug/sources.mk b/Debug/sources.mk new file mode 100644 index 0000000..6873d4c --- /dev/null +++ b/Debug/sources.mk @@ -0,0 +1,29 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +SIZE_OUTPUT := +OBJDUMP_LIST := +EXECUTABLES := +OBJS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Drivers/STM32F1xx_HAL_Driver/Src \ +Drivers/ili9341 \ +Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src \ +Middlewares/ST/STM32_USB_Device_Library/Core/Src \ +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS \ +Middlewares/Third_Party/FreeRTOS/Source \ +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 \ +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang \ +Src \ +Startup \ + diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h new file mode 100644 index 0000000..ce68992 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h @@ -0,0 +1,10238 @@ +/** + ****************************************************************************** + * @file stm32f103xb.h + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F1xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f103xb + * @{ + */ + +#ifndef __STM32F103xB_H +#define __STM32F103xB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ + #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ + __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ + uint32_t RESERVED[16]; + __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ +} ADC_Common_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DR4; + __IO uint32_t DR5; + __IO uint32_t DR6; + __IO uint32_t DR7; + __IO uint32_t DR8; + __IO uint32_t DR9; + __IO uint32_t DR10; + __IO uint32_t RTCCR; + __IO uint32_t CR; + __IO uint32_t CSR; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t OAR1; + __IO uint32_t OAR2; + __IO uint32_t DR; + __IO uint32_t SR1; + __IO uint32_t SR2; + __IO uint32_t CCR; + __IO uint32_t TRISE; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t CRH; + __IO uint32_t CRL; + __IO uint32_t PRLH; + __IO uint32_t PRLL; + __IO uint32_t DIVH; + __IO uint32_t DIVL; + __IO uint32_t CNTH; + __IO uint32_t CNTL; + __IO uint32_t ALRH; + __IO uint32_t ALRL; +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SR; + __IO uint32_t DR; + __IO uint32_t CRCPR; + __IO uint32_t RXCRCR; + __IO uint32_t TXCRCR; + __IO uint32_t I2SCFGR; +} SPI_TypeDef; + +/** + * @brief TIM Timers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +}TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ +} USB_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0801FFFFUL /*!< FLASH END address of bank1 */ +#define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) +#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) +#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) +#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) + + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ +#define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ + + + +#define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ + +/* USB device FS */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ + + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define USB ((USB_TypeDef *)USB_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) + + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ +#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ +#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ +#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ +#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ +#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ +#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ +#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ + +/* Legacy defines */ +#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 +#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 +#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 +#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 +#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 +#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 +#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 +#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 + +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_EWUP_Pos (8U) +#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D_Pos (0U) +#define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D_Pos (0U) +#define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D_Pos (0U) +#define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D_Pos (0U) +#define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D_Pos (0U) +#define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D_Pos (0U) +#define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D_Pos (0U) +#define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D_Pos (0U) +#define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D_Pos (0U) +#define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D_Pos (0U) +#define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ + +#define RTC_BKP_NUMBER 10 + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL_Pos (0U) +#define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ +#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ +#define BKP_RTCCR_CCO_Pos (7U) +#define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ +#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE_Pos (8U) +#define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ +#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS_Pos (9U) +#define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ +#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE_Pos (0U) +#define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ +#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ +#define BKP_CR_TPAL_Pos (1U) +#define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ +#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE_Pos (0U) +#define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ +#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ +#define BKP_CSR_CTI_Pos (1U) +#define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ +#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE_Pos (2U) +#define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ +#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF_Pos (8U) +#define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ +#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ +#define BKP_CSR_TIF_Pos (9U) +#define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ +#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY_Pos (1U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_Pos (3U) +#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ +#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL_Pos (8U) +#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ +#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ + +#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ + +#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ + +#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ + +#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE_Pos (14U) +#define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ +#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ + +#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE_Pos (17U) +#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ +#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL_Pos (18U) +#define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ + +#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ +#define RCC_CFGR_PLLMULL3_Pos (18U) +#define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ +#define RCC_CFGR_PLLMULL4_Pos (19U) +#define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ +#define RCC_CFGR_PLLMULL5_Pos (18U) +#define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ +#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ +#define RCC_CFGR_PLLMULL6_Pos (20U) +#define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ +#define RCC_CFGR_PLLMULL7_Pos (18U) +#define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ +#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ +#define RCC_CFGR_PLLMULL8_Pos (19U) +#define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ +#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ +#define RCC_CFGR_PLLMULL9_Pos (18U) +#define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ +#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ +#define RCC_CFGR_PLLMULL10_Pos (21U) +#define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ +#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ +#define RCC_CFGR_PLLMULL11_Pos (18U) +#define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ +#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ +#define RCC_CFGR_PLLMULL12_Pos (19U) +#define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ +#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ +#define RCC_CFGR_PLLMULL13_Pos (18U) +#define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ +#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ +#define RCC_CFGR_PLLMULL14_Pos (20U) +#define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ +#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ +#define RCC_CFGR_PLLMULL15_Pos (18U) +#define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ +#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ +#define RCC_CFGR_PLLMULL16_Pos (19U) +#define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ +#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ +#define RCC_CFGR_USBPRE_Pos (22U) +#define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ + +/*!< MCO configuration */ +#define RCC_CFGR_MCO_Pos (24U) +#define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ + +#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ +#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ +#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ + + /* Reference defines */ + #define RCC_CFGR_MCOSEL RCC_CFGR_MCO + #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 + #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 + #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 + #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK + #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK + #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI + #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE + #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF_Pos (0U) +#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF_Pos (1U) +#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF_Pos (2U) +#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF_Pos (3U) +#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF_Pos (4U) +#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF_Pos (7U) +#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ +#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE_Pos (8U) +#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE_Pos (9U) +#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE_Pos (10U) +#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE_Pos (11U) +#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE_Pos (12U) +#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ +#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC_Pos (16U) +#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ +#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC_Pos (17U) +#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ +#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC_Pos (18U) +#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ +#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC_Pos (19U) +#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ +#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC_Pos (20U) +#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ +#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC_Pos (23U) +#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ +#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST_Pos (0U) +#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST_Pos (2U) +#define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST_Pos (3U) +#define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST_Pos (4U) +#define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST_Pos (5U) +#define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST_Pos (9U) +#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ + +#define RCC_APB2RSTR_ADC2RST_Pos (10U) +#define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ + +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ + + +#define RCC_APB2RSTR_IOPERST_Pos (6U) +#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ + + + + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ + +#define RCC_APB1RSTR_CAN1RST_Pos (25U) +#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ + +#define RCC_APB1RSTR_BKPRST_Pos (27U) +#define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ + +#define RCC_APB1RSTR_TIM4RST_Pos (2U) +#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ +#define RCC_APB1RSTR_USART3RST_Pos (18U) +#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ + +#define RCC_APB1RSTR_USBRST_Pos (23U) +#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ + + + + + + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN_Pos (0U) +#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN_Pos (2U) +#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN_Pos (4U) +#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ +#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN_Pos (6U) +#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ + + + + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN_Pos (0U) +#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN_Pos (2U) +#define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN_Pos (3U) +#define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ +#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN_Pos (4U) +#define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN_Pos (5U) +#define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN_Pos (9U) +#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ + +#define RCC_APB2ENR_ADC2EN_Pos (10U) +#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ +#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ + +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ + + +#define RCC_APB2ENR_IOPEEN_Pos (6U) +#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ + + + + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ + +#define RCC_APB1ENR_CAN1EN_Pos (25U) +#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ + +#define RCC_APB1ENR_BKPEN_Pos (27U) +#define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ + +#define RCC_APB1ENR_TIM4EN_Pos (2U) +#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ +#define RCC_APB1ENR_USART3EN_Pos (18U) +#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ + +#define RCC_APB1ENR_USBEN_Pos (23U) +#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ + + + + + + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF_Pos (24U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ + + + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE_Pos (0U) +#define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0_Pos (0U) +#define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ + +#define GPIO_CRL_MODE1_Pos (4U) +#define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ +#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ +#define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ + +#define GPIO_CRL_MODE2_Pos (8U) +#define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ +#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ +#define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ + +#define GPIO_CRL_MODE3_Pos (12U) +#define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ +#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ +#define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ + +#define GPIO_CRL_MODE4_Pos (16U) +#define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ +#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ +#define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ + +#define GPIO_CRL_MODE5_Pos (20U) +#define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ +#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ +#define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ + +#define GPIO_CRL_MODE6_Pos (24U) +#define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ +#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ +#define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ + +#define GPIO_CRL_MODE7_Pos (28U) +#define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ +#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ +#define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ + +#define GPIO_CRL_CNF_Pos (2U) +#define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0_Pos (2U) +#define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ +#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ +#define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ + +#define GPIO_CRL_CNF1_Pos (6U) +#define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ +#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ +#define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ + +#define GPIO_CRL_CNF2_Pos (10U) +#define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ +#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ +#define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ + +#define GPIO_CRL_CNF3_Pos (14U) +#define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ +#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ +#define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ + +#define GPIO_CRL_CNF4_Pos (18U) +#define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ +#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ +#define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ + +#define GPIO_CRL_CNF5_Pos (22U) +#define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ +#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ +#define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ + +#define GPIO_CRL_CNF6_Pos (26U) +#define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ +#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ +#define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ + +#define GPIO_CRL_CNF7_Pos (30U) +#define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ +#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ +#define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE_Pos (0U) +#define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8_Pos (0U) +#define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ +#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ +#define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ + +#define GPIO_CRH_MODE9_Pos (4U) +#define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ +#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ +#define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ + +#define GPIO_CRH_MODE10_Pos (8U) +#define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ +#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ +#define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ + +#define GPIO_CRH_MODE11_Pos (12U) +#define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ +#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ +#define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ + +#define GPIO_CRH_MODE12_Pos (16U) +#define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ +#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ +#define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ + +#define GPIO_CRH_MODE13_Pos (20U) +#define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ +#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ +#define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ + +#define GPIO_CRH_MODE14_Pos (24U) +#define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ +#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ +#define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ + +#define GPIO_CRH_MODE15_Pos (28U) +#define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ +#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ +#define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ + +#define GPIO_CRH_CNF_Pos (2U) +#define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8_Pos (2U) +#define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ +#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ +#define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ + +#define GPIO_CRH_CNF9_Pos (6U) +#define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ +#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ +#define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ + +#define GPIO_CRH_CNF10_Pos (10U) +#define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ +#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ +#define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ + +#define GPIO_CRH_CNF11_Pos (14U) +#define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ +#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ +#define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ + +#define GPIO_CRH_CNF12_Pos (18U) +#define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ +#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ +#define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ + +#define GPIO_CRH_CNF13_Pos (22U) +#define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ +#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ +#define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ + +#define GPIO_CRH_CNF14_Pos (26U) +#define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ +#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ +#define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ + +#define GPIO_CRH_CNF15_Pos (30U) +#define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ +#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ +#define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN_Pos (0U) +#define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1_Pos (0U) +#define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2_Pos (1U) +#define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3_Pos (0U) +#define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ +#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4_Pos (2U) +#define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5_Pos (0U) +#define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ +#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6_Pos (1U) +#define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ +#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7_Pos (0U) +#define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ +#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8_Pos (3U) +#define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ +#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9_Pos (0U) +#define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ +#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10_Pos (1U) +#define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ +#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11_Pos (0U) +#define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ +#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12_Pos (2U) +#define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ +#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13_Pos (0U) +#define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ +#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14_Pos (1U) +#define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ +#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15_Pos (0U) +#define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT_Pos (4U) +#define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ +#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB_Pos (4U) +#define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC_Pos (5U) +#define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD_Pos (4U) +#define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE_Pos (6U) +#define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ + +#define AFIO_EVCR_EVOE_Pos (7U) +#define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ +#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP_Pos (0U) +#define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ +#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP_Pos (1U) +#define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ +#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP_Pos (2U) +#define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ +#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP_Pos (3U) +#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ +#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ +#define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP_Pos (12U) +#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ +#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ +#define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) +#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP_Pos (15U) +#define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ +#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ +#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ + +#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) +#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ +#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0_Pos (0U) +#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1_Pos (4U) +#define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2_Pos (8U) +#define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3_Pos (12U) +#define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) +#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) +#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) +#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) +#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4_Pos (0U) +#define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5_Pos (4U) +#define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6_Pos (8U) +#define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7_Pos (12U) +#define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) +#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) +#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) +#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) +#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8_Pos (0U) +#define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9_Pos (4U) +#define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10_Pos (8U) +#define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11_Pos (12U) +#define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) +#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) +#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) +#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) +#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12_Pos (0U) +#define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13_Pos (4U) +#define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14_Pos (8U) +#define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15_Pos (12U) +#define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) +#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) +#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) +#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) +#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ + +/****************** Bit definition for AFIO_MAPR2 register ******************/ + + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ + +/* References Defines */ +#define EXTI_IMR_IM0 EXTI_IMR_MR0 +#define EXTI_IMR_IM1 EXTI_IMR_MR1 +#define EXTI_IMR_IM2 EXTI_IMR_MR2 +#define EXTI_IMR_IM3 EXTI_IMR_MR3 +#define EXTI_IMR_IM4 EXTI_IMR_MR4 +#define EXTI_IMR_IM5 EXTI_IMR_MR5 +#define EXTI_IMR_IM6 EXTI_IMR_MR6 +#define EXTI_IMR_IM7 EXTI_IMR_MR7 +#define EXTI_IMR_IM8 EXTI_IMR_MR8 +#define EXTI_IMR_IM9 EXTI_IMR_MR9 +#define EXTI_IMR_IM10 EXTI_IMR_MR10 +#define EXTI_IMR_IM11 EXTI_IMR_MR11 +#define EXTI_IMR_IM12 EXTI_IMR_MR12 +#define EXTI_IMR_IM13 EXTI_IMR_MR13 +#define EXTI_IMR_IM14 EXTI_IMR_MR14 +#define EXTI_IMR_IM15 EXTI_IMR_MR15 +#define EXTI_IMR_IM16 EXTI_IMR_MR16 +#define EXTI_IMR_IM17 EXTI_IMR_MR17 +#define EXTI_IMR_IM18 EXTI_IMR_MR18 +#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ + +/* References Defines */ +#define EXTI_EMR_EM0 EXTI_EMR_MR0 +#define EXTI_EMR_EM1 EXTI_EMR_MR1 +#define EXTI_EMR_EM2 EXTI_EMR_MR2 +#define EXTI_EMR_EM3 EXTI_EMR_MR3 +#define EXTI_EMR_EM4 EXTI_EMR_MR4 +#define EXTI_EMR_EM5 EXTI_EMR_MR5 +#define EXTI_EMR_EM6 EXTI_EMR_MR6 +#define EXTI_EMR_EM7 EXTI_EMR_MR7 +#define EXTI_EMR_EM8 EXTI_EMR_MR8 +#define EXTI_EMR_EM9 EXTI_EMR_MR9 +#define EXTI_EMR_EM10 EXTI_EMR_MR10 +#define EXTI_EMR_EM11 EXTI_EMR_MR11 +#define EXTI_EMR_EM12 EXTI_EMR_MR12 +#define EXTI_EMR_EM13 EXTI_EMR_MR13 +#define EXTI_EMR_EM14 EXTI_EMR_MR14 +#define EXTI_EMR_EM15 EXTI_EMR_MR15 +#define EXTI_EMR_EM16 EXTI_EMR_MR16 +#define EXTI_EMR_EM17 EXTI_EMR_MR17 +#define EXTI_EMR_EM18 EXTI_EMR_MR18 + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18_Pos (18U) +#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ + +/* References Defines */ +#define EXTI_RTSR_RT0 EXTI_RTSR_TR0 +#define EXTI_RTSR_RT1 EXTI_RTSR_TR1 +#define EXTI_RTSR_RT2 EXTI_RTSR_TR2 +#define EXTI_RTSR_RT3 EXTI_RTSR_TR3 +#define EXTI_RTSR_RT4 EXTI_RTSR_TR4 +#define EXTI_RTSR_RT5 EXTI_RTSR_TR5 +#define EXTI_RTSR_RT6 EXTI_RTSR_TR6 +#define EXTI_RTSR_RT7 EXTI_RTSR_TR7 +#define EXTI_RTSR_RT8 EXTI_RTSR_TR8 +#define EXTI_RTSR_RT9 EXTI_RTSR_TR9 +#define EXTI_RTSR_RT10 EXTI_RTSR_TR10 +#define EXTI_RTSR_RT11 EXTI_RTSR_TR11 +#define EXTI_RTSR_RT12 EXTI_RTSR_TR12 +#define EXTI_RTSR_RT13 EXTI_RTSR_TR13 +#define EXTI_RTSR_RT14 EXTI_RTSR_TR14 +#define EXTI_RTSR_RT15 EXTI_RTSR_TR15 +#define EXTI_RTSR_RT16 EXTI_RTSR_TR16 +#define EXTI_RTSR_RT17 EXTI_RTSR_TR17 +#define EXTI_RTSR_RT18 EXTI_RTSR_TR18 + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18_Pos (18U) +#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ + +/* References Defines */ +#define EXTI_FTSR_FT0 EXTI_FTSR_TR0 +#define EXTI_FTSR_FT1 EXTI_FTSR_TR1 +#define EXTI_FTSR_FT2 EXTI_FTSR_TR2 +#define EXTI_FTSR_FT3 EXTI_FTSR_TR3 +#define EXTI_FTSR_FT4 EXTI_FTSR_TR4 +#define EXTI_FTSR_FT5 EXTI_FTSR_TR5 +#define EXTI_FTSR_FT6 EXTI_FTSR_TR6 +#define EXTI_FTSR_FT7 EXTI_FTSR_TR7 +#define EXTI_FTSR_FT8 EXTI_FTSR_TR8 +#define EXTI_FTSR_FT9 EXTI_FTSR_TR9 +#define EXTI_FTSR_FT10 EXTI_FTSR_TR10 +#define EXTI_FTSR_FT11 EXTI_FTSR_TR11 +#define EXTI_FTSR_FT12 EXTI_FTSR_TR12 +#define EXTI_FTSR_FT13 EXTI_FTSR_TR13 +#define EXTI_FTSR_FT14 EXTI_FTSR_TR14 +#define EXTI_FTSR_FT15 EXTI_FTSR_TR15 +#define EXTI_FTSR_FT16 EXTI_FTSR_TR16 +#define EXTI_FTSR_FT17 EXTI_FTSR_TR17 +#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18_Pos (18U) +#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ + +/* References Defines */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 +#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18_Pos (18U) +#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ +#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ + +/* References Defines */ +#define EXTI_PR_PIF0 EXTI_PR_PR0 +#define EXTI_PR_PIF1 EXTI_PR_PR1 +#define EXTI_PR_PIF2 EXTI_PR_PR2 +#define EXTI_PR_PIF3 EXTI_PR_PR3 +#define EXTI_PR_PIF4 EXTI_PR_PR4 +#define EXTI_PR_PIF5 EXTI_PR_PR5 +#define EXTI_PR_PIF6 EXTI_PR_PR6 +#define EXTI_PR_PIF7 EXTI_PR_PR7 +#define EXTI_PR_PIF8 EXTI_PR_PR8 +#define EXTI_PR_PIF9 EXTI_PR_PR9 +#define EXTI_PR_PIF10 EXTI_PR_PR10 +#define EXTI_PR_PIF11 EXTI_PR_PR11 +#define EXTI_PR_PIF12 EXTI_PR_PR12 +#define EXTI_PR_PIF13 EXTI_PR_PR13 +#define EXTI_PR_PIF14 EXTI_PR_PR14 +#define EXTI_PR_PIF15 EXTI_PR_PR15 +#define EXTI_PR_PIF16 EXTI_PR_PR16 +#define EXTI_PR_PIF17 EXTI_PR_PR17 +#define EXTI_PR_PIF18 EXTI_PR_PR18 + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register *******************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register ******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register *******************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register *******************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_SR_EOS_Pos (1U) +#define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ +#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_SR_JEOS_Pos (2U) +#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ +#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ +#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ +#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ +#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ + +/* Legacy defines */ +#define ADC_SR_EOC (ADC_SR_EOS) +#define ADC_SR_JEOC (ADC_SR_JEOS) + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ +#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ + +#define ADC_CR1_EOSIE_Pos (5U) +#define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ +#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ +#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CR1_JEOSIE_Pos (7U) +#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ +#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ +#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ +#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ +#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ +#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ +#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ +#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ +#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ +#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ +#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ +#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ + +#define ADC_CR1_DUALMOD_Pos (16U) +#define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ +#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ +#define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ +#define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ +#define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ +#define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ + +#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ +#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +/* Legacy defines */ +#define ADC_CR1_EOCIE (ADC_CR1_EOSIE) +#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ +#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ +#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ +#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CR2_CAL_Pos (2U) +#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ +#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ +#define ADC_CR2_RSTCAL_Pos (3U) +#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ +#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ +#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ +#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ +#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CR2_JEXTSEL_Pos (12U) +#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ +#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ +#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ +#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ + +#define ADC_CR2_JEXTTRIG_Pos (15U) +#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ + +#define ADC_CR2_EXTSEL_Pos (17U) +#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ +#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ +#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ +#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ + +#define ADC_CR2_EXTTRIG_Pos (20U) +#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ +#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ +#define ADC_CR2_JSWSTART_Pos (21U) +#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ +#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR2_SWSTART_Pos (22U) +#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ +#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR2_TSVREFE_Pos (23U) +#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ +#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10_Pos (0U) +#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP11_Pos (3U) +#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP12_Pos (6U) +#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP13_Pos (9U) +#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP14_Pos (12U) +#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP15_Pos (15U) +#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP16_Pos (18U) +#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP17_Pos (21U) +#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0_Pos (0U) +#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP1_Pos (3U) +#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP2_Pos (6U) +#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP3_Pos (9U) +#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP4_Pos (12U) +#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP5_Pos (15U) +#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP6_Pos (18U) +#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP7_Pos (21U) +#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP8_Pos (24U) +#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP9_Pos (27U) +#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13_Pos (0U) +#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ +#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ + +#define ADC_SQR1_SQ14_Pos (5U) +#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ +#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ +#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ + +#define ADC_SQR1_SQ15_Pos (10U) +#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ +#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ +#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ + +#define ADC_SQR1_SQ16_Pos (15U) +#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ +#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ +#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ + +#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7_Pos (0U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ8_Pos (5U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ + +#define ADC_SQR2_SQ9_Pos (10U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ + +#define ADC_SQR2_SQ10_Pos (15U) +#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ +#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ +#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ + +#define ADC_SQR2_SQ11_Pos (20U) +#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ +#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ +#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ + +#define ADC_SQR2_SQ12_Pos (25U) +#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ +#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1_Pos (0U) +#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ2_Pos (5U) +#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ +#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ + +#define ADC_SQR3_SQ3_Pos (10U) +#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ +#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ +#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ + +#define ADC_SQR3_SQ4_Pos (15U) +#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ +#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ +#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ + +#define ADC_SQR3_SQ5_Pos (20U) +#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ +#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ +#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ + +#define ADC_SQR3_SQ6_Pos (25U) +#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ +#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ + +#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ + +#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ + +#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_ADC2DATA_Pos (16U) +#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ +#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ + + +/*****************************************************************************/ +/* */ +/* Timers (TIM) */ +/* */ +/*****************************************************************************/ +/******************* Bit definition for TIM_CR1 register *******************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx + * @{ + */ + +#ifndef __STM32F1XX_H +#define __STM32F1XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F1) +#define STM32F1 +#endif /* STM32F1 */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ + !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ + !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) + /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ + /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ + /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ + /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ + /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ + /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ + /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ + /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ + /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ + /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ + /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ + /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ + /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ + /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V4.3.1 + */ +#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F1_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F100xB) + #include "stm32f100xb.h" +#elif defined(STM32F100xE) + #include "stm32f100xe.h" +#elif defined(STM32F101x6) + #include "stm32f101x6.h" +#elif defined(STM32F101xB) + #include "stm32f101xb.h" +#elif defined(STM32F101xE) + #include "stm32f101xe.h" +#elif defined(STM32F101xG) + #include "stm32f101xg.h" +#elif defined(STM32F102x6) + #include "stm32f102x6.h" +#elif defined(STM32F102xB) + #include "stm32f102xb.h" +#elif defined(STM32F103x6) + #include "stm32f103x6.h" +#elif defined(STM32F103xB) + #include "stm32f103xb.h" +#elif defined(STM32F103xE) + #include "stm32f103xe.h" +#elif defined(STM32F103xG) + #include "stm32f103xg.h" +#elif defined(STM32F105xC) + #include "stm32f105xc.h" +#elif defined(STM32F107xC) + #include "stm32f107xc.h" +#else + #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f1xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F1xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h new file mode 100644 index 0000000..8e33366 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.h + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..7d751fb --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..d8031b0 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..79a2cac --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..1bd41a4 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..3c90a2c --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..ae3f2e3 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..ec76ab2 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..2d0f106 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..6f82227 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..b9377e8 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..fd1c407 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..8202a8d --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..b0dfbd3 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..02f82e2 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..308b868 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..ada6c2a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..9086c64 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..665822d --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..7d4b600 --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..99ee9f9 --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..d4c1474 --- /dev/null +++ b/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 0000000..2063643 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,3645 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR + +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) +#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) +#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#endif /* STM32L4 */ + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 +#endif + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h new file mode 100644 index 0000000..9e86eef --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h @@ -0,0 +1,357 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_H +#define __STM32F1xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_conf.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode + * @brief Freeze/Unfreeze Peripherals in Debug mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @{ + */ + +/* Peripherals on APB1 */ +/** + * @brief TIM2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) + +/** + * @brief TIM3 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) + +#if defined (DBGMCU_CR_DBG_TIM4_STOP) +/** + * @brief TIM4 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM5_STOP) +/** + * @brief TIM5 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM6_STOP) +/** + * @brief TIM6 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM7_STOP) +/** + * @brief TIM7 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM12_STOP) +/** + * @brief TIM12 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM13_STOP) +/** + * @brief TIM13 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM14_STOP) +/** + * @brief TIM14 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) +#endif + +/** + * @brief WWDG Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) + +/** + * @brief IWDG Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) + +/** + * @brief I2C1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) + +#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +/** + * @brief I2C2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) +#endif + +#if defined (DBGMCU_CR_DBG_CAN1_STOP) +/** + * @brief CAN1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) +#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_CAN2_STOP) +/** + * @brief CAN2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) +#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) +#endif + +/* Peripherals on APB2 */ +#if defined (DBGMCU_CR_DBG_TIM1_STOP) +/** + * @brief TIM1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM8_STOP) +/** + * @brief TIM8 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM9_STOP) +/** + * @brief TIM9 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM10_STOP) +/** + * @brief TIM10 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM11_STOP) +/** + * @brief TIM11 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) +#endif + + +#if defined (DBGMCU_CR_DBG_TIM15_STOP) +/** + * @brief TIM15 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM16_STOP) +/** + * @brief TIM16 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) +#endif + +#if defined (DBGMCU_CR_DBG_TIM17_STOP) +/** + * @brief TIM17 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) +#endif + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h new file mode 100644 index 0000000..ce96197 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_CORTEX_H +#define __STM32F1xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk +#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1U) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h new file mode 100644 index 0000000..71f6b8c --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h @@ -0,0 +1,198 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_DEF +#define __STM32F1xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" +#if defined(USE_HAL_LEGACY) +#include "Legacy/stm32_hal_legacy.h" +#endif +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) +/* Reserved for future use */ +#error "USE_RTOS should be 0 in the current HAL release" +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler */ +#define __ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F1xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h new file mode 100644 index 0000000..7b2304d --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h @@ -0,0 +1,457 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_DMA_H +#define __STM32F1xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + +} DMA_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ +#define DMA_FLAG_GL1 0x00000001U +#define DMA_FLAG_TC1 0x00000002U +#define DMA_FLAG_HT1 0x00000004U +#define DMA_FLAG_TE1 0x00000008U +#define DMA_FLAG_GL2 0x00000010U +#define DMA_FLAG_TC2 0x00000020U +#define DMA_FLAG_HT2 0x00000040U +#define DMA_FLAG_TE2 0x00000080U +#define DMA_FLAG_GL3 0x00000100U +#define DMA_FLAG_TC3 0x00000200U +#define DMA_FLAG_HT3 0x00000400U +#define DMA_FLAG_TE3 0x00000800U +#define DMA_FLAG_GL4 0x00001000U +#define DMA_FLAG_TC4 0x00002000U +#define DMA_FLAG_HT4 0x00004000U +#define DMA_FLAG_TE4 0x00008000U +#define DMA_FLAG_GL5 0x00010000U +#define DMA_FLAG_TC5 0x00020000U +#define DMA_FLAG_HT5 0x00040000U +#define DMA_FLAG_TE5 0x00080000U +#define DMA_FLAG_GL6 0x00100000U +#define DMA_FLAG_TC6 0x00200000U +#define DMA_FLAG_HT6 0x00400000U +#define DMA_FLAG_TE6 0x00800000U +#define DMA_FLAG_GL7 0x01000000U +#define DMA_FLAG_TC7 0x02000000U +#define DMA_FLAG_HT7 0x04000000U +#define DMA_FLAG_TE7 0x08000000U +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) + + +/* Interrupt & Flag management */ + +/** + * @brief Enables the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Return the number of remaining data units in the current DMA Channel transfer. + * @param __HANDLE__: DMA handle + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32f1xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h new file mode 100644 index 0000000..d861f50 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h @@ -0,0 +1,277 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_DMA_EX_H +#define __STM32F1xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros + * @{ + */ +/* Interrupt & Flag management */ +#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ + defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices + * @{ + */ + +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ + (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ + (DMA1->IFCR = (__FLAG__))) + +/** + * @} + */ + +#else +/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices + * @{ + */ + +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + DMA_FLAG_GL7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +/** + * @} + */ + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ + /* STM32F103xG || STM32F105xC || STM32F107xC */ + +#endif /* __STM32F1xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h new file mode 100644 index 0000000..5d3b049 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_EXTI_H +#define STM32F1xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ + +/** + * @brief HAL EXTI common Callback ID enumeration definition + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#if defined(EXTI_IMR_IM18) +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ +#endif /* EXTI_IMR_IM18 */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#endif /* EXTI_IMR_IM19 */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#if defined (GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#if defined (GPIOF) +#define EXTI_GPIOF 0x00000005u +#endif /* GPIOF */ +#if defined (GPIOG) +#define EXTI_GPIOG 0x00000006u +#endif /* GPIOG */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_NB 20UL +#elif defined(EXTI_IMR_IM18) +#define EXTI_LINE_NB 19UL +#else /* EXTI_IMR_IM17 */ +#define EXTI_LINE_NB 18UL +#endif /* EXTI_IMR_IM19 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined (GPIOG) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG)) +#elif defined (GPIOF) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF)) +#elif defined (GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD)) +#endif /* GPIOG */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h new file mode 100644 index 0000000..8cd21b1 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_FLASH_H +#define __STM32F1xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + +#if defined(FLASH_ACR_LATENCY) +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1) || \ + ((__LATENCY__) == FLASH_LATENCY_2)) + +#else +#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) +#endif /* FLASH_ACR_LATENCY */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_PAGEERASE = 1U, + FLASH_PROC_MASSERASE = 2U, + FLASH_PROC_PROGRAMHALFWORD = 3U, + FLASH_PROC_PROGRAMWORD = 4U, + FLASH_PROC_PROGRAMDOUBLEWORD = 5U +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ + + __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code + This parameter can be a value of @ref FLASH_Error_Codes */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Codes FLASH Error Codes + * @{ + */ + +#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ +#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ +#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ + +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA) + +/** + * @brief Disable the FLASH half cycle access. + * @note half cycle access can only be used with a low-frequency clock of less than + 8 MHz that can be obtained with the use of HSI or HSE but not of PLL. + * @retval None + */ +#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) + +/** + * @} + */ + +#if defined(FLASH_ACR_LATENCY) +/** @defgroup FLASH_EM_Latency FLASH Latency + * @brief macros to handle FLASH Latency + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval None + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) + + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @} + */ + +#endif /* FLASH_ACR_LATENCY */ +/** @defgroup FLASH_Prefetch FLASH Prefetch + * @brief macros to handle FLASH Prefetch buffer + * @{ + */ +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32f1xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); + +/* FLASH IRQ handler function */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +void HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_FLASH_GetError(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private function -------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +#if defined(FLASH_BANK2_END) +HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); +#endif /* FLASH_BANK2_END */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h new file mode 100644 index 0000000..1dcaeed --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h @@ -0,0 +1,786 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of Flash HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_FLASH_EX_H +#define __STM32F1xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ + +#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U +#define OBR_REG_INDEX 1U +#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#if defined(FLASH_BANK2_END) +#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) +#endif /* FLASH_BANK2_END */ + +/* Low Density */ +#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) +#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ + +/* Medium Density */ +#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) +#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ + +/* High Density */ +#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) +#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ + +/* XL Density */ +#if defined(FLASH_BANK2_END) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) +#endif /* FLASH_BANK2_END */ + +/* Connectivity Line */ +#if (defined(STM32F105xC) || defined(STM32F107xC)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) +#endif /* STM32F105xC || STM32F107xC */ + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) + +#if defined(FLASH_BANK2_END) +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#else +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) +#endif /* FLASH_BANK2_END */ + +/* Low Density */ +#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) + +#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ + +/* Medium Density */ +#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ + ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ + ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) + +#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ + +/* High Density */ +#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \ + ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) + +#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ + +/* XL Density */ +#if defined(FLASH_BANK2_END) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ + ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) + +#endif /* FLASH_BANK2_END */ + +/* Connectivity Line */ +#if (defined(STM32F105xC) || defined(STM32F107xC)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ + ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) + +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled + This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END + (x = 1 or 2 depending on devices)*/ + + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. + This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Options bytes program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_OB_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_OB_WRP_State */ + + uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected + This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ + + uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ + +#if defined(FLASH_BANK2_END) + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY / BOOT1 + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ +#else + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY */ +#endif /* FLASH_BANK2_END */ + + uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed + This parameter can be a value of @ref FLASHEx_OB_Data_Address */ + + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ +} FLASH_OBProgramInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Constants FLASH Constants + * @{ + */ + +/** @defgroup FLASHEx_Page_Size Page Size + * @{ + */ +#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) +#define FLASH_PAGE_SIZE 0x400U +#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ + /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ + +#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) +#define FLASH_PAGE_SIZE 0x800U +#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ + /* STM32F101xG || STM32F103xG */ + /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Type_Erase Type Erase + * @{ + */ +#define FLASH_TYPEERASE_PAGES 0x00U /*!CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ + /* Enable Bank2 IT */ \ + SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ + } while(0U) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 + * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 + * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 + * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ + /* Disable Bank1 IT */ \ + CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ + /* Disable Bank2 IT */ \ + CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ + } while(0U) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 + * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 + * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 + * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 + * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 + * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 + * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 + * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ + (FLASH->OBR & FLASH_OBR_OPTERR) : \ + ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \ + (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \ + (FLASH->SR2 & ((__FLAG__) >> 16U)))) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 + * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 + * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 + * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 + * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 + * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 + * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 + * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ + /* Clear FLASH_FLAG_OPTVERR flag */ \ + if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ + { \ + CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ + } \ + else { \ + /* Clear Flag in Bank1 */ \ + if (((__FLAG__) & SR_FLAG_MASK) != RESET) \ + { \ + FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \ + } \ + /* Clear Flag in Bank2 */ \ + if (((__FLAG__) >> 16U) != RESET) \ + { \ + FLASH->SR2 = ((__FLAG__) >> 16U); \ + } \ + } \ + } while(0U) +#else +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_BSY FLASH Busy flag + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ + (FLASH->OBR & FLASH_OBR_OPTERR) : \ + (FLASH->SR & (__FLAG__))) +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ + /* Clear FLASH_FLAG_OPTVERR flag */ \ + if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ + { \ + CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ + } \ + else { \ + /* Clear Flag in Bank1 */ \ + FLASH->SR = (__FLAG__); \ + } \ + } while(0U) + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_FLASH_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h new file mode 100644 index 0000000..2973944 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h @@ -0,0 +1,308 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_GPIO_H +#define STM32F1xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0u, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ + +#define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ + +/** + * @} + */ + +/** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32f1xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ + ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h new file mode 100644 index 0000000..56bcb85 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h @@ -0,0 +1,894 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_GPIO_EX_H +#define STM32F1xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration + * @brief This section propose definition to use the Cortex EVENTOUT signal. + * @{ + */ + +/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin + * @{ + */ + +#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ +#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ +#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ +#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ +#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ +#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ +#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ +#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ +#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ +#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ +#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ +#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ +#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ +#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ +#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ +#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ + +#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \ + ((__PIN__) == AFIO_EVENTOUT_PIN_15)) +/** + * @} + */ + +/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port + * @{ + */ + +#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ +#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ +#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ +#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ +#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ + +#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ + ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \ + ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \ + ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \ + ((__PORT__) == AFIO_EVENTOUT_PORT_E)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping + * @brief This section propose definition to remap the alternate function to some other port/pins. + * @{ + */ + +/** + * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. + * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) + * @retval None + */ +#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) + +/** + * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. + * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) + * @retval None + */ +#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) + +/** + * @brief Enable the remapping of I2C1 alternate function SCL and SDA. + * @note ENABLE: Remap (SCL/PB8, SDA/PB9) + * @retval None + */ +#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) + +/** + * @brief Disable the remapping of I2C1 alternate function SCL and SDA. + * @note DISABLE: No remap (SCL/PB6, SDA/PB7) + * @retval None + */ +#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) + +/** + * @brief Enable the remapping of USART1 alternate function TX and RX. + * @note ENABLE: Remap (TX/PB6, RX/PB7) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) + +/** + * @brief Disable the remapping of USART1 alternate function TX and RX. + * @note DISABLE: No remap (TX/PA9, RX/PA10) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) + +/** + * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. + * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) + +/** + * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. + * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) + +/** + * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. + * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. + * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) + +/** + * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. + * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) + * @retval None + */ +#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) + * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) + * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) + +/** + * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) + * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) + +/** + * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 + * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) + * @note TIM3_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 + * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) + * @note TIM3_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) + +/** + * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 + * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) + * @note TIM3_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) + +/** + * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. + * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) + * @note TIM4_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) + +/** + * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. + * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) + * @note TIM4_ETR on PE0 is not re-mapped. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) + +#if defined(AFIO_MAPR_CAN_REMAP_REMAP1) + +/** + * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. + * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) + +/** + * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. + * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) + +/** + * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. + * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) + +#endif + +/** + * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * on 100-pin and 144-pin packages, no need for remapping). + * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. + * @retval None + */ +#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) + +/** + * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * on 100-pin and 144-pin packages, no need for remapping). + * @note DISABLE: No remapping of PD0 and PD1 + * @retval None + */ +#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) + +#if defined(AFIO_MAPR_TIM5CH4_IREMAP) +/** + * @brief Enable the remapping of TIM5CH4. + * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. + * @note This function is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) + +/** + * @brief Disable the remapping of TIM5CH4. + * @note DISABLE: TIM5_CH4 is connected to PA3 + * @note This function is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) +#endif + +#if defined(AFIO_MAPR_ETH_REMAP) +/** + * @brief Enable the remapping of Ethernet MAC connections with the PHY. + * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) + +/** + * @brief Disable the remapping of Ethernet MAC connections with the PHY. + * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) +#endif + +#if defined(AFIO_MAPR_CAN2_REMAP) + +/** + * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. + * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) + +/** + * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. + * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) +#endif + +#if defined(AFIO_MAPR_MII_RMII_SEL) +/** + * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. + * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) + +/** + * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. + * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) +#endif + +/** + * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). + * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) + +/** + * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). + * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) + +/** + * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). + * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) + +/** + * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). + * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) + +#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) + +/** + * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). + * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) + +/** + * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). + * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) +#endif + +#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) + +/** + * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) + +/** + * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 + * @retval None + */ +#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) +#endif + +/** + * @brief Enable the Serial wire JTAG configuration + * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State + * @retval None + */ +#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) + +/** + * @brief Enable the Serial wire JTAG configuration + * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST + * @retval None + */ +#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) + +/** + * @brief Enable the Serial wire JTAG configuration + * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled + * @retval None + */ + +#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) + +/** + * @brief Disable the Serial wire JTAG configuration + * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled + * @retval None + */ +#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) + +#if defined(AFIO_MAPR_SPI3_REMAP) + +/** + * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. + * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) + +/** + * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. + * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) +#endif + +#if defined(AFIO_MAPR_TIM2ITR1_IREMAP) + +/** + * @brief Control of TIM2_ITR1 internal mapping. + * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) + +/** + * @brief Control of TIM2_ITR1 internal mapping. + * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) +#endif + +#if defined(AFIO_MAPR_PTP_PPS_REMAP) + +/** + * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @note ENABLE: PTP_PPS is output on PB5 pin. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) + +/** + * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @note DISABLE: PTP_PPS not output on PB5 pin. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM9_REMAP) + +/** + * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. + * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) + +/** + * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. + * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM10_REMAP) + +/** + * @brief Enable the remapping of TIM10_CH1. + * @note ENABLE: Remap (TIM10_CH1 on PF6). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) + +/** + * @brief Disable the remapping of TIM10_CH1. + * @note DISABLE: No remap (TIM10_CH1 on PB8). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM11_REMAP) +/** + * @brief Enable the remapping of TIM11_CH1. + * @note ENABLE: Remap (TIM11_CH1 on PF7). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) + +/** + * @brief Disable the remapping of TIM11_CH1. + * @note DISABLE: No remap (TIM11_CH1 on PB9). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM13_REMAP) + +/** + * @brief Enable the remapping of TIM13_CH1. + * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) + +/** + * @brief Disable the remapping of TIM13_CH1. + * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM14_REMAP) + +/** + * @brief Enable the remapping of TIM14_CH1. + * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) + +/** + * @brief Disable the remapping of TIM14_CH1. + * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) +#endif + +#if defined(AFIO_MAPR2_FSMC_NADV_REMAP) + +/** + * @brief Controls the use of the optional FSMC_NADV signal. + * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. + * @retval None + */ +#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) + +/** + * @brief Controls the use of the optional FSMC_NADV signal. + * @note CONNECTED: The NADV signal is connected to the output (default). + * @retval None + */ +#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM15_REMAP) + +/** + * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. + * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) + +/** + * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. + * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM16_REMAP) + +/** + * @brief Enable the remapping of TIM16_CH1. + * @note ENABLE: Remap (TIM16_CH1 on PA6). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) + +/** + * @brief Disable the remapping of TIM16_CH1. + * @note DISABLE: No remap (TIM16_CH1 on PB8). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM17_REMAP) + +/** + * @brief Enable the remapping of TIM17_CH1. + * @note ENABLE: Remap (TIM17_CH1 on PA7). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) + +/** + * @brief Disable the remapping of TIM17_CH1. + * @note DISABLE: No remap (TIM17_CH1 on PB9). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) +#endif + +#if defined(AFIO_MAPR2_CEC_REMAP) + +/** + * @brief Enable the remapping of CEC. + * @note ENABLE: Remap (CEC on PB10). + * @retval None + */ +#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) + +/** + * @brief Disable the remapping of CEC. + * @note DISABLE: No remap (CEC on PB8). + * @retval None + */ +#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM1_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. + * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. + * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. + * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. + * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) +#endif + +#if defined(AFIO_MAPR2_TIM12_REMAP) + +/** + * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. + * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). + * @note This bit is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) + +/** + * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. + * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). + * @note This bit is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) +#endif + +#if defined(AFIO_MAPR2_MISC_REMAP) + +/** + * @brief Miscellaneous features remapping. + * This bit is set and cleared by software. It controls miscellaneous features. + * The DMA2 channel 5 interrupt position in the vector table. + * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). + * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is + * selected as DAC Trigger 3, TIM15 triggers TIM1/3. + * @note This bit is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) + +/** + * @brief Miscellaneous features remapping. + * This bit is set and cleared by software. It controls miscellaneous features. + * The DMA2 channel 5 interrupt position in the vector table. + * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). + * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO + * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. + * @note This bit is available only in high density value line devices. + * @retval None + */ +#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros + * @{ + */ +#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :3uL) +#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :4uL) +#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL :\ + ((__GPIOx__) == (GPIOF))? 5uL :6uL) +#endif + +#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ + tmpreg |= AFIO_MAPR_SWJ_CFG; \ + tmpreg |= REMAP_PIN; \ + AFIO->MAPR = tmpreg; \ + }while(0u) + +#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ + tmpreg |= AFIO_MAPR_SWJ_CFG; \ + tmpreg &= ~REMAP_PIN; \ + AFIO->MAPR = tmpreg; \ + }while(0u) + +#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ + tmpreg &= ~REMAP_PIN_MASK; \ + tmpreg |= AFIO_MAPR_SWJ_CFG; \ + tmpreg |= REMAP_PIN; \ + AFIO->MAPR = tmpreg; \ + }while(0u) + +#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ + tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ + tmpreg |= DBGAFR_SWJCFG; \ + AFIO->MAPR = tmpreg; \ + }while(0u) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIOEx_Exported_Functions + * @{ + */ + +/** @addtogroup GPIOEx_Exported_Functions_Group1 + * @{ + */ +void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); +void HAL_GPIOEx_EnableEventout(void); +void HAL_GPIOEx_DisableEventout(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h new file mode 100644 index 0000000..0ae95d1 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h @@ -0,0 +1,735 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_I2C_H +#define __STM32F1xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_general_call_addressing_mode */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_nostretch_mode */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initilisation status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (Peripheral in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ +#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ +#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C transfer options */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode + context for internal usage */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + + __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ + + __IO uint32_t EventCount; /*!< I2C Event counter */ + + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode + * @{ + */ +#define I2C_DUTYCYCLE_2 0x00000000U +#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY +/** + * @} + */ + +/** @defgroup I2C_addressing_mode I2C addressing mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT 0x00004000U +#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) +/** + * @} + */ + +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE 0x00000000U +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL +/** + * @} + */ + +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE 0x00000000U +#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC +/** + * @} + */ + +/** @defgroup I2C_nostretch_mode I2C nostretch mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE 0x00000000U +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT 0x00000001U +#define I2C_MEMADD_SIZE_16BIT 0x00000010U +/** + * @} + */ + +/** @defgroup I2C_XferDirection_definition I2C XferDirection definition + * @{ + */ +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U +/** + * @} + */ + +/** @defgroup I2C_XferOptions_definition I2C XferOptions definition + * @{ + */ +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U +#define I2C_NEXT_FRAME 0x00000004U +#define I2C_FIRST_AND_LAST_FRAME 0x00000008U +#define I2C_LAST_FRAME_NO_STOP 0x00000010U +#define I2C_LAST_FRAME 0x00000020U + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x00AA0000U) +#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_BUF I2C_CR2_ITBUFEN +#define I2C_IT_EVT I2C_CR2_ITEVTEN +#define I2C_IT_ERR I2C_CR2_ITERREN +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ + +#define I2C_FLAG_OVR 0x00010800U +#define I2C_FLAG_AF 0x00010400U +#define I2C_FLAG_ARLO 0x00010200U +#define I2C_FLAG_BERR 0x00010100U +#define I2C_FLAG_TXE 0x00010080U +#define I2C_FLAG_RXNE 0x00010040U +#define I2C_FLAG_STOPF 0x00010010U +#define I2C_FLAG_ADD10 0x00010008U +#define I2C_FLAG_BTF 0x00010004U +#define I2C_FLAG_ADDR 0x00010002U +#define I2C_FLAG_SB 0x00010001U +#define I2C_FLAG_DUALF 0x00100080U +#define I2C_FLAG_GENCALL 0x00100010U +#define I2C_FLAG_TRA 0x00100004U +#define I2C_FLAG_BUSY 0x00100002U +#define I2C_FLAG_MSL 0x00100001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif + +/** @brief Enable or disable the specified I2C interrupts. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag + * @arg I2C_FLAG_RXNE: Data register not empty flag + * @arg I2C_FLAG_STOPF: Stop detection flag + * @arg I2C_FLAG_ADD10: 10-bit header sent flag + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag + * Address matched flag + * @arg I2C_FLAG_SB: Start bit flag + * @arg I2C_FLAG_DUALF: Dual flag + * @arg I2C_FLAG_GENCALL: General call header flag + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \ + (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \ + (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)) + +/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) + +/** @brief Clears the I2C ADDR pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + tmpreg = (__HANDLE__)->Instance->SR2; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Clears the I2C STOPF pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define I2C_FLAG_MASK 0x0000FFFFU +#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */ +#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST)) +#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR) +#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U)) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters + * @{ + */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ + ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F1xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h new file mode 100644 index 0000000..7d96b87 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h @@ -0,0 +1,1010 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pcd.h + * @author MCD Application Team + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_PCD_H +#define STM32F1xx_HAL_PCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_usb.h" + +#if defined (USB) || defined (USB_OTG_FS) + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structure definition + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 +} PCD_StateTypeDef; + +/* Device LPM suspend state */ +typedef enum +{ + LPM_L0 = 0x00, /* on */ + LPM_L1 = 0x01, /* LPM L1 sleep */ + LPM_L2 = 0x02, /* suspend */ + LPM_L3 = 0x03, /* off */ +} PCD_LPM_StateTypeDef; + +typedef enum +{ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ +} PCD_LPM_MsgTypeDef; + +typedef enum +{ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, + +} PCD_BCD_MsgTypeDef; + +#if defined (USB) + +#endif /* defined (USB) */ +#if defined (USB_OTG_FS) +typedef USB_OTG_GlobalTypeDef PCD_TypeDef; +typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_OTG_FS) */ +#if defined (USB) +typedef USB_TypeDef PCD_TypeDef; +typedef USB_CfgTypeDef PCD_InitTypeDef; +typedef USB_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB) */ + +/** + * @brief PCD Handle Structure definition + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +typedef struct __PCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ +#if defined (USB_OTG_FS) + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_OTG_FS) */ +#if defined (USB) + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ +#endif /* defined (USB) */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + uint32_t BESL; + + void *pData; /*!< Pointer to upper stack Handler */ + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ + void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ + void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ + void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ + void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ + void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ + void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ + + void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ + void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ + void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ + void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ + + void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +} PCD_HandleTypeDef; + +/** + * @} + */ + +/* Include PCD HAL Extended module */ +#include "stm32f1xx_hal_pcd_ex.h" + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Speed PCD Speed + * @{ + */ +#define PCD_SPEED_FULL USBD_FS_SPEED +/** + * @} + */ + +/** @defgroup PCD_PHY_Module PCD PHY Module + * @{ + */ +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U +/** + * @} + */ + +/** @defgroup PCD_Error_Code_definition PCD Error Code definition + * @brief PCD Error Code definition + * @{ + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#if defined (USB_OTG_FS) +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + + +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ + ~(USB_OTG_PCGCCTL_STOPCLK) + +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK + +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) + +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE + +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) + +#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE +#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) +#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE) +#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE + +#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \ + } while(0U) + +#endif /* defined (USB) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition + * @brief HAL USB OTG PCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ + HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ + HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ + HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ + HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ + HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + + HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ + HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ + +} HAL_PCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition + * @brief HAL USB OTG PCD Callback pointer definition + * @{ + */ + +typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ +typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ +typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ +typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ +typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ + +/** + * @} + */ + +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); + +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#if defined (USB_OTG_FS) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U +#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU +#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U + +#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB) */ + +/** + * @} + */ +#if defined (USB) +/** @defgroup PCD_EP0_MPS PCD EP0 MPS + * @{ + */ +#define PCD_EP0MPS_64 DEP0CTL_MPS_64 +#define PCD_EP0MPS_32 DEP0CTL_MPS_32 +#define PCD_EP0MPS_16 DEP0CTL_MPS_16 +#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +/** + * @} + */ + +/** @defgroup PCD_ENDP PCD ENDP + * @{ + */ +#define PCD_ENDP0 0U +#define PCD_ENDP1 1U +#define PCD_ENDP2 2U +#define PCD_ENDP3 3U +#define PCD_ENDP4 4U +#define PCD_ENDP5 5U +#define PCD_ENDP6 6U +#define PCD_ENDP7 7U +/** + * @} + */ + +/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind + * @{ + */ +#define PCD_SNG_BUF 0U +#define PCD_DBL_BUF 1U +/** + * @} + */ +#endif /* defined (USB) */ +/** + * @} + */ + +#if defined (USB_OTG_FS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif +#endif /* defined (USB_OTG_FS) */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ +#if defined (USB) +/******************** Bit definition for USB_COUNTn_RX register *************/ +#define USB_CNTRX_NBLK_MSK (0x1FU << 10) +#define USB_CNTRX_BLSIZE (0x1U << 15) + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) + +/* GetENDPOINT */ +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) + +/* ENDPOINT transfer */ +#define USB_EP0StartXfer USB_EPStartXfer + +/** + * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. + * @retval None + */ +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ + ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) + +/** + * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Endpoint Type + */ +#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpNum, bDir + * @retval None + */ +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ +} while(0) + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TX_STATUS */ + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_RX_STATUS */ + +/** + * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. + * @retval None + */ +#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TXRX_STATUS */ + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval status + */ +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) + +/** + * @brief sets directly the VALID tx/rx-status into the endpoint register + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) +#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) + +/** + * @brief checks stall condition in an endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval TRUE = endpoint in stall condition. + */ +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ + == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ + == USB_EP_RX_STALL) + +/** + * @brief set & clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ + } while(0) /* PCD_SET_EP_KIND */ + +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_EP_KIND */ + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_RX_EP_CTR */ + +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \ + } while(0) /* PCD_CLEAR_TX_EP_CTR */ + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ + } while(0) /* PCD_RX_DTOG */ + +#define PCD_TX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \ + } while(0) /* PCD_TX_DTOG */ +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\ + { \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_RX_DTOG */ + +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\ + { \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_TX_DTOG */ + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \ + register uint16_t _wRegVal; \ + \ + _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_ADDRESS */ + +/** + * @brief Gets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) + +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \ + register __IO uint16_t *_wRegVal; \ + register uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ +} while(0) /* PCD_SET_EP_TX_ADDRESS */ + +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \ + register __IO uint16_t *_wRegVal; \ + register uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ +} while(0) /* PCD_SET_EP_RX_ADDRESS */ + +/** + * @brief Gets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval address of the buffer. + */ +#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param pdwReg Register pointer + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ +#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \ + (wNBlocks) = (wCount) >> 5; \ + if (((wCount) & 0x1fU) == 0U) \ + { \ + (wNBlocks)--; \ + } \ + *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ + } while(0) /* PCD_CALC_BLK32 */ + +#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \ + (wNBlocks) = (wCount) >> 1; \ + if (((wCount) & 0x1U) != 0U) \ + { \ + (wNBlocks)++; \ + } \ + *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ + } while(0) /* PCD_CALC_BLK2 */ + +#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \ + uint32_t wNBlocks; \ + if ((wCount) == 0U) \ + { \ + *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if((wCount) <= 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ + else \ + { \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + } \ + } while(0) /* PCD_SET_EP_CNT_RX_REG */ + +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \ + register uint32_t _wRegBase = (uint32_t)(USBx); \ + register __IO uint16_t *pdwReg; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ + } while(0) + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \ + register uint32_t _wRegBase = (uint32_t)(USBx); \ + register __IO uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + *_wRegVal = (uint16_t)(wCount); \ +} while(0) + +#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \ + register uint32_t _wRegBase = (uint32_t)(USBx); \ + register __IO uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ +} while(0) + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) + +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @retval Counter value + */ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \ + PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ + } while(0) /* PCD_SET_EP_DBUF0_ADDR */ +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \ + PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF1_ADDR */ + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF_ADDR */ + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \ + if ((bDir) == 0U) \ + /* OUT endpoint */ \ + { \ + PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + } \ + } while(0) /* SetEPDblBuf0Count*/ + +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \ + register uint32_t _wBase = (uint32_t)(USBx); \ + __IO uint16_t *_wEPRegVal; \ + \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + _wBase += (uint32_t)(USBx)->BTABLE; \ + _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + *_wEPRegVal = (uint16_t)(wCount); \ + } \ + } \ + } while(0) /* SetEPDblBuf1Count */ + +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + } while(0) /* PCD_SET_EP_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) + +#endif /* defined (USB) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB) || defined (USB_OTG_FS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_PCD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h new file mode 100644 index 0000000..7e5eebf --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h @@ -0,0 +1,90 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pcd_ex.h + * @author MCD Application Team + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_PCD_EX_H +#define STM32F1xx_HAL_PCD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +#if defined (USB) || defined (USB_OTG_FS) +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ + +#if defined (USB_OTG_FS) +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress); + +void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); +#endif /* defined (USB) */ +void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); +void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB) || defined (USB_OTG_FS) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F1xx_HAL_PCD_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h new file mode 100644 index 0000000..2b1b4ed --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h @@ -0,0 +1,388 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_PWR_H +#define __STM32F1xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + + +/** + * @} + */ + + +/* Internal constants --------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants + * @{ + */ + +#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 + +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins + * @{ + */ + +#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP + +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON 0x00000000U +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS + +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) + +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +/* #define HAL_PWR_ConfigPVD 12*/ +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + + + +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F1xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h new file mode 100644 index 0000000..f0097cb --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h @@ -0,0 +1,1378 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RCC_H +#define __STM32F1xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ +} RCC_PLLInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ + +#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ + +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U +#define RCC_OSCILLATORTYPE_HSE 0x00000001U +#define RCC_OSCILLATORTYPE_HSI 0x00000002U +#define RCC_OSCILLATORTYPE_LSE 0x00000004U +#define RCC_OSCILLATORTYPE_LSI 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ + +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ + +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ +/** + * @} + */ + + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ + +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U + +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) +#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_BKP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) + +#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) +#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_AFIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) +#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) + +#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) + +#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) + +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) + +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) + +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) + +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macro to enable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) + +/** @brief Macro to disable the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macro to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) + +/** @brief Macro to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) + +/** @brief Macro to configure the main PLL clock source and multiplication factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 + * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 + @if STM32F105xC + * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 + @elseif STM32F107xC + * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 + @else + * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 + * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 + * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 + * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 + * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 + * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 + * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 + * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 + * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 + @endif + * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 + * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) + +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +#if defined(RCC_CFGR_MCO_3) +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#else +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#endif + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) + + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration +* @{ +*/ + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macro to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) + +/** @brief Macro to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) + +/** @brief Macro to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + * @arg @ref RCC_IT_CSS Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + @if STM32F105xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @elsif STM32F107xx + * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. + * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. + @endif + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. + @if STM32F105xx + * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. + * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. + @elsif STM32F107xx + * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. + * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. + @endif + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. + * @arg @ref RCC_FLAG_PINRST Pin reset. + * @arg @ref RCC_FLAG_PORRST POR/PDR reset. + * @arg @ref RCC_FLAG_SFTRST Software reset. + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. + * @arg @ref RCC_FLAG_LPWRRST Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ + RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f1xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ + +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00U +#define RCC_CFGR_OFFSET 0x04U +#define RCC_CIR_OFFSET 0x08U +#define RCC_BDCR_OFFSET 0x20U +#define RCC_CSR_OFFSET 0x24U + +/** + * @} + */ + +/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) +#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) +#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) +#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) +#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos +#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) +/* Alias word address of HSEON bit */ +#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos +#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos +#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos +#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos +#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) + +/* Alias word address of RMVF bit */ +#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos +#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) + +/* --- BDCR Registers ---*/ +/* Alias word address of LSEON bit */ +#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos +#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) + +/* Alias word address of LSEON bit */ +#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos +#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) + +/* Alias word address of RTCEN bit */ +#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos +#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) + +/* Alias word address of BDRST bit */ +#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos +#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) + +/** + * @} + */ + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1) +#define BDCR_REG_INDEX ((uint8_t)2) +#define CSR_REG_INDEX ((uint8_t)3) + +#define RCC_FLAG_MASK ((uint8_t)0x1F) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +/** + * @} + */ + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) + +#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h new file mode 100644 index 0000000..0bf4ccd --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h @@ -0,0 +1,1908 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RCC_EX_H +#define __STM32F1xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/** @addtogroup RCCEx_Private_Constants + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + +/* Alias word address of PLLI2SON bit */ +#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos +#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) +/* Alias word address of PLL2ON bit */ +#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos +#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) + +#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ +#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ + +#endif /* STM32F105xC || STM32F107xC */ + + +#define CR_REG_INDEX ((uint8_t)1) + +/** + * @} + */ + +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ + ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ + ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) + +#else +#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL6_5)) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) + +#else +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ + ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ + ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ + ((__MUL__) == RCC_PLL_MUL16)) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) + +#endif /* STM32F105xC || STM32F107xC*/ + +#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ + ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) + +#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) + +#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) + +#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ + ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ + ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ + ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ + ((__MUL__) == RCC_PLLI2S_MUL20)) + +#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ + ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) + +#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ + ((__PLL__) == RCC_PLL2_ON)) + +#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ + ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ + ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ + ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ + ((__MUL__) == RCC_PLL2_MUL20)) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + +#elif defined(STM32F103xE) || defined(STM32F103xG) + +#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) + +#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + + +#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + +#else + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) + +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + +#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** + * @brief RCC PLL2 configuration structure definition + */ +typedef struct +{ + uint32_t PLL2State; /*!< The new state of the PLL2. + This parameter can be a value of @ref RCCEx_PLL2_Config */ + + uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock + This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. + This parameter can be a value of @ref RCCEx_Prediv2_Factor */ + +#endif /* STM32F105xC || STM32F107xC */ +} RCC_PLL2InitTypeDef; + +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t Prediv1Source; /*!< The Prediv1 source value. + This parameter can be a value of @ref RCCEx_Prediv1_Source */ +#endif /* STM32F105xC || STM32F107xC */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) + This parameter can be a value of @ref RCCEx_Prediv1_Factor */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ +#endif /* STM32F105xC || STM32F107xC */ +} RCC_OscInitTypeDef; + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** + * @brief RCC PLLI2S configuration structure definition + */ +typedef struct +{ + uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock + This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ + +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. + This parameter can be a value of @ref RCCEx_Prediv2_Factor */ + +#endif /* STM32F105xC || STM32F107xC */ +} RCC_PLLI2SInitTypeDef; +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< specifies the RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t AdcClockSelection; /*!< ADC clock source + This parameter can be a value of @ref RCCEx_ADC_Prescaler */ + +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) + uint32_t I2s2ClockSelection; /*!< I2S2 clock source + This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ + + uint32_t I2s3ClockSelection; /*!< I2S3 clock source + This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters + This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ + +#endif /* STM32F105xC || STM32F107xC */ +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Prescaler */ + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +} RCC_PeriphCLKInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_RTC 0x00000001U +#define RCC_PERIPHCLK_ADC 0x00000002U +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define RCC_PERIPHCLK_I2S2 0x00000004U +#define RCC_PERIPHCLK_I2S3 0x00000008U +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_PERIPHCLK_USB 0x00000010U +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler + * @{ + */ +#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 +#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 +#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 +#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 + +/** + * @} + */ + +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source + * @{ + */ +#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source + * @{ + */ +#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + +/** @defgroup RCCEx_USB_Prescaler USB Prescaler + * @{ + */ +#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE +#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U + +/** + * @} + */ + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_USB_Prescaler USB Prescaler + * @{ + */ +#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE +#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U + +/** + * @} + */ + +/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor + * @{ + */ + +#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ +#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ +#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ +#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ +#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ +#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ +#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ +#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ +#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Prediv1_Source Prediv1 Source + * @{ + */ + +#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE +#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor + * @{ + */ + +#define RCC_HSE_PREDIV_DIV1 0x00000000U + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 +#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 +#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 +#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 +#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 +#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 +#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 +#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 +#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 +#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 +#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 +#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 +#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 +#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 +#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 +#else +#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor + * @{ + */ + +#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ +#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ +#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ +#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ +#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ +#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ +#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ +#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ +#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ +#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ +#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ +#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ +#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ +#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ +#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ +#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCCEx_PLL2_Config PLL Config + * @{ + */ +#define RCC_PLL2_NONE 0x00000000U +#define RCC_PLL2_OFF 0x00000001U +#define RCC_PLL2_ON 0x00000002U + +/** + * @} + */ + +/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor + * @{ + */ + +#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ +#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ +#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ +#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ +#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ +#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ +#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ +#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ +#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ + +/** + * @} + */ + +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#else +#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 +#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 +#endif /* STM32F105xC || STM32F107xC */ +#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 +#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 +#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 +#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 +#else +#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 +#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 +#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 +#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 +#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) +#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) +#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) +#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) +#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) +#if defined(STM32F105xC) || defined(STM32F107xC) +#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) +#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) +#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) +#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) +#endif /* STM32F105xC || STM32F107xC*/ +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Interrupt RCCEx Interrupt + * @{ + */ +#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) +#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) +/** + * @} + */ + +/** @defgroup RCCEx_Flag RCCEx Flag + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - XX : Register index + * - 01: CR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC*/ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ + || defined (STM32F100xE) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined (STM32F100xE) +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ + +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) + + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ + UNUSED(tmpreg); \ + } while(0U) + + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) +#endif /* STM32F105xC || STM32F107xC*/ + +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) + +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0U) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0U) + +#endif /* STM32F107xC*/ + +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ + || defined (STM32F100xE) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined (STM32F100xE) +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) +#endif /* STM32F103xE || STM32F103xG */ +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) +#endif /* STM32F105xC || STM32F107xC*/ +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) +#endif /* STM32F107xC*/ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ + || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined (STM32F100xE) +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#endif /* STM32F100xB || STM32F100xE */ + +#ifdef STM32F100xE +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#endif /* STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#endif /* STM32F101xG || STM32F103xG*/ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ + || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ +#if defined(STM32F100xB) || defined (STM32F100xE) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#endif /* STM32F100xB || STM32F100xE */ +#ifdef STM32F100xE +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#endif /* STM32F100xE */ +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#endif /* STM32F105xC || STM32F107xC */ +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#endif /* STM32F101xG || STM32F103xG*/ + +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ + || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ + || defined(STM32F103xG) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xB) || defined(STM32F100xE) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) +#endif /* STM32F100xB || STM32F100xE */ + +#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ + || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ + || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) +#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ + +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xE) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) +#endif /* STM32F100xE */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +#endif /* STM32F101xG || STM32F103xG */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ + || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ + || defined(STM32F103xG) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ +#if defined(STM32F100xB) || defined(STM32F100xE) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) +#endif /* STM32F100xB || STM32F100xE */ +#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ + || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ + || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) +#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#endif /* STM32F103xE || STM32F103xG */ +#if defined(STM32F100xE) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) +#endif /* STM32F100xE */ +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +#endif /* STM32F101xG || STM32F103xG */ + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) +#endif /* STM32F107xC */ + +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) +#if defined(STM32F107xC) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) +#endif /* STM32F107xC */ + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) + +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ + || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) + +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F100xB) || defined (STM32F100xE) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#endif /* STM32F100xB || STM32F100xE */ + +#if defined (STM32F100xE) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) + +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#endif /* STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) + +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) + +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#endif /* STM32F101xG || STM32F103xG */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ + +#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ + || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ + || defined(STM32F103xG) +#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) + +#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) +#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xB) || defined(STM32F100xE) +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) + +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) +#endif /* STM32F100xB || STM32F100xE */ + +#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ + || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ + || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ + || defined(STM32F107xC) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) +#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ + +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ + || defined(STM32F103xG) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) + +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ + +#if defined(STM32F103xE) || defined(STM32F103xG) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) + +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F100xE) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) + +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) +#endif /* STM32F100xE */ + +#if defined(STM32F101xG) || defined(STM32F103xG) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) + +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +#endif /* STM32F101xG || STM32F103xG*/ + +/** + * @} + */ + +/** @defgroup RCCEx_HSE_Configuration HSE Configuration + * @{ + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) +#else +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ + MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) + +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) +/** + * @brief Macro to get prediv1 factor for PLL. + */ +#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) + +#else +/** + * @brief Macro to get prediv1 factor for PLL. + */ +#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) + +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration + * @{ + */ + +/** @brief Macros to enable the main PLLI2S. + * @note After enabling the main PLLI2S, the application software should wait on + * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can + * be used as system clock source. + * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) + +/** @brief Macros to disable the main PLLI2S. + * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) + +/** @brief macros to configure the main PLLI2S multiplication factor. + * @note This function must be used only when the main PLLI2S is disabled. + * + * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 + * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 + * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 + * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 + * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 + * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 + * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 + * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 + * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 + * + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) + +/** + * @} + */ + +#endif /* STM32F105xC || STM32F107xC */ + +/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration + * @brief Macros to configure clock source of different peripherals. + * @{ + */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) +/** @brief Macro to configure the USB clock. + * @param __USBCLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) + +/** @brief Macro to get the USB clock (USBCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) + +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + +/** @brief Macro to configure the USB OTSclock. + * @param __USBCLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) + +/** @brief Macro to get the USB clock (USBCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) + +#endif /* STM32F105xC || STM32F107xC */ + +/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). + * @param __ADCCLKSOURCE__ specifies the ADC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock + */ +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) + +/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock + * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + +/** @addtogroup RCCEx_HSE_Configuration + * @{ + */ + +/** + * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. + * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock + * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and + * then change the PREDIV2 factor. + * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. + * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) + +/** + * @brief Macro to get prediv2 factor for PLL2 & PLL3. + */ +#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) + +/** + * @} + */ + +/** @addtogroup RCCEx_PLLI2S_Configuration + * @{ + */ + +/** @brief Macros to enable the main PLL2. + * @note After enabling the main PLL2, the application software should wait on + * PLL2RDY flag to be set indicating that PLL2 clock is stable and can + * be used as system clock source. + * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) + +/** @brief Macros to disable the main PLL2. + * @note The main PLL2 can not be disabled if it is used indirectly as system clock source + * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) + +/** @brief macros to configure the main PLL2 multiplication factor. + * @note This function must be used only when the main PLL2 is disabled. + * + * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 + * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 + * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 + * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 + * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 + * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 + * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 + * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 + * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 + * + */ +#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) + +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Configuration I2S Configuration + * @brief Macros to configure clock source of I2S peripherals. + * @{ + */ + +/** @brief Macro to configure the I2S2 clock. + * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) + +/** @brief Macro to get the I2S2 clock (I2S2CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) + +/** @brief Macro to configure the I2S3 clock. + * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) + +/** @brief Macro to get the I2S3 clock (I2S3CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry + * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry + */ +#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) + +/** + * @} + */ + +#endif /* STM32F105xC || STM32F107xC */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); + +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h new file mode 100644 index 0000000..cb0f947 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h @@ -0,0 +1,607 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rtc.h + * @author MCD Application Team + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RTC_H +#define __STM32F1xx_HAL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @addtogroup RTC_Private_Macros + * @{ + */ + +#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) +#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A) +#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \ + ((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \ + ((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \ + ((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND)) + + +/** + * @} + */ + +/** @addtogroup RTC_Private_Constants + * @{ + */ +/** @defgroup RTC_Timeout_Value Default Timeout Value + * @{ + */ +#define RTC_TIMEOUT_VALUE 1000U +/** + * @} + */ + +/** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event + * @{ + */ +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types + * @{ + */ +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + +} RTC_TimeTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ + + uint32_t Alarm; /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1). + This parameter can be a value of @ref RTC_Alarms_Definitions */ +} RTC_AlarmTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ + +} HAL_RTCStateTypeDef; + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF or RTC_AUTO_1_SECOND + If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC Tamper pin. + This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */ + +} RTC_InitTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate). + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ + +} RTC_DateTypeDef; + +/** + * @brief Time Handle Structure definition + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +typedef struct __RTC_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +{ + RTC_TypeDef *Instance; /*!< Register base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + RTC_DateTypeDef DateToUpdate; /*!< Current date set by user and updated automatically */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ + + void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ + + void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ + + void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ + +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + +} RTC_HandleTypeDef; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RTC Callback ID enumeration definition + */ +typedef enum +{ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */ + HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */ +} HAL_RTC_CallbackIDTypeDef; + +/** + * @brief HAL RTC Callback pointer definition + */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC Exported Constants + * @{ + */ + +/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase + * @{ + */ +#define RTC_AUTO_1_SECOND 0xFFFFFFFFU + +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format + * @{ + */ +#define RTC_FORMAT_BIN 0x000000000U +#define RTC_FORMAT_BCD 0x000000001U + +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions Month Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x00) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions Alarms Definitions + * @{ + */ +#define RTC_ALARM_A 0U /*!< Specify alarm ID (mainly for legacy purposes) */ + +/** + * @} + */ + + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin + * @{ + */ + +#define RTC_OUTPUTSOURCE_NONE 0x00000000U /*!< No output on the TAMPER pin */ +#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */ +#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */ +#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */ + +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions + * @{ + */ +#define RTC_IT_OW RTC_CRH_OWIE /*!< Overflow interrupt */ +#define RTC_IT_ALRA RTC_CRH_ALRIE /*!< Alarm interrupt */ +#define RTC_IT_SEC RTC_CRH_SECIE /*!< Second interrupt */ +#define RTC_IT_TAMP1 BKP_CSR_TPIE /*!< TAMPER Pin interrupt enable */ +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions Flags Definitions + * @{ + */ +#define RTC_FLAG_RTOFF RTC_CRL_RTOFF /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF RTC_CRL_RSF /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW RTC_CRL_OWF /*!< Overflow flag */ +#define RTC_FLAG_ALRAF RTC_CRL_ALRF /*!< Alarm flag */ +#define RTC_FLAG_SEC RTC_CRL_SECF /*!< Second flag */ +#define RTC_FLAG_TAMP1F BKP_CSR_TEF /*!< Tamper Interrupt Flag */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_macros RTC Exported Macros + * @{ + */ + +/** @brief Reset RTC handle state + * @param __HANDLE__: RTC handle. + * @retval None + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0u) +#else +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Disable the write protection for RTC registers. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF) + +/** + * @brief Enable the write protection for RTC registers. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF) + +/** + * @brief Enable the RTC Alarm interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Disable the RTC Alarm interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Alarm's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @retval None + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Check whether the specified RTC Alarm interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Alarm's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @retval None + */ +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__) + +/** + * @brief Enable interrupt on ALARM Exti Line 17. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable interrupt on ALARM Exti Line 17. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Enable event on ALARM Exti Line 17. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable event on ALARM Exti Line 17. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT) + + +/** + * @brief ALARM EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT) + + +/** + * @brief Disable the ALARM Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT) + + +/** + * @brief ALARM EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable the ALARM Extended Interrupt Rising Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief ALARM EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do{ \ + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do{ \ + __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Check whether the specified ALARM EXTI interrupt flag is set or not. + * @retval EXTI ALARM Line Status. + */ +#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Clear the ALARM EXTI flag. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT) +/** + * @} + */ + +/* Include RTC HAL Extension module */ +#include "stm32f1xx_hal_rtc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_Exported_Functions + * @{ + */ + + +/* Initialization and de-initialization functions ****************************/ +/** @addtogroup RTC_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* RTC Time and Date functions ************************************************/ +/** @addtogroup RTC_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +/** + * @} + */ + +/* RTC Alarm functions ********************************************************/ +/** @addtogroup RTC_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/* Peripheral State functions *************************************************/ +/** @addtogroup RTC_Exported_Functions_Group4 + * @{ + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/** @addtogroup RTC_Exported_Functions_Group5 + * @{ + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RTC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h new file mode 100644 index 0000000..9185b6e --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h @@ -0,0 +1,412 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rtc_ex.h + * @author MCD Application Team + * @brief Header file of RTC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_RTC_EX_H +#define __STM32F1xx_HAL_RTC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTCEx + * @{ + */ + +/** @addtogroup RTCEx_Private_Macros + * @{ + */ + +/** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy + * @{ + */ +#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler + +/** + * @} + */ + +/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters + * @{ + */ +#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1) + +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + +#if RTC_BKP_NUMBER > 10U +#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42))) +#else +#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER) +#endif +#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Types RTCEx Exported Types + * @{ + */ +/** + * @brief RTC Tamper structure definition + */ +typedef struct +{ + uint32_t Tamper; /*!< Specifies the Tamper Pin. + This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ + + uint32_t Trigger; /*!< Specifies the Tamper Trigger. + This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ + +} RTC_TamperTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants + * @{ + */ + +/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions + * @{ + */ +#define RTC_TAMPER_1 BKP_CR_TPE /*!< Select tamper to be enabled (mainly for legacy purposes) */ + +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions + * @{ + */ +#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ + +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions + * @{ + */ +#if RTC_BKP_NUMBER > 0U +#define RTC_BKP_DR1 0x00000001U +#define RTC_BKP_DR2 0x00000002U +#define RTC_BKP_DR3 0x00000003U +#define RTC_BKP_DR4 0x00000004U +#define RTC_BKP_DR5 0x00000005U +#define RTC_BKP_DR6 0x00000006U +#define RTC_BKP_DR7 0x00000007U +#define RTC_BKP_DR8 0x00000008U +#define RTC_BKP_DR9 0x00000009U +#define RTC_BKP_DR10 0x0000000AU +#endif /* RTC_BKP_NUMBER > 0 */ + +#if RTC_BKP_NUMBER > 10U +#define RTC_BKP_DR11 0x00000010U +#define RTC_BKP_DR12 0x00000011U +#define RTC_BKP_DR13 0x00000012U +#define RTC_BKP_DR14 0x00000013U +#define RTC_BKP_DR15 0x00000014U +#define RTC_BKP_DR16 0x00000015U +#define RTC_BKP_DR17 0x00000016U +#define RTC_BKP_DR18 0x00000017U +#define RTC_BKP_DR19 0x00000018U +#define RTC_BKP_DR20 0x00000019U +#define RTC_BKP_DR21 0x0000001AU +#define RTC_BKP_DR22 0x0000001BU +#define RTC_BKP_DR23 0x0000001CU +#define RTC_BKP_DR24 0x0000001DU +#define RTC_BKP_DR25 0x0000001EU +#define RTC_BKP_DR26 0x0000001FU +#define RTC_BKP_DR27 0x00000020U +#define RTC_BKP_DR28 0x00000021U +#define RTC_BKP_DR29 0x00000022U +#define RTC_BKP_DR30 0x00000023U +#define RTC_BKP_DR31 0x00000024U +#define RTC_BKP_DR32 0x00000025U +#define RTC_BKP_DR33 0x00000026U +#define RTC_BKP_DR34 0x00000027U +#define RTC_BKP_DR35 0x00000028U +#define RTC_BKP_DR36 0x00000029U +#define RTC_BKP_DR37 0x0000002AU +#define RTC_BKP_DR38 0x0000002BU +#define RTC_BKP_DR39 0x0000002CU +#define RTC_BKP_DR40 0x0000002DU +#define RTC_BKP_DR41 0x0000002EU +#define RTC_BKP_DR42 0x0000002FU +#endif /* RTC_BKP_NUMBER > 10 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros + * @{ + */ + +/** + * @brief Enable the RTC Tamper interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP1: Tamper A interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__)) + +/** + * @brief Disable the RTC Tamper interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP1: Tamper A interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked. + * This parameter can be: + * @arg RTC_IT_TAMP1 + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked. + * This parameter can be: + * @arg RTC_IT_TAMP1 + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI) + +/** + * @brief Enable the RTC Second interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled + * This parameter can be any combination of the following values: + * @arg RTC_IT_SEC: Second A interrupt + * @retval None + */ +#define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Disable the RTC Second interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_SEC: Second A interrupt + * @retval None + */ +#define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Second interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_SEC: Second A interrupt + * @retval None + */ +#define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Second's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_SEC + * @retval None + */ +#define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Second's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_SEC + * @retval None + */ +#define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__) + +/** + * @brief Enable the RTC Overflow interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow A interrupt + * @retval None + */ +#define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Disable the RTC Overflow interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow A interrupt + * @retval None + */ +#define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Overflow interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_OW: Overflow A interrupt + * @retval None + */ +#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Overflow's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_OW + * @retval None + */ +#define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Overflow's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_OW + * @retval None + */ +#define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTCEx_Exported_Functions + * @{ + */ + +/* RTC Tamper functions *****************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); + +/** + * @} + */ + +/* RTC Second functions *****************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc); + +/** + * @} + */ + +/* Extension Control functions ************************************************/ +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @{ + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); + +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_RTC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h new file mode 100644 index 0000000..482d876 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h @@ -0,0 +1,727 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_SPI_H +#define STM32F1xx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Code SPI Error Code + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000U) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000U) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_8BIT (0x00000000U) +#define SPI_DATASIZE_16BIT SPI_CR1_DFF +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000U) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000U) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT (0x00000000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000U) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000U) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\ + | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0U) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */ +#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of SPI SR regsiter. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @retval SET or RESET. + */ +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of SPI CR2 regsiter. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Select management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is disabled. + * @param __MODE__ SPI_TIMODE_DISABLE. Device not support Ti Mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) + +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h new file mode 100644 index 0000000..8fcffda --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h @@ -0,0 +1,2018 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_TIM_H +#define STM32F1xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP))) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P))) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f1xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F1xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h new file mode 100644 index 0000000..265ca96 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h @@ -0,0 +1,261 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_HAL_TIM_EX_H +#define STM32F1xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F1xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h new file mode 100644 index 0000000..15e7fc9 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h @@ -0,0 +1,852 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_UART_H +#define __STM32F1xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UART_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. This feature is only available + on STM32F100xx family, so OverSampling parameter should always be set to 16. */ +} UART_InitTypeDef; + +/** + * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef enum +{ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ +} HAL_UART_StateTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_Error_Code UART Error Code + * @{ + */ +#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ +#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Word_Length UART Word Length + * @{ + */ +#define UART_WORDLENGTH_8B 0x00000000U +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_1 0x00000000U +#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U +#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U +#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) +#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX ((uint32_t)USART_CR1_RE) +#define UART_MODE_TX ((uint32_t)USART_CR1_TE) +#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U +#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U +#if defined(USART_CR1_OVER8) +#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) +#endif /* USART_CR1_OVER8 */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U +#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) +/** + * @} + */ + +/** @defgroup UART_WakeUp_functions UART Wakeup Functions + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U +#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) +/** + * @} + */ + +/** @defgroup UART_Flags UART FLags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the SR register + * @{ + */ +#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) +#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) +#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define UART_FLAG_TC ((uint32_t)USART_SR_TC) +#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define UART_FLAG_NE ((uint32_t)USART_SR_NE) +#define UART_FLAG_FE ((uint32_t)USART_SR_FE) +#define UART_FLAG_PE ((uint32_t)USART_SR_PE) +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupt Definitions + * Elements values convention: 0xY000XXXX + * - XXXX : Interrupt mask (16 bits) in the Y register + * - Y : Interrupt source register (2bits) + * - 0001: CR1 register + * - 0010: CR2 register + * - 0011: CR3 register + * @{ + */ + +#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) +#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) +#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) +#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) +#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) + +#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) + +#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) +#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle gstate & RxState + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flushes the UART DR register + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + +/** @brief Checks whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg UART_FLAG_LBD: LIN Break detection flag + * @arg UART_FLAG_TXE: Transmit data register empty flag + * @arg UART_FLAG_TC: Transmission Complete flag + * @arg UART_FLAG_RXNE: Receive data register not empty flag + * @arg UART_FLAG_IDLE: Idle Line detection flag + * @arg UART_FLAG_ORE: Overrun Error flag + * @arg UART_FLAG_NE: Noise Error flag + * @arg UART_FLAG_FE: Framing Error flag + * @arg UART_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg UART_FLAG_LBD: LIN Break detection flag. + * @arg UART_FLAG_TC: Transmission Complete flag. + * @arg UART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register followed by a read + * operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clears the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + } while(0U) + +/** @brief Clears the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Checks whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __IT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_ERR: Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) + +/** @brief Enable CTS flow control + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control + * This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control + * This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +#if defined(USART_CR3_ONEBIT) + +/** @brief Macro to enable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Macro to disable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) +#endif /* UART_ONE_BIT_SAMPLE_Feature */ + +/** @brief Enable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +/** @brief UART interruptions flag mask + * + */ +#define UART_IT_MASK 0x0000FFFFU + +#define UART_CR1_REG_INDEX 1U +#define UART_CR2_REG_INDEX 2U +#define UART_CR3_REG_INDEX 3U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ + ((STOPBITS) == UART_STOPBITS_2)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ + ((PARITY) == UART_PARITY_EVEN) || \ + ((PARITY) == UART_PARITY_ODD)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS) || \ + ((CONTROL) == UART_HWCONTROL_CTS) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) +#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) +#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ + ((STATE) == UART_STATE_ENABLE)) +#if defined(USART_CR1_OVER8) +#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ + ((SAMPLING) == UART_OVERSAMPLING_8)) +#endif /* USART_CR1_OVER8 */ +#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) +#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) +#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4500000U) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) + +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) +#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ +#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) + +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) +#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ +#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ + ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ + (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_UART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h new file mode 100644 index 0000000..672a214 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h @@ -0,0 +1,651 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_usb.h + * @author MCD Application Team + * @brief Header file of USB Low Layer HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F1xx_LL_USB_H +#define STM32F1xx_LL_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +#if defined (USB) || defined (USB_OTG_FS) +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup USB_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief USB Mode definition + */ +#if defined (USB_OTG_FS) + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; + +/** + * @brief URB States definition + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL +} USB_OTG_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_OTG_HCStateTypeDef; + +/** + * @brief USB OTG Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref USB_Core_PHY_ */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + + uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ +} USB_OTG_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_EP_Type_ */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ +} USB_OTG_EPTypeDef; + +typedef struct +{ + uint8_t dev_addr ; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_EP_Type_ */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count.*/ + + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ +} USB_OTG_HCTypeDef; +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) + +typedef enum +{ + USB_DEVICE_MODE = 0 +} USB_ModeTypeDef; + +/** + * @brief USB Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref USB_Core_PHY */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ + + uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ +} USB_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_EP_Type */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ + + uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral + This parameter is added to ensure compatibility across USB peripherals */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + +} USB_EPTypeDef; +#endif /* defined (USB) */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +#if defined (USB_OTG_FS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_FS_SPEED 2U +#define USBH_FS_SPEED 1U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_FS_SPEED 2U +/** + * @} + */ + +#define BTABLE_ADDRESS 0x000U +#define PMA_ACCESS 2U +#endif /* defined (USB) */ +#if defined (USB_OTG_FS) +#define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_FS) */ +#if defined (USB) +#define EP_ADDR_MSK 0x7U +#endif /* defined (USB) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_FS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup); +uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc); +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); +void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup); +uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); +uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); +void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +#endif /* defined (USB) */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB) || defined (USB_OTG_FS) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F1xx_LL_USB_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c new file mode 100644 index 0000000..34ed588 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c @@ -0,0 +1,596 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32F1xx HAL Driver version number V1.1.4 + */ +#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32F1xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ +#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ + |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32F1xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK 0x00000FFFU + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) de-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) +#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \ + defined(STM32F102x6) || defined(STM32F102xB) || \ + defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ + defined(STM32F105xC) || defined(STM32F107xC) + + /* Prefetch buffer is not available on value line devices */ + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + +#if defined(STM32F105xC) || defined(STM32F107xC) + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); +#endif + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status == HAL_OK) + { + uwTickFreq = Freq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Returns the HAL revision + * @retval version 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F1xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Returns the device identifier. + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * Note: On all STM32F1 devices: + * If the system tick timer interrupt is enabled during the Stop mode + * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup + * the system from Stop mode. + * Workaround: To debug the Stop mode, disable the system tick timer + * interrupt. + * Refer to errata sheet of these devices for more details. + * Note: On all STM32F1 devices: + * If the system tick timer interrupt is enabled during the Stop mode + * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup + * the system from Stop mode. + * Workaround: To debug the Stop mode, disable the system tick timer + * interrupt. + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * Note: On devices STM32F10xx8 and STM32F10xxB, + * STM32F101xC/D/E and STM32F103xC/D/E, + * STM32F101xF/G and STM32F103xF/G + * STM32F10xx4 and STM32F10xx6 + * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in + * debug mode (not accessible by the user software in normal mode). + * Refer to errata sheet of these devices for more details. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c new file mode 100644 index 0000000..a89150a --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c @@ -0,0 +1,505 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M3 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value 0x0F. + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f1xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup: The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) + * @param PreemptPriority: The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority: the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00U; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != RESET) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00U; + MPU->RASR = 0x00U; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @param PriorityGroup: the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c new file mode 100644 index 0000000..c9bc061 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c @@ -0,0 +1,899 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to the Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Channel, program the required configuration through the following parameters: + Channel request, Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e. a member of DMA handle structure). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + + /* Check the DMA handle allocation */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->DmaBaseAddress = DMA2; + } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; +#endif /* DMA2 */ + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + hdma->Instance->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + hdma->Instance->CPAR = 0U; + + /* Reset DMA Channel memory address register */ + hdma->Instance->CMAR = 0U; + +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->DmaBaseAddress = DMA2; + } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; +#endif /* DMA2 */ + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if(NULL != hdma->XferHalfCpltCallback) + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + } + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + } + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel: Specifies the DMA level complete. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0U; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); + } + else + { + /* Half Transfer Complete flag */ + temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) + { + if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Update error code */ + SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + return; +} + +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback: pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA hande state. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + /* Return DMA handle state */ + return hdma->State; +} + +/** + * @brief Return the DMA error code. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c new file mode 100644 index 0000000..44daaff --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c @@ -0,0 +1,559 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = AFIO->EXTICR[linepos >> 2u]; + regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + AFIO->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = AFIO->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + else + { + pExtiConfig->GPIOSel = 0x00u; + } + } + else + { + /* No Trigger selected */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = AFIO->EXTICR[linepos >> 2u]; + regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + AFIO->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t maskline; + uint32_t linepos; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c new file mode 100644 index 0000000..50abf92 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c @@ -0,0 +1,967 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F1xx devices. + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page, erase all pages + (++) Program functions: half word, word and doubleword + (#) FLASH Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + (++) Erase Option Bytes + (++) Program the data Option Bytes + (++) Get the Write protection. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the half cycle access + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro ---------------------------- ---------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim +@endverbatim + * @{ + */ + +/** + * @brief Program halfword, word or double word at a specified address + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @note FLASH should be previously erased before new programmation (only exception to this + * is when 0x0000 is programmed) + * + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint8_t index = 0; + uint8_t nbiterations = 0; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + +#if defined(FLASH_BANK2_END) + if(Address <= FLASH_BANK1_END) + { +#endif /* FLASH_BANK2_END */ + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +#if defined(FLASH_BANK2_END) + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_BANK2_END */ + + if(status == HAL_OK) + { + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /* Program halfword (16-bit) at a specified address. */ + nbiterations = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /* Program word (32-bit = 2*16-bit) at a specified address. */ + nbiterations = 2U; + } + else + { + /* Program double word (64-bit = 4*16-bit) at a specified address. */ + nbiterations = 4U; + } + + for (index = 0U; index < nbiterations; index++) + { + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + +#if defined(FLASH_BANK2_END) + if(Address <= FLASH_BANK1_END) + { +#endif /* FLASH_BANK2_END */ + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); +#if defined(FLASH_BANK2_END) + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); + } +#endif /* FLASH_BANK2_END */ + /* In case of error, stop programation procedure */ + if (status != HAL_OK) + { + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program halfword, word or double word at a specified address with interrupt enabled. + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param TypeProgram: Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address: Specifies the address to be programmed. + * @param Data: Specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + +#if defined(FLASH_BANK2_END) + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + if(Address <= FLASH_BANK1_END) + { + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1); + + }else + { + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); + } +#else + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); +#endif /* FLASH_BANK2_END */ + + pFlash.Address = Address; + pFlash.Data = Data; + + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + /* Program halfword (16-bit) at a specified address. */ + pFlash.DataRemaining = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + /* Program word (32-bit : 2*16-bit) at a specified address. */ + pFlash.DataRemaining = 2U; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + /* Program double word (64-bit : 4*16-bit) at a specified address. */ + pFlash.DataRemaining = 4U; + } + + /* Program halfword (16-bit) at a specified address. */ + FLASH_Program_HalfWord(Address, (uint16_t)Data); + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))) +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) +#endif /* FLASH_BANK2_END */ + { + /* Return the faulty address */ + addresstmp = pFlash.Address; + /* Reset address */ + pFlash.Address = 0xFFFFFFFFU; + + /* Save the Error code */ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1); +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); +#endif /* FLASH_BANK2_END */ + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase */ + if(pFlash.DataRemaining != 0U) + { + addresstmp = pFlash.Address; + /*Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + addresstmp = pFlash.Address + FLASH_PAGE_SIZE; + pFlash.Address = addresstmp; + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ + pFlash.Address = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + +#if defined(FLASH_BANK2_END) + /* Stop Mass Erase procedure if no pending mass erase on other bank */ + if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) + { +#endif /* FLASH_BANK2_END */ + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0U); + + /* Stop Mass Erase procedure*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } +#if defined(FLASH_BANK2_END) + } +#endif /* FLASH_BANK2_END */ + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2U; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); + } + + /* Reset Address and stop Program procedure */ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } + +#if defined(FLASH_BANK2_END) + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase*/ + if(pFlash.DataRemaining != 0U) + { + /* Indicate user which page address has been erased*/ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + + /* Increment page address to next page */ + pFlash.Address += FLASH_PAGE_SIZE; + addresstmp = pFlash.Address; + + /* Operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /*No more pages to Erase*/ + + /*Reset Address and stop Erase pages procedure*/ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); + + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) + { + /* MassErase ended. Return the selected bank*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0U); + + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2U; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U); + } + + /* Reset Address and stop Program procedure*/ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } +#endif + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { +#if defined(FLASH_BANK2_END) + /* Operation is completed, disable the PG, PER and MER Bits for both bank */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); + + /* Disable End of FLASH Operation and Error source interrupts for both banks */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); +#else + /* Operation is completed, disable the PG, PER and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); +#endif /* FLASH_BANK2_END */ + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } +#if defined(FLASH_BANK2_END) + if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) + { + /* Authorize the FLASH BANK2 Registers access */ + WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + + /* Verify Flash BANK2 is unlocked */ + if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) + { + status = HAL_ERROR; + } + } +#endif /* FLASH_BANK2_END */ + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + +#if defined(FLASH_BANK2_END) + /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ + SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); + +#endif /* FLASH_BANK2_END */ + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @note This function will reset automatically the MCU. + * @retval None + */ +void HAL_FLASH_OB_Launch(void) +{ + /* Initiates a system reset request to launch the option byte loading */ + HAL_NVIC_SystemReset(); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @ref FLASH_Error_Codes + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined(FLASH_BANK2_END) + if(Address <= FLASH_BANK1_END) + { +#endif /* FLASH_BANK2_END */ + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); +#if defined(FLASH_BANK2_END) + } + else + { + /* Proceed to program the new data */ + SET_BIT(FLASH->CR2, FLASH_CR2_PG); + } +#endif /* FLASH_BANK2_END */ + + /* Write data in the address */ + *(__IO uint16_t*)Address = Data; +} + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + +#if defined(FLASH_BANK2_END) +/** + * @brief Wait for a FLASH BANK2 operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) +{ + /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset. + Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* If there is an error flag set */ + return HAL_OK; + +} +#endif /* FLASH_BANK2_END */ + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + uint32_t flags = 0U; + +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) +#endif /* FLASH_BANK2_END */ + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; +#if defined(FLASH_BANK2_END) + flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; +#else + flags |= FLASH_FLAG_WRPERR; +#endif /* FLASH_BANK2_END */ + } +#if defined(FLASH_BANK2_END) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) +#else + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) +#endif /* FLASH_BANK2_END */ + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; +#if defined(FLASH_BANK2_END) + flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; +#else + flags |= FLASH_FLAG_PGERR; +#endif /* FLASH_BANK2_END */ + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); + } + + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c new file mode 100644 index 0000000..ebd6f8b --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c @@ -0,0 +1,1127 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * + Extended Initialization/de-initialization functions + * + Extended I/O operation functions + * + Extended Peripheral Control functions + * + @verbatim + ============================================================================== + ##### Flash peripheral extended features ##### + ============================================================================== + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F1xxx devices. It includes + + (++) Set/Reset the write protection + (++) Program the user Option Bytes + (++) Get the Read protection Level + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos +#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos +#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +/* Erase operations */ +static void FLASH_MassErase(uint32_t Banks); +void FLASH_PageErase(uint32_t PageAddress); + +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); +static uint32_t FLASH_OB_GetWRP(void); +static uint32_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) @ref HAL_FLASHEx_Erase: return only when erase has been done + (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback + is called with parameter 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + +@endverbatim + * @{ + */ + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t address = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { +#if defined(FLASH_BANK2_END) + if (pEraseInit->Banks == FLASH_BANK_BOTH) + { + /* Mass Erase requested for Bank1 and Bank2 */ + /* Wait for last operation to be completed */ + if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ + (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) + { + /*Mass erase to be done*/ + FLASH_MassErase(FLASH_BANK_BOTH); + + /* Wait for last operation to be completed */ + if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \ + (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) + { + status = HAL_OK; + } + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); + } + } + else if (pEraseInit->Banks == FLASH_BANK_2) + { + /* Mass Erase requested for Bank2 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(FLASH_BANK_2); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); + } + } + else +#endif /* FLASH_BANK2_END */ + { + /* Mass Erase requested for Bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(FLASH_BANK_1); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + } + } + } + else + { + /* Page Erase is requested */ + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + +#if defined(FLASH_BANK2_END) + /* Page Erase requested on address located on bank2 */ + if(pEraseInit->PageAddress > FLASH_BANK1_END) + { + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase by page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + else +#endif /* FLASH_BANK2_END */ + { + /* Page Erase requested on address located on bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + +#if defined(FLASH_BANK2_END) + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); + +#endif + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + FLASH_MassErase(pEraseInit->Banks); + } + else + { + /* Erase by page to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.DataRemaining = pEraseInit->NbPages; + pFlash.Address = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_PageErase(pEraseInit->PageAddress); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + option bytes operations. + +@endverbatim + * @{ + */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) +{ + uint8_t rdptmp = OB_RDP_LEVEL_0; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Get the actual read protection Option Byte value */ + rdptmp = FLASH_OB_GetRDP(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Restore the last read protection Option Byte value */ + status = FLASH_OB_RDP_LevelConfig(rdptmp); + } + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program option bytes + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected page */ + status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + } + else + { + /* Disable of Write protection on the selected page */ + status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + } + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* DATA configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + { + status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + + /*Get WRP*/ + pOBInit->WRPPage = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); +} + +/** + * @brief Get the Option byte user data + * @param DATAAdress Address of the option byte DATA + * This parameter can be one of the following values: + * @arg @ref OB_DATA_ADDRESS_DATA0 + * @arg @ref OB_DATA_ADDRESS_DATA1 + * @retval Value programmed in USER data + */ +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) +{ + uint32_t value = 0; + + if (DATAAdress == OB_DATA_ADDRESS_DATA0) + { + /* Get value programmed in OB USER Data0 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; + } + else + { + /* Get value programmed in OB USER Data1 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; + } + + return value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Full erase of FLASH memory Bank + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg @ref FLASH_BANK_1 Bank1 to be erased + @if STM32F101xG + * @arg @ref FLASH_BANK_2 Bank2 to be erased + * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased + @endif + @if STM32F103xG + * @arg @ref FLASH_BANK_2 Bank2 to be erased + * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased + @endif + * + * @retval None + */ +static void FLASH_MassErase(uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined(FLASH_BANK2_END) + if(Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR2, FLASH_CR2_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + SET_BIT(FLASH->CR2, FLASH_CR2_STRT); + } + else if(Banks == FLASH_BANK_2) + { + /*Only bank2 will be erased*/ + SET_BIT(FLASH->CR2, FLASH_CR2_MER); + SET_BIT(FLASH->CR2, FLASH_CR2_STRT); + } + else + { +#endif /* FLASH_BANK2_END */ +#if !defined(FLASH_BANK2_END) + /* Prevent unused argument(s) compilation warning */ + UNUSED(Banks); +#endif /* FLASH_BANK2_END */ + /* Only bank1 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +#if defined(FLASH_BANK2_END) + } +#endif /* FLASH_BANK2_END */ +} + +/** + * @brief Enable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write protected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFF; +#if defined(FLASH_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFF; +#endif /* FLASH_WRP1_WRP1 */ +#if defined(FLASH_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFF; +#endif /* FLASH_WRP2_WRP2 */ +#if defined(FLASH_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFF; +#endif /* FLASH_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be protected ******/ + WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES64TO95MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); +#endif /* OB_WRP_PAGES64TO95MASK */ +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES96TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO255MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO511MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES96TO127MASK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + /* Enable write protection */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP0_WRP0 */ + +#if defined(FLASH_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP1_WRP1 */ + +#if defined(FLASH_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP2_WRP2 */ + +#if defined(FLASH_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Disable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write unprotected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFF; +#if defined(FLASH_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFF; +#endif /* FLASH_WRP1_WRP1 */ +#if defined(FLASH_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFF; +#endif /* FLASH_WRP2_WRP2 */ +#if defined(FLASH_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFF; +#endif /* FLASH_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be unprotected ******/ + WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES64TO95MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); +#endif /* OB_WRP_PAGES64TO95MASK */ +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES96TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO255MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO511MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES96TO127MASK */ + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 |= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP0_WRP0 */ + +#if defined(FLASH_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 |= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP1_WRP1 */ + +#if defined(FLASH_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 |= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP2_WRP2 */ + +#if defined(FLASH_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 |= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* FLASH_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + return status; +} + +/** + * @brief Set the read protection level. + * @param ReadProtectLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + WRITE_REG(OB->RDP, ReadProtectLevel); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte. + * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), + * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). + * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); + assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); +#if defined(FLASH_BANK2_END) + assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); +#endif /* FLASH_BANK2_END */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_BANK2_END) + OB->USER = (UserConfig | 0xF0U); +#else + OB->USER = (UserConfig | 0x88U); +#endif /* FLASH_BANK2_END */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data specifies the data to be programmed. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enables the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval The FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(READ_REG(FLASH->WRPR)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH RDP level + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t readstatus = OB_RDP_LEVEL_0; + uint32_t tmp_reg = 0U; + + /* Read RDP level bits */ + tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); + + if (tmp_reg == FLASH_OBR_RDPRT) + { + readstatus = OB_RDP_LEVEL_1; + } + else + { + readstatus = OB_RDP_LEVEL_0; + } + + return readstatus; +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), + * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). + * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Erase the specified FLASH memory page + * @param PageAddress FLASH page to erase + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined(FLASH_BANK2_END) + if(PageAddress > FLASH_BANK1_END) + { + /* Proceed to erase the page */ + SET_BIT(FLASH->CR2, FLASH_CR2_PER); + WRITE_REG(FLASH->AR2, PageAddress); + SET_BIT(FLASH->CR2, FLASH_CR2_STRT); + } + else + { +#endif /* FLASH_BANK2_END */ + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, PageAddress); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +#if defined(FLASH_BANK2_END) + } +#endif /* FLASH_BANK2_END */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c new file mode 100644 index 0000000..52ead10 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c @@ -0,0 +1,588 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 20 edge detectors in connectivity + line devices, or 19 edge detectors in other devices for generating event/interrupt requests. + Each input line can be independently configured to select the type (event or interrupt) and + the corresponding trigger event (rising or falling or both). Each line can also masked + independently. A pending register maintains the status line of the interrupt requests + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PD0 and PD1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE 0x00000003u +#define EXTI_MODE 0x10000000u +#define GPIO_MODE_IT 0x00010000u +#define GPIO_MODE_EVT 0x00020000u +#define RISING_EDGE 0x00100000u +#define FALLING_EDGE 0x00200000u +#define GPIO_OUTPUT_TYPE 0x00000010u + +#define GPIO_NUMBER 16u + +/* Definitions for bit manipulation of CRL and CRH register */ +#define GPIO_CR_MODE_INPUT 0x00000000u /*!< 00: Input mode (reset state) */ +#define GPIO_CR_CNF_ANALOG 0x00000000u /*!< 00: Analog mode */ +#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004u /*!< 01: Floating input (reset state) */ +#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008u /*!< 10: Input with pull-up / pull-down */ +#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000u /*!< 00: General purpose output push-pull */ +#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004u /*!< 01: General purpose output Open-drain */ +#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008u /*!< 10: Alternate function output Push-pull */ +#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000Cu /*!< 11: Alternate function output Open-drain */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00u; + uint32_t ioposition; + uint32_t iocurrent; + uint32_t temp; + uint32_t config = 0x00u; + __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ + uint32_t registeroffset; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + { + /* Get the IO position */ + ioposition = (0x01uL << position); + + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if (iocurrent == ioposition) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + + /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ + switch (GPIO_Init->Mode) + { + /* If we are configuring the pin in OUTPUT push-pull mode */ + case GPIO_MODE_OUTPUT_PP: + /* Check the GPIO speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; + break; + + /* If we are configuring the pin in OUTPUT open-drain mode */ + case GPIO_MODE_OUTPUT_OD: + /* Check the GPIO speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; + break; + + /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ + case GPIO_MODE_AF_PP: + /* Check the GPIO speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; + break; + + /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ + case GPIO_MODE_AF_OD: + /* Check the GPIO speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; + break; + + /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ + case GPIO_MODE_INPUT: + case GPIO_MODE_IT_RISING: + case GPIO_MODE_IT_FALLING: + case GPIO_MODE_IT_RISING_FALLING: + case GPIO_MODE_EVT_RISING: + case GPIO_MODE_EVT_FALLING: + case GPIO_MODE_EVT_RISING_FALLING: + /* Check the GPIO pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + if (GPIO_Init->Pull == GPIO_NOPULL) + { + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; + } + else if (GPIO_Init->Pull == GPIO_PULLUP) + { + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + + /* Set the corresponding ODR bit */ + GPIOx->BSRR = ioposition; + } + else /* GPIO_PULLDOWN */ + { + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; + + /* Reset the corresponding ODR bit */ + GPIOx->BRR = ioposition; + } + break; + + /* If we are configuring the pin in INPUT analog mode */ + case GPIO_MODE_ANALOG: + config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; + break; + + /* Parameters are checked with assert_param */ + default: + break; + } + + /* Check if the current bit belongs to first half or last half of the pin count number + in order to address CRH or CRL register*/ + configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; + registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); + + /* Apply the new configuration of the pin to the register */ + MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable AFIO Clock */ + __HAL_RCC_AFIO_CLK_ENABLE(); + temp = AFIO->EXTICR[position >> 2u]; + CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); + AFIO->EXTICR[position >> 2u] = temp; + + + /* Configure the interrupt mask */ + if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + SET_BIT(EXTI->IMR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->IMR, iocurrent); + } + + /* Configure the event mask */ + if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + SET_BIT(EXTI->EMR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->EMR, iocurrent); + } + + /* Enable or disable the rising trigger */ + if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + SET_BIT(EXTI->RTSR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->RTSR, iocurrent); + } + + /* Enable or disable the falling trigger */ + if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + SET_BIT(EXTI->FTSR, iocurrent); + } + else + { + CLEAR_BIT(EXTI->FTSR, iocurrent); + } + } + } + + position++; + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; + __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ + uint32_t registeroffset; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = AFIO->EXTICR[position >> 2u]; + tmp &= 0x0FuL << (4u * (position & 0x03u)); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + { + tmp = 0x0FuL << (4u * (position & 0x03u)); + CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp); + + /* Clear EXTI line configuration */ + CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); + } + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Check if the current bit belongs to first half or last half of the pin count number + in order to address CRH or CRL register */ + configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; + registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); + + /* CRL/CRH default value is floating input(0x04) shifted to correct position */ + MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset); + + /* ODR default value is 0 */ + CLEAR_BIT(GPIOx->ODR, iocurrent); + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the GPIOs. + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; + } +} + +/** + * @brief Toggles the specified GPIO pin + * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != 0x00u) + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence +* has been applied on a port bit, it is no longer possible to modify the value of the port bit until +* the next reset. +* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral +* @param GPIO_Pin: specifies the port bit to be locked. +* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* @retval None +*/ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + SET_BIT(tmp, GPIO_Pin); + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin: Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin: Specifies the pins connected EXTI line + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c new file mode 100644 index 0000000..c2d810c --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_gpio_ex.c + * @author MCD Application Team + * @brief GPIO Extension HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. + * + Extended features functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral extension features ##### + ============================================================================== + [..] GPIO module on STM32F1 family, manage also the AFIO register: + (+) Possibility to use the EVENTOUT Cortex feature + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to use EVENTOUT Cortex feature + (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() + (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() + (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions + * @{ + */ + +/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + ============================================================================== + ##### Extended features functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() + (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() + (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() + +@endverbatim + * @{ + */ + +/** + * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. + * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. + * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. + * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. + * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. + * @retval None + */ +void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) +{ + /* Verify the parameters */ + assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); + assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); + + /* Apply the new configuration */ + MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); +} + +/** + * @brief Enables the Event Output. + * @retval None + */ +void HAL_GPIOEx_EnableEventout(void) +{ + SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); +} + +/** + * @brief Disables the Event Output. + * @retval None + */ +void HAL_GPIOEx_DisableEventout(void) +{ + CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c new file mode 100644 index 0000000..6e74e69 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c @@ -0,0 +1,7187 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State, Mode and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API. + + (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() + or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() + or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() + or using @ref HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() + or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() + or using @ref HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + @ref HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + @ref HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + @ref HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + @ref HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not + (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + [..] + Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + or @ref HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + + *** I2C Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + Below the list of all silicon limitations implemented for HAL on STM32F1xx product. + (@) See ErrataSheet to know full silicon limitation list of your product. + + (+) Workarounds Implemented inside I2C HAL Driver + (++) Wrong data read into data register (Polling and Interrupt mode) + (++) Start cannot be generated after a misplaced Stop + (++) Some software events must be managed before the current byte is being transferred: + Workaround: Use DMA in general, except when the Master is receiving a single byte. + For Interupt mode, I2C should have the highest priority in the application. + (++) Mismatch on the "Setup time for a repeated Start condition" timing parameter: + Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if + supported by the slave. + (++) Data valid time (tVD;DAT) violated without the OVR flag being set: + Workaround: If the slave device allows it, use the clock stretching mechanism + by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in @ref HAL_I2C_Init. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Define + * @{ + */ +#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ +#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +static void I2C_ITError(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); + +/* Private functions for I2C transfer IRQ handler */ +static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); +static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); +static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); +static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); +static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); + +static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); +static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); +static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Duty cycle + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + uint32_t freqrange; + uint32_t pclk1; + + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); + assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + + /* Check the minimum allowed PCLK1 frequency */ + if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) + { + return HAL_ERROR; + } + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address */ + if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until BTF flag is set */ + if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address */ + if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 + software sequence must complete before the current byte end of transfer */ + __disable_irq(); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Re-enable IRQs */ + __enable_irq(); + } + else if (hi2c->XferSize == 2U) + { + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 + software sequence must complete before the current byte end of transfer */ + __disable_irq(); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Re-enable IRQs */ + __enable_irq(); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + if (hi2c->XferSize <= 3U) + { + /* One byte */ + if (hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if (hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 + software sequence must complete before the current byte end of transfer */ + __disable_irq(); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Re-enable IRQs */ + __enable_irq(); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 + software sequence must complete before the current byte end of transfer */ + __disable_irq(); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Re-enable IRQs */ + __enable_irq(); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + } + } + + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == (uint16_t)0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while (hi2c->XferSize > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until BTF flag is set */ + if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 + software sequence must complete before the current byte end of transfer */ + __disable_irq(); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Re-enable IRQs */ + __enable_irq(); + } + else if (hi2c->XferSize == 2U) + { + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 + software sequence must complete before the current byte end of transfer */ + __disable_irq(); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Re-enable IRQs */ + __enable_irq(); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + if (hi2c->XferSize <= 3U) + { + /* One byte */ + if (hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if (hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 + software sequence must complete before the current byte end of transfer */ + __disable_irq(); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Re-enable IRQs */ + __enable_irq(); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 + software sequence must complete before the current byte end of transfer */ + __disable_irq(); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Re-enable IRQs */ + __enable_irq(); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + if (hi2c->XferSize > 0U) + { + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + /* Get tick */ + uint32_t tickstart = HAL_GetTick(); + uint32_t I2C_Trials = 1U; + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + do + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR or AF flag are set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->State = HAL_I2C_STATE_TIMEOUT; + } + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if the ADDR flag has been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear ADDR Flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Increment Trials */ + I2C_Trials++; + } + while (I2C_Trials < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if (hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ + /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ + if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0U; + uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) + { + if (Prev_State == I2C_STATE_MASTER_BUSY_RX) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ + enableIT &= ~I2C_IT_BUF; + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable interrupts */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0U; + uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear Last DMA bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if (hi2c->XferSize > 0U) + { + if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) + { + if (Prev_State == I2C_STATE_MASTER_BUSY_RX) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + } + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Update interrupt for only EVT and ERR */ + enableIT = (I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Update interrupt for only ERR */ + enableIT = I2C_IT_ERR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ + /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ + if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable interrupts */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(DevAddress); + + /* Abort Master transfer during Receive or Transmit process */ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->XferCount = 0U; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t sr1itflags; + uint32_t sr2itflags = 0U; + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + uint32_t CurrentXferOptions = hi2c->XferOptions; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* Master or Memory mode selected */ + if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + sr1itflags = READ_REG(hi2c->Instance->SR1); + + /* Exit IRQ event until Start Bit detected in case of Other frame requested */ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) + { + return; + } + + /* SB Set ----------------------------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + I2C_Master_SB(hi2c); + } + /* ADD10 Set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Master_ADD10(hi2c); + } + /* ADDR Set --------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Master_ADDR(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) + { + /* Do not check buffer and BTF flag if a Xfer DMA is on going */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_MasterTransmit_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* Do not check buffer and BTF flag if a Xfer DMA is on going */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) + { + /* RXNE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_MasterReceive_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + } + } + /* Slave mode selected */ + else + { + /* If an error is detected, read only SR1 register to prevent */ + /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + sr1itflags = READ_REG(hi2c->Instance->SR1); + } + else + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + sr1itflags = READ_REG(hi2c->Instance->SR1); + } + + /* ADDR set --------------------------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + /* Now time to read SR2, this will clear ADDR flag automatically */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + } + I2C_Slave_ADDR(hi2c, sr2itflags); + } + /* STOPF set --------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Slave_STOPF(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_SlaveTransmit_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset ----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_SlaveReceive_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + HAL_I2C_ModeTypeDef tmp1; + uint32_t tmp2; + HAL_I2C_StateTypeDef tmp3; + uint32_t tmp4; + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + uint32_t error = HAL_I2C_ERROR_NONE; + + /* I2C Bus error interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + /* Workaround: Start cannot be generated after a misplaced Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST); + } + + /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* I2C Acknowledge failure error interrupt occurred ------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + tmp1 = hi2c->Mode; + tmp2 = hi2c->XferCount; + tmp3 = hi2c->State; + tmp4 = hi2c->PreviousState; + if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ + ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ + ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) + { + I2C_Slave_AF(hi2c); + } + else + { + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + error |= HAL_I2C_ERROR_AF; + + /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + } + + /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_OVR; + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* Call the Error Callback in case of Error detected -----------------------*/ + if (error != HAL_I2C_ERROR_NONE) + { + hi2c->ErrorCode |= error; + I2C_ITError(hi2c); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle TXE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ + ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) + { + if (hi2c->XferCount == 0U) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + else + { + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + if (hi2c->EventCount == 0U) + { + /* If Memory address size is 8Bit */ + if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount += 2U; + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + } + else if (hi2c->EventCount == 1U) + { + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + else if (hi2c->EventCount == 2U) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief Handle BTF flag for Master transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + } +} + +/** + * @brief Handle RXNE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + uint32_t tmp; + + tmp = hi2c->XferCount; + if (tmp > 3U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if (hi2c->XferCount == (uint16_t)3) + { + /* Disable BUF interrupt, this help to treat correctly the last 4 bytes + on BTF subroutine */ + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + } + else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Do nothing */ + } + } +} + +/** + * @brief Handle BTF flag for Master receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (hi2c->XferCount == 4U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if (hi2c->XferCount == 3U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if (hi2c->XferCount == 2U) + { + /* Prepare next transfer or stop current transfer */ + if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else + { + /* Do nothing */ + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + hi2c->State = HAL_I2C_STATE_READY; + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle SB flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + if (hi2c->EventCount == 0U) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave 7 Bits address */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + + if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL)) + { + if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + } + } + else + { + if (hi2c->EventCount == 0U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); + } + else if (hi2c->EventCount == 1U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); + } + else + { + /* Do nothing */ + } + } + } +} + +/** + * @brief Handle ADD10 flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) +{ + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); + + if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL)) + { + if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + } +} + +/** + * @brief Handle ADDR flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + uint32_t Prev_State = hi2c->PreviousState; + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + hi2c->EventCount++; + } + else + { + if (hi2c->XferCount == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferCount == 1U) + { + if (CurrentXferOptions == I2C_NO_OPTION_FRAME) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + /* Prepare next transfer or stop current transfer */ + else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ + && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) + { + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + else if (hi2c->XferCount == 2U) + { + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) + { + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Reset Event counter */ + hi2c->EventCount = 0U; + } + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } +} + +/** + * @brief Handle TXE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Handle BTF flag for Slave transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle RXNE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->XferCount != 0U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Handle BTF flag for Slave receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->XferCount != 0U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle ADD flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param IT2Flags Interrupt2 flags to handle. + * @retval None + */ +static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) +{ + uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; + uint16_t SlaveAddrCode; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ + __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); + + /* Transfer Direction requested by Master */ + if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) + { + TransferDirection = I2C_DIRECTION_TRANSMIT; + } + + if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) + { + SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; + } + else + { + SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); +#else + HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief Handle STOPF flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If a DMA is ongoing, Update handle size context */ + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx)); + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Disable, stop the current DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else + { + hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx)); + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Disable, stop the current DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + } + else + { + if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ + (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else if (CurrentState == HAL_I2C_STATE_BUSY_TX) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Clear AF flag only */ + /* State Listen, but XferOptions == FIRST or NEXT */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } +} + +/** + * @brief I2C interrupts error process + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if ((hi2c->Mode == HAL_I2C_MODE_MASTER) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + } + + if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) + { + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + + /* Abort DMA transfer */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Call user error callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* STOP Flag is not set after a NACK reception */ + /* So may inform upper layer that listen phase is stopped */ + /* during NACK error treatment */ + CurrentState = hi2c->State; + if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief DMA I2C process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Clear Complete callback */ + hi2c->hdmatx->XferCpltCallback = NULL; + hi2c->hdmarx->XferCpltCallback = NULL; + + if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) + { + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0U; + + if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Do nothing */ + } + + /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ + else if (hi2c->Mode != HAL_I2C_MODE_NONE) + { + if (hi2c->XferCount == (uint16_t)1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Prepare next transfer or stop current transfer */ + if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + + /* Disable Last DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0U; + + /* Check if Errors has been detected during transfer */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Clear Complete callback */ + hi2c->hdmatx->XferCpltCallback = NULL; + hi2c->hdmarx->XferCpltCallback = NULL; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferCount = 0U; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* Clear Complete callback */ + hi2c->hdmatx->XferCpltCallback = NULL; + hi2c->hdmarx->XferCpltCallback = NULL; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferCount = 0U; + + /* Reset XferAbortCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Check if come from abort from user */ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Renable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for Master addressing phase. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c new file mode 100644 index 0000000..7330eb0 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c @@ -0,0 +1,2207 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pcd.c + * @author MCD Application Team + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable PCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup PCD PCD + * @brief PCD HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB) || defined (USB_OTG_FS) + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ +#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +#if defined (USB_OTG_FS) +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); +#endif /* defined (USB) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ + uint8_t i; + + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + +#if defined (USB_OTG_FS) + USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + if (hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback = HAL_PCD_SOFCallback; + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + hpcd->ResetCallback = HAL_PCD_ResetCallback; + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; + + if (hpcd->MspInitCallback == NULL) + { + hpcd->MspInitCallback = HAL_PCD_MspInit; + } + + /* Init the low level hardware */ + hpcd->MspInitCallback(hpcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + } + + hpcd->State = HAL_PCD_STATE_BUSY; + +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if ((USBx->CID & (0x1U << 8)) == 0U) + { + hpcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + + /* Disable the Interrupts */ + __HAL_PCD_DISABLE(hpcd); + + /*Init the Core (common init.) */ + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Device Mode*/ + (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; + (void)USB_DevDisconnect(hpcd->Instance); + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Stop Device */ + (void)HAL_PCD_Stop(hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + if (hpcd->MspDeInitCallback == NULL) + { + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hpcd->MspDeInitCallback(hpcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_PCD_MspDeInit(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + hpcd->State = HAL_PCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB PCD Callback + * To be used instead of the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = pCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = pCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = pCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = pCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = pCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = pCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = pCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Unregister an USB PCD Callback + * USB PCD callabck is redirected to the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + /* Setup Legacy weak Callbacks */ + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = HAL_PCD_SOFCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = HAL_PCD_ResetCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Register USB PCD Data OUT Stage Callback + * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data OUT Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Data OUT Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Data IN Stage Callback + * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data IN Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Data IN Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso OUT incomplete Callback + * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Iso OUT incomplete Callback + * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso IN incomplete Callback + * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Iso IN incomplete Callback + * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); +#if defined (USB) + HAL_PCDEx_SetConnectionState(hpcd, 1U); +#endif /* defined (USB) */ + (void)USB_DevConnect(hpcd->Instance); + __HAL_PCD_ENABLE(hpcd); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + __HAL_PCD_DISABLE(hpcd); + + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + __HAL_UNLOCK(hpcd); + return HAL_ERROR; + } + + (void)USB_DevDisconnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} +#if defined (USB_OTG_FS) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i, ep_intr, epint, epnum; + uint32_t fifoemptymsk, temp; + USB_OTG_EPTypeDef *ep; + + /* ensure that we are in device mode */ + if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + { + return; + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + { + /* incorrect mode, acknowledge the interrupt */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) + { + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + { + /* Class B setup phase done for previous decoded setup */ + (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + } + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); + } + + /* Clear Status Phase Received interrupt */ + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + + /* Clear OUT NAK interrupt */ + if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + { + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); + + epnum = 0U; + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); + } + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); + } + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); + } + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + { + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + /* Handle Resume Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { + /* Clear the Remote Wake-up Signaling */ + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + } + + /* Handle Suspend Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + { + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + } + /* Handle Reset Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + { + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + } + USBx_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) + { + USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM; + + USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + else + { + USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM | + USB_OTG_DOEPMSK_OTEPSPRM | + USB_OTG_DOEPMSK_NAKM; + + USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + + /* Set Default Address to 0 */ + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + + /* setup EP0 to receive SETUP packets */ + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + } + + /* Handle Enumeration done Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + { + (void)USB_ActivateSetup(hpcd->Instance); + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + + /* Set USB Turnaround time */ + (void)USB_SetTurnaroundTime(hpcd->Instance, + HAL_RCC_GetHCLKFreq(), + (uint8_t)hpcd->Init.speed); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + } + + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + temp = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + + if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + + /* Handle SOF Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Incomplete ISO IN Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + { + /* Keep application checking the corresponding Iso IN endpoint + causing the incomplete Interrupt */ + epnum = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); + } + + /* Handle Incomplete ISO OUT Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + /* Keep application checking the corresponding Iso OUT endpoint + causing the incomplete Interrupt */ + epnum = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + /* Handle Connection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ConnectCallback(hpcd); +#else + HAL_PCD_ConnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); + } + + /* Handle Disconnection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + { + temp = hpcd->Instance->GOTGINT; + + if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DisconnectCallback(hpcd); +#else + HAL_PCD_DisconnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + hpcd->Instance->GOTGINT |= temp; + } + } +} +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +/** + * @brief This function handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR)) + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + (void)PCD_EP_ISR_Handler(hpcd); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + (void)HAL_PCD_SetAddress(hpcd, 0U); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP)) + { + hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE); + hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP)) + { + /* Force low-power mode in the macrocell */ + hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + + hpcd->Instance->CNTR |= USB_CNTR_LP_MODE; + + /* WA: Clear Wakeup flag if raised with suspend signal */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF)) + { + /* clear ESOF flag in ISTR */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + } +} +#endif /* defined (USB) */ + +/** + * @brief Data OUT stage callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callback + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); +#if defined (USB) + HAL_PCDEx_SetConnectionState(hpcd, 1U); +#endif /* defined (USB) */ + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Disconnect the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); +#if defined (USB) + HAL_PCDEx_SetConnectionState(hpcd, 0U); +#endif /* defined (USB) */ + (void)USB_DevDisconnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Set the USB Device address. + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + hpcd->USB_Address = address; + (void)USB_SetDevAddress(hpcd->Instance, address); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} +/** + * @brief Open and configure an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->num = ep_addr & EP_ADDR_MSK; + ep->maxpacket = ep_mps; + ep->type = ep_type; + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + + __HAL_LOCK(hpcd); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return ret; +} + +/** + * @brief Deactivate an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0StartXfer(hpcd->Instance, ep); + } + else + { + (void)USB_EPStartXfer(hpcd->Instance, ep); + } + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0StartXfer(hpcd->Instance, ep); + } + else + { + (void)USB_EPStartXfer(hpcd->Instance, ep); + } + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; + } + + ep->is_stall = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + + (void)USB_EPSetStall(hpcd->Instance, ep); + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->is_stall = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_EPClearStall(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_ActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @brief De-activate remote wakeup signalling. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_DeActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD handle state. + * @param hpcd PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +{ + return hpcd->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup PCD_Private_Functions + * @{ + */ +#if defined (USB_OTG_FS) +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if (ep->xfer_len <= ep->xfer_count) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + + if ((gSNPSiD == USB_OTG_CORE_ID_310A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + + /* Inform the upper layer that a setup packet is available */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +/** + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) +{ + PCD_EPTypeDef *ep; + uint16_t count; + uint16_t wIstr; + uint16_t wEPVal; + uint8_t epindex; + + /* stay in loop while pending interrupts */ + while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) + { + wIstr = hpcd->Instance->ISTR; + /* extract highest priority endpoint number */ + epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (epindex == 0U) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0U) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + ep = &hpcd->IN_ep[0]; + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, 0U); +#else + HAL_PCD_DataInStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) + { + hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0U; + } + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if ((wEPVal & USB_EP_SETUP) != 0U) + { + /* Get SETUP Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, + ep->pmaadress, (uint16_t)ep->xfer_count); + + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Process SETUP Packet*/ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + else if ((wEPVal & USB_EP_CTR_RX) != 0U) + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Get Control Data OUT Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); + + ep->xfer_buff += ep->xfer_count; + + /* Process Control Data OUT Packet*/ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, 0U); +#else + HAL_PCD_DataOutStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + } + } + else + { + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); + if ((wEPVal & USB_EP_CTR_RX) != 0U) + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); + ep = &hpcd->OUT_ep[epindex]; + + /* OUT double Buffering*/ + if (ep->doublebuffer == 0U) + { + count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + } + } + else + { + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) + { + /*read from endpoint BUF0Addr buffer*/ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + /* free EP OUT Buffer */ + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); + } + /*multi-packet on the NON control OUT endpoint*/ + ep->xfer_count += count; + ep->xfer_buff += count; + + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) + { + /* RX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataOutStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + + } /* if((wEPVal & EP_CTR_RX) */ + + if ((wEPVal & USB_EP_CTR_TX) != 0U) + { + ep = &hpcd->IN_ep[epindex]; + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); + + /*multi-packet on the NON control IN endpoint*/ + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + } + } + } + return HAL_OK; +} +#endif /* defined (USB) */ + +/** + * @} + */ +#endif /* defined (USB) || defined (USB_OTG_FS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c new file mode 100644 index 0000000..ade6b9a --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c @@ -0,0 +1,246 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pcd_ex.c + * @author MCD Application Team + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx + * @brief PCD Extended HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB) || defined (USB_OTG_FS) +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update FIFO configuration + +@endverbatim + * @{ + */ +#if defined (USB_OTG_FS) +/** + * @brief Set Tx FIFO + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + + if (fifo == 0U) + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) + { + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } + + return HAL_OK; +} + +/** + * @brief Set Rx FIFO + * @param hpcd PCD handle + * @param size Size of Rx fifo + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + hpcd->Instance->GRXFSIZ = size; + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) */ +#if defined (USB) +/** + * @brief Configure PMA for EP + * @param hpcd Device instance + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind + * USB_SNG_BUF: Single Buffer used + * USB_DBL_BUF: Double Buffer used + * @param pmaadress: EP address in The PMA: In case of single buffer endpoint + * this parameter is 16-bit value providing the address + * in PMA allocated to endpoint. + * In case of double buffer endpoint this parameter + * is a 32-bit value providing the endpoint buffer 0 address + * in the LSB part of 32-bit value and endpoint buffer 1 address + * in the MSB part of 32-bit value. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, + uint16_t ep_addr, + uint16_t ep_kind, + uint32_t pmaadress) +{ + PCD_EPTypeDef *ep; + + /* initialize ep structure*/ + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + /* Here we check if the endpoint is single or double Buffer*/ + if (ep_kind == PCD_SNG_BUF) + { + /* Single Buffer */ + ep->doublebuffer = 0U; + /* Configure the PMA */ + ep->pmaadress = (uint16_t)pmaadress; + } + else /* USB_DBL_BUF */ + { + /* Double Buffer Endpoint */ + ep->doublebuffer = 1U; + /* Configure the PMA */ + ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); + ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); + } + + return HAL_OK; +} + +/** + * @brief Software Device Connection, + * this function is not required by USB OTG FS peripheral, it is used + * only by USB Device FS peripheral. + * @param hpcd: PCD handle + * @param state: connection state (0 : disconnected / 1: connected) + * @retval None + */ +__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(state); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PCDEx_SetConnectionState could be implemented in the user file + */ +} +#endif /* defined (USB) */ + +/** + * @brief Send LPM message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_LPM_Callback could be implemented in the user file + */ +} + +/** + * @brief Send BatteryCharging message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_BCD_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB) || defined (USB_OTG_FS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c new file mode 100644 index 0000000..c757976 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c @@ -0,0 +1,621 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT 0x00010000U +#define PVD_MODE_EVT 0x00020000U +#define PVD_RISING_EDGE 0x00000001U +#define PVD_FALLING_EDGE 0x00000002U +/** + * @} + */ + + +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define PWR_CR_OFFSET 0x00U +#define PWR_CSR_OFFSET 0x04U +#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) +#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) +/** + * @} + */ + +/** @defgroup PWR_CR_register_alias PWR CR Register alias address + * @{ + */ +/* --- CR Register ---*/ +/* Alias word address of LPSDSR bit */ +#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos +#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) + +/* Alias word address of DBP bit */ +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos +#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) + +/* Alias word address of PVDE bit */ +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos +#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) + +/** + * @} + */ + +/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address + * @{ + */ + +/* --- CSR Register ---*/ +/* Alias word address of EWUP1 bit */ +#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) +/** + * @} + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PWR_Private_Functions PWR Private Functions + * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) + * @{ + */ +static void PWR_OverloadWfe(void); + +/* Private functions ---------------------------------------------------------*/ +__NOINLINE +static void PWR_OverloadWfe(void) +{ + __asm volatile( "wfe" ); + __asm volatile( "nop" ); +} + +/** + * @} + */ + + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers ). + * @note If the HSE divided by 128 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + /* Enable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers). + * @note If the HSE divided by 128 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + /* Disable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There is one WakeUp pin: + WakeUp Pin 1 on PA.00. + + [..] + + *** Low Power modes configuration *** + ===================================== + [..] + The device features 3 low-power modes: + (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like + NVIC, SysTick, etc. are kept running + (+) Stop mode: All clocks are stopped + (+) Standby mode: 1.8V domain powered off + + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. + (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) + (+++) Any EXTI Line (Internal or External) configured in Event mode + + *** Stop mode *** + ================= + [..] + The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral + clock gating. The voltage regulator can be configured either in normal or low-power mode. + In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC + oscillators are disabled. SRAM and register contents are preserved. + In Stop mode, all I/O pins keep the same state as in Run mode. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) + function with: + (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. + (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. + (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + (+) Exit: + (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured + (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based on the + Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is + consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also + switched off. SRAM and register contents are lost except for registers in the Backup domain + and Standby circuitry + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in + NRSTpin, IWDG Reset + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + *** PWR Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + Below the list of all silicon limitations known on STM32F1xx prouct. + + (#)Workarounds Implemented inside PWR HAL Driver + (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + /* Enable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + /* Disable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Enable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Disable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software + * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + /* No check on Regulator because parameter not used in SLEEP mode */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by using an interrupt or a wakeup event, + * HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator: Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ + CLEAR_BIT(PWR->CR, PWR_CR_PDDS); + + /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + PWR_OverloadWfe(); /* WFE redefine locally */ + PWR_OverloadWfe(); /* WFE redefine locally */ + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - TAMPER pin if configured for tamper or calibration out. + * - WKUP pin (PA0) if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + SET_BIT(PWR->CR, PWR_CR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Enables CORTEX M3 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M3 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c new file mode 100644 index 0000000..95b5568 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c @@ -0,0 +1,1403 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals whose clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC +* @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +static void RCC_Delay(uint32_t mdelay); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M3 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, + HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 128. + (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly. This clock is derived of the main PLL through PLL Multiplier. + (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK + (+@) IWDG clock which is always the LSI clock. + + (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. + For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + @endverbatim + * @{ + */ + +/* + Additional consideration on the SYSCLK based on Latency settings: + +-----------------------------------------------+ + | Latency | SYSCLK clock frequency (MHz) | + |---------------|-------------------------------| + |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + |---------------|-------------------------------| + |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + |---------------|-------------------------------| + |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | + +-----------------------------------------------+ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL, PLL2 and PLL3 are OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS and MCO1 OFF + * - All interrupts disabled + * - All flags are cleared + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM bits to the reset value */ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Second step is to clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Ensure to reset PLLSRC and PLLMUL bits */ + CLEAR_REG(RCC->CFGR); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset HSEON & CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + +#if defined(RCC_PLL2_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLL2ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLL2_SUPPORT */ + +#if defined(RCC_PLLI2S_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLL3ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_CFGR2_PREDIV1) + /* Reset CFGR2 register */ + CLEAR_REG(RCC->CFGR2); +#endif /* RCC_CFGR2_PREDIV1 */ + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS) + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* To have a fully stabilized clock in the specified range, a software delay of 1ms + should be added.*/ + RCC_Delay(1); + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + +#if defined(RCC_CR_PLL2ON) + /*-------------------------------- PLL2 Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); + if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) + { + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + { + return HAL_ERROR; + } + else + { + if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); + assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLLI2S is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); + + /* Configure the main PLL2 multiplication factors. */ + __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); + + /* Enable the main PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Set PREDIV1 source to HSE */ + CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + +#endif /* RCC_CR_PLL2ON */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv factor --------------------------------*/ + /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ + if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) + { + /* Check the parameter */ + assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); +#if defined(RCC_CFGR2_PREDIV1SRC) + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); + + /* Set PREDIV1 source */ + SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); +#endif /* RCC_CFGR2_PREDIV1SRC */ + + /* Set PREDIV1 Value */ + __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); + } + + /* Configure the main PLL clock source and multiplication factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) + { + return HAL_ERROR; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * The value of this parameter depend on device used within the same series + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + +#if defined(FLASH_ACR_LATENCY) + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } +} + +#endif /* FLASH_ACR_LATENCY */ +/*-------------------------- HCLK Configuration --------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + +#if defined(FLASH_ACR_LATENCY) + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } +} +#endif /* FLASH_ACR_LATENCY */ + +/*-------------------------- PCLK1 Configuration ---------------------------*/ +if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + + @endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + @if STM32F105xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source + @endif + @if STM32F107xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source + * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source + @endif + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio = {0U}; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + UNUSED(RCC_MCODiv); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Pin = MCO1_PIN; + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + + /* Configure the MCO clock source */ + __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. + * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ +#if defined(RCC_CFGR2_PREDIV1SRC) + const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; +#if defined(RCC_CFGR2_PREDIV1) + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +#else + const uint8_t aPredivFactorTable[2] = {1, 2}; +#endif /*RCC_CFGR2_PREDIV1*/ + +#endif + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + uint32_t sysclockfreq = 0U; +#if defined(RCC_CFGR2_PREDIV1SRC) + uint32_t prediv2 = 0U, pll2mul = 0U; +#endif /*RCC_CFGR2_PREDIV1SRC*/ + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + { +#if defined(RCC_CFGR2_PREDIV1) + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; +#else + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; +#endif /*RCC_CFGR2_PREDIV1*/ +#if defined(RCC_CFGR2_PREDIV1SRC) + + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) + { + /* PLL2 selected as Prediv1 source */ + /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; + pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); + } + else + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); + } + + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ + /* In this case need to divide pllclk by 2 */ + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) + { + pllclk = pllclk / 2; + } +#else + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); +#endif /*RCC_CFGR2_PREDIV1SRC*/ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + } + sysclockfreq = pllclk; + break; + } + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + +#if defined(RCC_CFGR2_PREDIV1SRC) + /* Get the Prediv1 source --------------------------------------------------*/ + RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); +#endif /* RCC_CFGR2_PREDIV1SRC */ + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL); +#if defined(RCC_CR_PLL2ON) + /* Get the PLL2 configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON) + { + RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON; + } + else + { + RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF; + } + RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2(); + RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL); +#endif /* RCC_CR_PLL2ON */ +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(pFLatency != NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + +#if defined(FLASH_ACR_LATENCY) + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +#else + /* For VALUE lines devices, only LATENCY_0 can be set*/ + *pFLatency = (uint32_t)FLASH_LATENCY_0; +#endif +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay: specifies the delay time length, in milliseconds. + * @retval None + */ +static void RCC_Delay(uint32_t mdelay) +{ + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + do + { + __NOP(); + } + while (Delay --); +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c new file mode 100644 index 0000000..4719727 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c @@ -0,0 +1,863 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/** @defgroup RCCEx RCCEx + * @brief RCC Extension HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(RTC clock). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on + * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to + * manually disable it. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U, temp_reg = 0U; +#if defined(STM32F105xC) || defined(STM32F107xC) + uint32_t pllactive = 0U; +#endif /* STM32F105xC || STM32F107xC */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------------- RTC/LCD Configuration ------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + FlagStatus pwrclkchanged = RESET; + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + + /* Require to disable power clock if necessary */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*------------------------------ ADC clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + } + +#if defined(STM32F105xC) || defined(STM32F107xC) + /*------------------------------ I2S2 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + } + + /*------------------------------ I2S3 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); + + /* Configure the I2S3 clock source */ + __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); + } + + /*------------------------------ PLL I2S Configuration ----------------------*/ + /* Check that PLLI2S need to be enabled */ + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + { + /* Update flag to indicate that PLL I2S should be active */ + pllactive = 1; + } + + /* Check if PLL I2S need to be enabled */ + if (pllactive == 1) + { + /* Enable PLL I2S only if not active */ + if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); + assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLL2 is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); + + /* Configure the main PLLI2S multiplication factors. */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); + + /* Enable the main PLLI2S. */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ + if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) + { + return HAL_ERROR; + } + } + } +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + /*------------------------------ USB clock Configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + + return HAL_OK; +} + +/** + * @brief Get the PeriphClkInit according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t srcclk = 0U; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; + + /* Get the RTC configuration -----------------------------------------------*/ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + /* Source clock is LSE or LSI*/ + PeriphClkInit->RTCClockSelection = srcclk; + + /* Get the ADC clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC; + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + +#if defined(STM32F105xC) || defined(STM32F107xC) + /* Get the I2S2 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; + PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); + + /* Get the I2S3 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; + PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE(); + +#endif /* STM32F105xC || STM32F107xC */ + +#if defined(STM32F103xE) || defined(STM32F103xG) + /* Get the I2S2 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; + PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK; + + /* Get the I2S3 clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; + PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK; + +#endif /* STM32F103xE || STM32F103xG */ + +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + /* Get the USB clock configuration -----------------------------------------*/ + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +} + +/** + * @brief Returns the peripheral clock frequency + * @note Returns 0 if peripheral clock is unknown + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + @if STM32F103xE + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + @endif + @if STM32F103xG + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + @endif + @if STM32F105xC + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F107xC + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F102xx + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F103xx + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ +#if defined(STM32F105xC) || defined(STM32F107xC) + const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; + uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; +#endif /* STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ + defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; + const uint8_t aPredivFactorTable[2] = {1, 2}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + uint32_t temp_reg = 0U, frequency = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ + || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ + || defined(STM32F105xC) || defined(STM32F107xC) + case RCC_PERIPHCLK_USB: + { + /* Get RCC configuration ------------------------------------------------------*/ + temp_reg = RCC->CFGR; + + /* Check if PLL is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) + { + pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; + if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + { +#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ + || defined(STM32F100xE) + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; +#else + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; +#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ + +#if defined(STM32F105xC) || defined(STM32F107xC) + if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) + { + /* PLL2 selected as Prediv1 source */ + /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; + pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); + } + else + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); + } + + /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ + /* In this case need to divide pllclk by 2 */ + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) + { + pllclk = pllclk / 2; + } +#else + if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ + pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); + } +#endif /* STM32F105xC || STM32F107xC */ + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); + } + + /* Calcul of the USB frequency*/ +#if defined(STM32F105xC) || defined(STM32F107xC) + /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ + if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) + { + /* Prescaler of 2 selected for USB */ + frequency = pllclk; + } + else + { + /* Prescaler of 3 selected for USB */ + frequency = (2 * pllclk) / 3; + } +#else + /* USBCLK = PLLCLK / USB prescaler */ + if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) + { + /* No prescaler selected for USB */ + frequency = pllclk; + } + else + { + /* Prescaler of 1.5 selected for USB */ + frequency = (pllclk * 2) / 3; + } +#endif + } + break; + } +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) + case RCC_PERIPHCLK_I2S2: + { +#if defined(STM32F103xE) || defined(STM32F103xG) + /* SYSCLK used as source clock for I2S2 */ + frequency = HAL_RCC_GetSysClockFreq(); +#else + if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) + { + /* SYSCLK used as source clock for I2S2 */ + frequency = HAL_RCC_GetSysClockFreq(); + } + else + { + /* Check if PLLI2S is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) + { + /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + } + } +#endif /* STM32F103xE || STM32F103xG */ + break; + } + case RCC_PERIPHCLK_I2S3: + { +#if defined(STM32F103xE) || defined(STM32F103xG) + /* SYSCLK used as source clock for I2S3 */ + frequency = HAL_RCC_GetSysClockFreq(); +#else + if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) + { + /* SYSCLK used as source clock for I2S3 */ + frequency = HAL_RCC_GetSysClockFreq(); + } + else + { + /* Check if PLLI2S is enabled */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) + { + /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; + frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); + } + } +#endif /* STM32F103xE || STM32F103xG */ + break; + } +#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ + case RCC_PERIPHCLK_RTC: + { + /* Get RCC BDCR configuration ------------------------------------------------------*/ + temp_reg = RCC->BDCR; + + /* Check if LSE is ready if RTC clock selection is LSE */ + if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready if RTC clock selection is LSI */ + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + { + frequency = LSI_VALUE; + } + else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + { + frequency = HSE_VALUE / 128U; + } + /* Clock not enabled for RTC*/ + else + { + /* nothing to do: frequency already initialized to 0U */ + } + break; + } + case RCC_PERIPHCLK_ADC: + { + frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); + break; + } + default: + { + break; + } + } + return (frequency); +} + +/** + * @} + */ + +#if defined(STM32F105xC) || defined(STM32F107xC) +/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function + * @brief PLLI2S Management functions + * +@verbatim + =============================================================================== + ##### Extended PLLI2S Management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PLLI2S + activation or deactivation +@endverbatim + * @{ + */ + +/** + * @brief Enable PLLI2S + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart = 0U; + + /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ + if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL)); + assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLL2 is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Disable the main PLLI2S. */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); + + + /* Configure the main PLLI2S multiplication factors. */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); + + /* Enable the main PLLI2S. */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S + * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart = 0U; + + /* Disable PLL I2S as not requested by I2S2 or I2S3*/ + if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) + { + /* Disable the main PLLI2S. */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function + * @brief PLL2 Management functions + * +@verbatim + =============================================================================== + ##### Extended PLL2 Management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PLL2 + activation or deactivation +@endverbatim + * @{ + */ + +/** + * @brief Enable PLL2 + * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration information for the PLL2 + * @note The PLL2 configuration not modified if used indirectly as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) +{ + uint32_t tickstart = 0U; + + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + { + return HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL)); + assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value)); + + /* Prediv2 can be written only when the PLLI2S is disabled. */ + /* Return an error only if new value is different from the programmed value */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \ + (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) + { + return HAL_ERROR; + } + + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the HSE prediv2 factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); + + /* Configure the main PLL2 multiplication factors. */ + __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); + + /* Enable the main PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLL2 + * @note PLL2 is not disabled if used indirectly as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) +{ + uint32_t tickstart = 0U; + + /* This bit can not be cleared if the PLL2 clock is used indirectly as system + clock (i.e. it is used as PLL clock entry that is used as system clock). */ + if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \ + (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \ + ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) + { + return HAL_ERROR; + } + else + { + /* Disable the main PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @} + */ +#endif /* STM32F105xC || STM32F107xC */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c new file mode 100644 index 0000000..6d04d52 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c @@ -0,0 +1,1949 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rtc.c + * @author MCD Application Team + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) peripheral: + * + Initialization and de-initialization functions + * + RTC Time and Date functions + * + RTC Alarm functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous prescaler to generate RTC 1Hz time base) + using the HAL_RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + and HAL_RTC_SetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and configure the Tamper Level using the + HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt + mode using HAL_RTCEx_SetTamper_IT() function. + (+) The TAMPER1 alternate function can be mapped to PC13 + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() + function. + + ##### WARNING: Drivers Restrictions ##### + ================================================================== + [..] RTC version used on STM32F1 families is version V1. All the features supported by V2 + (other families) will be not supported on F1. + [..] As on V2, main RTC features are managed by HW. But on F1, date feature is completely + managed by SW. + [..] Then, there are some restrictions compared to other families: + (+) Only format 24 hours supported in HAL (format 12 hours not supported) + (+) Date is saved in SRAM. Then, when MCU is in STOP or STANDBY mode, date will be lost. + User should implement a way to save date before entering in low power mode (an + example is provided with firmware package based on backup registers) + (+) Date is automatically updated each time a HAL_RTC_GetTime or HAL_RTC_GetDate is called. + (+) Alarm detection is limited to 1 day. It will expire only 1 time (no alarm repetition, need + to program a new alarm) + + ##### Backup Domain Operating Condition ##### + ============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + [..] To allow the RTC operating even when the main digital supply (VDD) is turned + off, the VBAT pin powers the following blocks: + (#) The RTC + (#) The LSE oscillator + (#) The backup SRAM when the low power backup regulator is enabled + (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) + + [..] When the backup domain is supplied by VDD (analog switch connected to VDD), + the following pins are available: + (+) PC13 can be used as a Tamper pin + + [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT + because VDD is not present), the following pins are available: + (+) PC13 can be used as the Tamper pin + + ##### Backup Domain Reset ##### + ================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. + [..] A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + (#) Tamper detection event resets all data backup registers. + + ##### Backup Domain Access ##### + ================================================================== + [..] After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Call the function HAL_RCCEx_PeriphCLKConfig in using RCC_PERIPHCLK_RTC for + PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSE) + (+) Enable the BKP clock in using __HAL_RCC_BKP_CLK_ENABLE() + + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A), + and RTC tamper event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm. + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. + + [..] + Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + [..] + By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions : + example @ref AlarmAEventCallback(). + Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function + in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null + (not registered beforehand). + If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + [..] + Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() + or @ref HAL_RTC_Init() function. + [..] + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RTC_Private_Constants RTC Private Constants + * @{ + */ +#define RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF +#define RTC_ALARM_RESETVALUE 0xFFFFFFFFU + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ +static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc); +static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter); +static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc); +static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter); +static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); +static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); +static uint8_t RTC_IsLeapYear(uint16_t nYear); +static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed); +static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay); + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Asynchronous), disable RTC registers Write protection, + enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler should be programmed to generate the RTC 1Hz time base. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by setting the CNF bit in the RTC_CRL register. + (#) To read the calendar after wakeup from low power modes (Standby or Stop) + the software must first wait for the RSF bit (Register Synchronized Flag) + in the RTC_CRL register to be set by hardware. + The HAL_RTC_WaitForSynchro() function implements the above software + sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RTC peripheral + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + uint32_t prescaler = 0U; + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + assert_param(IS_RTC_CALIB_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + + if (hrtc->MspInitCallback == NULL) + { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); + + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Waiting for synchro */ + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Clear Flags Bits */ + CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC)); + + if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE) + { + /* Disable the selected Tamper pin */ + CLEAR_BIT(BKP->CR, BKP_CR_TPE); + } + + /* Set the signal which will be routed to RTC Tamper pin*/ + MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut); + + if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND) + { + /* RTC Prescaler provided directly by end-user*/ + prescaler = hrtc->Init.AsynchPrediv; + } + else + { + /* RTC Prescaler will be automatically calculated to get 1 second timebase */ + /* Get the RTCCLK frequency */ + prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); + + /* Check that RTC clock is enabled*/ + if (prescaler == 0U) + { + /* Should not happen. Frequency is not available*/ + hrtc->State = HAL_RTC_STATE_ERROR; + return HAL_ERROR; + } + else + { + /* RTC period = RTCCLK/(RTC_PR + 1) */ + prescaler = prescaler - 1U; + } + } + + /* Configure the RTC_PRLH / RTC_PRLL */ + MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U)); + MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL)); + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + + /* Initialize date to 1st of January 2000 */ + hrtc->DateToUpdate.Year = 0x00U; + hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; + hrtc->DateToUpdate.Date = 0x01U; + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; + } +} + +/** + * @brief DeInitializes the RTC peripheral + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note This function does not reset the RTC Backup Data registers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + CLEAR_REG(hrtc->Instance->CNTL); + CLEAR_REG(hrtc->Instance->CNTH); + WRITE_REG(hrtc->Instance->PRLL, 0x00008000U); + CLEAR_REG(hrtc->Instance->PRLH); + + /* Reset All CRH/CRL bits */ + CLEAR_REG(hrtc->Instance->CRH); + CLEAR_REG(hrtc->Instance->CRL); + + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + + /* Wait for synchro*/ + HAL_RTC_WaitForSynchro(hrtc); + + /* Clear RSF flag */ + CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); + +#else + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + hrtc->State = HAL_RTC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RTC Callback + * To be used instead of the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Unregister an RTC Callback + * RTC callabck is redirected to the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Initializes the RTC MSP. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the RTC MSP. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group2 Time and Date functions + * @brief RTC Time and Date functions + * +@verbatim + =============================================================================== + ##### RTC Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Time and Date features + +@endverbatim + * @{ + */ + +/** + * @brief Sets RTC current time. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTime: Pointer to Time structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t counter_time = 0U, counter_alarm = 0U; + + /* Check input parameters */ + if ((hrtc == NULL) || (sTime == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_HOUR24(sTime->Hours)); + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \ + ((uint32_t)sTime->Minutes * 60U) + \ + ((uint32_t)sTime->Seconds)); + } + else + { + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + + counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds)))); + } + + /* Write time counter in RTC registers */ + if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Clear Second and overflow flags */ + CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW)); + + /* Read current Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + + /* Set again alarm to match with new time if enabled */ + if (counter_alarm != RTC_ALARM_RESETVALUE) + { + if (counter_alarm < counter_time) + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + + /* Write new Alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + + hrtc->State = HAL_RTC_STATE_READY; + + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Gets RTC current time. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTime: Pointer to Time structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U; + + /* Check input parameters */ + if ((hrtc == NULL) || (sTime == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Check if counter overflow occurred */ + if (__HAL_RTC_OVERFLOW_GET_FLAG(hrtc, RTC_FLAG_OW)) + { + return HAL_ERROR; + } + + /* Read the time counter*/ + counter_time = RTC_ReadTimeCounter(hrtc); + + /* Fill the structure fields with the read parameters */ + hours = counter_time / 3600U; + sTime->Minutes = (uint8_t)((counter_time % 3600U) / 60U); + sTime->Seconds = (uint8_t)((counter_time % 3600U) % 60U); + + if (hours >= 24U) + { + /* Get number of days elapsed from last calculation */ + days_elapsed = (hours / 24U); + + /* Set Hours in RTC_TimeTypeDef structure*/ + sTime->Hours = (hours % 24U); + + /* Read Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + + /* Calculate remaining time to reach alarm (only if set and not yet expired)*/ + if ((counter_alarm != RTC_ALARM_RESETVALUE) && (counter_alarm > counter_time)) + { + counter_alarm -= counter_time; + } + else + { + /* In case of counter_alarm < counter_time */ + /* Alarm expiration already occurred but alarm not deactivated */ + counter_alarm = RTC_ALARM_RESETVALUE; + } + + /* Set updated time in decreasing counter by number of days elapsed */ + counter_time -= (days_elapsed * 24U * 3600U); + + /* Write time counter in RTC registers */ + if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set updated alarm to be set */ + if (counter_alarm != RTC_ALARM_RESETVALUE) + { + counter_alarm += counter_time; + + /* Write time counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + /* Alarm already occurred. Set it to reset values to avoid unexpected expiration */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Update date */ + RTC_DateUpdate(hrtc, days_elapsed); + } + else + { + sTime->Hours = hours; + } + + /* Check the input parameters format */ + if (Format != RTC_FORMAT_BIN) + { + /* Convert the time structure parameters to BCD format */ + sTime->Hours = (uint8_t)RTC_ByteToBcd2(sTime->Hours); + sTime->Minutes = (uint8_t)RTC_ByteToBcd2(sTime->Minutes); + sTime->Seconds = (uint8_t)RTC_ByteToBcd2(sTime->Seconds); + } + + return HAL_OK; +} + + +/** + * @brief Sets RTC current date. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sDate: Pointer to date structure + * @param Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t counter_time = 0U, counter_alarm = 0U, hours = 0U; + + /* Check input parameters */ + if ((hrtc == NULL) || (sDate == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + /* Change the current date */ + hrtc->DateToUpdate.Year = sDate->Year; + hrtc->DateToUpdate.Month = sDate->Month; + hrtc->DateToUpdate.Date = sDate->Date; + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + /* Change the current date */ + hrtc->DateToUpdate.Year = RTC_Bcd2ToByte(sDate->Year); + hrtc->DateToUpdate.Month = RTC_Bcd2ToByte(sDate->Month); + hrtc->DateToUpdate.Date = RTC_Bcd2ToByte(sDate->Date); + } + + /* WeekDay set by user can be ignored because automatically calculated */ + hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(hrtc->DateToUpdate.Year, hrtc->DateToUpdate.Month, hrtc->DateToUpdate.Date); + sDate->WeekDay = hrtc->DateToUpdate.WeekDay; + + /* Reset time to be aligned on the same day */ + /* Read the time counter*/ + counter_time = RTC_ReadTimeCounter(hrtc); + + /* Fill the structure fields with the read parameters */ + hours = counter_time / 3600U; + if (hours > 24U) + { + /* Set updated time in decreasing counter by number of days elapsed */ + counter_time -= ((hours / 24U) * 24U * 3600U); + /* Write time counter in RTC registers */ + if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + /* Read current Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + + /* Set again alarm to match with new time if enabled */ + if (counter_alarm != RTC_ALARM_RESETVALUE) + { + if (counter_alarm < counter_time) + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + + /* Write new Alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + + + } + + hrtc->State = HAL_RTC_STATE_READY ; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets RTC current date. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sDate: Pointer to Date structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + RTC_TimeTypeDef stime = {0U}; + + /* Check input parameters */ + if ((hrtc == NULL) || (sDate == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */ + if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK) + { + return HAL_ERROR; + } + + /* Fill the structure fields with the read parameters */ + sDate->WeekDay = hrtc->DateToUpdate.WeekDay; + sDate->Year = hrtc->DateToUpdate.Year; + sDate->Month = hrtc->DateToUpdate.Month; + sDate->Date = hrtc->DateToUpdate.Date; + + /* Check the input parameters format */ + if (Format != RTC_FORMAT_BIN) + { + /* Convert the date structure parameters to BCD format */ + sDate->Year = (uint8_t)RTC_ByteToBcd2(sDate->Year); + sDate->Month = (uint8_t)RTC_ByteToBcd2(sDate->Month); + sDate->Date = (uint8_t)RTC_ByteToBcd2(sDate->Date); + } + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group3 Alarm functions + * @brief RTC Alarm functions + * +@verbatim + =============================================================================== + ##### RTC Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Alarm feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets the specified RTC Alarm. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm: Pointer to Alarm structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t counter_alarm = 0U, counter_time; + RTC_TimeTypeDef stime = {0U}; + + /* Check input parameters */ + if ((hrtc == NULL) || (sAlarm == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */ + if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK) + { + return HAL_ERROR; + } + + /* Convert time in seconds */ + counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \ + ((uint32_t)stime.Minutes * 60U) + \ + ((uint32_t)stime.Seconds)); + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \ + ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \ + ((uint32_t)sAlarm->AlarmTime.Seconds)); + } + else + { + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \ + ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + } + + /* Check that requested alarm should expire in the same day (otherwise add 1 day) */ + if (counter_alarm < counter_time) + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + } + + /* Write Alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + hrtc->State = HAL_RTC_STATE_READY; + + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Sets the specified RTC Alarm with Interrupt + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm: Pointer to Alarm structure + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t counter_alarm = 0U, counter_time; + RTC_TimeTypeDef stime = {0U}; + + /* Check input parameters */ + if ((hrtc == NULL) || (sAlarm == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */ + if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK) + { + return HAL_ERROR; + } + + /* Convert time in seconds */ + counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \ + ((uint32_t)stime.Minutes * 60U) + \ + ((uint32_t)stime.Seconds)); + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \ + ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \ + ((uint32_t)sAlarm->AlarmTime.Seconds)); + } + else + { + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \ + ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + } + + /* Check that requested alarm should expire in the same day (otherwise add 1 day) */ + if (counter_alarm < counter_time) + { + /* Add 1 day to alarm counter*/ + counter_alarm += (uint32_t)(24U * 3600U); + } + + /* Write alarm counter in RTC registers */ + if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); + + hrtc->State = HAL_RTC_STATE_READY; + + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Gets the RTC Alarm value and masks. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm: Pointer to Date structure + * @param Alarm: Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: Alarm + * @param Format: Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +{ + uint32_t counter_alarm = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Alarm); + + /* Check input parameters */ + if ((hrtc == NULL) || (sAlarm == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(Alarm)); + + /* Read Alarm counter in RTC registers */ + counter_alarm = RTC_ReadAlarmCounter(hrtc); + + /* Fill the structure with the read parameters */ + /* Set hours in a day range (between 0 to 24)*/ + sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600U) % 24U); + sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600U) / 60U); + sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600U) % 60U); + + if (Format != RTC_FORMAT_BIN) + { + sAlarm->AlarmTime.Hours = RTC_ByteToBcd2(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Minutes = RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes); + sAlarm->AlarmTime.Seconds = RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds); + } + + return HAL_OK; +} + +/** + * @brief Deactive the specified RTC Alarm + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Alarm: Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Alarm); + + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Set to default values ALRH & ALRL registers */ + WRITE_REG(hrtc->Instance->ALRH, RTC_ALARM_RESETVALUE_REGISTER); + WRITE_REG(hrtc->Instance->ALRL, RTC_ALARM_RESETVALUE_REGISTER); + + /* RTC Alarm Interrupt Configuration: Disable EXTI configuration */ + __HAL_RTC_ALARM_EXTI_DISABLE_IT(); + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles Alarm interrupt request. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA)) + { + /* Get the status of the Interrupt */ + if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET) + { + /* AlarmA callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + } + } + + /* Clear the EXTI's line Flag for RTC Alarm */ + __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Alarm A callback. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles AlarmA Polling request. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Returns the RTC state. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +{ + return hrtc->State; +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group5 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Wait for RTC Time and Date Synchronization + +@endverbatim + * @{ + */ + +/** + * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) + * are synchronized with RTC APB clock. + * @note This function must be called before any read operation after an APB reset + * or an APB clock stop. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0U; + + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Clear RSF flag */ + CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF); + + tickstart = HAL_GetTick(); + + /* Wait the registers to be synchronised */ + while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + + +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions + * @{ + */ + + +/** + * @brief Read the time counter available in RTC_CNT registers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval Time counter + */ +static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc) +{ + uint16_t high1 = 0U, high2 = 0U, low = 0U; + uint32_t timecounter = 0U; + + high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); + low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT); + high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); + + if (high1 != high2) + { + /* In this case the counter roll over during reading of CNTL and CNTH registers, + read again CNTL register then return the counter value */ + timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); + } + else + { + /* No counter roll over during reading of CNTL and CNTH registers, counter + value is equal to first value of CNTL and CNTH */ + timecounter = (((uint32_t) high1 << 16U) | low); + } + + return timecounter; +} + +/** + * @brief Write the time counter in RTC_CNT registers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param TimeCounter: Counter to write in RTC_CNT registers + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Set RTC COUNTER MSB word */ + WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Read the time counter available in RTC_ALR registers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval Time counter + */ +static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc) +{ + uint16_t high1 = 0U, low = 0U; + + high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT); + low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT); + + return (((uint32_t) high1 << 16U) | low); +} + +/** + * @brief Write the time counter in RTC_ALR registers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param AlarmCounter: Counter to write in RTC_ALR registers + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set Initialization mode */ + if (RTC_EnterInitMode(hrtc) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Set RTC COUNTER MSB word */ + WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); + + /* Wait for synchro */ + if (RTC_ExitInitMode(hrtc) != HAL_OK) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Enters the RTC Initialization mode. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0U; + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + + return HAL_OK; +} + +/** + * @brief Exit the RTC Initialization mode. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0U; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted + * @retval Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint32_t bcdhigh = 0U; + + while (Value >= 10U) + { + bcdhigh++; + Value -= 10U; + } + + return ((uint8_t)(bcdhigh << 4U) | Value); +} + +/** + * @brief Converts from 2 digit BCD to Binary. + * @param Value: BCD value to be converted + * @retval Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint32_t tmp = 0U; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @brief Updates date when time is 23:59:59. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param DayElapsed: Number of days elapsed from last date update + * @retval None + */ +static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed) +{ + uint32_t year = 0U, month = 0U, day = 0U; + uint32_t loop = 0U; + + /* Get the current year*/ + year = hrtc->DateToUpdate.Year; + + /* Get the current month and day */ + month = hrtc->DateToUpdate.Month; + day = hrtc->DateToUpdate.Date; + + for (loop = 0U; loop < DayElapsed; loop++) + { + if ((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \ + (month == 8U) || (month == 10U) || (month == 12U)) + { + if (day < 31U) + { + day++; + } + /* Date structure member: day = 31 */ + else + { + if (month != 12U) + { + month++; + day = 1U; + } + /* Date structure member: day = 31 & month =12 */ + else + { + month = 1U; + day = 1U; + year++; + } + } + } + else if ((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U)) + { + if (day < 30U) + { + day++; + } + /* Date structure member: day = 30 */ + else + { + month++; + day = 1U; + } + } + else if (month == 2U) + { + if (day < 28U) + { + day++; + } + else if (day == 28U) + { + /* Leap year */ + if (RTC_IsLeapYear(year)) + { + day++; + } + else + { + month++; + day = 1U; + } + } + else if (day == 29U) + { + month++; + day = 1U; + } + } + } + + /* Update year */ + hrtc->DateToUpdate.Year = year; + + /* Update day and month */ + hrtc->DateToUpdate.Month = month; + hrtc->DateToUpdate.Date = day; + + /* Update day of the week */ + hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(year, month, day); +} + +/** + * @brief Check whether the passed year is Leap or not. + * @param nYear year to check + * @retval 1: leap year + * 0: not leap year + */ +static uint8_t RTC_IsLeapYear(uint16_t nYear) +{ + if ((nYear % 4U) != 0U) + { + return 0U; + } + + if ((nYear % 100U) != 0U) + { + return 1U; + } + + if ((nYear % 400U) == 0U) + { + return 1U; + } + else + { + return 0U; + } +} + +/** + * @brief Determines the week number, the day number and the week day number. + * @param nYear year to check + * @param nMonth Month to check + * @param nDay Day to check + * @note Day is calculated with hypothesis that year > 2000 + * @retval Value which can take one of the following parameters: + * @arg RTC_WEEKDAY_MONDAY + * @arg RTC_WEEKDAY_TUESDAY + * @arg RTC_WEEKDAY_WEDNESDAY + * @arg RTC_WEEKDAY_THURSDAY + * @arg RTC_WEEKDAY_FRIDAY + * @arg RTC_WEEKDAY_SATURDAY + * @arg RTC_WEEKDAY_SUNDAY + */ +static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay) +{ + uint32_t year = 0U, weekday = 0U; + + year = 2000U + nYear; + + if (nMonth < 3U) + { + /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/ + weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + ((year - 1U) / 4U) - ((year - 1U) / 100U) + ((year - 1U) / 400U)) % 7U; + } + else + { + /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/ + weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + (year / 4U) - (year / 100U) + (year / 400U) - 2U) % 7U; + } + + return (uint8_t)weekday; +} + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c new file mode 100644 index 0000000..93029d4 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_rtc_ex.c + * @author MCD Application Team + * @brief Extended RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) Extension peripheral: + * + RTC Tamper functions + * + Extension Control functions + * + Extension RTC features functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/** @defgroup RTCEx RTCEx + * @brief RTC Extended HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Macros RTCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + +/** @defgroup RTCEx_Exported_Functions_Group1 RTC Tamper functions + * @brief RTC Tamper functions + * +@verbatim + =============================================================================== + ##### RTC Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Tamper feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets Tamper + * @note By calling this API we disable the tamper interrupt for all tampers. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTamper: Pointer to Tamper Structure. + * @note Tamper can be enabled only if ASOE and CCO bit are reset + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + /* Check input parameters */ + if ((hrtc == NULL) || (sTamper == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (HAL_IS_BIT_SET(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE))) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger))); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets Tamper with interrupt. + * @note By calling this API we force the tamper interrupt for all tampers. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTamper: Pointer to RTC Tamper. + * @note Tamper can be enabled only if ASOE and CCO bit are reset + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + /* Check input parameters */ + if ((hrtc == NULL) || (sTamper == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (HAL_IS_BIT_SET(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE))) + { + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger))); + + /* Configure the Tamper Interrupt in the BKP->CSR */ + __HAL_RTC_TAMPER_ENABLE_IT(hrtc, RTC_IT_TAMP1); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates Tamper. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Tamper: Selected tamper pin. + * This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + /* Prevent unused argument(s) compilation warning */ + UNUSED(Tamper); + + assert_param(IS_RTC_TAMPER(Tamper)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the selected Tamper pin */ + CLEAR_BIT(BKP->CR, BKP_CR_TPE); + + /* Disable the Tamper Interrupt in the BKP->CSR */ + /* Configure the Tamper Interrupt in the BKP->CSR */ + __HAL_RTC_TAMPER_DISABLE_IT(hrtc, RTC_IT_TAMP1); + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + SET_BIT(BKP->CSR, BKP_CSR_CTE); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles Tamper interrupt request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the status of the Interrupt */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP1)) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET) + { + /* Tamper callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper1EventCallback(hrtc); +#else + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + } + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Tamper 1 callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles Tamper1 Polling. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Get the status of the Interrupt */ + while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == RESET) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group2 RTC Second functions + * @brief RTC Second functions + * +@verbatim + =============================================================================== + ##### RTC Second functions ##### + =============================================================================== + + [..] This section provides functions implementing second interupt handlers + +@endverbatim + * @{ + */ + +/** + * @brief Sets Interrupt for second + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Enable Second interuption */ + __HAL_RTC_SECOND_ENABLE_IT(hrtc, RTC_IT_SEC); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates Second. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Deactivate Second interuption*/ + __HAL_RTC_SECOND_DISABLE_IT(hrtc, RTC_IT_SEC); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles second interrupt request. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if (__HAL_RTC_SECOND_GET_IT_SOURCE(hrtc, RTC_IT_SEC)) + { + /* Get the status of the Interrupt */ + if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_SEC)) + { + /* Check if Overrun occurred */ + if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_OW)) + { + /* Second error callback */ + HAL_RTCEx_RTCEventErrorCallback(hrtc); + + /* Clear flag Second */ + __HAL_RTC_OVERFLOW_CLEAR_FLAG(hrtc, RTC_FLAG_OW); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + } + else + { + /* Second callback */ + HAL_RTCEx_RTCEventCallback(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Clear flag Second */ + __HAL_RTC_SECOND_CLEAR_FLAG(hrtc, RTC_FLAG_SEC); + } + } +} + +/** + * @brief Second event callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_RTCEventCallback could be implemented in the user file + */ +} + +/** + * @brief Second event error callback. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_RTCEventErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extension Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Writes a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Sets the Smooth calibration parameters. + +@endverbatim + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to + * specify the register (depending devices). + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)BKP_BASE; + tmp += (BackupRegister * 4U); + + *(__IO uint32_t *) tmp = (Data & BKP_DR1_D); +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to + * specify the register (depending devices). + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t backupregister = 0U; + uint32_t pvalue = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + backupregister = (uint32_t)BKP_BASE; + backupregister += (BackupRegister * 4U); + + pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D; + + /* Read the specified register */ + return pvalue; +} + + +/** + * @brief Sets the Smooth calibration parameters. + * @param hrtc: RTC handle + * @param SmoothCalibPeriod: Not used (only present for compatibility with another families) + * @param SmoothCalibPlusPulses: Not used (only present for compatibility with another families) + * @param SmouthCalibMinusPulsesValue: specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +{ + /* Check input parameters */ + if (hrtc == NULL) + { + return HAL_ERROR; + } + /* Prevent unused argument(s) compilation warning */ + UNUSED(SmoothCalibPeriod); + UNUSED(SmoothCalibPlusPulses); + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Sets RTC Clock Calibration value.*/ + MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, SmouthCalibMinusPulsesValue); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c new file mode 100644 index 0000000..ec5490d --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c @@ -0,0 +1,3898 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Master Receive mode restriction: + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or + bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + does not initiate a new transfer the following procedure has to be respected: + (##) HAL_SPI_DeInit() + (##) HAL_SPI_Init() + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + + [..] + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + [..] + When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. + + @endverbatim + + Additional table : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (8bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +#if (USE_SPI_CRC != 0U) && defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) +/* CRC WORKAOUND FEATURE: Variable used to determine if device is impacted by implementation + * of workaround related to wrong CRC errors detection on SPI2. Conditions in which this workaround + * has to be applied, are: + * - STM32F101CDE/STM32F103CDE + * - Revision ID : Z + * - SPI2 + * - In receive only mode, with CRC calculation enabled, at the end of the CRC reception, + * the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC: + * + If the value is 0, the complete data transfer is successful. + * + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA. + * If CRCERR is found reset, the complete data transfer is considered successful. + * + * Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for + * CRC errors wrongly detected + */ +/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode + * Revision ID information is only available in Debug mode, so Workaround could not be implemented + * to distinguish Rev Z devices (issue present) from more recent version (issue fixed). + * So, in case of Revison Z F101 or F103 devices, below define should be assigned to 1. + */ +#define USE_SPI_CRC_ERROR_WORKAROUND 0U +#endif +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on this device. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + } +#if (USE_SPI_CRC != 0U) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE)); + +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + uint16_t initial_TxXferCount; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + initial_TxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error: + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + /* this is done to handle the CRCNEXT before the latest data */ + hspi->RxXferCount--; + } +#endif /* USE_SPI_CRC */ + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + /* read the received data */ + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* freeze the CRC before the latest data */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + + /* Check if CRCNEXT is well reseted by hardware */ + if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT)) + { + /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */ + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + /* Read the latest data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* the latest data has not been received */ + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Receive last data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + } + + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Read CRC to Flush DR and RXNE flag */ + READ_REG(hspi->Instance->DR); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout) +{ + uint16_t initial_TxXferCount; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + uint32_t tickstart; + + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + initial_TxXferCount = Size; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Check RXNE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Wait until RXNE flag is reset */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Read CRC from DR to close CRC calculation process */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read CRC */ + READ_REG(hspi->Instance->DR); + } + + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + + errorcode = HAL_ERROR; + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + errorcode = HAL_ERROR; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + goto error; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + +error: + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + uint32_t abortcplt ; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + /* Abort the SPI DMA rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + hspi->State = HAL_SPI_STATE_READY; + return errorcode; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + + /* SPI in mode Receiver ----------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)) + && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + { + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + else + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + return; + } + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + + hspi->State = HAL_SPI_STATE_READY; + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->TxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Tx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC */ + READ_REG(hspi->Instance->DR); + } +#endif /* USE_SPI_CRC */ + + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + READ_REG(hspi->Instance->DR); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Tx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Rx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user TxRx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Stop the disable DMA transfer on SPI side */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + __IO uint32_t count; + + hspi->hdmatx->XferAbortCallback = NULL; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Check Busy flag */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8bit mode */ + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + + /* Check end of the reception */ + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 8bit CRC to flush Data Regsiter */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + /* Check the end of the transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 16bit CRC to flush Data Regsiter */ + READ_REG(hspi->Instance->DR); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + SPI_CloseRxTx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 8bit CRC to flush Data Register */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + /* Check if CRCNEXT is well reseted by hardware */ + if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT)) + { + /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */ + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 16bit CRC to flush Data Register */ + READ_REG(hspi->Instance->DR); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + /* Check if CRCNEXT is well reseted by hardware */ + if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT)) + { + /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */ + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle the check of the RX transaction complete. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)) + { + /* Wait the RXNE reset */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + else + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Handle the check of the RXTX or TX transaction complete. + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the RX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the TX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle abort a Rx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + /* Read CRC to flush Data Register */ + READ_REG(hspi->Instance->DR); + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @brief Handle abort a Tx or Rx/Tx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable TXEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->State = HAL_SPI_STATE_ABORT; +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors + * according to SPI instance, Device type, and revision ID. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR). + */ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) +{ +#if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U) + /* Check how to handle this CRC error (workaround to be applied or not) */ + /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */ + if(hspi->Instance == SPI2) + { + if(hspi->Instance->RXCRCR == 0U) + { + return (SPI_INVALID_CRC_ERROR); + } + } +#endif + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + return (SPI_VALID_CRC_ERROR); +} +#endif /* USE_SPI_CRC */ +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c new file mode 100644 index 0000000..4069298 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c @@ -0,0 +1,6651 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Change the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_ALL: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + default: + break; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + default: + break; + } + + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + default: + break; + } + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture/compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances + * supporting a break input. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + break; + } + return HAL_OK; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P); + tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P); + tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c new file mode 100644 index 0000000..7d4b5d8 --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c @@ -0,0 +1,1921 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c new file mode 100644 index 0000000..74bea9a --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c @@ -0,0 +1,3160 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (##) Enable the USARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins (TX as alternate function pull-up, RX as alternate function Input). + (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required + Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the huart Init structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. + + (#) For the Multi-Processor mode, initialize the UART registers by calling + the HAL_MultiProcessor_Init() API. + + [..] + (@) The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit + and receive process. + + [..] + (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the + low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized + HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_UART_RegisterCallback() to register a user callback. + Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() + and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() + or @ref HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_UART_Transmit() + (+) Receive an amount of data in blocking mode using HAL_UART_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + (+) Pause the DMA Transfer using HAL_UART_DMAPause() + (+) Resume the DMA Transfer using HAL_UART_DMAResume() + (+) Stop the DMA Transfer using HAL_UART_DMAStop() + + *** UART HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in UART HAL driver. + + (+) __HAL_UART_ENABLE: Enable the UART peripheral + (+) __HAL_UART_DISABLE: Disable the UART peripheral + (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not + (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag + (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt + (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt + (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not + + [..] + (@) You can refer to the UART HAL driver header file for more useful macros + + @endverbatim + [..] + (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup UART_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static void UART_SetConfig(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + please refer to Reference manual for possible UART frame formats. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs + follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration + procedures (details for the procedures are available in reference manuals + (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the UART mode according to the specified parameters in + * the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + } + else + { + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the LIN mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection + * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In LIN mode, the following bits must be kept cleared: + - CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL); + SET_BIT(huart->Instance->CR2, BreakDetectLength); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the Multi-Processor mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Address USART address + * @param WakeUpMethod specifies the USART wake-up method. + * This parameter can be one of the following values: + * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection + * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Check the Address & wake up method parameters */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + assert_param(IS_UART_ADDRESS(Address)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In Multi-Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Set the USART address node */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD); + SET_BIT(huart->Instance->CR2, Address); + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE); + SET_BIT(huart->Instance->CR1, WakeUpMethod); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief UART MSP Init. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspInit could be implemented in the user file + */ +} + +/** + * @brief UART MSP DeInit. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, these API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected. + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t *tmp; + uint32_t tickstart = 0U; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + while (huart->TxXferCount > 0U) + { + huart->TxXferCount--; + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t *) pData; + huart->Instance->DR = (*tmp & (uint16_t)0x01FF); + if (huart->Init.Parity == UART_PARITY_NONE) + { + pData += 2U; + } + else + { + pData += 1U; + } + } + else + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + huart->Instance->DR = (*pData++ & (uint8_t)0xFF); + } + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t *tmp; + uint32_t tickstart = 0U; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Check the remain data to be received */ + while (huart->RxXferCount > 0U) + { + huart->RxXferCount--; + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + tmp = (uint16_t *) pData; + if (huart->Init.Parity == UART_PARITY_NONE) + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + pData += 2U; + } + else + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); + pData += 1U; + } + + } + else + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (huart->Init.Parity == UART_PARITY_NONE) + { + *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + + } + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Transmit data register empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + + /* Enable the UART Data Register not empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + tmp = (uint32_t *)&pData; + HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); + + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + tmp = (uint32_t *)&pData; + HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); + + /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + */ + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->RxState and huart->gState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t AbortCplt = 0x01U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + AbortCplt = 0x01U; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (AbortCplt == 0x01U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief This function handles UART interrupt request. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->SR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags = 0x00U; + uint32_t dmarequest = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + if (errorflags == RESET) + { + /* UART in mode Receiver -------------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + return; + } + } + + /* If some errors occur */ + if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + { + /* UART parity error interrupt occurred ----------------------------------*/ + if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART noise error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART frame error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART Over-Run interrupt occurred --------------------------------------*/ + if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver -----------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + } /* End if some error occurs */ + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + { + UART_Transmit_IT(huart); + return; + } + + /* UART in mode Transmitter end --------------------------------------------*/ + if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + { + UART_EndTransmit_IT(huart); + return; + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief UART error callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character. + (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. + (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software. + (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode + (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode + +@endverbatim + * @{ + */ + +/** + * @brief Transmits break characters. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + SET_BIT(huart->Instance->CR1, USART_CR1_SBK); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enters the UART in mute mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Exits the UART mute mode: wake up software. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART transmitter and disables the UART receiver. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_TE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART receiver and disables the UART transmitter. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_RE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. + (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + uint32_t temp1 = 0x00U, temp2 = 0x00U; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART error code + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + huart->TxXferCount = 0x00U; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + huart->RxXferCount = 0U; + + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t dmarequest = 0x00U; + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + huart->TxXferCount = 0x00U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + huart->RxXferCount = 0x00U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief This function handles UART Communication Timeout. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Flag specifies the UART flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + huart->RxXferCount = 0x00U; + huart->TxXferCount = 0x00U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + tmp = (uint16_t *) huart->pTxBuffPtr; + huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); + if (huart->Init.Parity == UART_PARITY_NONE) + { + huart->pTxBuffPtr += 2U; + } + else + { + huart->pTxBuffPtr += 1U; + } + } + else + { + huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); + } + + if (--huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + return HAL_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + tmp = (uint16_t *) huart->pRxBuffPtr; + if (huart->Init.Parity == UART_PARITY_NONE) + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + huart->pRxBuffPtr += 2U; + } + else + { + *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); + huart->pRxBuffPtr += 1U; + } + } + else + { + if (huart->Init.Parity == UART_PARITY_NONE) + { + *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + } + + if (--huart->RxXferCount == 0U) + { + /* Disable the UART Data Register not empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + return HAL_OK; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits + according to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the UART Word Length, Parity and mode: + Set the M bits according to huart->Init.WordLength value + Set PCE and PS bits according to huart->Init.Parity value + Set TE and RE bits according to huart->Init.Mode value + Set OVER8 bit according to huart->Init.OverSampling value */ + +#if defined(USART_CR1_OVER8) + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); +#else + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), + tmpreg); +#endif /* USART_CR1_OVER8 */ + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); + +#if defined(USART_CR1_OVER8) + /* Check the Over Sampling */ + if(huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + /*-------------------------- USART BRR Configuration ---------------------*/ + if(huart->Instance == USART1) + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } + } + else + { + /*-------------------------- USART BRR Configuration ---------------------*/ + if(huart->Instance == USART1) + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } + } +#else + /*-------------------------- USART BRR Configuration ---------------------*/ + if(huart->Instance == USART1) + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } +#endif /* USART_CR1_OVER8 */ +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c new file mode 100644 index 0000000..e0714af --- /dev/null +++ b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c @@ -0,0 +1,2591 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_usb.c + * @author MCD Application Team + * @brief USB Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. + + (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_LL_USB_DRIVER + * @{ + */ + +#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) +#if defined (USB) || defined (USB_OTG_FS) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + if (cfg.use_external_vbus == 1U) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + } + else /* FS interface (embedded Phy) */ + { + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select and set Host mode */ + ret = USB_CoreReset(USBx); + + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status +*/ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode : Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE: Peripheral mode + * @arg USB_HOST_MODE: Host mode + * @arg USB_DRD_MODE: Dual Role Device mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode) +{ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + } + else if (mode == USB_DEVICE_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + } + else + { + return HAL_ERROR; + } + HAL_Delay(50U); + + return HAL_OK; +} + +/** + * @brief USB_DevInit : Initializes the USB_OTG controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + + /* Enable HW VBUS sensing */ + USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + /* Device mode configuration */ + USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; + + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + + /* Flush the FIFOs */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } + } + else + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } + } + else + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + + /* Enable the common interrupts */ + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; + + if (cfg.Sof_enable != 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + } + + if (cfg.vbus_sensing_enable == 1U) + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + } + + return ret; +} + +/** + * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO + * @param USBx Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + uint32_t count = 0U; + + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t count = 0; + + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG |= speed; + return HAL_OK; +} + +/** + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg PCD_SPEED_FULL: Full speed mode + */ +uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + } + else + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } + return HAL_OK; +} + +/** + * @brief Activate and configure a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); + } + else + { + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + } + } + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len); + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + +/** + * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pSrc = (uint32_t *)src; + uint32_t count32b, i; + + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + } + + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pDest = (uint32_t *)dest; + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; + } + + return ((void *)pDest); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + HAL_Delay(3U); + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + HAL_Delay(3U); + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg, msk, emp; + + msk = USBx_DEVICE->DIEPMSK; + emp = USBx_DEVICE->DIEPEMPMSK; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +{ + USBx->GINTSTS |= interrupt; +} + +/** + * @brief Returns USB core mode + * @param USBx Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 0 : Host + * 1 : Device + */ +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* Set the MPS of the IN EP0 to 64 bytes */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + + return HAL_OK; +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) +{ + UNUSED(psetup); + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + + if (gSNPSiD > USB_OTG_CORE_ID_300A) + { + if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + return HAL_OK; + } + } + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return HAL_OK; +} + +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSASEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSBSEN); + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + + /* Make sure the FIFOs are flushed. */ + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINTMSK = 0U; + } + + /* Enable VBUS driving */ + (void)USB_DriveVbus(USBx, 1U); + + HAL_Delay(200U); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xFFFFFFFFU; + + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + /* Enable the common interrupts */ + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return HAL_OK; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = 48000U; + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = 6000U; + } + else + { + /* ... */ + } + + return HAL_OK; +} + +/** +* @brief USB_OTG_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + + return HAL_OK; +} + +/** + * @brief USB_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : VBUS Active + * 1 : VBUS Inactive + * @retval HAL status +*/ +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + } + return HAL_OK; +} + +/** + * @brief Return Host Core speed + * @param USBx Selected device + * @retval speed : Host speed + * This parameter can be one of these values: + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number +*/ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir, HCcharLowSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + if (speed == HPRT0_PRTSPD_LOW_SPEED) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + + if (ep_type == EP_TYPE_INTR) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + static __IO uint32_t tmpreg = 0U; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = 256U; + + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + if (hc->ep_is_in != 0U) + { + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len); + } + + return HAL_OK; +} + +/** + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do + { + if (++count > 1000U) + { + break; + } + } + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do + { + if (++count > 1000U) + { + break; + } + } + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + + return HAL_OK; +} + +/** + * @brief Initiate Do Ping protocol + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t count = 0U; + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + + /* Flush FIFO */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + + do + { + if (++count > 1000U) + { + break; + } + } + while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = 0xFFFFFFFFU; + USBx->GINTSTS = 0xFFFFFFFFU; + + (void)USB_EnableGlobalInt(USBx); + + return HAL_OK; +} + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) */ + +#if defined (USB) +/** + * @brief Initializes the USB Core + * @param USBx: USB Instance + * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(cfg); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) +{ + uint16_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM; + + /* Set interrupt mask */ + USBx->CNTR |= winterruptmask; + + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx : Selected device + * @retval HAL status +*/ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) +{ + uint16_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM; + + /* Clear interrupt mask */ + USBx->CNTR &= ~winterruptmask; + + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode : Set functional mode + * @param USBx : Selected device + * @param mode : current core mode + * This parameter can be one of the these values: + * @arg USB_DEVICE_MODE: Peripheral mode mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(mode); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; +} + +/** + * @brief USB_DevInit : Initializes the USB controller registers + * for device mode + * @param USBx : Selected device + * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(cfg); + + /* Init Device */ + /*CNTR_FRES = 1*/ + USBx->CNTR = USB_CNTR_FRES; + + /*CNTR_FRES = 0*/ + USBx->CNTR = 0; + + /*Clear pending interrupts*/ + USBx->ISTR = 0; + + /*Set Btable Address*/ + USBx->BTABLE = BTABLE_ADDRESS; + + /* Enable USB Device Interrupt mask */ + (void)USB_EnableGlobalInt(USBx); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed :Initializes the device speed + * depending on the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(speed); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_FlushTxFifo : Flush a Tx FIFO + * @param USBx : Selected device + * @param num : FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(num); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint16_t wEpRegVal; + + wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; + + /* initialize Endpoint */ + switch (ep->type) + { + case EP_TYPE_CTRL: + wEpRegVal |= USB_EP_CONTROL; + break; + + case EP_TYPE_BULK: + wEpRegVal |= USB_EP_BULK; + break; + + case EP_TYPE_INTR: + wEpRegVal |= USB_EP_INTERRUPT; + break; + + case EP_TYPE_ISOC: + wEpRegVal |= USB_EP_ISOCHRONOUS; + break; + + default: + ret = HAL_ERROR; + break; + } + + PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX); + + PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); + + if (ep->doublebuffer == 0U) + { + if (ep->is_in != 0U) + { + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + } + else + { + /*Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); + /*Set the endpoint Receive buffer counter*/ + PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); + PCD_CLEAR_RX_DTOG(USBx, ep->num); + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + } + /*Double Buffer*/ + else + { + /* Set the endpoint as double buffered */ + PCD_SET_EP_DBUF(USBx, ep->num); + /* Set buffer address for double buffered mode */ + PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); + + if (ep->is_in == 0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + /* Reset value of the data toggle bits for the endpoint out */ + PCD_TX_DTOG(USBx, ep->num); + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_RX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } + + return ret; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + if (ep->doublebuffer == 0U) + { + if (ep->is_in != 0U) + { + PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } + /*Double Buffer*/ + else + { + if (ep->is_in == 0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(USBx, ep->num); + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_RX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + uint16_t pmabuffer; + uint32_t len; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /*Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len -= len; + } + else + { + len = ep->xfer_len; + ep->xfer_len = 0U; + } + + /* configure and validate Tx endpoint */ + if (ep->doublebuffer == 0U) + { + USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); + PCD_SET_EP_TX_CNT(USBx, ep->num, len); + } + else + { + /* Write the data to the USB endpoint */ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + } + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); + } + + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); + } + else /* OUT endpoint */ + { + /* Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len -= len; + } + else + { + len = ep->xfer_len; + ep->xfer_len = 0U; + } + + /* configure and validate Rx endpoint */ + if (ep->doublebuffer == 0U) + { + /*Set RX buffer count*/ + PCD_SET_EP_RX_CNT(USBx, ep->num, len); + } + else + { + /*Set the Double buffer counter*/ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + } + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + + return HAL_OK; +} + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx : Selected device + * @param src : pointer to source buffer + * @param ch_ep_num : endpoint or host channel number + * @param len : Number of bytes to write + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(src); + UNUSED(ch_ep_num); + UNUSED(len); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the Tx FIFO associated + * with the EP/channel + * @param USBx : Selected device + * @param dest : destination pointer + * @param len : Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(dest); + UNUSED(len); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return ((void *)NULL); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + if (ep->is_in != 0U) + { + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); + } + else + { + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx : Selected device + * @param ep: pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) +{ + if (ep->doublebuffer == 0U) + { + if (ep->is_in != 0U) + { + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + } + + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) +{ + /* disable all interrupts and force USB reset */ + USBx->CNTR = USB_CNTR_FRES; + + /* clear interrupt status register */ + USBx->ISTR = 0; + + /* switch-off device */ + USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); + + return HAL_OK; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx : Selected device + * @param address : new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) +{ + if (address == 0U) + { + /* set device address and enable function */ + USBx->DADDR = USB_DADDR_EF; + } + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx : Selected device + * @retval HAL status + */ +uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->ISTR; + return tmpreg; +} + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx : Selected device + * @retval HAL status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return (0); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx : Selected device + * @retval HAL status + */ +uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return (0); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx : Selected device + * @param epnum : endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(epnum); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return (0); +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx : Selected device + * @param epnum : endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(epnum); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return (0); +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(interrupt); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(psetup); + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + return HAL_OK; +} + +/** + * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) +{ + USBx->CNTR |= USB_CNTR_RESUME; + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) +{ + USBx->CNTR &= ~(USB_CNTR_RESUME); + return HAL_OK; +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp1, temp2; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) + { + temp1 = *pBuf; + pBuf++; + temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8)); + *pdwVal = (uint16_t)temp2; + pdwVal++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + + pBuf++; + } +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx: USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes: no. of bytes to be copied. + * @retval None + */ +void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (uint32_t)wNBytes >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) + { + temp = *(__IO uint16_t *)pdwVal; + pdwVal++; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + pBuf++; + *pBuf = (uint8_t)((temp >> 8) & 0xFFU); + pBuf++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + } + + if ((wNBytes % 2U) != 0U) + { + temp = *pdwVal; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + } +} +#endif /* defined (USB) */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB) || defined (USB_OTG_FS) */ +#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/ili9341/fonts.c b/Drivers/ili9341/fonts.c new file mode 100644 index 0000000..8e6377a --- /dev/null +++ b/Drivers/ili9341/fonts.c @@ -0,0 +1,300 @@ +/* vim: set ai et ts=4 sw=4: */ +#include "fonts.h" + +static const uint16_t Font7x10 [] = { +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // sp +0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x0000, 0x0000, // ! +0x2800, 0x2800, 0x2800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // " +0x2400, 0x2400, 0x7C00, 0x2400, 0x4800, 0x7C00, 0x4800, 0x4800, 0x0000, 0x0000, // # +0x3800, 0x5400, 0x5000, 0x3800, 0x1400, 0x5400, 0x5400, 0x3800, 0x1000, 0x0000, // $ +0x2000, 0x5400, 0x5800, 0x3000, 0x2800, 0x5400, 0x1400, 0x0800, 0x0000, 0x0000, // % +0x1000, 0x2800, 0x2800, 0x1000, 0x3400, 0x4800, 0x4800, 0x3400, 0x0000, 0x0000, // & +0x1000, 0x1000, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ' +0x0800, 0x1000, 0x2000, 0x2000, 0x2000, 0x2000, 0x2000, 0x2000, 0x1000, 0x0800, // ( +0x2000, 0x1000, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x1000, 0x2000, // ) +0x1000, 0x3800, 0x1000, 0x2800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // * +0x0000, 0x0000, 0x1000, 0x1000, 0x7C00, 0x1000, 0x1000, 0x0000, 0x0000, 0x0000, // + +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1000, 0x1000, 0x1000, // , +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3800, 0x0000, 0x0000, 0x0000, 0x0000, // - +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, // . +0x0800, 0x0800, 0x1000, 0x1000, 0x1000, 0x1000, 0x2000, 0x2000, 0x0000, 0x0000, // / +0x3800, 0x4400, 0x4400, 0x5400, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // 0 +0x1000, 0x3000, 0x5000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // 1 +0x3800, 0x4400, 0x4400, 0x0400, 0x0800, 0x1000, 0x2000, 0x7C00, 0x0000, 0x0000, // 2 +0x3800, 0x4400, 0x0400, 0x1800, 0x0400, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // 3 +0x0800, 0x1800, 0x2800, 0x2800, 0x4800, 0x7C00, 0x0800, 0x0800, 0x0000, 0x0000, // 4 +0x7C00, 0x4000, 0x4000, 0x7800, 0x0400, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // 5 +0x3800, 0x4400, 0x4000, 0x7800, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // 6 +0x7C00, 0x0400, 0x0800, 0x1000, 0x1000, 0x2000, 0x2000, 0x2000, 0x0000, 0x0000, // 7 +0x3800, 0x4400, 0x4400, 0x3800, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // 8 +0x3800, 0x4400, 0x4400, 0x4400, 0x3C00, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // 9 +0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, // : +0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, 0x1000, 0x1000, 0x1000, // ; +0x0000, 0x0000, 0x0C00, 0x3000, 0x4000, 0x3000, 0x0C00, 0x0000, 0x0000, 0x0000, // < +0x0000, 0x0000, 0x0000, 0x7C00, 0x0000, 0x7C00, 0x0000, 0x0000, 0x0000, 0x0000, // = +0x0000, 0x0000, 0x6000, 0x1800, 0x0400, 0x1800, 0x6000, 0x0000, 0x0000, 0x0000, // > +0x3800, 0x4400, 0x0400, 0x0800, 0x1000, 0x1000, 0x0000, 0x1000, 0x0000, 0x0000, // ? +0x3800, 0x4400, 0x4C00, 0x5400, 0x5C00, 0x4000, 0x4000, 0x3800, 0x0000, 0x0000, // @ +0x1000, 0x2800, 0x2800, 0x2800, 0x2800, 0x7C00, 0x4400, 0x4400, 0x0000, 0x0000, // A +0x7800, 0x4400, 0x4400, 0x7800, 0x4400, 0x4400, 0x4400, 0x7800, 0x0000, 0x0000, // B +0x3800, 0x4400, 0x4000, 0x4000, 0x4000, 0x4000, 0x4400, 0x3800, 0x0000, 0x0000, // C +0x7000, 0x4800, 0x4400, 0x4400, 0x4400, 0x4400, 0x4800, 0x7000, 0x0000, 0x0000, // D +0x7C00, 0x4000, 0x4000, 0x7C00, 0x4000, 0x4000, 0x4000, 0x7C00, 0x0000, 0x0000, // E +0x7C00, 0x4000, 0x4000, 0x7800, 0x4000, 0x4000, 0x4000, 0x4000, 0x0000, 0x0000, // F +0x3800, 0x4400, 0x4000, 0x4000, 0x5C00, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // G +0x4400, 0x4400, 0x4400, 0x7C00, 0x4400, 0x4400, 0x4400, 0x4400, 0x0000, 0x0000, // H +0x3800, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x3800, 0x0000, 0x0000, // I +0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // J +0x4400, 0x4800, 0x5000, 0x6000, 0x5000, 0x4800, 0x4800, 0x4400, 0x0000, 0x0000, // K +0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x4000, 0x7C00, 0x0000, 0x0000, // L +0x4400, 0x6C00, 0x6C00, 0x5400, 0x4400, 0x4400, 0x4400, 0x4400, 0x0000, 0x0000, // M +0x4400, 0x6400, 0x6400, 0x5400, 0x5400, 0x4C00, 0x4C00, 0x4400, 0x0000, 0x0000, // N +0x3800, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // O +0x7800, 0x4400, 0x4400, 0x4400, 0x7800, 0x4000, 0x4000, 0x4000, 0x0000, 0x0000, // P +0x3800, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x5400, 0x3800, 0x0400, 0x0000, // Q +0x7800, 0x4400, 0x4400, 0x4400, 0x7800, 0x4800, 0x4800, 0x4400, 0x0000, 0x0000, // R +0x3800, 0x4400, 0x4000, 0x3000, 0x0800, 0x0400, 0x4400, 0x3800, 0x0000, 0x0000, // S +0x7C00, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // T +0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // U +0x4400, 0x4400, 0x4400, 0x2800, 0x2800, 0x2800, 0x1000, 0x1000, 0x0000, 0x0000, // V +0x4400, 0x4400, 0x5400, 0x5400, 0x5400, 0x6C00, 0x2800, 0x2800, 0x0000, 0x0000, // W +0x4400, 0x2800, 0x2800, 0x1000, 0x1000, 0x2800, 0x2800, 0x4400, 0x0000, 0x0000, // X +0x4400, 0x4400, 0x2800, 0x2800, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // Y +0x7C00, 0x0400, 0x0800, 0x1000, 0x1000, 0x2000, 0x4000, 0x7C00, 0x0000, 0x0000, // Z +0x1800, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1800, // [ +0x2000, 0x2000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0800, 0x0800, 0x0000, 0x0000, /* \ */ +0x3000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x3000, // ] +0x1000, 0x2800, 0x2800, 0x4400, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ^ +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xFE00, // _ +0x2000, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ` +0x0000, 0x0000, 0x3800, 0x4400, 0x3C00, 0x4400, 0x4C00, 0x3400, 0x0000, 0x0000, // a +0x4000, 0x4000, 0x5800, 0x6400, 0x4400, 0x4400, 0x6400, 0x5800, 0x0000, 0x0000, // b +0x0000, 0x0000, 0x3800, 0x4400, 0x4000, 0x4000, 0x4400, 0x3800, 0x0000, 0x0000, // c +0x0400, 0x0400, 0x3400, 0x4C00, 0x4400, 0x4400, 0x4C00, 0x3400, 0x0000, 0x0000, // d +0x0000, 0x0000, 0x3800, 0x4400, 0x7C00, 0x4000, 0x4400, 0x3800, 0x0000, 0x0000, // e +0x0C00, 0x1000, 0x7C00, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // f +0x0000, 0x0000, 0x3400, 0x4C00, 0x4400, 0x4400, 0x4C00, 0x3400, 0x0400, 0x7800, // g +0x4000, 0x4000, 0x5800, 0x6400, 0x4400, 0x4400, 0x4400, 0x4400, 0x0000, 0x0000, // h +0x1000, 0x0000, 0x7000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // i +0x1000, 0x0000, 0x7000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0xE000, // j +0x4000, 0x4000, 0x4800, 0x5000, 0x6000, 0x5000, 0x4800, 0x4400, 0x0000, 0x0000, // k +0x7000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x0000, 0x0000, // l +0x0000, 0x0000, 0x7800, 0x5400, 0x5400, 0x5400, 0x5400, 0x5400, 0x0000, 0x0000, // m +0x0000, 0x0000, 0x5800, 0x6400, 0x4400, 0x4400, 0x4400, 0x4400, 0x0000, 0x0000, // n +0x0000, 0x0000, 0x3800, 0x4400, 0x4400, 0x4400, 0x4400, 0x3800, 0x0000, 0x0000, // o +0x0000, 0x0000, 0x5800, 0x6400, 0x4400, 0x4400, 0x6400, 0x5800, 0x4000, 0x4000, // p +0x0000, 0x0000, 0x3400, 0x4C00, 0x4400, 0x4400, 0x4C00, 0x3400, 0x0400, 0x0400, // q +0x0000, 0x0000, 0x5800, 0x6400, 0x4000, 0x4000, 0x4000, 0x4000, 0x0000, 0x0000, // r +0x0000, 0x0000, 0x3800, 0x4400, 0x3000, 0x0800, 0x4400, 0x3800, 0x0000, 0x0000, // s +0x2000, 0x2000, 0x7800, 0x2000, 0x2000, 0x2000, 0x2000, 0x1800, 0x0000, 0x0000, // t +0x0000, 0x0000, 0x4400, 0x4400, 0x4400, 0x4400, 0x4C00, 0x3400, 0x0000, 0x0000, // u +0x0000, 0x0000, 0x4400, 0x4400, 0x2800, 0x2800, 0x2800, 0x1000, 0x0000, 0x0000, // v +0x0000, 0x0000, 0x5400, 0x5400, 0x5400, 0x6C00, 0x2800, 0x2800, 0x0000, 0x0000, // w +0x0000, 0x0000, 0x4400, 0x2800, 0x1000, 0x1000, 0x2800, 0x4400, 0x0000, 0x0000, // x +0x0000, 0x0000, 0x4400, 0x4400, 0x2800, 0x2800, 0x1000, 0x1000, 0x1000, 0x6000, // y +0x0000, 0x0000, 0x7C00, 0x0800, 0x1000, 0x2000, 0x4000, 0x7C00, 0x0000, 0x0000, // z +0x1800, 0x1000, 0x1000, 0x1000, 0x2000, 0x2000, 0x1000, 0x1000, 0x1000, 0x1800, // { +0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, // | +0x3000, 0x1000, 0x1000, 0x1000, 0x0800, 0x0800, 0x1000, 0x1000, 0x1000, 0x3000, // } +0x0000, 0x0000, 0x0000, 0x7400, 0x4C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ~ +}; + +static const uint16_t Font11x18 [] = { +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // sp +0x0000, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // ! +0x0000, 0x1B00, 0x1B00, 0x1B00, 0x1B00, 0x1B00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // " +0x0000, 0x1980, 0x1980, 0x1980, 0x1980, 0x7FC0, 0x7FC0, 0x1980, 0x3300, 0x7FC0, 0x7FC0, 0x3300, 0x3300, 0x3300, 0x3300, 0x0000, 0x0000, 0x0000, // # +0x0000, 0x1E00, 0x3F00, 0x7580, 0x6580, 0x7400, 0x3C00, 0x1E00, 0x0700, 0x0580, 0x6580, 0x6580, 0x7580, 0x3F00, 0x1E00, 0x0400, 0x0400, 0x0000, // $ +0x0000, 0x7000, 0xD800, 0xD840, 0xD8C0, 0xD980, 0x7300, 0x0600, 0x0C00, 0x1B80, 0x36C0, 0x66C0, 0x46C0, 0x06C0, 0x0380, 0x0000, 0x0000, 0x0000, // % +0x0000, 0x1E00, 0x3F00, 0x3300, 0x3300, 0x3300, 0x1E00, 0x0C00, 0x3CC0, 0x66C0, 0x6380, 0x6180, 0x6380, 0x3EC0, 0x1C80, 0x0000, 0x0000, 0x0000, // & +0x0000, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ' +0x0080, 0x0100, 0x0300, 0x0600, 0x0600, 0x0400, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0400, 0x0600, 0x0600, 0x0300, 0x0100, 0x0080, // ( +0x2000, 0x1000, 0x1800, 0x0C00, 0x0C00, 0x0400, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0400, 0x0C00, 0x0C00, 0x1800, 0x1000, 0x2000, // ) +0x0000, 0x0C00, 0x2D00, 0x3F00, 0x1E00, 0x3300, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // * +0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0xFFC0, 0xFFC0, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // + +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0400, 0x0400, 0x0800, // , +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x1E00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // - +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // . +0x0000, 0x0300, 0x0300, 0x0300, 0x0600, 0x0600, 0x0600, 0x0600, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x1800, 0x1800, 0x1800, 0x0000, 0x0000, 0x0000, // / +0x0000, 0x1E00, 0x3F00, 0x3300, 0x6180, 0x6180, 0x6180, 0x6D80, 0x6D80, 0x6180, 0x6180, 0x6180, 0x3300, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 0 +0x0000, 0x0600, 0x0E00, 0x1E00, 0x3600, 0x2600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, // 1 +0x0000, 0x1E00, 0x3F00, 0x7380, 0x6180, 0x6180, 0x0180, 0x0300, 0x0600, 0x0C00, 0x1800, 0x3000, 0x6000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, // 2 +0x0000, 0x1C00, 0x3E00, 0x6300, 0x6300, 0x0300, 0x0E00, 0x0E00, 0x0300, 0x0180, 0x0180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 3 +0x0000, 0x0600, 0x0E00, 0x0E00, 0x1E00, 0x1E00, 0x1600, 0x3600, 0x3600, 0x6600, 0x7F80, 0x7F80, 0x0600, 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, // 4 +0x0000, 0x7F00, 0x7F00, 0x6000, 0x6000, 0x6000, 0x6E00, 0x7F00, 0x6380, 0x0180, 0x0180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 5 +0x0000, 0x1E00, 0x3F00, 0x3380, 0x6180, 0x6000, 0x6E00, 0x7F00, 0x7380, 0x6180, 0x6180, 0x6180, 0x3380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 6 +0x0000, 0x7F80, 0x7F80, 0x0180, 0x0300, 0x0300, 0x0600, 0x0600, 0x0C00, 0x0C00, 0x0C00, 0x0800, 0x1800, 0x1800, 0x1800, 0x0000, 0x0000, 0x0000, // 7 +0x0000, 0x1E00, 0x3F00, 0x6380, 0x6180, 0x6180, 0x2100, 0x1E00, 0x3F00, 0x6180, 0x6180, 0x6180, 0x6180, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 8 +0x0000, 0x1E00, 0x3F00, 0x7300, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F80, 0x1D80, 0x0180, 0x6180, 0x7300, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // 9 +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // : +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C00, 0x0C00, 0x0400, 0x0400, 0x0800, // ; +0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0380, 0x0E00, 0x3800, 0x6000, 0x3800, 0x0E00, 0x0380, 0x0080, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // < +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // = +0x0000, 0x0000, 0x0000, 0x0000, 0x4000, 0x7000, 0x1C00, 0x0700, 0x0180, 0x0700, 0x1C00, 0x7000, 0x4000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // > +0x0000, 0x1F00, 0x3F80, 0x71C0, 0x60C0, 0x00C0, 0x01C0, 0x0380, 0x0700, 0x0E00, 0x0C00, 0x0C00, 0x0000, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // ? +0x0000, 0x1E00, 0x3F00, 0x3180, 0x7180, 0x6380, 0x6F80, 0x6D80, 0x6D80, 0x6F80, 0x6780, 0x6000, 0x3200, 0x3E00, 0x1C00, 0x0000, 0x0000, 0x0000, // @ +0x0000, 0x0E00, 0x0E00, 0x1B00, 0x1B00, 0x1B00, 0x1B00, 0x3180, 0x3180, 0x3F80, 0x3F80, 0x3180, 0x60C0, 0x60C0, 0x60C0, 0x0000, 0x0000, 0x0000, // A +0x0000, 0x7C00, 0x7E00, 0x6300, 0x6300, 0x6300, 0x6300, 0x7E00, 0x7E00, 0x6300, 0x6180, 0x6180, 0x6380, 0x7F00, 0x7E00, 0x0000, 0x0000, 0x0000, // B +0x0000, 0x1E00, 0x3F00, 0x3180, 0x6180, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6180, 0x3180, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // C +0x0000, 0x7C00, 0x7F00, 0x6300, 0x6380, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6300, 0x6300, 0x7E00, 0x7C00, 0x0000, 0x0000, 0x0000, // D +0x0000, 0x7F80, 0x7F80, 0x6000, 0x6000, 0x6000, 0x6000, 0x7F00, 0x7F00, 0x6000, 0x6000, 0x6000, 0x6000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, // E +0x0000, 0x7F80, 0x7F80, 0x6000, 0x6000, 0x6000, 0x6000, 0x7F00, 0x7F00, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x0000, 0x0000, 0x0000, // F +0x0000, 0x1E00, 0x3F00, 0x3180, 0x6180, 0x6000, 0x6000, 0x6000, 0x6380, 0x6380, 0x6180, 0x6180, 0x3180, 0x3F80, 0x1E00, 0x0000, 0x0000, 0x0000, // G +0x0000, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x7F80, 0x7F80, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, // H +0x0000, 0x3F00, 0x3F00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x3F00, 0x3F00, 0x0000, 0x0000, 0x0000, // I +0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x6180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // J +0x0000, 0x60C0, 0x6180, 0x6300, 0x6600, 0x6600, 0x6C00, 0x7800, 0x7C00, 0x6600, 0x6600, 0x6300, 0x6180, 0x6180, 0x60C0, 0x0000, 0x0000, 0x0000, // K +0x0000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, // L +0x0000, 0x71C0, 0x71C0, 0x7BC0, 0x7AC0, 0x6AC0, 0x6AC0, 0x6EC0, 0x64C0, 0x60C0, 0x60C0, 0x60C0, 0x60C0, 0x60C0, 0x60C0, 0x0000, 0x0000, 0x0000, // M +0x0000, 0x7180, 0x7180, 0x7980, 0x7980, 0x7980, 0x6D80, 0x6D80, 0x6D80, 0x6580, 0x6780, 0x6780, 0x6780, 0x6380, 0x6380, 0x0000, 0x0000, 0x0000, // N +0x0000, 0x1E00, 0x3F00, 0x3300, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x3300, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // O +0x0000, 0x7E00, 0x7F00, 0x6380, 0x6180, 0x6180, 0x6180, 0x6380, 0x7F00, 0x7E00, 0x6000, 0x6000, 0x6000, 0x6000, 0x6000, 0x0000, 0x0000, 0x0000, // P +0x0000, 0x1E00, 0x3F00, 0x3300, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6580, 0x6780, 0x3300, 0x3F80, 0x1E40, 0x0000, 0x0000, 0x0000, // Q +0x0000, 0x7E00, 0x7F00, 0x6380, 0x6180, 0x6180, 0x6380, 0x7F00, 0x7E00, 0x6600, 0x6300, 0x6300, 0x6180, 0x6180, 0x60C0, 0x0000, 0x0000, 0x0000, // R +0x0000, 0x0E00, 0x1F00, 0x3180, 0x3180, 0x3000, 0x3800, 0x1E00, 0x0700, 0x0380, 0x6180, 0x6180, 0x3180, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // S +0x0000, 0xFFC0, 0xFFC0, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // T +0x0000, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // U +0x0000, 0x60C0, 0x60C0, 0x60C0, 0x3180, 0x3180, 0x3180, 0x1B00, 0x1B00, 0x1B00, 0x1B00, 0x0E00, 0x0E00, 0x0E00, 0x0400, 0x0000, 0x0000, 0x0000, // V +0x0000, 0xC0C0, 0xC0C0, 0xC0C0, 0xC0C0, 0xC0C0, 0xCCC0, 0x4C80, 0x4C80, 0x5E80, 0x5280, 0x5280, 0x7380, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, // W +0x0000, 0xC0C0, 0x6080, 0x6180, 0x3300, 0x3B00, 0x1E00, 0x0C00, 0x0C00, 0x1E00, 0x1F00, 0x3B00, 0x7180, 0x6180, 0xC0C0, 0x0000, 0x0000, 0x0000, // X +0x0000, 0xC0C0, 0x6180, 0x6180, 0x3300, 0x3300, 0x1E00, 0x1E00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // Y +0x0000, 0x3F80, 0x3F80, 0x0180, 0x0300, 0x0300, 0x0600, 0x0C00, 0x0C00, 0x1800, 0x1800, 0x3000, 0x6000, 0x7F80, 0x7F80, 0x0000, 0x0000, 0x0000, // Z +0x0F00, 0x0F00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0F00, 0x0F00, // [ +0x0000, 0x1800, 0x1800, 0x1800, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, 0x0300, 0x0000, 0x0000, 0x0000, /* \ */ +0x1E00, 0x1E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x1E00, 0x1E00, // ] +0x0000, 0x0C00, 0x0C00, 0x1E00, 0x1200, 0x3300, 0x3300, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ^ +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xFFE0, 0x0000, // _ +0x0000, 0x3800, 0x1800, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ` +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1F00, 0x3F80, 0x6180, 0x0180, 0x1F80, 0x3F80, 0x6180, 0x6380, 0x7F80, 0x38C0, 0x0000, 0x0000, 0x0000, // a +0x0000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6E00, 0x7F00, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x7F00, 0x6E00, 0x0000, 0x0000, 0x0000, // b +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x3F00, 0x7380, 0x6180, 0x6000, 0x6000, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // c +0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x1D80, 0x3F80, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F80, 0x1D80, 0x0000, 0x0000, 0x0000, // d +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x3F00, 0x7300, 0x6180, 0x7F80, 0x7F80, 0x6000, 0x7180, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // e +0x0000, 0x07C0, 0x0FC0, 0x0C00, 0x0C00, 0x7F80, 0x7F80, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, // f +0x0000, 0x0000, 0x0000, 0x0000, 0x1D80, 0x3F80, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F80, 0x1D80, 0x0180, 0x6380, 0x7F00, 0x3E00, // g +0x0000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6F00, 0x7F80, 0x7180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, // h +0x0000, 0x0600, 0x0600, 0x0000, 0x0000, 0x3E00, 0x3E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, // i +0x0600, 0x0600, 0x0000, 0x0000, 0x3E00, 0x3E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x4600, 0x7E00, 0x3C00, // j +0x0000, 0x6000, 0x6000, 0x6000, 0x6000, 0x6180, 0x6300, 0x6600, 0x6C00, 0x7C00, 0x7600, 0x6300, 0x6300, 0x6180, 0x60C0, 0x0000, 0x0000, 0x0000, // k +0x0000, 0x3E00, 0x3E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, // l +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xDD80, 0xFFC0, 0xCEC0, 0xCCC0, 0xCCC0, 0xCCC0, 0xCCC0, 0xCCC0, 0xCCC0, 0xCCC0, 0x0000, 0x0000, 0x0000, // m +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6F00, 0x7F80, 0x7180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x0000, 0x0000, 0x0000, // n +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x3F00, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F00, 0x1E00, 0x0000, 0x0000, 0x0000, // o +0x0000, 0x0000, 0x0000, 0x0000, 0x6E00, 0x7F00, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x7F00, 0x6E00, 0x6000, 0x6000, 0x6000, 0x6000, // p +0x0000, 0x0000, 0x0000, 0x0000, 0x1D80, 0x3F80, 0x7380, 0x6180, 0x6180, 0x6180, 0x6180, 0x7380, 0x3F80, 0x1D80, 0x0180, 0x0180, 0x0180, 0x0180, // q +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6700, 0x3F80, 0x3900, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x0000, 0x0000, 0x0000, // r +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1E00, 0x3F80, 0x6180, 0x6000, 0x7F00, 0x3F80, 0x0180, 0x6180, 0x7F00, 0x1E00, 0x0000, 0x0000, 0x0000, // s +0x0000, 0x0000, 0x0800, 0x1800, 0x1800, 0x7F00, 0x7F00, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1F80, 0x0F80, 0x0000, 0x0000, 0x0000, // t +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6180, 0x6380, 0x7F80, 0x3D80, 0x0000, 0x0000, 0x0000, // u +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x60C0, 0x3180, 0x3180, 0x3180, 0x1B00, 0x1B00, 0x1B00, 0x0E00, 0x0E00, 0x0600, 0x0000, 0x0000, 0x0000, // v +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xDD80, 0xDD80, 0xDD80, 0x5500, 0x5500, 0x5500, 0x7700, 0x7700, 0x2200, 0x2200, 0x0000, 0x0000, 0x0000, // w +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6180, 0x3300, 0x3300, 0x1E00, 0x0C00, 0x0C00, 0x1E00, 0x3300, 0x3300, 0x6180, 0x0000, 0x0000, 0x0000, // x +0x0000, 0x0000, 0x0000, 0x0000, 0x6180, 0x6180, 0x3180, 0x3300, 0x3300, 0x1B00, 0x1B00, 0x1B00, 0x0E00, 0x0E00, 0x0E00, 0x1C00, 0x7C00, 0x7000, // y +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x7FC0, 0x7FC0, 0x0180, 0x0300, 0x0600, 0x0C00, 0x1800, 0x3000, 0x7FC0, 0x7FC0, 0x0000, 0x0000, 0x0000, // z +0x0380, 0x0780, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0E00, 0x1C00, 0x1C00, 0x0E00, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0780, 0x0380, // { +0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, // | +0x3800, 0x3C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0E00, 0x0700, 0x0700, 0x0E00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x0C00, 0x3C00, 0x3800, // } +0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3880, 0x7F80, 0x4700, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // ~ +}; + +static const uint16_t Font16x26 [] = { +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [ ] +0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03C0,0x03C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [!] +0x1E3C,0x1E3C,0x1E3C,0x1E3C,0x1E3C,0x1E3C,0x1E3C,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = ["] +0x01CE,0x03CE,0x03DE,0x039E,0x039C,0x079C,0x3FFF,0x7FFF,0x0738,0x0F38,0x0F78,0x0F78,0x0E78,0xFFFF,0xFFFF,0x1EF0,0x1CF0,0x1CE0,0x3CE0,0x3DE0,0x39E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [#] +0x03FC,0x0FFE,0x1FEE,0x1EE0,0x1EE0,0x1EE0,0x1EE0,0x1FE0,0x0FE0,0x07E0,0x03F0,0x01FC,0x01FE,0x01FE,0x01FE,0x01FE,0x01FE,0x01FE,0x3DFE,0x3FFC,0x0FF0,0x01E0,0x01E0,0x0000,0x0000,0x0000, // Ascii = [$] +0x3E03,0xF707,0xE78F,0xE78E,0xE39E,0xE3BC,0xE7B8,0xE7F8,0xF7F0,0x3FE0,0x01C0,0x03FF,0x07FF,0x07F3,0x0FF3,0x1EF3,0x3CF3,0x38F3,0x78F3,0xF07F,0xE03F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [%] +0x07E0,0x0FF8,0x0F78,0x1F78,0x1F78,0x1F78,0x0F78,0x0FF0,0x0FE0,0x1F80,0x7FC3,0xFBC3,0xF3E7,0xF1F7,0xF0F7,0xF0FF,0xF07F,0xF83E,0x7C7F,0x3FFF,0x1FEF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [&] +0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03C0,0x01C0,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = ['] +0x003F,0x007C,0x01F0,0x01E0,0x03C0,0x07C0,0x0780,0x0780,0x0F80,0x0F00,0x0F00,0x0F00,0x0F00,0x0F00,0x0F00,0x0F80,0x0780,0x0780,0x07C0,0x03C0,0x01E0,0x01F0,0x007C,0x003F,0x000F,0x0000, // Ascii = [(] +0x7E00,0x1F00,0x07C0,0x03C0,0x01E0,0x01F0,0x00F0,0x00F0,0x00F8,0x0078,0x0078,0x0078,0x0078,0x0078,0x0078,0x00F8,0x00F0,0x00F0,0x01F0,0x01E0,0x03C0,0x07C0,0x1F00,0x7E00,0x7800,0x0000, // Ascii = [)] +0x03E0,0x03C0,0x01C0,0x39CE,0x3FFF,0x3F7F,0x0320,0x0370,0x07F8,0x0F78,0x1F3C,0x0638,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [*] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0xFFFF,0xFFFF,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [+] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x01E0,0x01E0,0x01E0,0x01C0,0x0380, // Ascii = [,] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3FFE,0x3FFE,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [-] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [.] +0x000F,0x000F,0x001E,0x001E,0x003C,0x003C,0x0078,0x0078,0x00F0,0x00F0,0x01E0,0x01E0,0x03C0,0x03C0,0x0780,0x0780,0x0F00,0x0F00,0x1E00,0x1E00,0x3C00,0x3C00,0x7800,0x7800,0xF000,0x0000, // Ascii = [/] +0x07F0,0x0FF8,0x1F7C,0x3E3E,0x3C1E,0x7C1F,0x7C1F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x7C1F,0x7C1F,0x3C1E,0x3E3E,0x1F7C,0x0FF8,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [0] +0x00F0,0x07F0,0x3FF0,0x3FF0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x3FFF,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [1] +0x0FE0,0x3FF8,0x3C7C,0x003C,0x003E,0x003E,0x003E,0x003C,0x003C,0x007C,0x00F8,0x01F0,0x03E0,0x07C0,0x0780,0x0F00,0x1E00,0x3E00,0x3C00,0x3FFE,0x3FFE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [2] +0x0FF0,0x1FF8,0x1C7C,0x003E,0x003E,0x003E,0x003C,0x003C,0x00F8,0x0FF0,0x0FF8,0x007C,0x003E,0x001E,0x001E,0x001E,0x001E,0x003E,0x1C7C,0x1FF8,0x1FE0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [3] +0x0078,0x00F8,0x00F8,0x01F8,0x03F8,0x07F8,0x07F8,0x0F78,0x1E78,0x1E78,0x3C78,0x7878,0x7878,0xFFFF,0xFFFF,0x0078,0x0078,0x0078,0x0078,0x0078,0x0078,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [4] +0x1FFC,0x1FFC,0x1FFC,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1FE0,0x1FF8,0x00FC,0x007C,0x003E,0x003E,0x001E,0x003E,0x003E,0x003C,0x1C7C,0x1FF8,0x1FE0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [5] +0x01FC,0x07FE,0x0F8E,0x1F00,0x1E00,0x3E00,0x3C00,0x3C00,0x3DF8,0x3FFC,0x7F3E,0x7E1F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3E0F,0x1E1F,0x1F3E,0x0FFC,0x03F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [6] +0x3FFF,0x3FFF,0x3FFF,0x000F,0x001E,0x001E,0x003C,0x0038,0x0078,0x00F0,0x00F0,0x01E0,0x01E0,0x03C0,0x03C0,0x0780,0x0F80,0x0F80,0x0F00,0x1F00,0x1F00,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [7] +0x07F8,0x0FFC,0x1F3E,0x1E1E,0x3E1E,0x3E1E,0x1E1E,0x1F3C,0x0FF8,0x07F0,0x0FF8,0x1EFC,0x3E3E,0x3C1F,0x7C1F,0x7C0F,0x7C0F,0x3C1F,0x3F3E,0x1FFC,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [8] +0x07F0,0x0FF8,0x1E7C,0x3C3E,0x3C1E,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x3C1F,0x3E3F,0x1FFF,0x07EF,0x001F,0x001E,0x001E,0x003E,0x003C,0x38F8,0x3FF0,0x1FE0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [9] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [:] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03E0,0x03E0,0x03E0,0x03E0,0x01E0,0x01E0,0x01E0,0x03C0,0x0380, // Ascii = [;] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0003,0x000F,0x003F,0x00FC,0x03F0,0x0FC0,0x3F00,0xFE00,0x3F00,0x0FC0,0x03F0,0x00FC,0x003F,0x000F,0x0003,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [<] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xFFFF,0xFFFF,0x0000,0x0000,0x0000,0xFFFF,0xFFFF,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [=] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xE000,0xF800,0x7E00,0x1F80,0x07E0,0x01F8,0x007E,0x001F,0x007E,0x01F8,0x07E0,0x1F80,0x7E00,0xF800,0xE000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [>] +0x1FF0,0x3FFC,0x383E,0x381F,0x381F,0x001E,0x001E,0x003C,0x0078,0x00F0,0x01E0,0x03C0,0x03C0,0x07C0,0x07C0,0x0000,0x0000,0x0000,0x07C0,0x07C0,0x07C0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [?] +0x03F8,0x0FFE,0x1F1E,0x3E0F,0x3C7F,0x78FF,0x79EF,0x73C7,0xF3C7,0xF38F,0xF38F,0xF38F,0xF39F,0xF39F,0x73FF,0x7BFF,0x79F7,0x3C00,0x1F1C,0x0FFC,0x03F8,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [@] +0x0000,0x0000,0x0000,0x03E0,0x03E0,0x07F0,0x07F0,0x07F0,0x0F78,0x0F78,0x0E7C,0x1E3C,0x1E3C,0x3C3E,0x3FFE,0x3FFF,0x781F,0x780F,0xF00F,0xF007,0xF007,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [A] +0x0000,0x0000,0x0000,0x3FF8,0x3FFC,0x3C3E,0x3C1E,0x3C1E,0x3C1E,0x3C3E,0x3C7C,0x3FF0,0x3FF8,0x3C7E,0x3C1F,0x3C1F,0x3C0F,0x3C0F,0x3C1F,0x3FFE,0x3FF8,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [B] +0x0000,0x0000,0x0000,0x01FF,0x07FF,0x1F87,0x3E00,0x3C00,0x7C00,0x7800,0x7800,0x7800,0x7800,0x7800,0x7C00,0x7C00,0x3E00,0x3F00,0x1F83,0x07FF,0x01FF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [C] +0x0000,0x0000,0x0000,0x7FF0,0x7FFC,0x787E,0x781F,0x781F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x780F,0x781F,0x781E,0x787E,0x7FF8,0x7FE0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [D] +0x0000,0x0000,0x0000,0x3FFF,0x3FFF,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3FFE,0x3FFE,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3FFF,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [E] +0x0000,0x0000,0x0000,0x1FFF,0x1FFF,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1FFF,0x1FFF,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x1E00,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [F] +0x0000,0x0000,0x0000,0x03FE,0x0FFF,0x1F87,0x3E00,0x7C00,0x7C00,0x7800,0xF800,0xF800,0xF87F,0xF87F,0x780F,0x7C0F,0x7C0F,0x3E0F,0x1F8F,0x0FFF,0x03FE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [G] +0x0000,0x0000,0x0000,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7FFF,0x7FFF,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x7C1F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [H] +0x0000,0x0000,0x0000,0x3FFF,0x3FFF,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x3FFF,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [I] +0x0000,0x0000,0x0000,0x1FFC,0x1FFC,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x007C,0x0078,0x0078,0x38F8,0x3FF0,0x3FC0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [J] +0x0000,0x0000,0x0000,0x3C1F,0x3C1E,0x3C3C,0x3C78,0x3CF0,0x3DE0,0x3FE0,0x3FC0,0x3F80,0x3FC0,0x3FE0,0x3DF0,0x3CF0,0x3C78,0x3C7C,0x3C3E,0x3C1F,0x3C0F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [K] +0x0000,0x0000,0x0000,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3FFF,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [L] +0x0000,0x0000,0x0000,0xF81F,0xFC1F,0xFC1F,0xFE3F,0xFE3F,0xFE3F,0xFF7F,0xFF77,0xFF77,0xF7F7,0xF7E7,0xF3E7,0xF3E7,0xF3C7,0xF007,0xF007,0xF007,0xF007,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [M] +0x0000,0x0000,0x0000,0x7C0F,0x7C0F,0x7E0F,0x7F0F,0x7F0F,0x7F8F,0x7F8F,0x7FCF,0x7BEF,0x79EF,0x79FF,0x78FF,0x78FF,0x787F,0x783F,0x783F,0x781F,0x781F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [N] +0x0000,0x0000,0x0000,0x07F0,0x1FFC,0x3E3E,0x7C1F,0x780F,0x780F,0xF80F,0xF80F,0xF80F,0xF80F,0xF80F,0xF80F,0x780F,0x780F,0x7C1F,0x3E3E,0x1FFC,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [O] +0x0000,0x0000,0x0000,0x3FFC,0x3FFF,0x3E1F,0x3E0F,0x3E0F,0x3E0F,0x3E0F,0x3E1F,0x3E3F,0x3FFC,0x3FF0,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x3E00,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [P] +0x0000,0x0000,0x0000,0x07F0,0x1FFC,0x3E3E,0x7C1F,0x780F,0x780F,0xF80F,0xF80F,0xF80F,0xF80F,0xF80F,0xF80F,0x780F,0x780F,0x7C1F,0x3E3E,0x1FFC,0x07F8,0x007C,0x003F,0x000F,0x0003,0x0000, // Ascii = [Q] +0x0000,0x0000,0x0000,0x3FF0,0x3FFC,0x3C7E,0x3C3E,0x3C1E,0x3C1E,0x3C3E,0x3C3C,0x3CFC,0x3FF0,0x3FE0,0x3DF0,0x3CF8,0x3C7C,0x3C3E,0x3C1E,0x3C1F,0x3C0F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [R] +0x0000,0x0000,0x0000,0x07FC,0x1FFE,0x3E0E,0x3C00,0x3C00,0x3C00,0x3E00,0x1FC0,0x0FF8,0x03FE,0x007F,0x001F,0x000F,0x000F,0x201F,0x3C3E,0x3FFC,0x1FF0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [S] +0x0000,0x0000,0x0000,0xFFFF,0xFFFF,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [T] +0x0000,0x0000,0x0000,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x7C0F,0x3C1E,0x3C1E,0x3E3E,0x1FFC,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [U] +0x0000,0x0000,0x0000,0xF007,0xF007,0xF807,0x780F,0x7C0F,0x3C1E,0x3C1E,0x3E1E,0x1E3C,0x1F3C,0x1F78,0x0F78,0x0FF8,0x07F0,0x07F0,0x07F0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [V] +0x0000,0x0000,0x0000,0xE003,0xF003,0xF003,0xF007,0xF3E7,0xF3E7,0xF3E7,0x73E7,0x7BF7,0x7FF7,0x7FFF,0x7F7F,0x7F7F,0x7F7E,0x3F7E,0x3E3E,0x3E3E,0x3E3E,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [W] +0x0000,0x0000,0x0000,0xF807,0x7C0F,0x3E1E,0x3E3E,0x1F3C,0x0FF8,0x07F0,0x07E0,0x03E0,0x03E0,0x07F0,0x0FF8,0x0F7C,0x1E7C,0x3C3E,0x781F,0x780F,0xF00F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [X] +0x0000,0x0000,0x0000,0xF807,0x7807,0x7C0F,0x3C1E,0x3E1E,0x1F3C,0x0F78,0x0FF8,0x07F0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [Y] +0x0000,0x0000,0x0000,0x7FFF,0x7FFF,0x000F,0x001F,0x003E,0x007C,0x00F8,0x00F0,0x01E0,0x03E0,0x07C0,0x0F80,0x0F00,0x1E00,0x3E00,0x7C00,0x7FFF,0x7FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [Z] +0x07FF,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x07FF,0x07FF,0x0000, // Ascii = [[] +0x7800,0x7800,0x3C00,0x3C00,0x1E00,0x1E00,0x0F00,0x0F00,0x0780,0x0780,0x03C0,0x03C0,0x01E0,0x01E0,0x00F0,0x00F0,0x0078,0x0078,0x003C,0x003C,0x001E,0x001E,0x000F,0x000F,0x0007,0x0000, // Ascii = [\] +0x7FF0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x00F0,0x7FF0,0x7FF0,0x0000, // Ascii = []] +0x00C0,0x01C0,0x01C0,0x03E0,0x03E0,0x07F0,0x07F0,0x0778,0x0F78,0x0F38,0x1E3C,0x1E3C,0x3C1E,0x3C1E,0x380F,0x780F,0x7807,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [^] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xFFFF,0xFFFF,0x0000,0x0000,0x0000, // Ascii = [_] +0x00F0,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [`] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0FF8,0x3FFC,0x3C7C,0x003E,0x003E,0x003E,0x07FE,0x1FFE,0x3E3E,0x7C3E,0x783E,0x7C3E,0x7C7E,0x3FFF,0x1FCF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [a] +0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3DF8,0x3FFE,0x3F3E,0x3E1F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C1F,0x3C1E,0x3F3E,0x3FFC,0x3BF0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [b] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03FE,0x0FFF,0x1F87,0x3E00,0x3E00,0x3C00,0x7C00,0x7C00,0x7C00,0x3C00,0x3E00,0x3E00,0x1F87,0x0FFF,0x03FE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [c] +0x001F,0x001F,0x001F,0x001F,0x001F,0x001F,0x07FF,0x1FFF,0x3E3F,0x3C1F,0x7C1F,0x7C1F,0x7C1F,0x781F,0x781F,0x7C1F,0x7C1F,0x3C3F,0x3E7F,0x1FFF,0x0FDF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [d] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x03F8,0x0FFC,0x1F3E,0x3E1E,0x3C1F,0x7C1F,0x7FFF,0x7FFF,0x7C00,0x7C00,0x3C00,0x3E00,0x1F07,0x0FFF,0x03FE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [e] +0x01FF,0x03E1,0x03C0,0x07C0,0x07C0,0x07C0,0x7FFF,0x7FFF,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x07C0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [f] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x07EF,0x1FFF,0x3E7F,0x3C1F,0x7C1F,0x7C1F,0x781F,0x781F,0x781F,0x7C1F,0x7C1F,0x3C3F,0x3E7F,0x1FFF,0x0FDF,0x001E,0x001E,0x001E,0x387C,0x3FF8, // Ascii = [g] +0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3DFC,0x3FFE,0x3F9E,0x3F1F,0x3E1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [h] +0x01F0,0x01F0,0x0000,0x0000,0x0000,0x0000,0x7FE0,0x7FE0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [i] +0x00F8,0x00F8,0x0000,0x0000,0x0000,0x0000,0x3FF8,0x3FF8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F8,0x00F0,0x71F0,0x7FE0, // Ascii = [j] +0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3C00,0x3C1F,0x3C3E,0x3C7C,0x3CF8,0x3DF0,0x3DE0,0x3FC0,0x3FC0,0x3FE0,0x3DF0,0x3CF8,0x3C7C,0x3C3E,0x3C1F,0x3C1F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [k] +0x7FF0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x01F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [l] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xF79E,0xFFFF,0xFFFF,0xFFFF,0xFBE7,0xF9E7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0xF1C7,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [m] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3DFC,0x3FFE,0x3F9E,0x3F1F,0x3E1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x3C1F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [n] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x07F0,0x1FFC,0x3E3E,0x3C1F,0x7C1F,0x780F,0x780F,0x780F,0x780F,0x780F,0x7C1F,0x3C1F,0x3E3E,0x1FFC,0x07F0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [o] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3DF8,0x3FFE,0x3F3E,0x3E1F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C0F,0x3C1F,0x3E1E,0x3F3E,0x3FFC,0x3FF8,0x3C00,0x3C00,0x3C00,0x3C00,0x3C00, // Ascii = [p] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x07EE,0x1FFE,0x3E7E,0x3C1E,0x7C1E,0x781E,0x781E,0x781E,0x781E,0x781E,0x7C1E,0x7C3E,0x3E7E,0x1FFE,0x0FDE,0x001E,0x001E,0x001E,0x001E,0x001E, // Ascii = [q] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x1F7F,0x1FFF,0x1FE7,0x1FC7,0x1F87,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x1F00,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [r] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x07FC,0x1FFE,0x1E0E,0x3E00,0x3E00,0x3F00,0x1FE0,0x07FC,0x00FE,0x003E,0x001E,0x001E,0x3C3E,0x3FFC,0x1FF0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [s] +0x0000,0x0000,0x0000,0x0780,0x0780,0x0780,0x7FFF,0x7FFF,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x0780,0x07C0,0x03FF,0x01FF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [t] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C1E,0x3C3E,0x3C7E,0x3EFE,0x1FFE,0x0FDE,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [u] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xF007,0x780F,0x780F,0x3C1E,0x3C1E,0x3E1E,0x1E3C,0x1E3C,0x0F78,0x0F78,0x0FF0,0x07F0,0x07F0,0x03E0,0x03E0,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [v] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xF003,0xF1E3,0xF3E3,0xF3E7,0xF3F7,0xF3F7,0x7FF7,0x7F77,0x7F7F,0x7F7F,0x7F7F,0x3E3E,0x3E3E,0x3E3E,0x3E3E,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [w] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7C0F,0x3E1E,0x3E3C,0x1F3C,0x0FF8,0x07F0,0x07F0,0x03E0,0x07F0,0x07F8,0x0FF8,0x1E7C,0x3E3E,0x3C1F,0x781F,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [x] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xF807,0x780F,0x7C0F,0x3C1E,0x3C1E,0x1E3C,0x1E3C,0x1F3C,0x0F78,0x0FF8,0x07F0,0x07F0,0x03E0,0x03E0,0x03C0,0x03C0,0x03C0,0x0780,0x0F80,0x7F00, // Ascii = [y] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3FFF,0x3FFF,0x001F,0x003E,0x007C,0x00F8,0x01F0,0x03E0,0x07C0,0x0F80,0x1F00,0x1E00,0x3C00,0x7FFF,0x7FFF,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [z] +0x01FE,0x03E0,0x03C0,0x03C0,0x03C0,0x03C0,0x01E0,0x01E0,0x01E0,0x01C0,0x03C0,0x3F80,0x3F80,0x03C0,0x01C0,0x01E0,0x01E0,0x01E0,0x03C0,0x03C0,0x03C0,0x03C0,0x03E0,0x01FE,0x007E,0x0000, // Ascii = [{] +0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x01C0,0x0000, // Ascii = [|] +0x3FC0,0x03E0,0x01E0,0x01E0,0x01E0,0x01E0,0x01C0,0x03C0,0x03C0,0x01C0,0x01E0,0x00FE,0x00FE,0x01E0,0x01C0,0x03C0,0x03C0,0x01C0,0x01E0,0x01E0,0x01E0,0x01E0,0x03E0,0x3FC0,0x3F00,0x0000, // Ascii = [}] +0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x3F07,0x7FC7,0x73E7,0xF1FF,0xF07E,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, // Ascii = [~] +}; + +FontDef Font_7x10 = {7,10,Font7x10}; +FontDef Font_11x18 = {11,18,Font11x18}; +FontDef Font_16x26 = {16,26,Font16x26}; diff --git a/Drivers/ili9341/fonts.h b/Drivers/ili9341/fonts.h new file mode 100644 index 0000000..afeeb53 --- /dev/null +++ b/Drivers/ili9341/fonts.h @@ -0,0 +1,17 @@ +/* vim: set ai et ts=4 sw=4: */ +#ifndef __FONTS_H__ +#define __FONTS_H__ + +#include + +typedef struct { + const uint8_t width; + uint8_t height; + const uint16_t *data; +} FontDef; + +extern FontDef Font_7x10; +extern FontDef Font_11x18; +extern FontDef Font_16x26; + +#endif // __FONTS_H__ diff --git a/Drivers/ili9341/ili9341.c b/Drivers/ili9341/ili9341.c new file mode 100644 index 0000000..8fda2f5 --- /dev/null +++ b/Drivers/ili9341/ili9341.c @@ -0,0 +1,491 @@ +/* vim: set ai et ts=4 sw=4: */ +#include "stm32f1xx_hal.h" +#include "ili9341.h" +#include + +#ifndef _swap_int16_t +#define _swap_int16_t(a, b) { int16_t t = a; a = b; b = t; } +#endif + +static void ILI9341_Select() { + HAL_GPIO_WritePin(ILI9341_CS_GPIO_Port, ILI9341_CS_Pin, GPIO_PIN_RESET); +} + +void ILI9341_Unselect() { + HAL_GPIO_WritePin(ILI9341_CS_GPIO_Port, ILI9341_CS_Pin, GPIO_PIN_SET); +} + +static void ILI9341_Reset() { + HAL_GPIO_WritePin(ILI9341_RES_GPIO_Port, ILI9341_RES_Pin, GPIO_PIN_RESET); + HAL_Delay(5); + HAL_GPIO_WritePin(ILI9341_RES_GPIO_Port, ILI9341_RES_Pin, GPIO_PIN_SET); +} + +static void ILI9341_WriteCommand(uint8_t cmd) { + HAL_GPIO_WritePin(ILI9341_DC_GPIO_Port, ILI9341_DC_Pin, GPIO_PIN_RESET); + HAL_SPI_Transmit(&ILI9341_SPI_PORT, &cmd, sizeof(cmd), HAL_MAX_DELAY); +} + +static void ILI9341_WriteData(uint8_t* buff, size_t buff_size) { + HAL_GPIO_WritePin(ILI9341_DC_GPIO_Port, ILI9341_DC_Pin, GPIO_PIN_SET); + + // split data in small chunks because HAL can't send more then 64K at once + while(buff_size > 0) { + uint16_t chunk_size = buff_size > 32768 ? 32768 : buff_size; + HAL_SPI_Transmit(&ILI9341_SPI_PORT, buff, chunk_size, HAL_MAX_DELAY); + buff += chunk_size; + buff_size -= chunk_size; + } +} + +static void ILI9341_SetAddressWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) { + // column address set + ILI9341_WriteCommand(0x2A); // CASET + { + uint8_t data[] = { (x0 >> 8) & 0xFF, x0 & 0xFF, (x1 >> 8) & 0xFF, x1 & 0xFF }; + ILI9341_WriteData(data, sizeof(data)); + } + + // row address set + ILI9341_WriteCommand(0x2B); // RASET + { + uint8_t data[] = { (y0 >> 8) & 0xFF, y0 & 0xFF, (y1 >> 8) & 0xFF, y1 & 0xFF }; + ILI9341_WriteData(data, sizeof(data)); + } + + // write to RAM + ILI9341_WriteCommand(0x2C); // RAMWR +} + +void ILI9341_Init() { + ILI9341_Select(); + ILI9341_Reset(); + + // command list is based on https://github.com/martnak/STM32-ILI9341 + + // SOFTWARE RESET + ILI9341_WriteCommand(0x01); + HAL_Delay(1000); + + // POWER CONTROL A + ILI9341_WriteCommand(0xCB); + { + uint8_t data[] = { 0x39, 0x2C, 0x00, 0x34, 0x02 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // POWER CONTROL B + ILI9341_WriteCommand(0xCF); + { + uint8_t data[] = { 0x00, 0xC1, 0x30 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // DRIVER TIMING CONTROL A + ILI9341_WriteCommand(0xE8); + { + uint8_t data[] = { 0x85, 0x00, 0x78 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // DRIVER TIMING CONTROL B + ILI9341_WriteCommand(0xEA); + { + uint8_t data[] = { 0x00, 0x00 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // POWER ON SEQUENCE CONTROL + ILI9341_WriteCommand(0xED); + { + uint8_t data[] = { 0x64, 0x03, 0x12, 0x81 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // PUMP RATIO CONTROL + ILI9341_WriteCommand(0xF7); + { + uint8_t data[] = { 0x20 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // POWER CONTROL,VRH[5:0] + ILI9341_WriteCommand(0xC0); + { + uint8_t data[] = { 0x23 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // POWER CONTROL,SAP[2:0];BT[3:0] + ILI9341_WriteCommand(0xC1); + { + uint8_t data[] = { 0x10 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // VCM CONTROL + ILI9341_WriteCommand(0xC5); + { + uint8_t data[] = { 0x3E, 0x28 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // VCM CONTROL 2 + ILI9341_WriteCommand(0xC7); + { + uint8_t data[] = { 0x86 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // MEMORY ACCESS CONTROL + ILI9341_WriteCommand(0x36); + { + uint8_t data[] = { 0x48 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // PIXEL FORMAT + ILI9341_WriteCommand(0x3A); + { + uint8_t data[] = { 0x55 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // FRAME RATIO CONTROL, STANDARD RGB COLOR + ILI9341_WriteCommand(0xB1); + { + uint8_t data[] = { 0x00, 0x18 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // DISPLAY FUNCTION CONTROL + ILI9341_WriteCommand(0xB6); + { + uint8_t data[] = { 0x08, 0x82, 0x27 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // 3GAMMA FUNCTION DISABLE + ILI9341_WriteCommand(0xF2); + { + uint8_t data[] = { 0x00 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // GAMMA CURVE SELECTED + ILI9341_WriteCommand(0x26); + { + uint8_t data[] = { 0x01 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // POSITIVE GAMMA CORRECTION + ILI9341_WriteCommand(0xE0); + { + uint8_t data[] = { 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, 0x4E, 0xF1, + 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00 }; + ILI9341_WriteData(data, sizeof(data)); + } + + // NEGATIVE GAMMA CORRECTION + ILI9341_WriteCommand(0xE1); + { + uint8_t data[] = { 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, 0x31, 0xC1, + 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F }; + ILI9341_WriteData(data, sizeof(data)); + } + + // EXIT SLEEP + ILI9341_WriteCommand(0x11); + HAL_Delay(120); + + // TURN ON DISPLAY + ILI9341_WriteCommand(0x29); + + // MADCTL + ILI9341_WriteCommand(0x36); + { + uint8_t data[] = { ILI9341_ROTATION }; + ILI9341_WriteData(data, sizeof(data)); + } + + ILI9341_Unselect(); +} + +void ILI9341_DrawPixel(uint16_t x, uint16_t y, uint16_t color) { + if((x >= ILI9341_WIDTH) || (y >= ILI9341_HEIGHT)) + return; + + ILI9341_Select(); + + ILI9341_SetAddressWindow(x, y, x+1, y+1); + uint8_t data[] = { color >> 8, color & 0xFF }; + ILI9341_WriteData(data, sizeof(data)); + + ILI9341_Unselect(); +} + +static void ILI9341_WriteChar(uint16_t x, uint16_t y, char ch, FontDef font, uint16_t color, uint16_t bgcolor) { + uint32_t i, b, j; + + ILI9341_SetAddressWindow(x, y, x+font.width-1, y+font.height-1); + + for(i = 0; i < font.height; i++) { + b = font.data[(ch - 32) * font.height + i]; + for(j = 0; j < font.width; j++) { + if((b << j) & 0x8000) { + uint8_t data[] = { color >> 8, color & 0xFF }; + ILI9341_WriteData(data, sizeof(data)); + } else { + uint8_t data[] = { bgcolor >> 8, bgcolor & 0xFF }; + ILI9341_WriteData(data, sizeof(data)); + } + } + } +} + +void ILI9341_WriteString(uint16_t x, uint16_t y, const char* str, FontDef font, uint16_t color, uint16_t bgcolor) { + ILI9341_Select(); + + while(*str) { + if(x + font.width >= ILI9341_WIDTH) { + x = 0; + y += font.height; + if(y + font.height >= ILI9341_HEIGHT) { + break; + } + + if(*str == ' ') { + // skip spaces in the beginning of the new line + str++; + continue; + } + } + + ILI9341_WriteChar(x, y, *str, font, color, bgcolor); + x += font.width; + str++; + } + + ILI9341_Unselect(); +} + +void ILI9341_FillRectangle(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color) { + // clipping + if((x >= ILI9341_WIDTH) || (y >= ILI9341_HEIGHT)) return; + if((x + w - 1) >= ILI9341_WIDTH) w = ILI9341_WIDTH - x; + if((y + h - 1) >= ILI9341_HEIGHT) h = ILI9341_HEIGHT - y; + + ILI9341_Select(); + ILI9341_SetAddressWindow(x, y, x+w-1, y+h-1); + + uint8_t data[] = { color >> 8, color & 0xFF }; + HAL_GPIO_WritePin(ILI9341_DC_GPIO_Port, ILI9341_DC_Pin, GPIO_PIN_SET); + for(y = h; y > 0; y--) { + for(x = w; x > 0; x--) { + HAL_SPI_Transmit(&ILI9341_SPI_PORT, data, sizeof(data), HAL_MAX_DELAY); + } + } + + ILI9341_Unselect(); +} + +void ILI9341_writeLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color) { + + int16_t steep = abs(y1 - y0) > abs(x1 - x0); + if (steep) { + _swap_int16_t(x0, y0); + _swap_int16_t(x1, y1); + } + + if (x0 > x1) { + _swap_int16_t(x0, x1); + _swap_int16_t(y0, y1); + } + + int16_t dx, dy; + dx = x1 - x0; + dy = abs(y1 - y0); + + int16_t err = dx / 2; + int16_t ystep; + + if (y0 < y1) { + ystep = 1; + } else { + ystep = -1; + } + + for (; x0<=x1; x0++) { + if (steep) { + ILI9341_writePixel(y0, x0, color); + } else { + ILI9341_writePixel(x0, y0, color); + } + err -= dy; + if (err < 0) { + y0 += ystep; + err += dx; + } + } +} + +void ILI9341_DrawArrow(int16_t x1, int16_t y1, int16_t x2, int16_t y2, float k, uint16_t color) +{ + float dx, dy, x2Outer,y2Outer,x3,y3,x4,y4; + + dx = x2 + (x1 - x2) * k; + dy = y2 + (y1 - y2) * k; + + x2Outer = x2 - dx; + y2Outer = dy - y2; + x3 = y2Outer * k + dx; + y3 = x2Outer * k + dy; + x4 = dx - y2Outer * k; + y4 = dy - x2Outer * k; + ILI9341_writeLine(round(x1), round(y1), round(x2), round(y2), color); + ILI9341_writeLine(round(x1), round(y1), round(dx), round(dy), color); + ILI9341_writeLine(round(x3), round(y3), round(x2), round(y2), color); + ILI9341_writeLine(round(x2), round(y2), round(x4), round(y4), color); +} + +void ILI9341_drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color) { + ILI9341_Select(); + ILI9341_writeLine(x, y, x+w-1, y, color); + ILI9341_Unselect(); +} + +void ILI9341_writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color) { + // Overwrite in subclasses if startWrite is defined! + // Example: writeLine(x, y, x+w-1, y, color); + // or writeFillRect(x, y, w, 1, color); + ILI9341_drawFastHLine(x, y, w, color); +} + +void ILI9341_drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color) { + ILI9341_Select(); + ILI9341_writeLine(x, y, x, y+h-1, color); + ILI9341_Unselect(); +} + +void ILI9341_writeFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color) { + // Overwrite in subclasses if startWrite is defined! + // Can be just writeLine(x, y, x, y+h-1, color); + // or writeFillRect(x, y, 1, h, color); + ILI9341_drawFastVLine(x, y, h, color); +} + +void ILI9341_writePixel(int16_t x, int16_t y, uint16_t color){ + ILI9341_DrawPixel(x, y, color); +} + +void ILI9341_drawCircleHelper( int16_t x0, int16_t y0, int16_t r, uint8_t cornername, uint16_t color) { + int16_t f = 1 - r; + int16_t ddF_x = 1; + int16_t ddF_y = -2 * r; + int16_t x = 0; + int16_t y = r; + + while (x= 0) { + y--; + ddF_y += 2; + f += ddF_y; + } + x++; + ddF_x += 2; + f += ddF_x; + if (cornername & 0x4) { + ILI9341_writePixel(x0 + x, y0 + y, color); + ILI9341_writePixel(x0 + y, y0 + x, color); + } + if (cornername & 0x2) { + ILI9341_writePixel(x0 + x, y0 - y, color); + ILI9341_writePixel(x0 + y, y0 - x, color); + } + if (cornername & 0x8) { + ILI9341_writePixel(x0 - y, y0 + x, color); + ILI9341_writePixel(x0 - x, y0 + y, color); + } + if (cornername & 0x1) { + ILI9341_writePixel(x0 - y, y0 - x, color); + ILI9341_writePixel(x0 - x, y0 - y, color); + } + } +} + + +void ILI9341_drawRoundRect(int16_t x, int16_t y, int16_t w, int16_t h, int16_t r, uint16_t color) { + int16_t max_radius = ((w < h) ? w : h) / 2; // 1/2 minor axis + if(r > max_radius) r = max_radius; + // smarter version + ILI9341_Select(); + ILI9341_writeFastHLine(x+r , y , w-2*r, color); // Top + ILI9341_writeFastHLine(x+r , y+h-1, w-2*r, color); // Bottom + ILI9341_writeFastVLine(x , y+r , h-2*r, color); // Left + ILI9341_writeFastVLine(x+w-1, y+r , h-2*r, color); // Right + // draw four corners + ILI9341_drawCircleHelper(x+r , y+r , r, 1, color); + ILI9341_drawCircleHelper(x+w-r-1, y+r , r, 2, color); + ILI9341_drawCircleHelper(x+w-r-1, y+h-r-1, r, 4, color); + ILI9341_drawCircleHelper(x+r , y+h-r-1, r, 8, color); + ILI9341_Unselect(); +} + +void ILI9341_drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color) { + int16_t f = 1 - r; + int16_t ddF_x = 1; + int16_t ddF_y = -2 * r; + int16_t x = 0; + int16_t y = r; + + ILI9341_Select(); + ILI9341_writePixel(x0 , y0+r, color); + ILI9341_writePixel(x0 , y0-r, color); + ILI9341_writePixel(x0+r, y0 , color); + ILI9341_writePixel(x0-r, y0 , color); + + while (x= 0) { + y--; + ddF_y += 2; + f += ddF_y; + } + x++; + ddF_x += 2; + f += ddF_x; + + ILI9341_writePixel(x0 + x, y0 + y, color); + ILI9341_writePixel(x0 - x, y0 + y, color); + ILI9341_writePixel(x0 + x, y0 - y, color); + ILI9341_writePixel(x0 - x, y0 - y, color); + ILI9341_writePixel(x0 + y, y0 + x, color); + ILI9341_writePixel(x0 - y, y0 + x, color); + ILI9341_writePixel(x0 + y, y0 - x, color); + ILI9341_writePixel(x0 - y, y0 - x, color); + } + ILI9341_Unselect(); +} + + +void ILI9341_FillScreen(uint16_t color) { + ILI9341_FillRectangle(0, 0, ILI9341_WIDTH, ILI9341_HEIGHT, color); +} + +void ILI9341_DrawImage(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint16_t* data) { + if((x >= ILI9341_WIDTH) || (y >= ILI9341_HEIGHT)) return; + if((x + w - 1) >= ILI9341_WIDTH) return; + if((y + h - 1) >= ILI9341_HEIGHT) return; + + ILI9341_Select(); + ILI9341_SetAddressWindow(x, y, x+w-1, y+h-1); + ILI9341_WriteData((uint8_t*)data, sizeof(uint16_t)*w*h); + ILI9341_Unselect(); +} + +void ILI9341_InvertColors(bool invert) { + ILI9341_Select(); + ILI9341_WriteCommand(invert ? 0x21 /* INVON */ : 0x20 /* INVOFF */); + ILI9341_Unselect(); +} + diff --git a/Drivers/ili9341/ili9341.h b/Drivers/ili9341/ili9341.h new file mode 100644 index 0000000..ba5fe8b --- /dev/null +++ b/Drivers/ili9341/ili9341.h @@ -0,0 +1,89 @@ +/* vim: set ai et ts=4 sw=4: */ +#ifndef __ILI9341_H__ +#define __ILI9341_H__ + +#include "fonts.h" +#include + +#define ILI9341_MADCTL_MY 0x80 +#define ILI9341_MADCTL_MX 0x40 +#define ILI9341_MADCTL_MV 0x20 +#define ILI9341_MADCTL_ML 0x10 +#define ILI9341_MADCTL_RGB 0x00 +#define ILI9341_MADCTL_BGR 0x08 +#define ILI9341_MADCTL_MH 0x04 + +/*** Redefine if necessary ***/ +#define ILI9341_SPI_PORT hspi2 +extern SPI_HandleTypeDef ILI9341_SPI_PORT; + +#define ILI9341_RES_Pin GPIO_PIN_7 +#define ILI9341_RES_GPIO_Port GPIOA +#define ILI9341_CS_Pin GPIO_PIN_6 +#define ILI9341_CS_GPIO_Port GPIOA +#define ILI9341_DC_Pin GPIO_PIN_5 +#define ILI9341_DC_GPIO_Port GPIOA + +// default orientation +/* +#define ILI9341_WIDTH 240 +#define ILI9341_HEIGHT 320 +#define ILI9341_ROTATION (ILI9341_MADCTL_MX | ILI9341_MADCTL_BGR) +*/ +// rotate right + +#define ILI9341_WIDTH 320 +#define ILI9341_HEIGHT 240 +#define ILI9341_ROTATION (ILI9341_MADCTL_MX | ILI9341_MADCTL_MY | ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR) + + +// rotate left +/* +#define ILI9341_WIDTH 320 +#define ILI9341_HEIGHT 240 +#define ILI9341_ROTATION (ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR) +*/ + +// upside down +/* +#define ILI9341_WIDTH 240 +#define ILI9341_HEIGHT 320 +#define ILI9341_ROTATION (ILI9341_MADCTL_MY | ILI9341_MADCTL_BGR) +*/ + +/****************************/ + +// Color definitions +#define ILI9341_BLACK 0x0000 +#define ILI9341_BLUE 0x001F +#define ILI9341_RED 0xF800 +#define ILI9341_GREEN 0x07E0 +#define ILI9341_CYAN 0x07FF +#define ILI9341_MAGENTA 0xF81F +#define ILI9341_YELLOW 0xFFE0 +#define ILI9341_WHITE 0xFFFF +#define ILI9341_COLOR565(r, g, b) (((r & 0xF8) << 8) | ((g & 0xFC) << 3) | ((b & 0xF8) >> 3)) + +// call before initializing any SPI devices +void ILI9341_Unselect(); + +void ILI9341_Init(void); +void ILI9341_DrawPixel(uint16_t x, uint16_t y, uint16_t color); +void ILI9341_WriteString(uint16_t x, uint16_t y, const char* str, FontDef font, uint16_t color, uint16_t bgcolor); +void ILI9341_FillRectangle(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color); +void ILI9341_FillScreen(uint16_t color); +void ILI9341_DrawImage(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint16_t* data); +void ILI9341_drawRoundRect(int16_t x, int16_t y, int16_t w, int16_t h, int16_t r, uint16_t color); +void ILI9341_DrawArrow(int16_t x1, int16_t y1, int16_t x2, int16_t y2, float k, uint16_t color); +void ILI9341_writeLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color); +void ILI9341_drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color); +void ILI9341_writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color); +void ILI9341_drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color); +void ILI9341_writeFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color); +void ILI9341_drawCircleHelper( int16_t x0, int16_t y0, int16_t r, uint8_t cornername, uint16_t color); +void ILI9341_writePixel(int16_t x, int16_t y, uint16_t color); +void ILI9341_drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color); + +void ILI9341_InvertColors(bool invert); + +#endif // __ILI9341_H__ diff --git a/Drivers/ili9341/ili9341_touch.c b/Drivers/ili9341/ili9341_touch.c new file mode 100644 index 0000000..167c6ef --- /dev/null +++ b/Drivers/ili9341/ili9341_touch.c @@ -0,0 +1,69 @@ +/* vim: set ai et ts=4 sw=4: */ + +#include "stm32f1xx_hal.h" +#include "ili9341_touch.h" + +#define READ_X 0xD0 +#define READ_Y 0x90 + +static void ILI9341_TouchSelect() { + HAL_GPIO_WritePin(ILI9341_TOUCH_CS_GPIO_Port, ILI9341_TOUCH_CS_Pin, GPIO_PIN_RESET); +} + +void ILI9341_TouchUnselect() { + HAL_GPIO_WritePin(ILI9341_TOUCH_CS_GPIO_Port, ILI9341_TOUCH_CS_Pin, GPIO_PIN_SET); +} + +bool ILI9341_TouchPressed() { + return HAL_GPIO_ReadPin(ILI9341_TOUCH_IRQ_GPIO_Port, ILI9341_TOUCH_IRQ_Pin) == GPIO_PIN_RESET; +} + +bool ILI9341_TouchGetCoordinates(uint16_t* x, uint16_t* y) { + static const uint8_t cmd_read_x[] = { READ_X }; + static const uint8_t cmd_read_y[] = { READ_Y }; + static const uint8_t zeroes_tx[] = { 0x00, 0x00 }; + + ILI9341_TouchSelect(); + + uint32_t avg_x = 0; + uint32_t avg_y = 0; + uint8_t nsamples = 0; + for(uint8_t i = 0; i < 16; i++) { + if(!ILI9341_TouchPressed()) + break; + + nsamples++; + + HAL_SPI_Transmit(&ILI9341_TOUCH_SPI_PORT, (uint8_t*)cmd_read_y, sizeof(cmd_read_y), HAL_MAX_DELAY); + uint8_t y_raw[2]; + HAL_SPI_TransmitReceive(&ILI9341_TOUCH_SPI_PORT, (uint8_t*)zeroes_tx, y_raw, sizeof(y_raw), HAL_MAX_DELAY); + + HAL_SPI_Transmit(&ILI9341_TOUCH_SPI_PORT, (uint8_t*)cmd_read_x, sizeof(cmd_read_x), HAL_MAX_DELAY); + uint8_t x_raw[2]; + HAL_SPI_TransmitReceive(&ILI9341_TOUCH_SPI_PORT, (uint8_t*)zeroes_tx, x_raw, sizeof(x_raw), HAL_MAX_DELAY); + + avg_x += (((uint16_t)x_raw[0]) << 8) | ((uint16_t)x_raw[1]); + avg_y += (((uint16_t)y_raw[0]) << 8) | ((uint16_t)y_raw[1]); + } + + ILI9341_TouchUnselect(); + + if(nsamples < 16) + return false; + + uint32_t raw_x = (avg_x / 16); + if(raw_x < ILI9341_TOUCH_MIN_RAW_X) raw_x = ILI9341_TOUCH_MIN_RAW_X; + if(raw_x > ILI9341_TOUCH_MAX_RAW_X) raw_x = ILI9341_TOUCH_MAX_RAW_X; + + uint32_t raw_y = (avg_y / 16); + if(raw_y < ILI9341_TOUCH_MIN_RAW_X) raw_y = ILI9341_TOUCH_MIN_RAW_Y; + if(raw_y > ILI9341_TOUCH_MAX_RAW_Y) raw_y = ILI9341_TOUCH_MAX_RAW_Y; + + // Uncomment this line to calibrate touchscreen: + // UART_Printf("raw_x = %d, raw_y = %d\r\n", x, y); + + *x = (raw_x - ILI9341_TOUCH_MIN_RAW_X) * ILI9341_TOUCH_SCALE_X / (ILI9341_TOUCH_MAX_RAW_X - ILI9341_TOUCH_MIN_RAW_X); + *y = (raw_y - ILI9341_TOUCH_MIN_RAW_Y) * ILI9341_TOUCH_SCALE_Y / (ILI9341_TOUCH_MAX_RAW_Y - ILI9341_TOUCH_MIN_RAW_Y); + + return true; +} diff --git a/Drivers/ili9341/ili9341_touch.h b/Drivers/ili9341/ili9341_touch.h new file mode 100644 index 0000000..4b05d5a --- /dev/null +++ b/Drivers/ili9341/ili9341_touch.h @@ -0,0 +1,34 @@ +/* vim: set ai et ts=4 sw=4: */ +#ifndef __ILI9341_TOUCH_H__ +#define __ILI9341_TOUCH_H__ + +#include + +/*** Redefine if necessary ***/ + +// Warning! Use SPI bus with < 1.3 Mbit speed, better ~650 Kbit to be save. +#define ILI9341_TOUCH_SPI_PORT hspi2 +extern SPI_HandleTypeDef ILI9341_TOUCH_SPI_PORT; + +#define ILI9341_TOUCH_IRQ_Pin GPIO_PIN_4 // Arduino D5 +#define ILI9341_TOUCH_IRQ_GPIO_Port GPIOB +#define ILI9341_TOUCH_CS_Pin GPIO_PIN_10 // Arduino D2 +#define ILI9341_TOUCH_CS_GPIO_Port GPIOA + +// change depending on screen orientation +#define ILI9341_TOUCH_SCALE_X 240 +#define ILI9341_TOUCH_SCALE_Y 320 + +// to calibrate uncomment UART_Printf line in ili9341_touch.c +#define ILI9341_TOUCH_MIN_RAW_X 1500 +#define ILI9341_TOUCH_MAX_RAW_X 31000 +#define ILI9341_TOUCH_MIN_RAW_Y 3276 +#define ILI9341_TOUCH_MAX_RAW_Y 30110 + +// call before initializing any SPI devices +void ILI9341_TouchUnselect(); + +bool ILI9341_TouchPressed(); +bool ILI9341_TouchGetCoordinates(uint16_t* x, uint16_t* y); + +#endif // __ILI9341_TOUCH_H__ diff --git a/Drivers/ili9341/testimg.h b/Drivers/ili9341/testimg.h new file mode 100644 index 0000000..7b10fef --- /dev/null +++ b/Drivers/ili9341/testimg.h @@ -0,0 +1,242 @@ +const uint16_t test_img_240x240[][240] = { +{0x0B63,0x0B63,0x0B6B,0xEB6A,0x2B6B,0x2B63,0x2B6B,0x2B6B,0x2B6B,0x2B6B,0x2B6B,0x2B6B,0x2C6B,0x2B6B,0x4C63,0x2B6B,0x4C6B,0x6C73,0xCB6B,0x4B7C,0xAB84,0x4B8D,0xAC9D,0x4C9E,0x0CA7,0xCCBF,0xECD7,0xCDDF,0xCDE7,0xECEF,0xCCF7,0xCBF7,0xCBF7,0xEAF7,0xCAFF,0xCBF7,0xCCFF,0xCBFF,0xCBFF,0xCBFF,0xEBF7,0xECF7,0xECEF,0xCCE7,0xECE7,0xCCE7,0xCBEF,0xCCEF,0x93E7,0x3DC7,0xFFBE,0xDFBE,0xFFBE,0xDFBE,0x5FA6,0xFE85,0x5C75,0xB964,0x194C,0xBD4B,0x9D4B,0x3E7C,0xFF94,0x5F8D,0xBFA5,0xDFAD,0xFFA5,0x1FAE,0x3FB6,0xFFAD,0x3F8D,0x5E74,0x1C6C,0xD95B,0x5653,0x164B,0xF752,0x1763,0x375B,0x1553,0xF44A,0xD34A,0xB142,0x7342,0x9852,0x9D73,0xDD63,0x9C63,0x5E84,0x9FAD,0xFD74,0x7D4B,0xBFAD,0xFFCE,0x1FCF,0x3FD7,0x1FCF,0x5EAE,0xF97C,0xB753,0x1B6C,0xFA83,0x3DB5,0xDFBD,0x7E9D,0xBA84,0xB87C,0x7684,0x978C,0x9584,0x337C,0x127C,0xF483,0xF37B,0xD373,0xF473,0x147C,0x748C,0x1384,0x366B,0xFC62,0x3EA5,0x7FB6,0x9FBE,0xBFBE,0x3FA6,0xBFA5,0xFFA5,0x397D,0x0B2A,0x2E31,0xF439,0xB221,0x1831,0x5D7B,0x5F9D,0x1F95,0x1FBE,0x1FCF,0x3FC7,0x5E8E,0xFD6B,0x1C74,0xBB53,0xBE84,0x9E63,0xBF84,0xDE53,0x9A3A,0xDE6B,0x9F74,0x7B4B,0xBB42,0x3D53,0xFC4A,0x1D4B,0x3E5B,0x3F9D,0x3FB6,0x9FB6,0xBFB6,0x9F8D,0xBF8C,0x1F8D,0xBF7C,0x3F8D,0xDE7C,0x1E6C,0xBF84,0x9E7C,0x7F9D,0xDEB6,0x5C8D,0x9884,0xB763,0x7C63,0xDE6B,0xBF7C,0x3E74,0x3F8D,0xBFB5,0xFFCE,0xDFBE,0xBFCE,0x9FAE,0x1E9E,0x7C84,0xDFB5,0x3FD7,0x7FE7,0x7B9E,0xAE5B,0xCA5A,0xCA62,0xCA62,0xAA5A,0xAA5A,0x895A,0x6A5A,0x695A,0x695A,0x6A5A,0x685A,0x6952,0x8952,0x4952,0x4952,0x2852,0x2852,0x2842,0x4842,0x284A,0x0842,0x0742,0x084A,0x0742,0x0742,0xE741,0xC749,0xC741,0xC739,0xC639,0xC641,0xC639,0xA639,0xA639,0x8631,0x8639,0x8631,0x8531,0x6531,0x8431,0x4531,0x6529,0x4529,0x4421,0x2429,0x2429,0x2421,0x0321,}, +{0x2B63,0x0C63,0x0B6B,0x0B63,0x0C6B,0x2B6B,0x2B63,0x2B6B,0x2C6B,0x2B6B,0x2C6B,0x2C6B,0x2C6B,0x2C6B,0x2C63,0x4C6B,0x2C63,0xAC6B,0x0B74,0xAC84,0x4A95,0xEAA5,0x6BB6,0x2BC7,0xABD7,0xCBDF,0xEBDF,0xCCE7,0xCDE7,0xECEF,0xEBF7,0xCAFF,0xEAFF,0xEAFF,0xCBFF,0xCBF7,0xCCFF,0xEBFF,0xCBFF,0xCCF7,0xCDF7,0xCEEF,0xCEE7,0xCDD7,0xCDCF,0xADC7,0x4CC7,0x0CB7,0x90A6,0x7AA6,0x9FA6,0x9FAE,0xBFB6,0xBFC6,0xBFB6,0x5FAE,0xDF9D,0x1F85,0xBE7C,0x7E64,0xFD5B,0x583B,0xBB53,0x3E74,0xBF84,0x1F8D,0x5F95,0x7F95,0x7F9D,0x7F9D,0x3F95,0x9F7C,0xFA5B,0x7753,0x365B,0x165B,0xD452,0x5242,0x9242,0x5463,0x535B,0xF35A,0x904A,0x4F4A,0x5042,0x323A,0x574A,0x5A63,0x9B63,0x9B6B,0x5EAD,0x9E95,0x3C54,0x7D84,0xFFBD,0x1FD7,0x1FCF,0xBFBE,0x7FBE,0xDC95,0xDC84,0x596C,0x5663,0xB87B,0xFC83,0xDE9C,0xFC94,0xDA9C,0xFA94,0x5AAD,0x199D,0x958C,0x3484,0x1384,0x9484,0x747C,0x3374,0xF383,0x1384,0x9273,0xF46A,0xD962,0x9E8C,0x3FB6,0x5FB6,0x5FB6,0x5FAE,0xFE84,0x7F9D,0x7C8D,0x8F3A,0x2D31,0x1342,0x3132,0xF118,0xBB62,0x9F7C,0xDF8C,0xDFAD,0x9FBE,0x1FC7,0xFFAE,0xBE7D,0x3D5C,0x9F84,0xBE74,0x5D53,0x9E7C,0xBC53,0xBB3A,0x1D53,0xFD63,0x1B43,0x9E4B,0xBE5B,0x5C43,0xDC4A,0x5E5B,0xFF94,0xFFAD,0x3FB6,0x3FAE,0xFF84,0x7E74,0x1F5C,0x7F84,0xFF7C,0x5E6C,0x7E74,0xBF7C,0xDF84,0x3FBE,0x5FC7,0x7E9E,0x585C,0x585B,0x1B5B,0x7E63,0x5F6C,0x7E7C,0x3F95,0x5FBE,0xDFBE,0x3FB6,0x9FC6,0x7FB6,0x1E9E,0x1E9D,0xBFCE,0x3FCF,0x1FC7,0x7B9E,0xCD5B,0xEA5A,0xEA62,0xCA5A,0xCA62,0xAA5A,0xA952,0x895A,0x8962,0x695A,0x695A,0x8952,0x6952,0x4952,0x4852,0x4852,0x484A,0x484A,0x284A,0x484A,0x284A,0xE749,0x074A,0x0842,0x0742,0x0742,0xE741,0xC741,0xE739,0xE639,0xE739,0xC639,0xA739,0xA639,0xA531,0xA639,0x8639,0x8631,0x8531,0x6529,0x6531,0x6529,0x4531,0x4429,0x4429,0x2429,0x2421,0x2421,}, +{0x4A63,0x0B63,0x0B6B,0x0B63,0xEC72,0x2B73,0x0B6B,0x2C6B,0x2C63,0x0B6B,0x2C6B,0x2B6B,0x4C6B,0x4C6B,0x4C6B,0x2C73,0xAC6B,0x4C7C,0x0C85,0xCB95,0x8AA6,0x0AB7,0x8AC7,0xCBD7,0xCCE7,0xCCDF,0xECE7,0xCCEF,0xCCF7,0xCAF7,0xCBFF,0xCAFF,0xEAFF,0xCBFF,0xEBFF,0xCBFF,0xEBFF,0xCCFF,0xCCFF,0xECFF,0xCEF7,0xCFEF,0xD0DF,0xCECF,0x8DAF,0xCC9E,0x4C8E,0xEC85,0xAE6D,0x957D,0x9E8D,0xDF8D,0x3FA6,0x7FB6,0x9FC6,0x7FAE,0x1FA6,0x9F9D,0x9E74,0x5C64,0x3E7C,0x3E7C,0x3C74,0xFC63,0xDD6B,0xFE6B,0x9F84,0xBF84,0xFF8C,0x1F8D,0x9E7C,0x1C74,0x5A6C,0xF863,0xB553,0xF24A,0x7042,0x714A,0xB152,0x7052,0x9152,0xF56A,0x1353,0xF152,0xF04A,0x4D32,0xEC29,0xB041,0xB449,0x564A,0xD94A,0xFE9C,0x5FB6,0xBD85,0xFA4B,0x1C7C,0x5EA5,0x1FBE,0x9FBE,0x5FB6,0x1FB6,0xBE95,0x5B8D,0x7774,0xF66B,0x9863,0x9D8C,0x7C84,0xF873,0x7A8C,0xBC8C,0xFD9C,0xB894,0x1484,0x7684,0x3484,0xF17B,0xD27B,0xF183,0xB17B,0x506B,0x746B,0x5A6B,0x7E8C,0x1FAE,0xDF95,0xBF9D,0x9F95,0xFF84,0x1E74,0x3D74,0x744B,0xCE29,0x744A,0xD129,0x7331,0xBB52,0x7E74,0x3F7C,0x1F95,0xFFAD,0xBFC6,0xFFBE,0xBFA6,0x3E7D,0x9E6C,0x1E64,0xDA42,0x9C63,0x982A,0xBB3A,0x5932,0xBE53,0x9E53,0x1C4B,0x1C4B,0xDC42,0xDC42,0xFD4A,0xDE9C,0x9FBE,0xFFBE,0x5FA6,0xFE74,0x3E6C,0x3E5B,0x7F74,0x1E6C,0xDF84,0x7E7C,0xDF84,0x7F9D,0x9FC6,0x5FC7,0x7FA6,0x9A6C,0x5B6B,0xFC52,0x7E63,0xFE5B,0x9E7C,0xBFA5,0xBFC6,0x9FBE,0x5FB6,0x7FBE,0x9FB6,0xDE8D,0xBFBD,0x1FD7,0x3FCF,0x3FC7,0x9AA6,0x8C5B,0x8D6B,0xF59C,0x8C53,0xAA5A,0xAA5A,0x8A62,0x895A,0x8A5A,0x8952,0x8952,0x8952,0x4952,0x6952,0x4952,0x484A,0x6852,0x484A,0x284A,0x284A,0x2742,0x0852,0x0742,0x074A,0x0742,0xE741,0xE741,0xE741,0xC641,0xC639,0xC639,0xC739,0xA639,0xA639,0x8639,0x8631,0x8531,0x8531,0x6531,0x8531,0x6431,0x4531,0x4529,0x4529,0x2429,0x2429,0x2421,}, +{0x0B6B,0x2B6B,0x2B63,0x2B6B,0x0C63,0x0B6B,0xEB6A,0x2B6B,0x2B6B,0x4C6B,0x2B63,0x0B73,0x2B73,0x2C6B,0x4B6B,0xAC73,0x6B7C,0x6B8D,0x4A9E,0xEAAE,0x6AC7,0xAACF,0xCAD7,0xCBDF,0xECEF,0xEDEF,0xECEF,0xCCF7,0xCBF7,0xEAFF,0xEBFF,0xEAFF,0xEAFF,0xCBFF,0xCBFF,0xCBFF,0xECFF,0xCCF7,0xCCFF,0xCCF7,0xEEF7,0xD0EF,0xF1DF,0xCFD7,0x4FB7,0x6F9E,0xCF7D,0x4E75,0x0F65,0xB164,0xB96C,0xBE74,0x9F8D,0xBFAD,0x1FAE,0x3FB6,0x3FAE,0xDFAD,0xFF84,0x1C64,0xD963,0xDA63,0xBA6B,0x1D7C,0x1E74,0xFC73,0xDB5B,0xFC63,0x3E7C,0xDF8C,0xFD8C,0x3A85,0xB864,0xF863,0xF973,0x3974,0xB563,0xCE42,0xEB31,0xCB31,0xCB39,0x2F42,0xD352,0xF45A,0xF34A,0x3363,0xF14A,0x4D3A,0xCB29,0xF252,0xF963,0xDC84,0x5EA5,0x3FBE,0x9FC6,0x3EAE,0x1B6D,0x5C74,0x7F9D,0x7FBE,0xBFC6,0x3FA6,0xFFA5,0xDE9D,0x3C85,0x3874,0x3784,0xBB94,0x9EA5,0x9A7C,0x7C94,0xDD94,0xDE94,0xDA8C,0x167C,0x157C,0xD373,0x907B,0x917B,0x4F73,0xCE62,0xED62,0xEF62,0x965A,0x5B7B,0xBE9C,0xDFA5,0x9F95,0xDE84,0x7E7C,0xFC6B,0xFB6B,0x1743,0xD64A,0x7853,0xB232,0xB431,0xFA49,0x9D6B,0xBF6B,0x7F84,0xBFA5,0xFFAD,0x9FB6,0x9FAE,0x9F85,0x5E64,0xBD4B,0x983A,0x1B4B,0xFB3A,0x7B43,0x172A,0x9C42,0x9D5B,0xB93A,0x3D4B,0x3C4B,0xDB42,0xF931,0x5EA5,0x7FD7,0x7FCF,0x9FA6,0x3E85,0x3C43,0xFE8C,0xFC5B,0x5E7C,0xDD63,0xBD73,0xBF94,0x9FA5,0xDFCE,0x3FC7,0xDFA6,0xDD6C,0x7C5B,0x3A4B,0x5C53,0xBE5B,0xBF8C,0xFFB5,0x7FBE,0x7FBE,0x7FC6,0x7FB6,0xBFBE,0x5F95,0xBFD6,0x3FCF,0x5FCF,0x5FCF,0x5575,0x4E6B,0x9BA4,0x5CAE,0xCE53,0xCA5A,0xAA5A,0xAA5A,0xAA5A,0x895A,0x8952,0x8952,0x6952,0x8952,0x4952,0x4852,0x684A,0x4852,0x4852,0x484A,0x2852,0x284A,0x284A,0x274A,0x0742,0x0742,0x0742,0xE741,0xC749,0xC741,0xE741,0xC741,0xC639,0xA639,0xA639,0x8639,0x8531,0x8639,0x8531,0x8531,0x6531,0x6531,0x6529,0x6529,0x4429,0x4429,0x4421,}, +{0x0A73,0x0B6B,0x0B6B,0x2B6B,0x0C6B,0x0B6B,0x0B6B,0x2B6B,0x2B6B,0x2B6B,0x2C73,0x2C6B,0x4C6B,0x2C6B,0xAB73,0x8C84,0xED9D,0x0FBF,0xAECF,0xCED7,0xCDD7,0xCDD7,0xCDD7,0xEDDF,0xCDE7,0xCDEF,0xCDF7,0xCCF7,0xCBF7,0xCBFF,0xCBFF,0xCAFF,0xEBFF,0xEBFF,0xCCFF,0xCCFF,0xCCFF,0xECF7,0xCDFF,0xCDF7,0xEEEF,0xD0E7,0xD2D7,0xD1D7,0x51CF,0x709E,0xB085,0x3185,0x117D,0xB274,0xB564,0xFD7C,0xFE84,0x5F8D,0x9F9D,0xDFAD,0xFFAD,0xDFAD,0x3F95,0x7E6C,0x5B6C,0x5B6C,0x7B6C,0x5964,0x3A64,0x5B64,0x3B64,0xF95B,0xBB63,0x9B63,0xFB73,0x5CAD,0x3D9D,0x596C,0xD65B,0xD663,0xB86B,0x5A7C,0xB45B,0x8C32,0x2A42,0x2A3A,0x2E42,0x925A,0x5042,0xEE39,0x1042,0x504A,0x5142,0xB34A,0x396B,0x5FA5,0x7FBE,0x7EA6,0x5E8D,0x1E9D,0x3FB6,0x9FBE,0x5FB6,0xBFBE,0xDFC6,0xBFB6,0x9FB6,0xBFB6,0x1F9E,0x7E8D,0x3C8D,0x797C,0x5C8C,0x5D8C,0x3B84,0x5A7C,0x9D7C,0xBD8C,0x5D95,0x5784,0xF673,0x927B,0x9073,0x316B,0x5063,0xCE5A,0x6A5A,0x0B4A,0x1463,0x3974,0xDE6B,0xFE7B,0xBE84,0x7F9D,0xFE7C,0xFD84,0xF763,0x1132,0xF541,0xBB63,0x774B,0x963A,0x5521,0x394A,0xFF73,0x3F7C,0x3F95,0xBFA5,0x7FB6,0x9FAE,0xFF8D,0xFE6C,0xFD5B,0x393B,0x3D5B,0xDA52,0xFB63,0x782A,0xD529,0x9C4A,0x1C4B,0x5A3A,0x9A42,0xBB4B,0x3942,0xDFC5,0x7FDF,0x7FCF,0x7FA6,0x5E85,0x3A53,0x9D7C,0xFC63,0xBC5B,0x3B74,0xDD63,0x7FAD,0xBFB5,0xFFCE,0x5FC7,0xFFAE,0x3E7D,0xFC53,0x795B,0xDD63,0xDD5B,0xFF8C,0xFFAD,0x3FB6,0x1FB6,0x5FBE,0x3FB6,0x5FA6,0x7FA5,0x1FD7,0x3FCF,0x3FC7,0xBDAE,0x515C,0xF97B,0x5FCE,0xBCA6,0x0F64,0xAA5A,0x8A62,0xAA5A,0xA95A,0x8962,0x895A,0x895A,0x6952,0x6952,0x4952,0x495A,0x6852,0x6852,0x2852,0x484A,0x4852,0x284A,0x2742,0x2842,0x084A,0xE741,0x0742,0x0742,0xE741,0xE741,0xC741,0xC639,0xA641,0xA639,0xA639,0xA631,0x8639,0x8631,0x8531,0x8531,0x6531,0x6531,0x6529,0x4429,0x4429,0x4429,}, +{0x2B63,0x0B63,0x2B6B,0x2B63,0x0B6B,0x2B6B,0x2B6B,0x2B6B,0x2B73,0x0B6B,0x4B6B,0x4B6B,0x2B6B,0x4B6B,0xAC73,0xED94,0x4FBE,0x31E7,0xD1EF,0xF1EF,0xD1E7,0xCFE7,0xCEEF,0xEEEF,0xCFEF,0xCEF7,0xECF7,0xCBFF,0xCCFF,0xCBFF,0xCBFF,0xCBFF,0xCBFF,0xEBFF,0xCBFF,0xEBFF,0xCCFF,0xCDFF,0xCEF7,0xEEF7,0xD0F7,0xD0EF,0xD1D7,0xD1BF,0x72CF,0x509E,0xB18D,0x5385,0x128D,0xD68C,0xDEAD,0x5FB6,0x1FA6,0xBF8D,0x7F95,0x9F9D,0x9F9D,0xBFA5,0x1F8D,0x9D74,0xDE7C,0x9FA5,0x7FB6,0x9FB6,0xBFB6,0x9FAE,0x3E96,0x7B7D,0x995C,0x3B64,0xD863,0xD973,0x996B,0xFB73,0x5DA5,0x3B8D,0x9874,0xD873,0x3C8C,0x5974,0x926B,0xED52,0xCE52,0x7052,0xD24A,0x6E3A,0xCB29,0xAA29,0x6A19,0x8E21,0xD231,0xD531,0x9A62,0x9E94,0x3FC6,0x9FB6,0x7FB6,0x9FAE,0x3EAE,0x1FAE,0x9F9D,0x9FC6,0x1FC7,0xDFBE,0x9FB6,0x5FA6,0xFF9D,0x3E8D,0x7C6C,0x985B,0xDC7B,0xBB84,0x3B84,0x9D8C,0x9FA5,0xFC84,0x9B8C,0x587C,0x7263,0xAF5A,0x3463,0x125B,0xCF52,0x0A3A,0xD462,0x9FA5,0xDFBE,0x5F96,0x9D64,0x5C5B,0xBE8C,0x5F9D,0x1E85,0x1964,0x703A,0x7331,0x574A,0x7B5B,0x3B43,0xD73A,0xB939,0x5E53,0x5E63,0x9F84,0x7F95,0x3FAE,0x9FAE,0x1F96,0x3F7D,0xFD53,0xD842,0x573A,0xF839,0x5C53,0x9A53,0xB429,0xF839,0xFB42,0x9B53,0xBB4A,0xFC5B,0x7B42,0x7EB5,0x7FD7,0x7FCF,0x7FA6,0xDD6C,0xFA5A,0x9E9D,0x1864,0x9B84,0x9D6C,0xDE8C,0x9FA5,0xBFB5,0x1FCF,0x1FC7,0xBFAE,0x5E75,0x9D7C,0x5C6C,0x7D6C,0x1E64,0x1F8D,0xBFA5,0x3FB6,0xFFAD,0x1FAE,0x3FB6,0xDF95,0x1FBE,0x1FCF,0x1FC7,0xFFC6,0xDDAE,0x1B7D,0x1FAE,0x1FD7,0x5C9E,0xCF63,0xAA5A,0xAB5A,0xAA5A,0xAA5A,0x8962,0x895A,0x6952,0x695A,0x8952,0x6952,0x6952,0x4852,0x4952,0x684A,0x4852,0x284A,0x284A,0x084A,0x084A,0x084A,0x074A,0x074A,0xE741,0xE741,0xE741,0xC639,0xC641,0xC639,0xC639,0xA631,0xA631,0x8539,0x8531,0x8531,0x8531,0x6531,0x6529,0x4529,0x6529,0x2429,}, +{0x0B63,0x0B63,0x0B6B,0x2B6B,0x0C6B,0x2B6B,0x2B6B,0x2B6B,0x2B6B,0x0B73,0x4A6B,0x2B6B,0x2C6B,0x6C6B,0xCC73,0x4C84,0x4D9D,0x4FB6,0x70D7,0xD1EF,0xD0EF,0xEFF7,0xCDF7,0xCDF7,0xCDF7,0xCDF7,0xECF7,0xCBFF,0xCBFF,0xCBFF,0xCBFF,0xEBFF,0xEBFF,0xECFF,0xEBFF,0xEBFF,0xCCFF,0xEDFF,0xCDFF,0xF0F7,0xD2EF,0xD2E7,0xD2DF,0xB2BF,0x71CF,0x709E,0x12A6,0x759D,0x368D,0x967C,0xDC84,0xDFB5,0xBFCE,0xDFC6,0x9FA6,0x3FA6,0xDF9D,0xBF95,0x5F9D,0x1F95,0xFF84,0x5F95,0xBFAD,0xFFB5,0x9FC6,0xFFCE,0x1FCF,0x3FC7,0x1FBF,0x9FAE,0x1D96,0x3B7D,0xF753,0x7753,0x796B,0x3C7C,0xDD94,0x5A7C,0xB56B,0xB983,0x7B8C,0xF46B,0xAE52,0x2F4A,0x935A,0x145B,0x555B,0x7253,0x925B,0x5153,0x3043,0x114B,0x7132,0x542A,0x1C63,0xDF94,0x1FB6,0x1FD7,0x1FD7,0xFFBE,0x7FAE,0x5F8D,0xBFAD,0xDFCE,0x1FD7,0x1FC7,0xDFB6,0x7FAE,0xBF9D,0x5C64,0xD942,0x7A6B,0x9C84,0xDA6B,0xBE8C,0x7D84,0x5C8C,0x976B,0x1874,0x1574,0x745B,0xF052,0x2F42,0x2F4A,0x3352,0x1D74,0x1F9D,0x7FB6,0x1FBF,0x5F9E,0xBD6C,0x5B5B,0x1E74,0xFC5B,0x5B64,0x585C,0xD432,0x5852,0xDA42,0x9942,0x5A4B,0xDB42,0x7C42,0x1E53,0x1F7C,0x7F9D,0xDFA5,0x5FAE,0x1F96,0x3F7D,0xBC53,0xD842,0xF93A,0xF831,0x583A,0xF942,0x3943,0xD729,0x994A,0x7D53,0x9B3A,0x7D53,0x9C3A,0xBEA4,0x1FCF,0x1FB7,0x1F96,0x3D7D,0xDB6B,0x5D95,0xDD8C,0xFFB6,0x5E85,0x3F95,0x3FA5,0xBFB5,0xFFC6,0xFFBE,0xDFAE,0x3E7D,0x7EA5,0x3E8D,0x9D64,0x5E6C,0xDE8C,0xBFA5,0xBFA5,0xDFAD,0xBF95,0x1FB6,0xBFA5,0xFFD6,0x1FC7,0xFFC6,0xDFC6,0xBFB6,0xBFBE,0xDFCE,0x1FCF,0xDB8D,0xAD5B,0x8A62,0xAA5A,0xC952,0xA95A,0xAA5A,0x895A,0x8952,0x6952,0x495A,0x6952,0x4852,0x484A,0x484A,0x4852,0x484A,0x284A,0x284A,0x284A,0x074A,0x074A,0x074A,0xE741,0xE741,0xE741,0xE741,0xC739,0xC639,0xC639,0xC639,0xA639,0x8639,0xA531,0x8531,0x8531,0x8531,0x6529,0x6531,0x6429,0x4529,}, +{0x2B63,0x0B63,0x0B73,0x2B63,0x2B6B,0x2B63,0x2B6B,0x0B63,0x2B6B,0x0C7B,0x2A73,0x4B6B,0x4C6B,0x4B6B,0x8B6B,0xCB73,0x4C7C,0x2C8D,0x4DA6,0x6DC7,0xCDD7,0xCDE7,0xEDEF,0xECF7,0xCCF7,0xCCFF,0xCCFF,0xEBFF,0xCBFF,0xEAFF,0xCBFF,0xEBFF,0xEBFF,0xCBFF,0xEBFF,0xCCFF,0xCBFF,0xEDFF,0xCCFF,0xCEFF,0xF1F7,0xF4E7,0xD5CF,0x76A7,0x34BF,0x73AE,0x129E,0x5295,0x358D,0xF994,0xDC8C,0xFF7C,0x7F9D,0x3FBE,0xDFCE,0xFFBE,0xBFB6,0x5FA6,0xDFA5,0x5F95,0x1F8D,0xDF84,0x9E7C,0xFF84,0x5F9D,0x9FA5,0x3FBE,0xBFCE,0x1FCF,0x3FCF,0x1FC7,0xFFC6,0xDEAE,0x9C85,0x5754,0x554B,0xF64A,0xDB83,0x7C94,0x755B,0x1563,0x7C8C,0x787C,0x2F53,0x6D4A,0x6F52,0xB15A,0xB35A,0xB252,0x746B,0xB773,0x387C,0x186C,0xB66B,0xD773,0x795B,0xDC73,0x1EA5,0x1FB6,0x9FBE,0xFFC6,0xFFC6,0xFF9D,0x5E9D,0x9FCE,0x1FCF,0x3FCF,0x3FC7,0xBFB6,0x5FA6,0x1D7D,0x3A6C,0x3FBE,0x5D95,0x9963,0xFB7B,0x5A6B,0xDB6B,0xD963,0xD773,0xB763,0x966B,0x956B,0x1153,0x314A,0x1A5B,0xBE73,0xBF8C,0xFFB5,0xFFC6,0x1FBF,0x1F9E,0xBB6C,0xFA52,0xBC63,0xBB63,0xFC5B,0x3B5B,0xD942,0xB742,0xF639,0x5D5B,0x1B43,0x1932,0x3D5B,0x9F6B,0xDF8C,0x9F9D,0xBF9D,0x9F8D,0x9E6C,0x5B43,0xFA4A,0x763A,0x793A,0xDB4A,0x1A4B,0xB832,0x7532,0xD831,0xBA42,0xBB32,0xDC3A,0x7C3A,0xFD93,0xFFC6,0x1FBF,0x5FAE,0x7D8D,0x9C84,0x5E8D,0x5FC6,0x1FBF,0xDE7C,0x3E6C,0x1FA5,0xBFB5,0xFFC6,0xFFBE,0x9FA6,0xFE8C,0xBFC6,0xFE95,0x5B6C,0x7F7C,0xBFA5,0x5F8D,0x7F95,0xBF9D,0x3F8D,0x1FAE,0x5FC6,0xFFCE,0x9FBE,0x9FBE,0xFFCE,0x5FCF,0x1FCF,0x3FD7,0xFFB6,0x5BAE,0x8D5B,0xC95A,0xAA5A,0xC95A,0xAA5A,0x8A5A,0x895A,0x895A,0x6952,0x4852,0x4852,0x4852,0x484A,0x2852,0x484A,0x4852,0x284A,0x284A,0x274A,0x084A,0x2742,0x073A,0x0742,0x073A,0xE739,0xE741,0xC641,0xC739,0xC639,0xA639,0x8639,0x8639,0x8639,0xA631,0xA531,0x8529,0x8429,0x6531,0x6531,}, +{0x0B63,0x2B63,0x0B6B,0x2B63,0x2B6B,0x2B6B,0x0B73,0x2C6B,0x6B6B,0x2B6B,0x4C6B,0x2B6B,0x2C6B,0x4C6B,0x8C6B,0x8B73,0xEC73,0x8C7C,0x8C9D,0xEBBE,0xCCD7,0xCDDF,0xCDE7,0xECEF,0xECF7,0xCCFF,0xCCFF,0xEBFF,0xCAFF,0xEBFF,0xCAFF,0xCBFF,0xEBFF,0xCBFF,0xCCFF,0xECFF,0xCCFF,0xCDFF,0xEDFF,0xCDFF,0xEFFF,0xF2EF,0xD5D7,0x78BF,0xFAB6,0x7AB6,0x18A6,0x94A5,0x3285,0x9484,0x3B84,0x5D74,0xDF84,0x5F95,0xDFA5,0x7FBE,0xDFC6,0xDFBE,0x9FB6,0x5FAE,0xBFA5,0x3F8D,0xDE7C,0x7D74,0x7E84,0xBF84,0xFF8C,0x3F9D,0xBFAD,0x3FBE,0xBFCE,0x1FCF,0x1FC7,0xFFBE,0xBFAE,0xDD95,0x9764,0xD242,0xB65A,0xDB6B,0xB65B,0x524B,0x5A84,0x978C,0x306B,0x8B4A,0x8D4A,0x8F52,0x4D42,0x7042,0xD352,0x9242,0xAF31,0xF049,0x7252,0x945A,0xF562,0xD75A,0xDC83,0x3FB6,0xBFC6,0xBF9D,0x9F9D,0x5F8D,0x1E7C,0xDFB5,0x9FC6,0xFFC6,0x1FCF,0x1FC7,0x7FB6,0xDF95,0xBD8C,0x5B94,0x5A7C,0xDA73,0xF86B,0x976B,0x3873,0x176B,0xD873,0xB673,0x755B,0xF452,0xB35A,0x3542,0x1C5B,0x7E63,0x9F84,0x7FA5,0x5FB6,0xFFC6,0xDFAE,0xDE8D,0x5B5C,0x9C5B,0x3B53,0x7C5B,0xB93A,0x9B4A,0x9A53,0xF731,0xF831,0xBB42,0xFC42,0xDA39,0xDE5A,0x3F74,0xDF84,0xFF84,0xFF7C,0x5F64,0x1C3B,0xFB42,0x993A,0x983A,0x3B4B,0xFD63,0x7A4B,0x562A,0x7832,0xB729,0xFB52,0xBA3A,0xDD42,0x9E7B,0xBFC6,0xDFAE,0xFF9D,0xBF95,0xBD84,0x1E9D,0xDFBE,0x9FA6,0xDF74,0x1F95,0x1F9D,0x3FB6,0xDFBE,0xBFB6,0xDF95,0x5F9D,0xFFBE,0xDE95,0x3D74,0xFF8C,0x7F95,0xDF7C,0xBF7C,0x7F95,0xFE94,0x9F9D,0x9FBE,0x7FB6,0x7FB6,0x5FBE,0x1FCF,0xDFC6,0x3FD7,0x1FC7,0xBFC6,0x3685,0xEB62,0xAA5A,0xA95A,0xA95A,0xAA5A,0x895A,0x8952,0xA95A,0x8952,0x6952,0x495A,0x684A,0x4852,0x494A,0x484A,0x284A,0x2852,0x284A,0x274A,0x284A,0x0742,0x0742,0x074A,0xE749,0xE739,0xC741,0xC641,0xC639,0xC739,0xC639,0xC639,0xA639,0xA631,0xA539,0x8531,0x6531,0x6529,0x6531,}, +{0x2A6B,0x0B63,0x0B6B,0x2B6B,0x2B6B,0x2B6B,0x2B6B,0x0C6B,0x4B6B,0x2C63,0x4C6B,0x4C6B,0x2C6B,0x4B73,0xEB73,0x2C7C,0x6B84,0xCB84,0x2B8D,0x0BAE,0x6BD7,0xCDEF,0xCDF7,0xCCF7,0xCCF7,0xCCFF,0xECFF,0xEBFF,0xCAFF,0xCAFF,0xCAFF,0xEAFF,0xEBFF,0xCDF7,0xCEEF,0xEEF7,0xCFF7,0xD0FF,0xCDFF,0xCCFF,0xEDFF,0xF0F7,0xD3DF,0x76D7,0xDAAE,0x9BBE,0x3EB6,0xBBA5,0x568D,0x948C,0x1464,0x1A6C,0x5E74,0x9F84,0x1F85,0x7F95,0xDFA5,0x7FBE,0xDFC6,0xDFBE,0x3FAE,0xBFA5,0x1E8D,0xBD74,0x5C6C,0x1C74,0xFE73,0x7F8C,0xDF84,0xFF94,0x3F95,0xFFAD,0x7FBE,0xDFC6,0xBFBE,0x7FB6,0x1FAE,0x7D95,0x165C,0xF342,0x1763,0xD663,0xB46B,0x1463,0xF15A,0x7073,0xEC52,0xEF5A,0x0E53,0xCE4A,0xB042,0xD24A,0x1353,0x7063,0x905B,0x0E53,0x8D42,0x6E52,0x3252,0xF972,0x5FAD,0xDFCE,0x9FB6,0xFF7C,0x1F54,0xDE4A,0x9E94,0x5FBE,0x7FBE,0xDFC6,0xFFC6,0x9FAE,0xFF9D,0x9B74,0x7663,0x3B74,0x9763,0xF96B,0x986B,0xD773,0xB67B,0xF35A,0xD252,0xB452,0x925A,0x724A,0x743A,0x5842,0x1D5B,0xDE73,0xFF9C,0x1FAE,0x7FBE,0xFFBE,0x7FA6,0x3E7D,0x7A53,0x5A4B,0x1B53,0xFA42,0x383A,0x1B43,0x1A3B,0x762A,0x5A3A,0x793A,0x1932,0x5C4A,0x7E5B,0x1F6C,0x5F6C,0x1F64,0xBE4B,0xDA3A,0x783A,0xDA3A,0xB942,0x7942,0x7D53,0xFB4A,0xF93A,0xB832,0x362A,0x9842,0x7A42,0xDC3A,0x3D73,0x5FB6,0x3FA6,0xDE84,0x5D64,0xBF84,0x1EA5,0x1FC7,0x7FA6,0x3F8D,0xDF8C,0x3F95,0x1FB6,0x9FB6,0x7FAE,0xDF7C,0xDFBD,0x1FC7,0x3E7D,0x5E74,0xBF84,0x9E7C,0xDF84,0x7E7C,0xDE7C,0xBFAD,0xFFAD,0x3FAE,0x3FB6,0xBFA5,0xBFC6,0xFFBE,0xDFC6,0x3FD7,0xDFB6,0x5DAE,0x2F6C,0xEB62,0x8C6B,0xCA5A,0xA95A,0x8A5A,0x8A52,0x695A,0xA952,0x695A,0x6852,0x695A,0x4852,0x4852,0x4852,0x4852,0x484A,0x2852,0x2852,0x274A,0x2742,0x2742,0x074A,0xE749,0xE741,0xE739,0xE641,0xE639,0xE639,0xC639,0xC639,0xC639,0xA539,0xA631,0x8631,0x8531,0x6531,0x6531,}, +{0x2A6B,0x2B63,0x0B6B,0x2B73,0x0B6B,0x2B6B,0x2B63,0x2C6B,0x2C6B,0x0C6B,0x4B6B,0x4C63,0x4C73,0x8B73,0xEB7B,0x6B8C,0xEB9C,0x2CA5,0xCBA5,0x4B9E,0x0BAF,0xECD7,0xECF7,0xCCFF,0xCBFF,0xCCFF,0xECFF,0xCBFF,0xCAFF,0xEAFF,0xEAFF,0xCAFF,0xCAFF,0xCBFF,0xCDE7,0xD1C7,0xD6C7,0xD7CF,0xF5E7,0xD2F7,0xCFFF,0xCFF7,0xCFF7,0xD3E7,0x38CF,0x99C6,0xFBA5,0x9DA5,0x1D95,0xDA94,0x997C,0x3874,0x3C74,0x5D74,0xBF84,0xFF94,0x3F95,0x9F9D,0x1FB6,0xBFBE,0x9FBE,0x1FA6,0xBF95,0xFF84,0x9E74,0xFB6B,0xFB73,0x9963,0x3B53,0xBD6B,0x5F7C,0xBF8C,0x1F8D,0x7F9D,0xBFA5,0xDFA5,0xDFAD,0xDFAD,0xFE7C,0x7B74,0xB663,0x1553,0xB56B,0x736B,0x125B,0x126B,0xD373,0x9363,0x9363,0x1053,0xAF42,0x8F42,0x2F42,0x915A,0xF683,0x1484,0x0F5B,0x8D5A,0x0C4A,0x1042,0x3652,0x9D83,0x9FB5,0x3FB6,0x7F6C,0x1C53,0xFA31,0x3D6B,0x7FA5,0x1FAE,0xFFAD,0x3FB6,0x3FB6,0x7F9D,0x7C7C,0x575B,0xB96B,0xB863,0xF86B,0xF76B,0xB56B,0x5563,0x335B,0x134B,0x9152,0xEE31,0xAF31,0xD752,0x774A,0x9A5A,0xDE6B,0x5F8C,0x9FAD,0x3FB6,0x9FB6,0x9FA6,0x7E85,0xBB53,0x3A4B,0x5742,0x973A,0xBA3A,0x3A43,0xB93A,0xD93A,0x5832,0x5832,0x9A3A,0xF929,0xBE4A,0x5E53,0x7F53,0xFB4A,0xFB42,0xB942,0x773A,0x5742,0xFB42,0xD93A,0x582A,0xBC63,0xDB53,0x9832,0xD73A,0x363A,0x3A53,0x9A3A,0xDD4A,0x3F95,0xFF7C,0x9F74,0xBE5B,0xFE73,0xBFAD,0x1FBF,0x9FAE,0xDF9D,0x3F8D,0x1F95,0x3FAE,0xFFA5,0x7F8D,0xDF94,0xFFD6,0xFFBE,0x5F85,0x7E84,0x7E74,0x5E7C,0xBD63,0x1F8D,0xFF8C,0x3FAE,0x3FA6,0xDF9D,0xDFA5,0xDEAD,0x1FC7,0xBFB6,0x3FDF,0x3FC7,0xDFC6,0xD99D,0xAE6B,0xDAB5,0x506C,0xAA62,0xAA5A,0x895A,0x8952,0xA952,0x695A,0x8952,0x694A,0x884A,0x495A,0x4852,0x684A,0x494A,0x484A,0x284A,0x284A,0x284A,0x284A,0x2742,0x074A,0x0742,0x0742,0xE741,0xE741,0xC639,0xC639,0xC639,0xC639,0xA639,0xA639,0xA639,0xA531,0x8531,0x6531,}, +{0x2A63,0x0B6B,0x2C6B,0x2C6B,0x2B6B,0x0B6B,0x2C6B,0x0B6B,0x2B6B,0x2B6B,0x4B6B,0x4C6B,0xCB73,0x0C7C,0x2C7C,0x8A7C,0xEA8C,0xCBAD,0xCBC6,0x6CCF,0xCDC7,0xEDD7,0xCCEF,0xEBF7,0xCBFF,0xCAFF,0xCAFF,0xCAFF,0xEAFF,0xE9FF,0xE9FF,0xE9FF,0xCAFF,0xC9FF,0xCAFF,0xCEE7,0xD6C7,0xDBAF,0xBDB7,0x7CBF,0xB9D7,0xD5EF,0xD2F7,0xD1DF,0x35CF,0x5ABE,0xDBA5,0x5C95,0xDC8C,0xBC8C,0xDC84,0x7A84,0x1864,0x3A74,0x1D74,0x3D7C,0xBF84,0xFF8C,0x5F9D,0xBF9D,0xFFAD,0x1FB6,0xFFAD,0x9F9D,0x1F85,0x3B64,0x995B,0x575B,0x595B,0x795B,0x194B,0x3B5B,0xDE6B,0x3F7C,0x9F7C,0x9F84,0x9F84,0x9E8C,0x9E7C,0x5D7C,0x3A74,0x3774,0xB35B,0x3363,0xD67B,0xB57B,0x1574,0x947B,0xD57B,0xF473,0x5263,0x1053,0xEF5A,0x8D5A,0x4E4A,0x1463,0x7373,0xAC52,0x0C4A,0x0D4A,0x1042,0x123A,0xB852,0x3D6B,0x7D5B,0x3B5B,0x9742,0xD629,0x7931,0xBD7B,0x1F95,0x3F95,0x3F95,0x9E84,0x7C7C,0x1A64,0xB663,0xB76B,0x356B,0x3663,0x9773,0xD873,0x7653,0x3553,0xD35A,0x4F42,0xED39,0x2E31,0xB341,0x964A,0x794A,0x1D63,0x1F7C,0xBF84,0x3F9D,0xBFA5,0x3FA6,0x3F8D,0x7F74,0xDD5B,0x5A43,0x9532,0x9529,0x1A4B,0x3B43,0x593A,0xD942,0x1732,0x993A,0x592A,0x7C3A,0xDD42,0x5D74,0xBC95,0xFA53,0xD842,0x763A,0x763A,0xB73A,0xD93A,0x1943,0x1A53,0x3D5C,0x7943,0x7A4B,0xF84A,0xF93A,0xB932,0x7B3A,0x7D63,0x7D63,0x9E53,0x5E53,0x1E5B,0x5FBE,0x1FBF,0xBFB6,0x9FAE,0x5E85,0x7F9D,0xDF9D,0x9F8D,0x7F6C,0xDE9C,0xFFC6,0x1FBF,0xDE74,0x1F8D,0x7F84,0x3C64,0xDE6B,0x7F84,0xFFB5,0x9FB6,0x5FAE,0x7F9D,0x1F85,0xBFC6,0xFFB6,0xBFD6,0x5FDF,0xDFC6,0x1DA6,0xB67C,0xFEBD,0x7CA6,0x4C5B,0xCB5A,0xAA5A,0xAA5A,0xAA52,0x6952,0xA952,0xA952,0x884A,0x6852,0x694A,0x884A,0x8852,0x4852,0x2852,0x484A,0x2842,0x474A,0x4742,0x074A,0x074A,0x0742,0x0642,0xE641,0xE741,0xE641,0xE639,0xC639,0xC539,0xA639,0xA639,0x8531,0x8539,0x8539,}, +{0x0B6B,0x0B63,0x4B6B,0x2C6B,0x2B6B,0x2B6B,0x2B6B,0x2B6B,0x2B6B,0x4C6B,0x4B63,0xAB73,0x8C8C,0x0C95,0x4C95,0x6B95,0xCA95,0xCBAE,0xABCF,0xCBE7,0xCDEF,0xEDEF,0xCCF7,0xCCF7,0xCBFF,0xCAFF,0xE9FF,0xC8FF,0xC9FF,0xE9FF,0xC9FF,0xC9FF,0xC9FF,0xE8FF,0xE9FF,0xEAFF,0xCEEF,0xD6D7,0x5DBF,0xBFAE,0x9FA6,0xBEAE,0xBDC6,0xBBCE,0x79C6,0xBBA5,0x5C8D,0xBE84,0x7C74,0x7C74,0xBE7C,0xBD84,0x5A74,0xF86B,0x7963,0x9A63,0xFD63,0x3E74,0xBF7C,0x1F8D,0x1F95,0x1F95,0x7F95,0x9F9D,0x1F95,0x5F7C,0xBC5B,0x9A5B,0x374B,0xF542,0x9542,0xD64A,0xF952,0x3B63,0x5B5B,0x5D63,0x3C4B,0x3A4B,0x194B,0x3953,0xBA73,0x9C8C,0xFC8C,0x9A7C,0x9884,0xD463,0x946B,0x7473,0xF78B,0x936B,0x7373,0x936B,0x9263,0x0F5B,0x6D4A,0x4E4A,0x925A,0x326B,0xF15A,0x8E4A,0x0B3A,0xEC31,0x334A,0x3652,0x563A,0x9742,0x5853,0xF43A,0xF129,0x5219,0xB739,0x3D63,0x1F6C,0x1E6C,0x3C64,0xF963,0xD75B,0xF66B,0xD473,0x7463,0x135B,0x3463,0x345B,0xB34A,0xF352,0x903A,0x2D32,0x8B29,0x4B29,0x4E29,0xB539,0xBA42,0x9A4A,0xBD6B,0x3F7C,0xBF84,0x5F9D,0x7F95,0x1F8D,0xBE7C,0x7C53,0x1E54,0x7A43,0x7A42,0xFB42,0x7C4B,0x3B43,0xF731,0xBA42,0x3B3B,0x1932,0x9B3A,0x9C4A,0xDF94,0x1FBF,0x7E9E,0x5B54,0xD842,0xF952,0x3632,0xBB42,0x7C4B,0x1C53,0x7C5B,0x7C5B,0xDC5B,0x194B,0x573A,0xF942,0x383A,0x3832,0xDB4A,0x1C4B,0xFC52,0x1E6B,0xBFC6,0x1FC7,0x3FC7,0x9FAE,0xDE84,0x3F95,0x3F85,0xDF7C,0x1E74,0x7FBE,0x3FCF,0xFFB6,0x9E7C,0xDE6B,0x9E7C,0xBC6B,0x5E74,0x9E84,0x5FBE,0xFFA5,0x3F85,0x9F95,0x7FB5,0xFFC6,0x5EA6,0xBFC6,0xDFBE,0x5FB6,0xBD95,0xBFB5,0xDFC6,0x577D,0xEA5A,0x8A62,0xA95A,0x8A5A,0x895A,0x8952,0x8A52,0x8A52,0x6852,0x4952,0x485A,0x6852,0x4852,0x4852,0x484A,0x484A,0x484A,0x2842,0x274A,0x074A,0x0742,0x074A,0xE641,0xE641,0xE741,0xE639,0xC639,0xC639,0xA631,0xA639,0xA639,0x8631,0x8539,}, +{0x0C6B,0x0C63,0x2B6B,0x0C6B,0x4B63,0x2B63,0x2C6B,0x0C6B,0x2B6B,0x6C6B,0xEB73,0xAB8C,0x6C9D,0xECAD,0x4CAE,0xABB6,0x4BBF,0xABCF,0xEBDF,0xCBE7,0xEBEF,0xCCF7,0xCCFF,0xCCFF,0xCCFF,0xCAFF,0xC9FF,0xE8FF,0xC8FF,0xC9FF,0xC9FF,0xC9FF,0xE9FF,0xC9FF,0xE9FF,0xC9F7,0xCAF7,0xEDEF,0x93C7,0xDCAE,0x1F96,0xBF85,0x5F7D,0xFF74,0x9E6C,0x7F6C,0x9F74,0x9F6C,0xBF6C,0xBF74,0x7E6C,0x5E6C,0x5C74,0x3A74,0xD75B,0x7553,0x765B,0x796B,0xBC63,0xDE6B,0xFE73,0x1F6C,0x9F7C,0xBF84,0x3F6C,0xFE73,0xBD5B,0xFA42,0x963A,0xD542,0xF74A,0x1553,0xF752,0x1653,0xF542,0xD74A,0xB752,0x953A,0x953A,0x5532,0x123A,0x5342,0x1863,0x3C7C,0xDE94,0xBD74,0xBA74,0xB453,0xF25A,0x135B,0x325B,0xB052,0xB15A,0xF15A,0x3263,0x3253,0x6E3A,0x2D3A,0xCE41,0x9352,0x7473,0x9473,0xB14A,0x8D31,0x9131,0x753A,0x3A5B,0xFA5B,0xD85B,0x344B,0x0D2A,0x2E19,0x5431,0x794A,0x3B5B,0x375B,0x755B,0xF56B,0x746B,0x5363,0x5463,0x545B,0xB46B,0x9353,0x3053,0x8F42,0x104B,0x6A31,0x2A29,0x8D31,0x5332,0xB229,0x1642,0x9A42,0xBB4A,0x5D63,0xDE73,0x9F84,0xBF84,0xDF8C,0x3FAE,0x7EA6,0xFC6C,0xBB4B,0x7D5B,0x3D64,0xBD4B,0x3B3B,0x3632,0x3832,0x7A32,0x1722,0x382A,0xBC42,0xDF94,0x7FB6,0x1FB7,0xBE7D,0x1943,0xDA32,0x9832,0x1A3A,0x9B42,0x5C5B,0xD942,0x1C53,0xBB53,0x9B53,0x7A4B,0x783A,0xB83A,0x9742,0x9842,0xB742,0x5A3A,0xDE83,0xDFBE,0xBFBE,0xFFC6,0xBFAE,0xBE74,0x5F95,0xDE74,0xDD6B,0x1F9D,0xDFC6,0x1FC7,0x5EA6,0x9E74,0x9F7C,0x5E64,0x7C5B,0x9D63,0x1F9D,0x3FAE,0x1F8D,0xBF8C,0x5F7C,0x3FBE,0x9FAE,0x1FB6,0xBFBE,0xBFBE,0x3FAE,0xFFB5,0xDFC6,0xDEB6,0x7164,0xEA62,0xCA5A,0xA95A,0xAA5A,0xAA52,0x8A52,0x6A5A,0x8952,0x6952,0x6952,0x6952,0x4852,0x494A,0x4852,0x684A,0x484A,0x484A,0x474A,0x274A,0x284A,0x074A,0x0742,0x0742,0xE741,0x063A,0xE641,0xC641,0xC639,0xC639,0xA639,0xA631,0xA531,}, +{0xEC6A,0x0B63,0x0B63,0x2C63,0x4C6B,0x2C6B,0x2B6B,0x2C63,0x6C6B,0x4B7C,0x2C8D,0xECA5,0x8BAE,0xCCBE,0x6CBF,0xCBCF,0xCAD7,0xCCDF,0xCCE7,0xCBEF,0xE9EF,0xC9EF,0xCAF7,0xEAFF,0xCBFF,0xCAFF,0xE9FF,0xC8FF,0xC8FF,0xC8FF,0xC8FF,0xE8FF,0xC9FF,0xC9FF,0xE9FF,0xE9F7,0xEAF7,0xE9EF,0xEBF7,0x90DF,0xBAA6,0x1F9E,0xDF95,0x5F7D,0x5F5C,0xFF53,0x7F64,0xFF84,0xFF8C,0xFF84,0x1F8D,0x1F85,0x3E8D,0xFE8C,0xFD84,0xBB74,0x376C,0xD563,0x765B,0x9963,0x9B63,0x9C5B,0xBE5B,0x9E63,0x9D53,0x9C5B,0x5A53,0x5A53,0x1743,0xF64A,0x154B,0x1443,0xB642,0xB442,0x165B,0x3653,0xD54A,0x9242,0x1453,0x1453,0xF242,0x8F4A,0xD252,0x165B,0xDB6B,0x9E84,0x5F95,0x3E85,0x1C85,0xBA7C,0xBA7C,0x777C,0xF56B,0x725B,0xF052,0x536B,0x925B,0xD47B,0x715B,0xD04A,0x4F3A,0x324A,0xF752,0x975B,0x344B,0x1343,0x333A,0x964A,0xF85A,0x385B,0x3353,0xD14A,0x8F42,0x2E32,0x9031,0x1142,0xB24A,0xF252,0x125B,0x5163,0x7363,0x935B,0xB35B,0x3153,0x114B,0x904A,0xD24A,0x4F42,0x0C3A,0x8B29,0x0E21,0x143A,0x7542,0x563A,0xF641,0x5C4A,0xBC42,0x1D5B,0xFE52,0x3E53,0x7D73,0xFFB5,0xBFAE,0xDFAE,0x9D85,0xDC53,0xDD5B,0x5E53,0x5B4B,0xF421,0x7621,0x1732,0x582A,0x9A32,0x7E5B,0xBF8C,0xFFAD,0xDFAE,0x5F96,0x5C54,0x9942,0xB93A,0xBC4A,0xB93A,0xDA42,0x3A3B,0xBA4A,0x3B4B,0xBD5B,0xFD7C,0x784B,0x973A,0x752A,0x785B,0x7642,0xB939,0xBF94,0xBFBE,0xBFB6,0x7FB6,0x9FAE,0x5E7C,0x1F85,0x3B4B,0x5D6B,0x5FBE,0x3FD7,0xFFB6,0xBE95,0xFE94,0x7F95,0x9B6C,0x9D7C,0x1E74,0x9FA5,0xDD6B,0xDF7C,0x5F7C,0xBE94,0x7FB6,0xBFA5,0x3FAE,0x1FAE,0x5FB6,0x1FB6,0xDFD6,0x1FC7,0x5C9E,0xAD5B,0xCA62,0xAA5A,0xAA5A,0xAA5A,0xA95A,0x895A,0xA952,0x6952,0x8952,0x6952,0x694A,0x6952,0x6952,0x684A,0x284A,0x4842,0x484A,0x474A,0x084A,0x064A,0x074A,0x0742,0x0642,0x0742,0xE641,0xE739,0xE539,0xC639,0xC639,0xA639,0xA631,}, +{0x0B6B,0x0B73,0x2B63,0x0C6B,0x0B63,0x2C73,0x2B6B,0x4C6B,0xEB6B,0x0B95,0x4CAE,0xCBC6,0x4CC7,0xACCF,0xCCD7,0xEBDF,0xCAE7,0xCBE7,0xEBEF,0xCBF7,0xE9F7,0xC9F7,0xCAFF,0xEAFF,0xCAFF,0xEAFF,0xC8FF,0xC8FF,0xE8FF,0xE8FF,0xE8FF,0xC9FF,0xC9FF,0xC9FF,0xE9FF,0xC9F7,0xEAF7,0xE9EF,0xC9F7,0xC9F7,0x6FDF,0xB8AE,0x1E9E,0x9F8D,0xFF74,0x7F54,0x9F74,0x9F7C,0xBF74,0x9F74,0xBF74,0x1F8D,0x5F95,0x5F9D,0x3F85,0xFF7C,0xBE7C,0x9E7C,0x7C74,0x386C,0x7653,0x184B,0x1953,0x1843,0xF942,0xF94A,0xBA4A,0xF952,0xF752,0x185B,0xF86B,0xBA84,0xDB7C,0x1B7D,0x5A85,0x996C,0xB853,0x1964,0xD75B,0x775B,0x195C,0x1764,0xB553,0x354B,0xF652,0x3953,0xFC73,0xBE8C,0xFE8C,0xFF8C,0x1E8D,0x9C74,0x3A74,0x3874,0x1774,0x9463,0x735B,0x957B,0xF683,0x1784,0x9563,0x945B,0xF352,0xF341,0x9752,0x7963,0x5963,0xF54A,0x9342,0x323A,0x5242,0xB352,0x534A,0xF25A,0xD052,0xB052,0x105B,0xCE52,0xCF4A,0x0F53,0xF152,0x1263,0x3353,0x1153,0x1153,0xAF4A,0x2D3A,0xCB39,0x8C31,0x3042,0x923A,0x3232,0x4F31,0x5229,0x5752,0x1642,0x172A,0x5842,0x5942,0x793A,0x9719,0x9C41,0x9F8C,0xDFBE,0x1FBF,0xFFAE,0xBD85,0x1B4B,0x5B5B,0xBB4B,0xD72A,0x1219,0xB629,0xF729,0x3A3A,0x3E5B,0x3F7C,0xDFA5,0x9FB6,0x9FAE,0xDD6C,0x993A,0x9732,0xD831,0xBB3A,0x1B43,0x1832,0x1D43,0xFC52,0x1D74,0xFE84,0x1A5C,0xB72A,0x1632,0x333A,0x365B,0xFB39,0x5FAD,0x7FAE,0x5FAE,0x5FAE,0x1E7D,0x9D42,0xBE6C,0x983A,0xDE94,0x7FBE,0x9FB6,0xDFAE,0xBC6B,0x3FB6,0x5F9E,0x9C74,0x3D74,0xDE8C,0x1C64,0xDE94,0x1E85,0x5E74,0xDFAD,0x7E95,0xBFA5,0xBFA5,0xDFAD,0xDFA5,0xDFCE,0xDFC6,0xFFBE,0x9985,0x2A63,0xAB62,0xC962,0xCA5A,0xCA62,0xAA5A,0x895A,0x895A,0x8952,0x6952,0x6952,0x694A,0x684A,0x684A,0x4852,0x484A,0x484A,0x474A,0x2742,0x274A,0x074A,0x0742,0x0742,0x0742,0x0742,0x063A,0xE639,0xC641,0xC639,0xA639,0xA639,}, +{0x0B6B,0x0C6B,0x2B6B,0x2B6B,0x0B6B,0x4C6B,0x4B6B,0xEB73,0xCB84,0xEB9D,0xCBB6,0x6AC7,0xCADF,0xECE7,0xCBDF,0xCAE7,0xC9EF,0xCAE7,0xC9E7,0xC9F7,0xC9F7,0xC9FF,0xE9FF,0xEAFF,0xE9FF,0xE9FF,0xC7FF,0xC7FF,0xC8FF,0xE8FF,0xC9FF,0xCAFF,0xCAFF,0xCAFF,0xCAFF,0xCAF7,0xCAF7,0xCAEF,0xC9EF,0xC8EF,0x8AEF,0xCFDE,0x36AE,0xBB8D,0x5E85,0x1D65,0x7F64,0x1F6C,0x1F74,0x1F6C,0x5F64,0x5F74,0xBF84,0xDF84,0xDF7C,0xDF84,0xDF7C,0xBF74,0x5E64,0xFC73,0xDA5B,0x774B,0xD54A,0xD53A,0x9442,0x7542,0x333A,0xF331,0x533A,0x7442,0x375B,0x7D84,0x7FA5,0x5FBE,0x7FC6,0x9FBE,0x5FAE,0x3FA6,0x1FA6,0xFE95,0x3F9E,0x5FAE,0xBFAE,0x9EA6,0x1D9E,0x1D75,0x7C64,0x1C6C,0xFB63,0x3C74,0x7D7C,0xFB6B,0x7B7C,0x1974,0x397C,0xF96B,0x975B,0x345B,0x1363,0xB25A,0xF35A,0xD452,0x166B,0xD44A,0x7342,0x524A,0xF341,0x554A,0xB652,0x924A,0x924A,0x514A,0x5042,0x6F42,0x4E4A,0x6E4A,0x6E4A,0x6F4A,0xAF4A,0x9053,0xCE4A,0x8D4A,0x6E4A,0x6F4A,0x6E4A,0x2D42,0x0C3A,0x8A31,0x6929,0x4B29,0x2C29,0x9031,0x9342,0x3432,0x3232,0x7129,0x553A,0x7642,0x353A,0x1432,0x1943,0xD932,0x1819,0x7D62,0xBFAD,0x1FCF,0x5FC7,0x1FAF,0x7C85,0x7C5B,0xBD53,0x762A,0xB221,0xD942,0x572A,0xBA31,0x5F4B,0xDF73,0x5F9D,0x3FAE,0x7FA6,0x9F75,0x5B43,0xB82A,0xD831,0x5A32,0xFA42,0x7521,0xBA3A,0x1B4B,0xFB52,0x1D74,0x1D75,0x331A,0xB752,0xBC95,0xD953,0x1B52,0x9FA5,0xFFA5,0x3FAE,0xDF95,0xBB53,0x5B42,0x7D74,0xBD6B,0x9FA5,0xBFBE,0xFFC6,0xBF8D,0xFE94,0xFFBE,0x9E85,0xFD73,0xFE8C,0x9E74,0x1A53,0x1F74,0xBD63,0xDF94,0x3F8D,0xFF8C,0xBF7C,0xBFAD,0xDF9D,0x1FC6,0xDFBE,0xDFBE,0x7EA6,0x7274,0xEA5A,0xCA62,0xCA62,0xAA5A,0xAA62,0xA95A,0xA952,0xA852,0x695A,0x6952,0x6952,0x894A,0x4852,0x6852,0x484A,0x284A,0x484A,0x2852,0x2842,0x2842,0x074A,0x0742,0xE741,0xE741,0x0742,0xE741,0xC641,0xC641,0xA639,0xA639,}, +{0x2B6B,0x0C6B,0x2C6B,0x2B6B,0x2C6B,0x6B6B,0xEB6B,0xEA84,0xCBA5,0xCAB6,0x4ABF,0xC9CF,0xC9DF,0xEBE7,0xCAEF,0xE9EF,0xC9EF,0xCAEF,0xC9EF,0xC8EF,0xC8EF,0xC8F7,0xE9FF,0xE9FF,0xC9FF,0xE8FF,0xC8FF,0xC8FF,0xC7FF,0xE8FF,0xC9FF,0xCBFF,0xEAFF,0xEBFF,0xCBF7,0xCCF7,0xCDEF,0xCEE7,0xCEEF,0xCBEF,0x6CDF,0xADE6,0xEEB5,0x5185,0x5885,0x7B8D,0x1C75,0x1C4C,0x5C3B,0x5D53,0xFF6B,0x3F6C,0x3F64,0x3F64,0x3F6C,0x1F6C,0xFF5B,0x1F6C,0xFE5B,0x9C6B,0xD963,0xD75B,0xF54A,0xB43A,0x7342,0x7242,0x1032,0x2E3A,0x503A,0x934A,0x144B,0x9A63,0xBE63,0x1F74,0x9F84,0x3F9D,0xBFAD,0x3FBE,0x7FBE,0xFFCE,0x3FCF,0x9FD7,0xBFDF,0xBFE7,0xBFDF,0x3FBF,0xDFAE,0x7FA6,0xDE95,0x3E7D,0xBD7C,0xFA63,0x3A6C,0x3A6C,0xB963,0x785B,0x1753,0xF552,0x355B,0x1453,0x755B,0x1553,0x103A,0x534A,0xB552,0xD652,0xD44A,0xB24A,0x7042,0xED31,0x8C31,0x4C31,0x8D39,0xAC39,0x2D42,0x8F52,0x0C3A,0x2D3A,0xAD4A,0xCE4A,0xCC4A,0xAA42,0x2A3A,0x2D4A,0x2B4A,0x0C42,0x4C4A,0x2C3A,0xEC31,0x4A29,0xE820,0xE818,0x4F29,0x0F21,0x5021,0x7432,0xD54A,0x733A,0xD129,0x3232,0x9429,0xD942,0x1D64,0x3943,0xD930,0xBE83,0x7FC6,0x1FCF,0x1FC7,0xFEAE,0x3C64,0x7B5B,0xFA42,0x9421,0xB93A,0x3722,0xB829,0x9C4A,0x5E5B,0x3F95,0x5FAE,0x5FA6,0xDF85,0x7C4B,0xF83A,0x583A,0x573A,0xD93A,0x5832,0x163A,0x5832,0x9A42,0x1D7C,0x7D75,0xD853,0x7D8C,0x1FAF,0x9E7D,0xDE6B,0xDFA5,0x9F9D,0xBF95,0x9E6C,0xD83A,0x7A4A,0x3E74,0x1F95,0xBFA5,0xFFAD,0x7FAE,0x1E6C,0x3FBE,0xDFB6,0x5E85,0x7D7C,0x9D84,0xDA53,0x3C5B,0xFD63,0x1E74,0x9E7C,0x7F84,0x7F74,0xBF8C,0xDFA5,0x3FB6,0xBFCE,0xDFC6,0x1FB7,0x5A8D,0xAE63,0xEA5A,0xEA5A,0xCA5A,0xAA5A,0xA962,0x8962,0xA95A,0x895A,0x8952,0x6852,0x6952,0x6852,0x6952,0x6852,0x6852,0x684A,0x284A,0x284A,0x2842,0x274A,0x0742,0x074A,0x0742,0x073A,0xE741,0xC741,0xC639,0xC639,0xA639,}, +{0x0B6B,0x2B6B,0x4B63,0x2B6B,0x8C6B,0x2B74,0x0B7D,0xEA9D,0xCAB6,0x8ACF,0xCAD7,0xCAD7,0xCADF,0xEBE7,0xEBEF,0xEAF7,0xEAF7,0xCAF7,0xC9F7,0xC8F7,0xC8F7,0xC8FF,0xC8FF,0xC8FF,0xE8FF,0xC8FF,0xC8FF,0xC9FF,0xE8FF,0xE9FF,0xEAFF,0xEAFF,0xCBFF,0xCCFF,0xCBFF,0xEEF7,0xF2EF,0xD4DF,0xB5D7,0x72D7,0x12D7,0x52D6,0xB2B5,0x5295,0xD584,0x1985,0x1A7D,0xFA74,0x5964,0xB843,0x5943,0xBE6B,0xDF6B,0xDF63,0x9F5B,0x5F53,0x5E4B,0x5E4B,0x3C4B,0xF942,0x795B,0x9873,0xD54A,0xB44A,0x924A,0xB04A,0x325B,0xB363,0xF863,0x5B7C,0x9B84,0x1B74,0xDC63,0xDD53,0xBD5B,0xBE6B,0xBE6B,0x1F74,0x7F84,0xBF8C,0x3F9D,0xBFAD,0x1FB6,0x7FC6,0xDFCE,0x1FCF,0x3FDF,0x5FD7,0x3FCF,0xBFBE,0xFF9D,0xFE74,0x3B64,0x7853,0x1853,0x385B,0x9863,0xF86B,0x345B,0x155B,0x1553,0x723A,0x5032,0x303A,0xAF29,0x5031,0xD239,0x334A,0x944A,0xB152,0x7152,0x0D42,0x4C42,0x2B3A,0xEB39,0x0E4A,0x1453,0x735B,0xEE52,0x4C4A,0x2B42,0x4B4A,0x4B4A,0x4C4A,0x2B42,0x0C42,0x2D42,0x704A,0x9242,0x7032,0x923A,0x102A,0xEE29,0xB029,0x2E21,0x0D21,0xAB18,0x3021,0x5332,0x3132,0x7121,0x7221,0x1629,0xBB4A,0xBD74,0x1954,0xBA49,0x7E94,0x9FBE,0xFFBE,0xFFB6,0x7C7D,0xFA42,0xF83A,0xD531,0xFB3A,0x562A,0x5519,0x5B42,0x3F63,0xBF8C,0x3FA6,0xFFB6,0xDFA6,0xBB4B,0xDA3A,0xFA42,0x373A,0xD229,0xB842,0x773A,0x3732,0x3842,0x3A4A,0x9F8D,0x5D64,0x1F9D,0xFFB6,0x5F9E,0x5F8D,0x9F95,0x5F95,0x3F85,0x3D5C,0x3532,0x1D5B,0x5F95,0xDE6B,0x1F95,0xBFA5,0x9F8D,0xDE8C,0xBFBE,0x7FAE,0xBD7C,0x7A63,0xFD84,0xB642,0x3C74,0x3B6C,0x5C6C,0xDE8C,0x1E6C,0xFE6B,0x5F9D,0xDFA5,0x9FCE,0xBFBE,0xFFC6,0x7EAE,0x7474,0x0A63,0xCA62,0xEA5A,0xCA5A,0xCA62,0x8A62,0xA962,0xA95A,0x895A,0x895A,0x695A,0x8952,0x8952,0x6852,0x484A,0x484A,0x4952,0x484A,0x484A,0x284A,0x2842,0x074A,0x0742,0x0742,0x0642,0xE741,0xE639,0xE639,0xA639,}, +{0x0B6B,0x4B6B,0x2C6B,0xAB6B,0x8B7C,0x6A8D,0x6AAE,0x0AB7,0xAAC7,0xEADF,0xCAE7,0xCAE7,0xEAEF,0xCAEF,0xEAEF,0xCAF7,0xCAF7,0xC9F7,0xC8F7,0xC8F7,0xC9FF,0xE9FF,0xC8FF,0xC8FF,0xC8FF,0xC7FF,0xC8FF,0xC9FF,0xC9FF,0xE9FF,0xE9FF,0xCAFF,0xCCFF,0xEDF7,0xCEFF,0xD1F7,0xF4EF,0xB7DF,0x39CF,0x18BF,0xB9BE,0x38AE,0x749D,0xB28C,0x146C,0x1764,0x9A74,0x9A6C,0x7964,0xD75B,0x774B,0x3653,0x996B,0x5A5B,0xFA4A,0xDB52,0xBA42,0xF93A,0xB732,0x5632,0x764A,0xD54A,0xF452,0x924A,0x9152,0xF052,0xB25A,0x576B,0xFC7B,0x5E7C,0xDD6B,0x9C5B,0xBD73,0xDE6B,0xDE63,0x1B4B,0x373A,0x3A3A,0x9C52,0x7E6B,0x3F7C,0x7F84,0xDF7C,0xDF84,0x1F8D,0x3F9D,0x5FA5,0xBFAD,0x1FB6,0x1FAE,0x1FAE,0x7F95,0xDE7C,0xDA5B,0x374B,0xB442,0x933A,0x954A,0x1553,0x555B,0x545B,0x5032,0x713A,0x0E3A,0x503A,0x9242,0x704A,0x0E3A,0xCD31,0x4F42,0x313A,0xCF41,0x6E42,0xAF42,0xD352,0x335B,0xD352,0x7773,0x3A7C,0x935B,0x115B,0xB36B,0xAD52,0x4B4A,0x2B42,0xCC41,0x304A,0xD552,0xB54A,0x154B,0x543A,0x763A,0x523A,0x5442,0xB63A,0x943A,0x5132,0x4B21,0xAA18,0x2E21,0x0F19,0x4E21,0x2E11,0xD018,0x1531,0x7C74,0x7D85,0xFA53,0x7B5A,0x7FA5,0x7FB6,0xDFB6,0xDE95,0xBC53,0x7B43,0x3722,0xF521,0x9932,0xF721,0xDB31,0x3E63,0xBFAD,0x3FCF,0x3FBF,0x7F9E,0x3A3B,0xD729,0x1A43,0xB83A,0xD431,0x3532,0x763A,0x1532,0x1732,0x3C4A,0x1E85,0xFF84,0x9FAD,0xBFB6,0x9FA6,0xFF95,0xFE84,0xBE84,0xDB5B,0x5A4B,0x9A42,0x9E63,0x3E6C,0xDD6B,0x5E74,0xDF84,0x1F8D,0x9FAD,0xBF9D,0x5E95,0x7953,0x3E7C,0xB76C,0xDA6B,0x9B8C,0x3B64,0x7E84,0x5E64,0x5D53,0x5F84,0xDFAD,0xFFBD,0xBFBE,0xBFC6,0xFFBE,0x9C9D,0xEE6B,0xEB62,0xCA62,0xEA62,0xEA5A,0xCA5A,0xAA5A,0xA95A,0x8A5A,0x8952,0x8952,0x8952,0x8852,0x6952,0x6952,0x484A,0x4952,0x6852,0x474A,0x284A,0x274A,0x274A,0x084A,0x074A,0xE749,0xE749,0x0742,0x0642,0xC639,}, +{0x2B63,0x4B6B,0xAC73,0x8B7C,0x6A95,0x8AB6,0x69C7,0xCAD7,0xC9DF,0xC9E7,0xEAE7,0xCAEF,0xEAF7,0xCBF7,0xCAF7,0xCAF7,0xC9F7,0xC9F7,0xC9F7,0xC8F7,0xC8F7,0xE8F7,0xE8FF,0xC7FF,0xC8FF,0xE7FF,0xC8FF,0xE9FF,0xE9FF,0xE9FF,0xEAFF,0xCBFF,0xECFF,0xCDFF,0xEFFF,0xD0F7,0xD3E7,0x96D7,0xDAC6,0x7DAE,0x5D9E,0xFD95,0x9A8D,0xD57C,0xD363,0x9453,0x396C,0x9B74,0x9A74,0xD753,0x5543,0x354B,0x345B,0x5663,0x1553,0xD442,0xD442,0xB752,0x9542,0xB54A,0xF44A,0xF35A,0xD24A,0x9142,0x704A,0x4F42,0x0E42,0x0E3A,0x1242,0x9852,0x5C6B,0x9C6B,0x195B,0xB84A,0x594A,0xFA52,0xF952,0x563A,0x1422,0x7421,0x1719,0x7831,0x3B4A,0xBC52,0x7D63,0x9F7C,0x7F85,0x5F85,0xBF8D,0xBF8D,0xFF95,0xDF95,0x5E85,0x1D7D,0xBC8D,0x3B85,0xDA7C,0x3664,0x744B,0xB13A,0x713A,0xD34A,0x144B,0x7032,0x2F3A,0x0E32,0xCD31,0xEE41,0xF673,0x198D,0x5974,0x1453,0x755B,0x765B,0x365B,0x966B,0x765B,0x766B,0x146B,0x5A84,0xBA7C,0x5A7C,0x5C95,0xB77C,0xB35B,0xF04A,0x0C3A,0x8E39,0x334A,0xD54A,0x5542,0xB942,0x553A,0x9742,0x374B,0x743A,0x153A,0x9542,0x323A,0xD029,0x8D21,0x4D21,0x2C11,0x2A11,0xEB18,0x7018,0x7639,0xBD7C,0x5D75,0xBC5B,0xFD7B,0xFFAD,0xBF9D,0xDF6C,0xDE53,0x5C4B,0xF83A,0xF629,0x9B42,0x7A22,0x9931,0xFE62,0x1F9D,0x5FCF,0x7FAE,0x3F7D,0x1B3B,0x783A,0x973A,0xB542,0x5642,0x5632,0x1432,0x142A,0x7621,0x1721,0xBD52,0xDF8C,0xBFA5,0xFFAE,0xBFA6,0xDF85,0xFB5B,0x5C6C,0x3C6C,0x9B5B,0x3C53,0x9A4A,0x7C5B,0x1D6C,0xFE6B,0x1D7C,0xBE84,0xFF94,0x9FA5,0xDB74,0x1D74,0x3CA5,0x5EAE,0xF763,0x396C,0x7A6B,0xBE84,0x5C53,0xFF6B,0x1FA5,0x3E9D,0xDFC6,0x9FB6,0xFFBE,0x1FAE,0xF794,0x2B6B,0xEA62,0xCA62,0xCA5A,0xCA5A,0xA95A,0xC962,0x895A,0x895A,0x895A,0x695A,0x8952,0x695A,0x895A,0x4852,0x8952,0x6852,0x684A,0x4852,0x274A,0x274A,0x284A,0x2742,0x2742,0x0742,0xE741,0xE639,0xE641,}, +{0x2B63,0xCB6B,0x8B7C,0x6A8D,0x8AAE,0x8AC7,0xCAD7,0xEADF,0xE9E7,0xCAE7,0xC9E7,0xC9EF,0xC9F7,0xCAF7,0xEBFF,0xEBFF,0xCAF7,0xEAF7,0xE9FF,0xC9FF,0xE9F7,0xE8FF,0xC8FF,0xC8F7,0xC8FF,0xC8FF,0xC8FF,0xC9FF,0xEAFF,0xCAFF,0xCAFF,0xCBFF,0xCCEF,0xCFEF,0xD1EF,0xD0F7,0xB1EF,0x34DF,0x79BE,0xFCA5,0xBE8D,0x7E85,0x3E8D,0x3D85,0x586C,0x9253,0x965B,0x5B7C,0x5A6C,0xF963,0xB75B,0xF23A,0xF34A,0xB252,0xF35A,0xD552,0x154B,0xB44A,0xD34A,0xD44A,0xD24A,0x1463,0x335B,0x124B,0xAF4A,0x8F42,0x4E42,0x6E4A,0xAF52,0x5042,0xCF39,0xB139,0x344A,0xB85A,0xD752,0x143A,0xD639,0x9842,0x9742,0x973A,0x9632,0x562A,0x3732,0x7632,0x5C74,0x7FBE,0xDFBE,0x1FCF,0x5FD7,0x5FCF,0x1FC7,0xFFB6,0x9FB6,0x7FAE,0x5FAE,0x1FA6,0xFFA5,0x7E95,0xFD7C,0x5A74,0xBA74,0x9774,0xB453,0x334B,0xF24A,0x914A,0x6F42,0x4F3A,0x3242,0xDC9C,0xFFC6,0xDEB6,0x3D9E,0x1C85,0x9A63,0x9963,0xB85B,0x5653,0x9673,0x798C,0xD97B,0x3D84,0xBE8C,0xBFA5,0xDFBE,0x7EA6,0x7C7D,0xF853,0xB14A,0x514A,0xF84A,0x5642,0x7742,0x993A,0x3742,0xD73A,0xD74A,0x3642,0x5532,0xD229,0xAE29,0xEC31,0x2B21,0x6919,0x0819,0xE918,0xAC10,0xF418,0x9B4A,0x3F8D,0xDE7C,0x3E53,0x5E74,0x9F74,0xBE5B,0xFC3A,0xBD53,0xD832,0xB521,0x5A2A,0xFB3A,0xF831,0x9C52,0x5F84,0xDF8C,0x7F85,0xDF64,0x1B3B,0x783A,0x9742,0x963A,0x953A,0x1432,0x3232,0x9029,0xF018,0xF828,0x9F5B,0xDE6B,0xFFAD,0xDFAE,0x7F9E,0x7D6D,0xF75A,0x9863,0x5D74,0xDA5B,0x3B4B,0xD629,0x3D4B,0x7B53,0x595B,0x9B73,0xDD73,0x3F95,0x1F9E,0x1B6C,0x3E95,0x7FBE,0xFC8D,0xBB84,0x565B,0x9C63,0xDD53,0x1D4B,0x7E63,0xFF8C,0x5FC6,0xBFB6,0x9FBE,0x1FA6,0xFDB5,0xEF63,0x0A5B,0xCA62,0xCA5A,0xCA5A,0xCA5A,0xCA62,0xA95A,0xA952,0x895A,0x895A,0x8952,0x8952,0x6952,0x6952,0x6852,0x694A,0x484A,0x684A,0x284A,0x074A,0x2842,0x274A,0x2742,0x0742,0xE741,0x0742,0xE641,}, +{0xAC6B,0x6B7C,0x6B95,0x8AAE,0x89CF,0xE9DF,0xC9E7,0xCAE7,0xEAE7,0xCAEF,0xEAEF,0xC9F7,0xE9F7,0xCAF7,0xCBFF,0xCBF7,0xCBF7,0xCAF7,0xCAFF,0xEAFF,0xEAFF,0xC9FF,0xEAFF,0xEAFF,0xCAFF,0xCAFF,0xEAFF,0xEBFF,0xCBFF,0xECFF,0xECFF,0xCCFF,0xCCF7,0xCFE7,0xB0BF,0x50C7,0xD1BE,0x53BE,0x75A5,0x388D,0x1B7D,0x1E75,0x3F85,0x5F95,0x3F95,0xBA7C,0xB24B,0x975B,0x1A6C,0x1A6C,0xB753,0x3653,0xB03A,0xD14A,0x124B,0x1253,0x354B,0x1353,0xB24A,0x914A,0xB142,0x9042,0x1253,0x936B,0x5263,0x946B,0x135B,0x115B,0x9252,0x513A,0x0F42,0xEF41,0xEE39,0x8E31,0x2F31,0x0F29,0x2F21,0x7229,0x9331,0xF539,0xF531,0x173A,0xF839,0x5742,0x583A,0xDD7B,0x3EA5,0xDFB5,0x1FB6,0x7FBE,0xBFC6,0xFFC6,0x1FCF,0x3FD7,0x5FCF,0x3FBF,0xFFBE,0x5FAE,0x9F95,0xFF7C,0x7E95,0x1FBF,0x9EA6,0x1D96,0x786C,0xB132,0x2F3A,0x6E29,0xD029,0x9429,0xDA62,0xBFAD,0x1FCF,0x5FC7,0xBEA6,0xFC7C,0x5D74,0x5C74,0xF973,0x3863,0x9773,0x175B,0x1C6B,0x1F95,0x7FA5,0x3FBE,0xFFBE,0xBFAE,0xDE8D,0x195C,0x134B,0xF439,0x994A,0x1632,0x3742,0x3632,0x7431,0x1532,0x343A,0xF339,0x3AB6,0x7ED7,0x7BA6,0xD66C,0x714B,0xEB29,0xCD29,0xD021,0xF010,0xD528,0x5C84,0x9F6C,0x3F53,0xBE63,0x5E6C,0x7D4B,0xF921,0x9B3A,0x7D43,0x9832,0x7629,0x383A,0x9A32,0xFB39,0xBF63,0x9F74,0x1F64,0x9E53,0x7932,0x583A,0xB842,0xD842,0x763A,0x133A,0x313A,0xD129,0xCF10,0x1721,0x5E4B,0xDE5A,0x3FB6,0xBFAE,0x7F96,0xDC6C,0xD542,0x395B,0xBB7C,0x7B5B,0x374B,0x1B5B,0xDD5B,0x9853,0xF762,0x7C73,0x7F9D,0xBFA5,0x5E7D,0x1F95,0x9FA5,0x5FBF,0xBE8D,0x1864,0xF952,0x1E6C,0x7D53,0x9E4B,0x9E7C,0x3EA5,0xBFBE,0x7FB6,0x1FA6,0xDFB5,0x368D,0x2A5B,0xEB62,0xCA5A,0xCA5A,0xEA5A,0xC95A,0xAA5A,0xA95A,0xA95A,0xA952,0xA952,0x8952,0x8952,0x6952,0x6952,0x6852,0x684A,0x684A,0x484A,0x284A,0x4842,0x2742,0x274A,0x0842,0x0742,0x0742,0xE739,}, +{0x0B74,0xEC8C,0x2AA6,0x4ABF,0xC9DF,0xC8E7,0xE9E7,0xE9E7,0xCAEF,0xC9F7,0xC9F7,0xC8F7,0xC9F7,0xCAFF,0xCBFF,0xEBFF,0xEBFF,0xEAFF,0xC9FF,0xCAFF,0xE9FF,0xE9FF,0xCAFF,0xCBFF,0xCCFF,0xEBFF,0xCAFF,0xCCFF,0xECFF,0xCDF7,0xCEFF,0xCEFF,0xCEF7,0xEFEF,0xB0E7,0xEFBE,0x10A6,0x519D,0xD284,0x9474,0x786C,0xBC74,0x1F85,0x5F8D,0x7F95,0x7F9D,0xDC7C,0x5754,0xF75B,0xB85B,0xD86B,0xD65B,0x945B,0x9253,0x514B,0x3253,0x114B,0xB14A,0x904A,0xB052,0x315B,0x3153,0x7363,0x946B,0x535B,0x7563,0x1553,0xF452,0xD652,0xF54A,0x514A,0x103A,0xCF39,0xAC31,0x2A29,0x0819,0x2919,0x0921,0x2A29,0x6E19,0x2E11,0x0E11,0x1019,0xCF18,0xAF10,0xB010,0x7618,0x3931,0xBC5A,0x1E84,0x3FA5,0xFFB5,0x3FB6,0x7FBE,0x5FBE,0x5FB6,0x7FBE,0x3FBE,0x5FAE,0x7FAE,0x5FD7,0x3FCF,0xBFB6,0x3FAE,0xFB7C,0x585B,0xB64A,0x7342,0xAF19,0x5232,0xF329,0x7931,0x3D7B,0xFFBD,0x3FCF,0x3FBF,0x1FBF,0xBE95,0x7E6C,0xDB63,0xB95B,0x7B53,0x353A,0x7939,0xBE7B,0x3F9D,0x9FA5,0x5FB6,0xDFBE,0x9FA6,0x9E85,0xD953,0x1432,0x5742,0xD742,0x963A,0x1432,0x6F31,0x2E21,0x3031,0x7573,0x976A,0x7D8C,0xDFB6,0x5FBF,0x7EB7,0xFC85,0xF64B,0xD321,0x152A,0x5319,0x1621,0x7D3A,0x7C32,0x9C5B,0xDC5B,0xBC32,0xDB3A,0x9C32,0x3C43,0x1A33,0x772A,0xD829,0x5A3A,0x5B32,0xFE4A,0x3F53,0x9F43,0x7C3A,0x572A,0xB642,0xB642,0xB93A,0x9953,0x7332,0xD229,0x541A,0xEF10,0x9418,0x9D42,0xDE62,0x1FAE,0xBFAE,0x9F9E,0xD95C,0x744A,0x7C74,0x3953,0xDB5B,0x3742,0x3A4B,0x3D5B,0xFC6B,0x3963,0x5E8C,0xDF9D,0xBF95,0x7E7C,0x5FB6,0x5FBE,0x1FAF,0x3D7D,0xB842,0x7C63,0x1F6C,0x3E6C,0x5F8D,0xFE8C,0x9FBE,0x7FB6,0x1FA6,0xFFAD,0x3CB6,0xAC63,0xEA6A,0xCA6A,0xEA62,0xCA62,0xCA5A,0xC962,0xA95A,0xC95A,0xC95A,0xA952,0x895A,0xA952,0x6952,0x8952,0x8952,0x884A,0x6852,0x484A,0x484A,0x4742,0x284A,0x274A,0x0742,0x0742,0x0742,0x0742,}, +{0x2C7D,0x2CAE,0x4ABF,0xC9CF,0xC9D7,0xCADF,0xEAE7,0xCAE7,0xC9E7,0xE9EF,0xE9F7,0xC9F7,0xC9F7,0xE9FF,0xC9FF,0xE9FF,0xCBFF,0xEAFF,0xE9FF,0xCAFF,0xCAFF,0xC9FF,0xCAFF,0xEBFF,0xCCFF,0xCCFF,0xCCFF,0xCCFF,0xCCF7,0xCDF7,0xCDF7,0xCFFF,0xCFF7,0xCEEF,0xB0DF,0xB2BE,0xD295,0xF274,0x725C,0x535C,0x1454,0xF753,0x3C6C,0xDE7C,0x5F8D,0x5F8D,0x1F95,0x9E7C,0x7B74,0x396C,0xD55B,0xF65B,0x166C,0x1664,0xF463,0x715B,0x715B,0x315B,0x1053,0x1063,0x3163,0xB473,0xF773,0xD46B,0x956B,0x955B,0x334B,0x9242,0x7342,0x744A,0x7452,0x553A,0x3132,0x0E2A,0x6B19,0x4A21,0x2821,0x0611,0x0921,0x0919,0x2D11,0x2F21,0x2E19,0x2D19,0xCB10,0x8908,0x6A00,0x2C08,0x7108,0x5610,0xB910,0x7C29,0x5E4A,0x5F7B,0x5E84,0xDE8C,0x5E95,0x5F95,0xDE7C,0x9E7C,0x7FA5,0x7FC6,0x9EC6,0x5FB6,0x1D8D,0xBA63,0x575B,0xD54A,0xD342,0xF34A,0xF752,0xB642,0xB529,0x3939,0xBD83,0x1FB6,0xDFC6,0x3FCF,0xDFAE,0xDF9D,0xDD7C,0xBA53,0x7742,0x773A,0x1729,0xDC41,0x1E7C,0x9FA5,0x9F9D,0x1FAE,0x7FAE,0xFF95,0xDD6C,0x1633,0xD531,0x142A,0x343A,0x6E21,0x8D21,0x2B21,0x2D29,0x4E29,0xB539,0xDC62,0xBF94,0x1FB6,0xBFBE,0x1FB7,0x9E9E,0x7A64,0x352A,0xF421,0x7319,0xB929,0x3A2A,0xF929,0x3C43,0x7D4B,0x9B32,0xBD53,0x3B4B,0x792A,0x5932,0x1722,0xD831,0x3A2A,0x1C32,0x9E32,0x1832,0x762A,0x153A,0x3753,0xB742,0xD94A,0xDA53,0x3743,0xB121,0xF529,0x2F11,0x3318,0x5D32,0x3E73,0x7FAE,0x9FA6,0xBF8E,0xB84B,0x1953,0xBA53,0xBD5B,0x9642,0x1A53,0xBB4A,0x7D63,0x9B5B,0xDC5A,0xDE8C,0x5F8D,0x3F8D,0x5FA5,0xFEAD,0x1FC7,0x1F96,0x7B64,0xB942,0xDE63,0x7E84,0x7FBE,0xFF9D,0xFFAD,0x7FB6,0xFF9D,0xBFB5,0xBFCE,0xD27C,0x0B63,0xCA62,0xEA62,0xCA62,0xCB62,0xCA5A,0xC962,0xC95A,0xA95A,0xAA5A,0xA95A,0x8952,0xA852,0x8952,0x894A,0x8952,0x6852,0x684A,0x484A,0x484A,0x484A,0x274A,0x284A,0x2742,0x0742,0xE741,}, +{0xEBAD,0xCBBE,0xA9DF,0xE9E7,0xCAE7,0xCAEF,0xCAEF,0xC9EF,0xC9EF,0xC8F7,0xC9F7,0xE9FF,0xC9FF,0xE9FF,0xE9FF,0xE9FF,0xC9FF,0xC9FF,0xEBFF,0xEBFF,0xC9FF,0xCAFF,0xCBFF,0xCBFF,0xCBFF,0xCBFF,0xECFF,0xCCFF,0xCCFF,0xCCF7,0xCDF7,0xCEEF,0xCFEF,0xCFEF,0x90D7,0x55A6,0x5C8D,0x3C7D,0x1D6D,0xBC5C,0x7D6C,0x7B5C,0xDC6C,0xFE74,0xFF74,0xFF84,0xFF8C,0xBE7C,0x7B74,0x5B74,0x5B7C,0x776C,0x3564,0x7774,0x1574,0xB473,0xD063,0x726B,0x505B,0x0F5B,0x2F53,0x324B,0xF242,0xF24A,0xF352,0xF65A,0x5763,0x585B,0x575B,0xF33A,0x3132,0xF131,0x1232,0xF039,0x8E21,0x4C19,0x2921,0x4821,0x0719,0x4819,0x2D21,0x2F19,0x0D19,0x0C19,0x0B19,0x4B11,0x4A19,0x2B21,0x4C19,0x0B11,0xCD10,0xB010,0x9210,0x5531,0xFB83,0x9EA5,0x5FB6,0xDFBE,0x3FC7,0x1FBF,0xBFAE,0x7FA6,0xFF9D,0x3E8D,0xDE7C,0xFE7C,0x7C64,0xD85B,0xF542,0x354B,0xB642,0x542A,0x1532,0x9642,0x1632,0x1831,0xDC83,0xFFBD,0x3FCF,0xFFC6,0xDF9D,0x5C7C,0xDA5B,0x394B,0x5932,0x3732,0x5931,0x1C52,0x3E7C,0x3F95,0x7F9D,0xBFA5,0xDF9D,0x5F7D,0xFB53,0x3432,0xF239,0x1232,0x8C19,0x6A19,0x4B21,0xEA28,0x2E21,0x9429,0xBD4A,0x7F63,0x7F8C,0x9FA5,0x7FAE,0xFFB6,0x9FA6,0x7C7D,0x9A43,0xD732,0x7621,0x793A,0xD839,0x9D9D,0x9A4B,0x5A32,0x7C3A,0xDB3A,0x182A,0x1822,0x3732,0x7619,0xF929,0xF829,0xF721,0xD221,0xD331,0x7542,0x553A,0x973A,0x9842,0x1A43,0x3843,0xF319,0x9221,0xD219,0x9629,0x3E4B,0x1E74,0x3F9E,0x5F9E,0xFE7D,0x7632,0x9D5B,0xBD5B,0x5A53,0xFA52,0xB942,0xFA39,0x1D53,0xBB3A,0xDE5A,0xBF84,0xDF7C,0x5E84,0x7FAE,0x5FC6,0x1FB7,0xDF95,0xDB4B,0x1D7C,0xDE9C,0x1FB6,0x1FAE,0xDFA5,0x9FB6,0x3FAE,0x1F95,0xFFB5,0x7795,0x4A63,0x0A63,0xEA5A,0x0A63,0xCB62,0xCA62,0xCA62,0xC95A,0xA95A,0xA95A,0xA95A,0x8952,0x8852,0x895A,0x6952,0x8952,0x8852,0x6852,0x4852,0x4852,0x284A,0x4752,0x2752,0x2742,0x2742,0x0742,}, +{0xC99D,0xC9A6,0x89BF,0xE8D7,0xC9E7,0xC9EF,0xC9EF,0xE9F7,0xE9F7,0xC8F7,0xC9F7,0xC8F7,0xC9FF,0xE9FF,0xC9FF,0xC9FF,0xE8FF,0xE9FF,0xEAFF,0xCBFF,0xEAFF,0xEAFF,0xCBFF,0xCBFF,0xEBFF,0xCBFF,0xCCF7,0xCCFF,0xECFF,0xCCF7,0xCCEF,0xCDEF,0xEDE7,0xCEE7,0x6FDF,0x74AE,0x5C7D,0xDF74,0xDF7C,0xFF84,0x1F8D,0xFF74,0xFF6C,0x1F85,0x1F8D,0xFF7C,0xBE74,0x9D74,0x9C74,0x7A6C,0x7A74,0x9B74,0x996C,0x5674,0x1674,0xD46B,0xF46B,0xB473,0xF583,0x3684,0x9A84,0xFC7C,0xFC8C,0xFB7C,0xBA6C,0x5A64,0xF963,0x5743,0xB742,0x964A,0xB74A,0x7542,0x1032,0x8D29,0x6F31,0x6E29,0xAB21,0xAA19,0x4919,0x4919,0x2C19,0x2F21,0x4F21,0x2F21,0x2E19,0x2D19,0x6E21,0x4D21,0xB029,0x101A,0xD021,0xD019,0xCF21,0xF021,0x9229,0xF931,0xDE52,0xBF73,0xBF94,0xBFAD,0x5FB6,0xBFBE,0xFFC6,0x1FC7,0xFFB6,0x5FAE,0x7F95,0xBD74,0x1A64,0x5753,0xB442,0x743A,0xB442,0x954A,0xB442,0xF74A,0xB63A,0x9839,0x7C73,0x5ECE,0x9FBE,0x7D8D,0x1C6C,0x1E7D,0x1C7D,0x1843,0xB842,0xB629,0x3821,0xFB49,0xBE73,0xDF8C,0xFF84,0x1F8D,0xDF7C,0xDB53,0x7532,0x1332,0x123A,0x8D19,0x4B19,0x8D29,0x4D19,0x9131,0x9529,0x9939,0xDE52,0x9F63,0x3F7C,0x9FA5,0x5FB6,0xFFB6,0x7F9E,0xDE6C,0x3B43,0xD832,0x593A,0x9A3A,0xFC42,0xD821,0xD929,0x9C42,0xDB32,0x582A,0x182A,0xD619,0x1622,0x5219,0xB419,0xD111,0x6E11,0xF121,0x5232,0x113A,0x553A,0x762A,0x1732,0xB932,0x5522,0x1211,0xF821,0x5721,0x7D42,0xBE6B,0x9F8D,0xDF8D,0xBD54,0xD731,0x1D4B,0xBD53,0x5642,0x5C64,0x5742,0xFA39,0x7E4B,0x1A32,0x5E63,0x3F64,0x9F74,0xBE94,0xFFAD,0x1FBF,0xDF95,0x7E64,0xF942,0xDD52,0x9FAD,0x9FB6,0xFFA5,0x1FB6,0x3FAE,0xFE84,0x7FCE,0x1BAE,0x8C63,0x0B5B,0x0A5B,0x0A5B,0xEA62,0x0A5B,0xEA5A,0xCA62,0xAA5A,0xCA5A,0xA962,0xAA52,0xA95A,0x895A,0x8852,0x8952,0x6852,0x6852,0x6852,0x484A,0x484A,0x484A,0x484A,0x474A,0x2742,0x0742,}, +{0xAAAE,0x6ABF,0xC8BF,0xC9C7,0xC9D7,0xE8E7,0xC8E7,0xC8EF,0xC8F7,0xC9F7,0xC9F7,0xC8F7,0xC9FF,0xC9FF,0xC8FF,0xC9FF,0xC9FF,0xE9FF,0xE9FF,0xC9FF,0xCBFF,0xCBFF,0xCAFF,0xC9FF,0xCAF7,0xEBF7,0xCBF7,0xCBF7,0xCBEF,0xCBEF,0xECE7,0xCCDF,0xCCDF,0x8CCF,0xCDB6,0x32A6,0xB785,0x1B6D,0x9F6C,0x5F6C,0x7F74,0xDF7C,0x5F95,0x7F9D,0x3F8D,0x3F8D,0x3F8D,0x3F85,0x1E75,0xDC74,0xBC7C,0x7A74,0x395C,0x377C,0x176C,0x156C,0xD46B,0xF673,0x9774,0xDA7C,0x5C6C,0x3C64,0x3C74,0x7E8C,0xDE94,0x1F95,0xFF94,0xBE84,0x3D74,0x1B5C,0x984B,0xD53A,0x733A,0x523A,0xB031,0x6C21,0x8D21,0x8B21,0xAA29,0x4A29,0x4A21,0x2B19,0xEA18,0x0C21,0x0E21,0x2C19,0x4E29,0x2F31,0x7019,0x9429,0x9429,0xB321,0xD121,0xF139,0x1232,0x7421,0xDA29,0x3C3A,0xFE52,0x7F5B,0xFF73,0x9F84,0xFF8C,0x5F9D,0xBFAD,0x1FB6,0x3FAE,0x9FA5,0xDD84,0x1964,0xD95B,0xF64A,0xD029,0xD131,0xB44A,0xD752,0x5753,0x144B,0x1242,0xF451,0x5B63,0xBF9D,0x7FAE,0x9FAE,0xBF95,0xFE7C,0x5C64,0xD63A,0x1532,0xF629,0xB731,0x9939,0xFC5A,0xBE63,0xBE5B,0x9D5B,0x1A43,0x3643,0x3342,0x9432,0x7332,0x6C21,0xF021,0x9229,0x3532,0x5842,0x182A,0x9C42,0xFE5A,0xBF7B,0x9F8C,0x9F9D,0x5FA6,0x7FA6,0x3F96,0x7D6C,0x3C4B,0xBA32,0xB931,0x5932,0xDA32,0x7842,0x5932,0x172A,0x192A,0x162A,0xB321,0x9121,0x3332,0xD021,0xEF19,0xAB19,0x312A,0xCF29,0x7029,0x342A,0x9932,0x141A,0x3219,0x9632,0xD419,0x392A,0xB921,0x9D3A,0xDF6B,0x3F7D,0x1F6D,0xB62A,0x3A3A,0xDC3A,0xBB4A,0xDFA5,0x3B7D,0xBA3A,0x1C4B,0x5B43,0x7C42,0x7E5B,0xBF63,0x1D5B,0xBFA5,0x1EB6,0x9F9E,0xDF7C,0x3D6C,0x9D53,0xDE9C,0x9FBE,0x7FB6,0xFFA5,0x1FAE,0x7F8D,0xDFBD,0x3DAE,0x0F6C,0x0A63,0x0A63,0x0B63,0xEA62,0xEA5A,0xEA5A,0xEA62,0xAA62,0xCA5A,0xC95A,0xC952,0xA95A,0xA95A,0xA952,0xA95A,0x895A,0x685A,0x685A,0x684A,0x484A,0x474A,0x274A,0x484A,0x274A,0x274A,}, +{0xAACF,0xEAD7,0xE9DF,0xC9E7,0xC9E7,0xE9E7,0xC8E7,0xC8E7,0xC8EF,0xC8F7,0xC9F7,0xE9F7,0xC8FF,0xC8FF,0xE8FF,0xC9FF,0xE9FF,0xC9FF,0xE9FF,0xE9FF,0xEAFF,0xCBF7,0xCBF7,0xCAF7,0xCAEF,0xCAE7,0xC9E7,0xCADF,0xEADF,0xE9E7,0xEBDF,0xCBD7,0xCCC7,0x4CB7,0x6C9E,0x6E85,0x537D,0x3975,0x7B74,0x1A54,0x1C5C,0x5F64,0xBF7C,0xDF84,0x1F8D,0x7F9D,0x5F8D,0x9F95,0x9F95,0x5F8D,0xDE7C,0xBC6C,0x1964,0xB663,0xF863,0x5974,0x5984,0x7B84,0xDE8C,0x5F95,0x9F9D,0x9FA5,0x9F95,0xBF9D,0x3F85,0xBE7C,0x5E74,0x9E74,0xDE7C,0x1F85,0xDF84,0x3D64,0x9A4B,0xD532,0x1122,0xF021,0xAE29,0xAC21,0x6A21,0x2A21,0x2B29,0x2D29,0x0A19,0xC918,0xCA18,0xCC18,0x0C19,0x0B21,0xEB18,0xCF18,0xCE10,0x1011,0xB111,0x7221,0xB329,0xB329,0x9429,0x1732,0x1732,0xB831,0xF941,0xBB52,0xFC5A,0x5D63,0x9E73,0xFE73,0x5E7C,0x1E74,0xDC6B,0x585B,0xF74A,0x945A,0x4F42,0x714A,0x1042,0x7242,0x723A,0xB44A,0x755B,0xF54A,0x573A,0x9E63,0x3F8D,0xBFB6,0xBFB6,0x5FAE,0x5F8D,0xDD74,0x9742,0xD842,0xF531,0x5421,0xB629,0x783A,0xF731,0xD931,0x5A3A,0xFD7C,0x5C85,0xB753,0xD842,0x7843,0xF021,0x3019,0xD529,0x7521,0x1832,0xFC4A,0x9D53,0x9E52,0x3E5B,0xDF6B,0x7F7C,0x7F9D,0x3F9E,0xBF95,0x3E7D,0xFA3A,0xF829,0x5932,0x192A,0x793A,0xB842,0xF742,0x7532,0xB519,0xB219,0xB219,0xB129,0x3122,0xEF21,0xCB19,0x8C19,0x0E22,0xCE21,0xB019,0xB329,0x7622,0xD319,0x5219,0x362A,0x9722,0xB821,0xFD5B,0x5D3A,0xFF63,0x7F64,0x1D44,0x593A,0x593A,0x7C3A,0x3D6B,0xBFAE,0xBE64,0x393B,0x7B4A,0x9B42,0x9C53,0xBE5B,0xBC5B,0xDC83,0x3FA6,0xDFB6,0x7F8D,0x1D53,0x5D7C,0xFE83,0xFFAD,0x7FB6,0x5FAE,0xFFA5,0x9F9D,0x1E95,0xBEA5,0x5885,0x6B5B,0x2B63,0xEA6A,0x0A63,0xEA62,0xEA5A,0xEA5A,0xCA62,0xEA5A,0xE95A,0xCA5A,0xC95A,0xA95A,0x8952,0xA852,0x8952,0x8952,0x695A,0x8852,0x684A,0x4752,0x484A,0x274A,0x484A,0x2842,}, +{0xA9CF,0xC9D7,0xE9E7,0xC9E7,0xC9EF,0xC9EF,0xC8EF,0xC9EF,0xC9F7,0xC8F7,0xC9F7,0xC9F7,0xC9FF,0xC9FF,0xC9FF,0xCAFF,0xC9FF,0xCAFF,0xC9FF,0xE9FF,0xEAFF,0xCAF7,0xCAF7,0xCAF7,0xE9EF,0xEAE7,0xE9DF,0xEAD7,0xEAD7,0xCADF,0xCBD7,0xCBD7,0xCCBF,0x2DA7,0x2C86,0x2B6D,0xAF6C,0x935C,0xF66B,0xB753,0xF863,0xFD63,0x5F6C,0x7F74,0x9F74,0x7F74,0x9F74,0xFF84,0x5F95,0xDF84,0x5E74,0x3E7C,0x1A6C,0x9974,0xBB7C,0xDC7C,0xBE74,0xDE74,0x5D6C,0x5E6C,0x7F7C,0x5F7C,0x9F84,0xDF8C,0xFF8C,0x5F9D,0x5FA5,0x9F95,0x9F95,0x3F8D,0xDF84,0x7F7C,0x1E5C,0x9C53,0xD742,0x732A,0xF021,0xCD19,0x8A21,0x6B21,0x4A21,0x2B21,0xB163,0x158D,0x704B,0xEF3A,0x133B,0x5443,0x353B,0xD632,0x7622,0x1522,0xF521,0xB321,0xB221,0x4F19,0x8F19,0x3121,0x1221,0x7329,0xB331,0xD739,0x373A,0x373A,0x793A,0x5842,0xD942,0x9642,0x353A,0x1342,0x113A,0x504A,0x6E42,0x2D32,0xAC31,0x8B31,0x8D29,0x8D39,0xCF39,0x133A,0x984A,0x983A,0xBB52,0x5F84,0x7FA5,0x1FAE,0x7FAE,0x9F95,0x5D6C,0x7A53,0x7A6C,0xDA74,0xD75B,0xD742,0xF742,0x1329,0x9531,0xD95A,0x1FAE,0xBFAE,0x5D8D,0xFC63,0xFB53,0xD43A,0xF429,0xF429,0x9519,0x1321,0x5529,0xFA39,0x7D32,0x5E32,0xDE52,0xDF6B,0x9F7C,0x3F95,0xFF7C,0xDE5B,0xDD53,0x7943,0xB721,0x193A,0xD942,0x9C63,0x9E64,0x9943,0x7219,0xB219,0x3332,0xD121,0xF029,0xEF19,0x8C19,0x4C19,0x8D29,0x6E11,0x1021,0xD329,0x7211,0x9421,0x1522,0x5419,0xF929,0x5942,0x1C5C,0xBE4A,0xDF5B,0x3D3B,0x772A,0x993A,0xB739,0x7D53,0xBE94,0x7F9E,0xDE6C,0x572A,0x3B53,0xDB63,0x1A53,0xBB53,0xDA4A,0x5E95,0xDF9D,0xDF95,0x3B43,0x9D63,0xDC42,0x7E8C,0x7FB6,0x5FAE,0xBF9D,0x3F95,0xDFA5,0xDF9D,0x7ECE,0x5485,0x2B63,0x0B6B,0x2A63,0xEB62,0xEA62,0x0B63,0xEA62,0xEA62,0xE95A,0xC95A,0xC952,0xC95A,0xC952,0x895A,0x8952,0x8852,0x8852,0x8952,0x8852,0x6852,0x4852,0x484A,0x484A,0x4842,}, +{0xA9C7,0xC8CF,0xE8D7,0xC9DF,0xCAEF,0xE9EF,0xC8F7,0xEAF7,0xCAF7,0xC9F7,0xC8F7,0xE9F7,0xC9FF,0xC9FF,0xE9FF,0xCAFF,0xE9FF,0xE9FF,0xEAFF,0xEBFF,0xCAFF,0xCAFF,0xCAF7,0xC9F7,0xE9E7,0xC9E7,0xC8D7,0xC9C7,0xC8C7,0xC9CF,0xEAC7,0xCABF,0x8DA7,0xCE96,0x507E,0x6D6D,0xAE64,0x9164,0x525C,0xF243,0x934B,0x584B,0x7C53,0x9E63,0x9E63,0xBE53,0xDE63,0x5F6C,0x7F74,0x5F6C,0x9D5B,0x7A53,0x1A84,0xFE9C,0x9FAD,0x1FBE,0x1FAE,0x1FB6,0x5FAE,0xFFC6,0x9EB6,0xDE6C,0x1F64,0xDF63,0xDF6B,0x3F74,0x5F74,0x7F7C,0x7F7C,0x9F84,0x9F84,0x7F74,0x9E53,0x3B4B,0x9842,0x5432,0x532A,0x102A,0xEE29,0x6B19,0x0919,0x6A21,0x38AD,0xFCA4,0xDA7B,0x5E84,0x1F8D,0xFF8C,0x1F74,0x3E4B,0x5E53,0x5C53,0xFA42,0x5632,0x1322,0x9119,0x9019,0xAF11,0x6E19,0x6E19,0x6E11,0x2D11,0xCC18,0x2E21,0x6F21,0x8F29,0xB021,0x8F29,0x0F2A,0xCE39,0x2E3A,0x4E42,0x6F4A,0x6F42,0x9142,0xAF4A,0x744B,0x745B,0x964B,0xD642,0xB54A,0xD74A,0xB84A,0x3A3A,0xBC5A,0x7E63,0xFF94,0xBFA5,0x9F95,0x9E74,0xDE84,0xBFB6,0x1FBF,0xBFAE,0x1F9E,0xFA74,0xF021,0x9429,0x3641,0xBD94,0xBFBE,0x9FA6,0xDF8D,0xDE74,0x9A43,0xD321,0xF729,0x973A,0xD529,0xD419,0xB218,0x5729,0x1B3A,0x1E32,0xBE52,0x7E63,0x3F6C,0x9F5B,0x7C3A,0x7D6C,0xBC74,0xB719,0x9529,0x3932,0x3D4B,0x3B43,0xDB4B,0x352A,0x1322,0x342A,0x532A,0x8F19,0xD019,0x8D19,0xAA18,0x8E21,0x2F21,0x3021,0x7311,0xF519,0x382A,0xD92A,0xF621,0x1829,0x5E64,0x9C3A,0x3D43,0x1B33,0xB63A,0xD63A,0xD832,0x1A32,0xFE5A,0xDFAD,0x1F96,0x7C64,0x3A42,0x7B5B,0xDC5B,0x5C4B,0xDC4A,0x7E63,0x1F85,0xBF95,0x7E6C,0xD931,0x9E74,0xFE73,0xFFAD,0x9FAE,0x1FA6,0xDF84,0x7F95,0x5E95,0x5FC6,0x7DBE,0x4F6C,0x0B6B,0x2A63,0x0B63,0x0B63,0x0A63,0xEA62,0xCA62,0xCA62,0x0A5B,0xCA5A,0xC95A,0xC95A,0xA962,0xA952,0x895A,0x885A,0x8952,0x6952,0x484A,0x4852,0x6752,0x474A,0x4842,}, +{0x89CF,0xC8CF,0xC9D7,0xE9D7,0xC9E7,0xC9E7,0xC9EF,0xCAF7,0xCAF7,0xCAF7,0xC9F7,0xC9F7,0xC9F7,0xE9FF,0xE9FF,0xC9FF,0xCAFF,0xCAFF,0xCAFF,0xEBFF,0xCBFF,0xC9FF,0xE9F7,0xE9EF,0xC9EF,0xC8E7,0xE7E7,0xE6D7,0xC6C7,0xA6BF,0x87B7,0x49AF,0xCB9E,0x6D86,0x1076,0x6F5D,0xCE54,0x6F54,0x104C,0x914B,0x304B,0xF232,0x933A,0x753A,0x9642,0xF84A,0x7B63,0xDD5B,0xBE5B,0x9E5B,0x5D53,0x9B4B,0x385B,0x384B,0x5B5B,0x9D6B,0x5E7C,0x3FA5,0xFFAD,0x9FC6,0xFFD6,0xBFCE,0x5F95,0x5F6C,0x3E4B,0xFE42,0xFF52,0xFE4A,0xDE4A,0x3F53,0x3E53,0xFE4A,0xBD4A,0x7B42,0x763A,0xF331,0xB029,0xAE21,0xAE21,0x8E21,0x8C19,0x6B29,0x6C31,0xAD20,0x2D08,0x5110,0x9518,0x7939,0xF720,0x7829,0xB839,0xB731,0x9629,0x9429,0xD331,0x132A,0x5432,0x143A,0x953A,0xF742,0xD73A,0x742A,0xD442,0xF642,0xF64A,0xF64A,0xD542,0x723A,0x913A,0x0E3A,0x6E42,0xEF52,0x4E4A,0x6D42,0xD14A,0x334B,0xF44A,0x3442,0x7542,0x7442,0x774A,0xD852,0xB752,0x784A,0x1B4B,0xF929,0x9D4A,0x7F6B,0x9F9D,0xDE9D,0x1D64,0x9D52,0x5E7C,0x5FBE,0x1FC7,0xFFBE,0xDEA6,0x397D,0x5764,0x3221,0xFB6A,0x1FAE,0x9FAE,0x3FA6,0x7F8D,0xBD64,0xF73A,0xF421,0x3321,0x182A,0x983A,0x7832,0x372A,0x5721,0x9939,0x1C32,0x9D42,0xDD3A,0x7C22,0xB829,0x5A52,0xDA3A,0x983A,0x372A,0x9729,0x1B3B,0xFB3A,0x3C54,0x1843,0x3643,0x3432,0x3332,0x122A,0x3322,0x1022,0xEC18,0x4C19,0x3019,0xB319,0x9211,0x5619,0x9B32,0xF629,0x9721,0x1A32,0xFD4B,0xFC32,0x5A3B,0x112A,0x5332,0x7322,0x5219,0xDB52,0x5E63,0x1FA6,0x3E75,0xF731,0x5D5B,0x9D53,0xBB42,0x9B42,0x9D3A,0x3F74,0x5F8D,0xDF74,0xBA3A,0x7D5B,0x7E63,0xBF94,0x7FB6,0xFFA5,0xBE7C,0x7F9D,0x3F8D,0x1FAE,0x3FB6,0x1A9E,0xAC5B,0x2A63,0x2A63,0x0B63,0x0A63,0xEA5A,0x0A63,0xEA62,0xE95A,0xE95A,0xC95A,0xC95A,0xA95A,0xC952,0x8952,0x8952,0x8952,0x6852,0x6852,0x4852,0x6852,0x684A,0x284A,}, +{0x4AC7,0xA8CF,0xC8D7,0xE8DF,0xC9E7,0xC9E7,0xC9EF,0xC8EF,0xE8EF,0xE9F7,0xC9F7,0xEAF7,0xCAF7,0xC9F7,0xC9F7,0xC9FF,0xEAFF,0xCAFF,0xEAFF,0xCBFF,0xCAFF,0xC9FF,0xC9F7,0xE9E7,0xC9EF,0xE8E7,0xC7E7,0xC6D7,0xC5CF,0x65BF,0x07BF,0xEAA6,0xAC96,0x2C76,0x6C5D,0xEB54,0xCE4C,0x8E44,0x0F4C,0x8F4B,0x0E3B,0x902A,0x7232,0x522A,0x312A,0x1443,0x9A53,0x1E5C,0xFF63,0xDE5B,0xBE5B,0x9A4B,0x794B,0x384B,0x1653,0xD74A,0x1843,0x7D5B,0x1E74,0x9E8C,0x9FAD,0xBFB5,0x1F9D,0x7F7C,0x3D4B,0x7932,0xF819,0x7719,0x7819,0xB931,0xF831,0xB829,0x5629,0x7319,0xF231,0xF331,0x1032,0xCF29,0xAC21,0x8B21,0x4911,0x2C21,0x8D29,0x6919,0xC510,0x6910,0x4F21,0xCE18,0xEE10,0x1119,0x5319,0x7419,0x9521,0xB429,0x1232,0x713A,0x3242,0x534A,0x533A,0xF639,0xB529,0x7229,0x5329,0xB429,0x133A,0xB439,0xB331,0xB129,0x0F32,0x2E42,0x6F42,0x4E4A,0x2D4A,0x2D42,0x4E42,0x9242,0xF65A,0x3863,0x365B,0xB54A,0x9642,0x954A,0xD74A,0x5642,0x353A,0x3432,0xB529,0xD941,0x7E8C,0x1FAE,0x9E95,0xDE74,0x9C4B,0x7C63,0x1D84,0xDFAD,0xFFC6,0xDFBE,0xFFB6,0x5D7D,0xF542,0xF730,0x1D7C,0xDF9D,0x1FA6,0x9F8D,0x3F7D,0x3E54,0x5B3B,0x593A,0xBA32,0x382A,0x9821,0x1822,0x382A,0x393A,0xF729,0xD729,0xB819,0x9719,0xF731,0x1E7D,0xDF8D,0xDD64,0xBA2A,0xD821,0xF929,0x393A,0xFD63,0x5E7D,0xDC7C,0xFA53,0xB43A,0x943A,0xF321,0x9121,0x7322,0x2F11,0x3019,0x5311,0x3319,0x5621,0x7B2A,0x7519,0x1621,0xDD4B,0x7932,0xF832,0xD432,0xAE29,0xCF21,0x2C19,0xB518,0x1E5C,0xBE7B,0xFF9D,0x1B54,0x773A,0x7A4B,0xDA42,0x1A4B,0x5C2A,0xBE52,0xBF7C,0x7F74,0x5B53,0x1A42,0xDF63,0x1E7C,0xBFAD,0x9F9D,0x3D74,0x3F95,0x3FA5,0x7F9D,0xDFAD,0xBFCE,0x9685,0x4B6B,0x0B63,0x2A63,0x0A6B,0x0A5B,0x0A5B,0xEA62,0x0A5B,0xEA62,0x095B,0xE95A,0xC95A,0xA95A,0xA952,0xA952,0x895A,0x8852,0x8852,0x8852,0x4952,0x4852,0x4842,}, +{0xE9BE,0x68C7,0xC7D7,0xE8DF,0xE8E7,0xE9E7,0xE8E7,0xC8EF,0xC8E7,0xC8EF,0xC9F7,0xEAEF,0xCCF7,0xECF7,0xCCFF,0xCAFF,0xEAFF,0xCAFF,0xE9FF,0xC9FF,0xCAFF,0xCAF7,0xCAF7,0xC9EF,0xE9EF,0xE8E7,0xC6E7,0xC5DF,0xC6CF,0x48CF,0x29B7,0xEB96,0xAB96,0x0D7E,0x8C5D,0x6E5D,0xCD4C,0x0B44,0x4A3B,0x4B3B,0x2C33,0x8D2A,0x2F2A,0x1032,0x513A,0xB963,0x9E8C,0x1F85,0xDF84,0x9F74,0x9F74,0x5E6C,0x1D5C,0x9B5B,0x5A5B,0x1743,0xF74A,0xD852,0xB84A,0x7A3A,0xDA42,0x1B5B,0xBB52,0x1D4B,0xFD4A,0xBB52,0x9A3A,0x7732,0x562A,0x342A,0x142A,0x9119,0x6F19,0xD129,0x333A,0x122A,0x1132,0x333A,0xF131,0x503A,0x9142,0xEC29,0x6A19,0x4921,0x6931,0x8829,0x6B31,0x6D39,0x4E19,0x1019,0x7319,0xB421,0x7529,0x9229,0x9031,0xCD31,0x2D29,0x8B10,0x8C08,0x8E08,0xAF08,0xF018,0x3219,0x5229,0x9229,0xB229,0xB221,0xD229,0x513A,0x2E3A,0x0D3A,0x2D3A,0x0C3A,0xCC41,0xCC39,0xCD39,0xCF39,0x3142,0xB25A,0x7442,0xB342,0x7242,0xF031,0x334A,0xD542,0xB642,0x9642,0x1632,0x5821,0xDC7B,0xBF9D,0x3F8D,0x9E74,0x3E8D,0x5F8D,0x9E63,0xBD73,0x5E95,0x9F9D,0x5F8D,0x5E8D,0x5C5C,0x782A,0x7939,0x3D84,0xBF95,0x7F8D,0xFF74,0x7E64,0x7A43,0xF621,0xD621,0xD729,0x1822,0x182A,0xD731,0xF629,0xF421,0xB419,0x9311,0x5319,0x5B4A,0x1F8D,0x1F9E,0xBF6C,0x1B43,0x582A,0x7419,0x7942,0x9E74,0x5F95,0x1FA6,0xDE8D,0xB853,0x5543,0xCD21,0x3219,0x7532,0xB121,0x5319,0x3211,0x1419,0xB919,0x361A,0xD118,0x9942,0x5B43,0xD832,0xF73A,0x342A,0xEC19,0x0919,0x8F08,0x7A31,0x1E5C,0x9E84,0x3F7D,0xDC4B,0x3C53,0x5D4B,0xBC53,0xF721,0x9A42,0x1D53,0x1E6C,0xDC5B,0x783A,0xFB4A,0x7C5B,0x1E74,0xFF8C,0x5C6C,0x1F95,0x7D84,0xDF8C,0x9F9D,0x5FC6,0x9CAE,0xCC63,0x0A63,0x2A63,0x2A63,0x0A63,0x2A5B,0x0A63,0xEB62,0xEA5A,0x0A5B,0xE95A,0xE95A,0xCA5A,0xA95A,0xA95A,0xA95A,0xAA52,0xA852,0x8952,0x6852,0x684A,0x484A,}, +{0x08BF,0x89BF,0xE8D7,0xE8DF,0xC8DF,0xC8E7,0xC8E7,0xC9E7,0xC8E7,0xC9EF,0xE9EF,0xC9F7,0xEBEF,0xCCF7,0xCDF7,0xCCF7,0xCCFF,0xEBFF,0xCAFF,0xE9FF,0xC9F7,0xC9F7,0xCAEF,0xCAEF,0xC9EF,0xC7EF,0xC5E7,0xC5DF,0xC5DF,0xA6D7,0x69B7,0x2CA7,0xAC96,0x2C76,0xAD6D,0x8F65,0xCE64,0x2C54,0x4A3B,0x0A3B,0xED42,0x6D3A,0x6D2A,0x4E32,0x2D2A,0xF74A,0xDE73,0x9F84,0xBF84,0x1F95,0x3F9D,0xFF84,0xDF7C,0x9F74,0x3E6C,0xDB6B,0xD963,0x164B,0x944A,0x953A,0x533A,0x343A,0x344A,0x5542,0x3732,0x5832,0x183A,0x573A,0x7942,0x7842,0x563A,0x3432,0x5342,0xD54A,0x7532,0xF431,0x543A,0x3342,0x7342,0x5342,0x9242,0x313A,0x4F3A,0x2C42,0xE931,0xEA31,0x2B42,0x0D3A,0xF039,0xAF29,0xF131,0x8F31,0x4C29,0xEB20,0xCD10,0xEC08,0x0E11,0x6F11,0x9111,0xF219,0xB121,0xF221,0xB219,0x9221,0x383A,0xFA42,0xD942,0x773A,0x3332,0xF031,0xCD31,0xEB31,0x2D42,0xEC41,0xCA31,0x8B31,0xAA39,0x0E42,0xF039,0x9129,0xF539,0xF84A,0x374B,0x3553,0x723A,0xF239,0x6F29,0x3321,0xB629,0xDB39,0xDE5A,0x1F8D,0xDF7C,0xFF63,0x9E53,0xFE6B,0xFF7C,0x1D64,0x5D5B,0x7E5B,0x7D63,0x9E6C,0x1B43,0x3B43,0x7832,0xDA41,0x3D7C,0xFF84,0x1F64,0x1C43,0x9932,0x782A,0x382A,0x3722,0x1622,0xB529,0xD521,0xD419,0xD321,0xB119,0xB219,0x5521,0x5A39,0xFF73,0x5F8D,0xFF74,0xFD53,0x992A,0x9421,0x1C4B,0x5F74,0xBF84,0xDF9D,0x7FA6,0xDD85,0xF74B,0x2B19,0x1129,0xF539,0x3319,0x7309,0xB208,0xF410,0x5922,0x8F09,0x1221,0x3B43,0xF629,0x3732,0xF529,0xB229,0xEF21,0xA900,0x6F10,0x7B42,0x3E6C,0x7F8D,0x1F75,0xFC4A,0xFD63,0x5B53,0x532A,0xFA4A,0x5B4B,0xDA4A,0xDA5B,0xB542,0x9329,0x595B,0x1A53,0xDC6B,0x9963,0x5D7C,0x7D84,0xFF84,0x3F8D,0x1FB6,0xFFCE,0x1475,0x4A63,0x4B6B,0x2B6B,0x0A63,0x0A5B,0x2B63,0x0B63,0x0A63,0x0A5B,0xE95A,0xEA5A,0xE95A,0xA962,0xC852,0xA95A,0xA952,0xA852,0xA85A,0x8852,0x8852,0x684A,}, +{0x29AF,0xA8C7,0xE7D7,0xC7DF,0xE8DF,0xC8DF,0xC8E7,0xCAEF,0xC9EF,0xC9F7,0xC9F7,0xC9F7,0xE9F7,0xCAF7,0xEBF7,0xCDF7,0xCDF7,0xCCF7,0xEBF7,0xEAF7,0xC9F7,0xC9F7,0xCAEF,0xEBEF,0xEAEF,0xE8EF,0xC6E7,0xE7DF,0xC7D7,0xA6D7,0x89BF,0x2AAF,0xAC8E,0x2C76,0xCD6D,0x2E55,0xCE5C,0x4E64,0xED5B,0x4B43,0xCA3A,0xAA2A,0x8C32,0x2B2A,0x2D2A,0xB332,0x1B4B,0x5E5B,0xBF63,0x1F74,0x1F7C,0x9F84,0xFF94,0xFF94,0xFF8C,0x7E74,0xFA5B,0x1753,0x9332,0x1332,0xF239,0xF241,0x3142,0x5342,0x7542,0x763A,0x563A,0x3432,0x142A,0xF429,0xD531,0xF339,0x553A,0x7742,0x7742,0x953A,0xD44A,0xF552,0x1553,0xB44A,0x934A,0x713A,0x4F3A,0x8E52,0x525B,0xF473,0x7563,0x5563,0x1463,0x503A,0xF031,0x8E31,0xF021,0x9632,0x594B,0xFA53,0x7C64,0x1B54,0x1C5C,0x1C5C,0xFA53,0x5843,0xD63A,0x152A,0xB621,0xDA31,0x9B3A,0xFB4A,0x9632,0x1132,0xED29,0xEC31,0x0C32,0xAC31,0x2B3A,0x6A42,0x4B4A,0xF262,0x9A63,0x5A4B,0x963A,0x3542,0x5542,0x7642,0x9742,0xF84A,0xF642,0x732A,0x542A,0x9421,0x3619,0x1831,0x1E74,0x1F7D,0x1F75,0x3E64,0x1B32,0x5C63,0x7E74,0x3F5C,0x1D3B,0x1A32,0xBD53,0x5D53,0x993A,0xD631,0x3932,0xFA31,0xBE5B,0x3E4B,0xDA3A,0x772A,0x152A,0xB319,0x5221,0x3219,0x9321,0xB321,0x9121,0xD019,0x4D11,0xD429,0x992A,0xD820,0xDE52,0xDF84,0xBF95,0xBE64,0xFA3A,0x7621,0x3831,0xDD5A,0xDF84,0x7F9D,0x1FA6,0x9E85,0x1954,0xD432,0xED18,0x1432,0xF621,0xF300,0xF200,0xF210,0x752A,0xED10,0x7832,0x962A,0xD421,0x7421,0x9421,0x132A,0xF021,0x8808,0x3110,0x7D63,0xFF84,0x3F85,0x7D64,0x9E84,0x3C5C,0x764B,0xB842,0x5A43,0x1A4B,0x365B,0x134B,0x5132,0xF552,0xB653,0x775B,0x7563,0xFA73,0x9D8C,0xBF7C,0x3F9D,0xBFAD,0x7FBE,0x9A8D,0x6B63,0x2B6B,0x2B6B,0x0A63,0x2B6B,0x2B63,0x0B6B,0xEA62,0x0A63,0xEA5A,0xEA62,0xEA62,0xCA62,0xC952,0xA95A,0xA95A,0xA85A,0xA852,0x8852,0x8952,0x684A,}, +{0x49AF,0xA7CF,0xC7CF,0xC7DF,0xC8D7,0xC8DF,0xC9E7,0xCAE7,0xCAEF,0xCBEF,0xEAF7,0xCAF7,0xCAF7,0xCAF7,0xCAF7,0xEBF7,0xCCF7,0xCCFF,0xEBF7,0xCAF7,0xCAF7,0xCAFF,0xEBF7,0xC9EF,0xC7E7,0xC7DF,0xE6D7,0xC7D7,0xC7D7,0xC7C7,0x6AAF,0xEB9E,0x4B86,0xCB75,0x8D65,0x0C55,0xCB54,0xEB4B,0xEC43,0x4B43,0xEB42,0xED3A,0xEF42,0x8F3A,0xB042,0xD34A,0xF742,0xB942,0x7A42,0xDD4A,0xDD52,0x3E4B,0x7F63,0xDF63,0x3F7C,0x1F74,0xDD63,0x1953,0x9542,0x533A,0x533A,0x113A,0x5042,0xB042,0xB24A,0x5242,0x543A,0x3532,0xF639,0x573A,0x1542,0xB54A,0x194B,0x194B,0xB642,0x1653,0xD54A,0x164B,0xF64A,0x7342,0x9242,0x9142,0x6F42,0x2D42,0x0F3A,0x114A,0x744A,0x554A,0x544A,0x1342,0x133A,0xD241,0xB529,0x3A3A,0x7D63,0x3E74,0xBF8C,0xDF84,0xDF84,0xBF84,0xDF7C,0x3F64,0x9C53,0x993A,0x7311,0xD608,0x3619,0xB721,0xD629,0x7221,0x4F21,0x0C11,0xEA18,0x4931,0x2C52,0x8C52,0xEC41,0x1042,0x7942,0xBE6B,0x3D64,0x7A53,0x1532,0x7221,0xF539,0xB842,0x9742,0xD429,0xF529,0x3632,0xF321,0x1211,0x7831,0x1D5B,0xDF7C,0x1F8D,0x1E7D,0x9B4B,0x5819,0xB931,0x7B3A,0x9C3A,0xF921,0xBA29,0xFC42,0xD92A,0x372A,0x793A,0xD721,0x9829,0x5B3A,0xBA3A,0x792A,0xB82A,0x3632,0x1632,0x141A,0xD219,0xB121,0xD021,0x8E21,0x8E21,0x3319,0x9B32,0xF929,0x7D52,0xFF8C,0x5F85,0x7F64,0x1B33,0x5219,0x9420,0xBC5A,0x1F8D,0x9F95,0x7F95,0x1F96,0x3F75,0xFA43,0x9019,0x373A,0x561A,0xB000,0xCE08,0xD421,0x8D11,0x9229,0x752A,0x573A,0x7522,0x8F10,0xB331,0x552A,0x5432,0xD011,0x7520,0xBE6B,0x5F74,0x3F85,0x1E64,0x3F7D,0x3A5C,0x353A,0xFB5B,0xB93A,0xD342,0x4F42,0xAB31,0x314A,0x755B,0xB563,0x536B,0x976B,0xDC6B,0xBF84,0x9F84,0x9E84,0xDFAD,0x7B8D,0x8C63,0x4C63,0x2B63,0x2A6B,0x2B6B,0x2963,0x2A63,0x0A63,0x0A63,0x0A6B,0xEA5A,0xCB5A,0xEA5A,0xE952,0xC95A,0xA95A,0xA95A,0xA95A,0xA852,0x8952,0x6852,}, +{0xC8A6,0x67B7,0xC6C7,0xC6D7,0xC7D7,0xE8E7,0xE8E7,0xE9E7,0xCAE7,0xCBEF,0xEAEF,0xCAF7,0xC9F7,0xC9F7,0xC9F7,0xEAEF,0xC9EF,0xE9F7,0xCAF7,0xCAF7,0xCAF7,0xCAF7,0xCAF7,0xC9EF,0xC8E7,0xC8E7,0xC6E7,0xC7D7,0xE8DF,0xC8BF,0x48A7,0x8986,0x097E,0xEB6D,0x8B55,0x2A4D,0xCB4C,0x4A4C,0x0B44,0x6B3B,0x6C43,0x2D43,0x5043,0xF13A,0xB03A,0x923A,0x9342,0x1232,0x153A,0x163A,0x373A,0x393A,0x7B3A,0xBD42,0xBD4A,0x9B4A,0x7942,0x563A,0x1232,0xF129,0x1132,0x4F32,0xB132,0x6F32,0x9232,0xF43A,0xF53A,0x543A,0x6F11,0x6E11,0x8F21,0xB229,0x5842,0xFA52,0x1853,0x7A53,0x3853,0x394B,0x584B,0x164B,0xF54A,0x9242,0x3032,0x0C32,0x4E42,0x6E42,0xED31,0x8E31,0x4B29,0x4A29,0x0A29,0x0B21,0xCB18,0x8F20,0xF320,0x5921,0x9B29,0x7D42,0xBD4A,0xBE4A,0xBD42,0x3B32,0x5A3A,0xD621,0x5111,0xF210,0xF308,0x3519,0x7619,0xD421,0x8F21,0xF021,0x0E32,0xAC39,0xAD31,0xB131,0x8F21,0x9119,0x5A42,0xBE63,0xBF63,0x9F7C,0x3F95,0xFC74,0x1743,0x7419,0xB629,0x373A,0x162A,0xB321,0x5432,0x343A,0x5119,0xF518,0x9A21,0xBC52,0xBF63,0x3F6C,0x9C4B,0x9832,0x1322,0x1211,0x1311,0x3419,0xF418,0x9729,0x5932,0x3732,0x762A,0xF631,0xFC52,0xFB42,0xBB3A,0x9932,0x7832,0xF731,0xF529,0xD421,0xF319,0xB021,0x4D19,0xB021,0x7119,0xD110,0x7B3A,0xFD42,0x5D4A,0x7F74,0x9F74,0x7F64,0x1B2B,0x5211,0x3218,0xF941,0x5E7C,0x5F95,0x5F8D,0x3F85,0xFF7C,0x3C54,0x9532,0x5722,0x3109,0x8B08,0xED18,0x512A,0xAA18,0x3432,0xD339,0x572A,0x342A,0x9039,0xF74A,0xF829,0x9932,0xB732,0x3729,0xBE6B,0x3F6C,0x5F6C,0xDF7C,0xFE85,0x332A,0x9C53,0xFA4A,0x3232,0xED31,0x8731,0x6B31,0xF14A,0xF052,0xF15A,0x536B,0xD863,0x5E7C,0x5E7C,0x3E6C,0x7F9D,0xDE95,0xCF63,0x4B63,0x4A63,0x4A6B,0x0B6B,0x4A63,0x2B63,0x2B63,0x0B63,0x0963,0x0A63,0xEA5A,0xE962,0xCA5A,0xCA5A,0xC952,0xA95A,0xA95A,0x8952,0xA952,0x8952,}, +{0x078E,0xC79E,0x66A7,0xC7B7,0xE7BF,0xC9CF,0xC9D7,0xE9D7,0xCAE7,0xCBE7,0xCBE7,0xEBEF,0xCAF7,0xE9EF,0xE9EF,0xE9EF,0xC8EF,0xE7EF,0xC8F7,0xE8F7,0xE9F7,0xC9F7,0xE9F7,0xC8EF,0xC8EF,0xC8E7,0xE7DF,0xC8E7,0xC9CF,0xA8B7,0x49A7,0xA986,0x6A7E,0x0B6E,0x8955,0x4B65,0xAA44,0x6B4C,0x2D44,0xAD43,0xCE4B,0x8E4B,0xD253,0x944B,0x324B,0x3243,0xD142,0x4F22,0x122A,0xF229,0xB229,0xB329,0xB421,0xB629,0x9631,0xB429,0xB429,0xB329,0x9021,0xB021,0x713A,0xF773,0xBC84,0xFC84,0xFC74,0x9C6C,0x7D6C,0x3D6C,0xDB53,0xF95B,0x5964,0x9B6C,0x1D75,0xFE7C,0x1E85,0x5F85,0x1E85,0x1E7D,0xFE7C,0x9D6C,0xDB5B,0x3653,0xD232,0xD042,0xB14A,0x8F42,0xEE41,0xCD29,0x6B31,0x4929,0x2721,0x2619,0x0611,0xA618,0x8A18,0x1121,0x7419,0x5719,0x3719,0x5719,0x7619,0xB719,0xD721,0x7419,0x4F19,0xED10,0xCC10,0xCF08,0xD110,0xEF20,0x0C11,0xED18,0x973A,0xDD7C,0x5D85,0xFE7C,0x7D64,0x7B4B,0x1B43,0x392A,0x7929,0x3A42,0x7E63,0xBF7C,0xFF7C,0x5C64,0x142A,0x7219,0xEF08,0x3221,0xB029,0xD031,0x9129,0xB521,0x7A32,0x7A3A,0x5D3A,0x3E4B,0xFC42,0xB832,0xD521,0x3532,0xB331,0x9121,0x4E19,0x2D19,0xEE18,0xF118,0x9521,0x782A,0x3421,0x7631,0xF729,0x3621,0xF931,0xFA3A,0xB832,0x172A,0xD421,0x9019,0x4E19,0x0C19,0xCD18,0xB111,0xD018,0xB831,0x9E53,0xDE4A,0xBF63,0x7F74,0x5F5C,0xFB32,0x9109,0x2D10,0x3420,0xDC5A,0xDF84,0x1F7D,0xFF7C,0x1F7D,0x9F64,0x783B,0xF311,0x2B09,0x6808,0x8D21,0x4919,0x8D29,0x323A,0x3532,0x1432,0x7119,0xED10,0xB018,0x9721,0x182A,0x5822,0x7929,0xBE42,0x9F5B,0x3F74,0x3F9E,0x3B5D,0x1A4B,0x5953,0x3232,0x0E32,0x4B3A,0x4829,0x2C3A,0x8E42,0x6E4A,0x1163,0xB66B,0xDA63,0x3D74,0x5E7C,0x7F95,0x1F9E,0xD674,0x6B63,0x4B6B,0x4B63,0x2B6B,0x2A6B,0x2A6B,0x2B63,0x0A5B,0x2A63,0x0A63,0xEA5A,0xEA5A,0xC95A,0xE962,0xCA5A,0xC952,0xC95A,0xAA52,0xA852,0x8952,}, +{0xE885,0xA78E,0x479F,0xA8AF,0xC7B7,0xE8BF,0xC8CF,0xC9CF,0xCAD7,0xCADF,0xCBE7,0xCBEF,0xCAEF,0xCAEF,0xC9EF,0xC9EF,0xC9EF,0xE9EF,0xC9EF,0xE9F7,0xC9F7,0xC9F7,0xC8EF,0xC8F7,0xC9F7,0xC9E7,0xC9DF,0xC8D7,0xC6BF,0x87AF,0x07A7,0xA88E,0x6A7E,0xEB6D,0x8B5D,0x0A55,0xCA3C,0x8C54,0x4D4C,0xEE43,0xCE4B,0x3154,0x766C,0xD65B,0x344B,0xD242,0x914A,0x903A,0x3232,0x102A,0xAE21,0x4E21,0x4F19,0x5019,0x1029,0x2F19,0x4E19,0x2F11,0x2D19,0x0B19,0x8C29,0x9452,0xFE83,0x7F84,0xFF94,0x3F9D,0x5F9D,0x3F9D,0x1F85,0x7F9D,0xBFA5,0xDFAD,0xFFAD,0xDFAD,0xDFA5,0xFFAD,0xDFA5,0xBFA5,0x9F9D,0x5F8D,0xFD63,0x1853,0xD642,0xF552,0x744A,0x523A,0xCF39,0x8F29,0x6A29,0x4A29,0x4821,0x6721,0x4621,0x0421,0xC618,0xCB20,0xEE18,0x9108,0xB208,0xF310,0xD310,0xB210,0xF210,0x3011,0x4E11,0x4D19,0x6D19,0x6E19,0x4E19,0x2B09,0x0A11,0xC910,0xF118,0x1A42,0x7E8C,0x9FA5,0xFFAD,0xBF95,0x9E74,0x1B4B,0x372A,0x9832,0x9C42,0x9D53,0xDE63,0xFE63,0x3A43,0x752A,0xB121,0x9121,0xD121,0x753A,0x763A,0xF731,0x9B32,0x3832,0x9829,0x1A32,0xDA3A,0x372A,0x762A,0x1632,0xB329,0x3019,0x0D19,0x2B21,0x0A11,0x2911,0xAB08,0xF010,0xB529,0xB521,0xB721,0xF919,0xF819,0x5819,0x9819,0x192A,0xBA32,0xB632,0x532A,0x7232,0x2D22,0x0A11,0xCD10,0x762A,0x9621,0x1821,0x9E42,0x1F53,0xBF5B,0xFF53,0xF93A,0x2E11,0x8C10,0x2F10,0x1829,0x7D63,0xBF74,0xDF7C,0x9F6C,0xDC4B,0x7633,0xAC19,0x8508,0x6818,0xAC32,0xAC29,0xEF39,0x3242,0x7442,0xCF21,0x9019,0x0E11,0xD010,0x7521,0xD521,0x9421,0x9821,0x9C3A,0xFF6B,0x5F95,0xBF96,0x3A54,0x5A63,0x7753,0xCD29,0xEE39,0x6829,0x0A3A,0x2C42,0x2C42,0x8E52,0x1363,0xD863,0x3D74,0x5D6C,0x1F8D,0xFFA5,0x3A85,0x8B63,0x6B6B,0x2B63,0x4B6B,0x4A6B,0x4B63,0x0B73,0x4A63,0x0B63,0x0A5B,0x0A63,0xEA62,0xEA5A,0xE95A,0xEA52,0xC95A,0xC95A,0xA952,0xC85A,0xA952,}, +{0x887E,0x298F,0xC8AF,0xC8C7,0xC8BF,0xC9CF,0xC9D7,0xEAD7,0xC9DF,0xCADF,0xEAE7,0xC9E7,0xCAEF,0xCBF7,0xCAEF,0xCAF7,0xCBF7,0xCAF7,0xEAF7,0xEAF7,0xCAFF,0xCAF7,0xE9F7,0xCAF7,0xCBEF,0xCCE7,0xCCE7,0xCCDF,0xECCF,0xCBC7,0xC9AF,0x8997,0x2A8F,0xAD86,0xE96D,0x4B65,0xEB54,0xAE5C,0x7054,0x0F4C,0x114C,0x345C,0x986C,0xD853,0x354B,0xD032,0xD242,0x9242,0x2F32,0xCF29,0x6E21,0x2F19,0x2E19,0x0E19,0xEC20,0x0B09,0xEB10,0xEB08,0xCA10,0xC810,0xC710,0xCA10,0xB341,0xFA62,0x9E73,0x9F5B,0xBF5B,0xBF63,0xFF6B,0x1F74,0xFF73,0x1F7C,0x5F7C,0x1F6C,0x3F74,0x1F6C,0xFF6B,0x3F74,0x1F6C,0xDF63,0x3D4B,0x983A,0x9842,0xF752,0xB642,0x9542,0xF331,0x9131,0x8C29,0x6A21,0x6921,0x8821,0x6729,0x2629,0x0521,0x0621,0x6829,0x0C19,0x5219,0xB419,0xB521,0xF419,0xD619,0x9419,0x7111,0x5111,0x9521,0xD521,0xF529,0xD119,0xEE21,0x0E2A,0x112A,0x9519,0x9B21,0x5E42,0xBF73,0x7F84,0xFE6B,0xDA42,0x7832,0xB83A,0x7A3A,0x3A32,0x5B42,0x9B42,0xFA42,0xB83A,0xF329,0x8F29,0xB129,0xF429,0xB429,0xB529,0xD521,0xB329,0x1319,0x1421,0xB529,0x3121,0xF521,0x172A,0x9521,0x9229,0x3022,0x5232,0x0E22,0x4A11,0x2911,0x4D11,0x2F21,0x9229,0xF721,0xF921,0x9A2A,0xB92A,0x5822,0xD619,0x7519,0xF118,0x1019,0xB229,0x7342,0x933A,0xF121,0x7021,0x9219,0xF621,0x7729,0x7C42,0xFF3A,0x3F4B,0xBA3A,0xF419,0x6E11,0x0C11,0x4B08,0x3220,0x9A39,0xDE63,0x3F64,0x1C43,0xB73A,0x102A,0xEA21,0x4518,0x6C2A,0xEA31,0x2D3A,0xD039,0x7242,0xCE29,0x3019,0x3219,0x7319,0x7119,0x2F21,0x1222,0x5219,0x1A2A,0x5E5B,0x5F7C,0x3F9E,0xDD7D,0x9752,0x5B6C,0xCC29,0xAC39,0x2731,0xA839,0xE939,0xEA41,0x0B42,0xAF52,0xB65B,0x5E6C,0xBE7C,0x1F85,0xFFAD,0x3D85,0x8D6B,0x4B6B,0x4A63,0x6A6B,0x4A6B,0x2B63,0x2B6B,0x2B63,0x2A63,0x2A63,0x2A63,0x2A6B,0xEA62,0xEA5A,0xEA5A,0xC95A,0xCA5A,0xC952,0xA85A,0xA952,}, +{0x678F,0xC99F,0xE9B7,0xC9CF,0xCACF,0xCAD7,0xCADF,0xCADF,0xC9E7,0xCAEF,0xEAF7,0xE9EF,0xC9F7,0xC9F7,0xE9EF,0xC9EF,0xC9EF,0xC9E7,0xCAE7,0xEBE7,0xCBE7,0xCDEF,0xCCEF,0xCCEF,0xEDEF,0xCCE7,0xCBE7,0xCCDF,0xCCD7,0xEDCF,0xCCBF,0xCDB7,0xF2BF,0xB5C7,0xED96,0x2E86,0x7165,0xF364,0xB46C,0x934C,0x7454,0xB95C,0xBA6C,0x584C,0xD753,0x364B,0xF342,0x912A,0xED29,0xAD21,0x2C19,0xCD10,0xEC10,0xEC08,0xCC18,0xCB08,0xCC10,0xAB10,0xAA08,0x8810,0xA510,0xA508,0xC708,0x2D21,0x9439,0x3A3A,0xDD42,0xFE42,0x1E4B,0xBE4A,0xDE52,0x3E5B,0x5E63,0x1E4B,0xFD52,0x9D4A,0x7C4A,0x7C4A,0x5A3A,0x5A3A,0xF831,0x9621,0x3429,0xD220,0xCF10,0xAE18,0xCE18,0x2D19,0x4C19,0x8A21,0x8921,0xAA29,0x8821,0x6521,0x2521,0xA931,0xAF29,0xB419,0x7719,0x5611,0x1509,0x9319,0x7732,0x1C3B,0x1C33,0x5B43,0xFC3A,0x7932,0xF721,0xF319,0x3132,0xF752,0x9A53,0xD932,0x9911,0xBA19,0xDC29,0x1C32,0xDA31,0xB729,0x5319,0xF731,0x3A32,0xBA3A,0x9A3A,0xDA3A,0xB942,0x783A,0x773A,0x374B,0x2E2A,0xF231,0xB432,0x132A,0xD429,0xD329,0x1432,0x3121,0xF010,0xCD10,0xED10,0x3221,0x142A,0xF329,0xB119,0x1319,0x132A,0x1122,0xCF19,0x6E19,0xED18,0xCC18,0xF118,0xB411,0x7621,0xD821,0xF721,0xB729,0xF721,0x9732,0x7432,0x0E19,0xB129,0x102A,0xAF19,0xAF21,0x6D21,0x6F21,0x5329,0xFA39,0x3B32,0x1B32,0x7B3A,0xD632,0xD021,0xB021,0x732A,0x321A,0x4F11,0x7428,0x5942,0x3B3B,0x352A,0x4E21,0x2C32,0x0822,0xAA29,0xEA31,0x6D3A,0x6D31,0x303A,0x4C21,0xCD10,0xF110,0xF210,0x5111,0x4D11,0x2F19,0x552A,0xB521,0x7E3A,0xBF63,0x5F8D,0x9F9E,0xF853,0x7D74,0xD13A,0x8831,0xC839,0x2A42,0xA739,0x6931,0xCB39,0xD04A,0xB35A,0x5E84,0xFD6B,0x1E8D,0x3FAE,0xDF9D,0x306C,0x4B6B,0x4B6B,0x2B6B,0x4B6B,0x4A63,0x4B6B,0x2B6B,0x4A6B,0x4A63,0x0A63,0x0A63,0x0A5B,0xE962,0xCB5A,0xEA52,0xEA5A,0xC95A,0xA95A,0x895A,}, +{0xCBBF,0xEBCF,0xEBD7,0xCBDF,0xCBE7,0xCBEF,0xCBEF,0xCAEF,0xCAF7,0xC9F7,0xC9F7,0xCAF7,0xCAF7,0xC9F7,0xC9F7,0xCAF7,0xCAF7,0xC9EF,0xC9E7,0xC9E7,0xCBE7,0xEDEF,0xCEEF,0xCFEF,0xCEEF,0xCCE7,0xCCE7,0xEBDF,0xCBD7,0xCBBF,0xCCAF,0xADAF,0x8FA7,0x5097,0xB096,0xB37D,0x3A65,0xBC54,0xBD54,0x9D4C,0xBE6C,0x1E7D,0x1F85,0xFE74,0xBD74,0x5C64,0xF953,0x3643,0x932A,0xCE21,0x4B19,0x0A11,0xA910,0xE810,0xAA08,0x8908,0x8800,0x8810,0x6808,0x8510,0xA410,0xA408,0xA610,0xE910,0x0C11,0x2F11,0x7429,0xDA39,0x3C3A,0x1A32,0x192A,0xD829,0xB721,0xB519,0xB619,0xB529,0xD629,0x1932,0xD739,0x5429,0xF218,0x6F11,0x712A,0xD432,0x3543,0x1743,0xD532,0x532A,0xEF29,0xAB29,0xCB29,0x0A32,0x0A32,0x2B3A,0xEE21,0x152A,0x7A32,0x9C2A,0xDB32,0x3C43,0x9C43,0xFA4A,0x1E64,0xDF7C,0x3F8D,0x5F8D,0x1F8D,0x3E6C,0xFA42,0xB63A,0x533A,0x1A42,0x3F7C,0x3F8D,0x3D64,0x7B32,0xFA21,0x5942,0x3943,0x352A,0x4F21,0xB010,0xB621,0x793A,0xDA42,0xFA42,0x7942,0x194B,0x383A,0xB94A,0x1C85,0x7A6C,0x183B,0x172A,0x372A,0xB321,0xD331,0x5129,0xF221,0x122A,0xB019,0x9019,0x3232,0x5532,0xB82A,0xF731,0x1532,0x7329,0xF421,0x5532,0xF029,0x2B19,0xB019,0x3522,0x9832,0xBA32,0x9922,0x372A,0x172A,0xF521,0x132A,0xF019,0x9021,0x8F19,0x4F21,0xAF29,0x8B29,0xCB21,0xAC19,0x2E21,0x9331,0x3529,0xB629,0x762A,0xB23A,0x7332,0x3422,0xB221,0xD121,0xF221,0xF021,0x6F21,0x9021,0x6C21,0x2921,0x4A3A,0xC829,0x0B32,0x0A32,0x6A29,0x8D29,0x4B21,0x2D19,0xEC10,0xCD18,0x0E09,0x4B11,0x4B11,0x3019,0xD419,0x5829,0x5F53,0xDF74,0x5F9E,0x3D86,0xDA6B,0x385C,0x8839,0x6A52,0x4F63,0xC839,0x4829,0x6F39,0x1B8D,0xD552,0x3E84,0x1A64,0x9D84,0x3FB6,0x1FA6,0x7364,0x6B6B,0x6A6B,0x4B63,0x4A63,0x4B6B,0x4B6B,0x2B6B,0x2A6B,0x2B63,0x0A63,0x0B63,0x0963,0xEA5A,0xEA62,0xCA5A,0xC95A,0xA95A,0xC95A,0xA95A,}, +{0xCCD7,0xCCD7,0xCBDF,0xEBE7,0xCAEF,0xCAEF,0xC9EF,0xE9EF,0xC9EF,0xE9F7,0xCAF7,0xCAF7,0xCAF7,0xC9F7,0xC9F7,0xCAEF,0xCAF7,0xCAF7,0xC9EF,0xE8EF,0xC8EF,0xC8EF,0xCBEF,0xCEEF,0xCEE7,0xCCE7,0xEBDF,0xE9D7,0xC8CF,0xA7B7,0x28A7,0xCA9E,0x6C86,0x2C7E,0x6D75,0xD15C,0x3854,0x1C64,0x3D54,0x3F54,0x3F64,0xBF7C,0x1F85,0xFF8C,0xFF8C,0xFF8C,0xBF7C,0x3E64,0x9A4B,0x723A,0xAD19,0x2B11,0x0911,0x0909,0xCA08,0xCA10,0xC810,0xA710,0xA808,0xA710,0xA710,0x8608,0x8808,0xC910,0xEB08,0xEC10,0xEC10,0xEE10,0x9210,0xF418,0x5521,0x9629,0x9521,0x7421,0xF318,0xD120,0x3111,0x1111,0x4F19,0x3222,0x1954,0x3D7D,0xBF9D,0x3F85,0x1F85,0xBF74,0xDD5B,0x1643,0x5332,0x0E32,0xEC29,0xCC29,0x8C29,0x3132,0xF93A,0xFE5B,0x3F64,0xBF74,0x9F7C,0x9F74,0x7E53,0x5A3A,0x9B29,0x7E3A,0xFF5A,0x3F5B,0xFE52,0x7D42,0x9831,0x9421,0x7019,0x1419,0x5B19,0x5E3A,0xBE52,0x1B3A,0xB819,0x7942,0x9E84,0x5E7D,0x5964,0x952A,0xB832,0xFC4A,0x5F74,0xDF7C,0x9A53,0x573A,0x1A4B,0x783A,0xB529,0xDD73,0x5F7D,0x1D5C,0x5A32,0xB83A,0xF631,0xB321,0xD521,0xF521,0x1532,0x1432,0xDB63,0x7E8D,0x7E85,0xDD74,0x3D64,0xBD53,0xD93A,0x573A,0xB429,0xF531,0xAE19,0xCD18,0xF218,0xD829,0x392A,0x372A,0xD929,0x362A,0x562A,0x9722,0x5532,0x3322,0xF121,0xEF29,0xAD29,0xEB29,0xEC29,0xAA29,0x2A29,0xCA18,0x8C18,0x9021,0x903A,0xEF29,0x9021,0x1532,0x7532,0xB019,0xCF21,0x703A,0xCD29,0xAA21,0xCA21,0x2829,0x2A32,0x2A3A,0x2B3A,0x4829,0x6C31,0xCC29,0x2C21,0xCC18,0x8810,0xCA18,0x6B19,0xAE11,0x2B19,0x5019,0x7521,0x3C3A,0xFF63,0x7F8D,0x3FB7,0x386C,0xFC84,0x6C42,0x4F6B,0x3163,0x6A42,0x4829,0x2F31,0x1D9D,0x175C,0xDC7B,0x185C,0xDD73,0xFFAD,0x3F9E,0x776C,0x8D6B,0x6A63,0x4B6B,0x4B6B,0x2B6B,0x4B63,0x2B6B,0x2B63,0x2B63,0x2A6B,0x0A63,0x0A63,0x0A5B,0x095B,0xEA5A,0xEA5A,0xC95A,0xC95A,0xA952,}, +{0xEBD7,0xEBD7,0xEAD7,0xCADF,0xC9E7,0xC9E7,0xE8EF,0xC8EF,0xE8EF,0xC9F7,0xCAF7,0xCAF7,0xCAF7,0xCAF7,0xCAF7,0xCBF7,0xCAF7,0xC9F7,0xC9F7,0xE9F7,0xE8F7,0xC7F7,0xE7EF,0xEBEF,0xCCEF,0xCBEF,0xCADF,0xE8D7,0xC8C7,0x67BF,0xE69E,0x278E,0x8875,0x0865,0x6A5C,0x2E3C,0xB243,0xB643,0xD84B,0x9C4B,0x9D4B,0xBF5B,0xDF6B,0xDE63,0xDF63,0xDF63,0x5D53,0x7E5B,0xFD4A,0x7642,0xD021,0x8E21,0x6C19,0x2C11,0xED08,0xCC08,0xAA00,0xAA08,0xAA08,0x8908,0xAB08,0xAC08,0xEC08,0x0D19,0x2E19,0x2C11,0x0A11,0xCB10,0x8A10,0x8A00,0x6A08,0x6B08,0x8D08,0x8C10,0x8C08,0x0E19,0x8F21,0xB542,0x5A5B,0x3E74,0xDF8C,0x5F9D,0x5F95,0xFF8C,0x5F7C,0x7E5B,0xDD42,0x382A,0xB421,0xF319,0xF319,0xB121,0x0F19,0x5031,0x9931,0x3D42,0x5E42,0x7E42,0x1E3A,0x7D29,0x1B11,0xF608,0x7208,0x5308,0x5508,0x3508,0x5308,0x3008,0x4D08,0xED08,0xCB08,0x0C11,0x1111,0x1821,0x3929,0x7821,0x1419,0x3519,0xFB31,0x5F63,0xDF8C,0x9F8D,0x7F6C,0xDF5B,0x5F74,0xBF7C,0x1F85,0x9C6C,0x353A,0xDA4A,0x162A,0x1732,0x1E6C,0x3E7C,0xDE63,0xDB32,0x192A,0xBA3A,0x1B3B,0xB932,0x5932,0x7D6C,0x9D5B,0xDD73,0xDF84,0x5F95,0x9F9D,0xBF8D,0x1F7D,0x7F64,0x3C43,0xB732,0x342A,0xD029,0x0E21,0x3219,0x1632,0xF731,0xF831,0xD721,0xD621,0xB429,0xB321,0xB221,0x9221,0xCF29,0x8D29,0x2D3A,0x733A,0xF53A,0xF53A,0x9643,0xB44B,0x4C19,0x0E21,0x122A,0x2F22,0xCB10,0xAE18,0x0E19,0xAF19,0x2C21,0x4B21,0x6929,0x0621,0x6729,0x2829,0xCA31,0xEA39,0x6729,0x4829,0x4B29,0xAC21,0xC918,0xC918,0xC910,0xC818,0x4E19,0xD119,0xAD19,0xB429,0x9721,0xFE4A,0x5F6C,0x9F9D,0xDA8D,0xFA6B,0xD24A,0x8D52,0x1574,0x4C3A,0xEA39,0x0C29,0x9A73,0x7B95,0x395B,0x9974,0x3A4B,0x9FA5,0xFFA5,0xBB6C,0x3474,0xAD63,0x4B6B,0x4B6B,0x2B6B,0x4B6B,0x4B6B,0x6B6B,0x2A6B,0x2B63,0x0A6B,0x0963,0x0A5B,0x0A5B,0xEA5A,0xEA5A,0xCA5A,0xC962,0xA95A,}, +{0xCCDF,0xCBDF,0xCAE7,0xC9E7,0xE8EF,0xE8EF,0xC8EF,0xE7EF,0xC8F7,0xC9F7,0xC9F7,0xCAFF,0xCAF7,0xCAF7,0xC9F7,0xEAF7,0xC9F7,0xC9F7,0xE9F7,0xC9F7,0xC9F7,0xC9F7,0xCAF7,0xCBF7,0xEBEF,0xCBE7,0xCAE7,0xCADF,0xCAD7,0x88C7,0xC7A6,0x078E,0x6A7D,0x8A64,0xCB4B,0x0F4C,0xCF3B,0xB13B,0xB543,0x7843,0xF942,0xBA32,0x9A3A,0xBA3A,0x9B32,0x3932,0x583A,0x5A42,0x183A,0xF431,0x132A,0xD229,0xD131,0x8F29,0x4E19,0x0D09,0x0A01,0xAA08,0xAA00,0xAB00,0x8C00,0xCD00,0xED08,0x3021,0x5121,0x4F19,0x4B11,0x0B09,0x8810,0xA910,0xA810,0xC808,0x0911,0xEA08,0x2D11,0x9009,0x5019,0x9429,0xF831,0x1B3A,0x3C3A,0xBD42,0x9D3A,0x5D3A,0xBC31,0xFC21,0xDB21,0xB921,0xB721,0x3619,0x1511,0xF218,0xCF08,0x8C10,0x7010,0x5308,0x7608,0x7808,0x7808,0x9708,0xD608,0x9108,0xAF00,0x8C00,0x6A00,0x4800,0x2908,0x6908,0x8A00,0xA910,0xE810,0x8811,0x4A11,0xCC18,0x8E10,0x8D10,0x6B10,0x3221,0xB821,0x7A21,0x5D4A,0xBE63,0x5F74,0xFE42,0x1F6C,0x9F7C,0x9F74,0xFF7C,0xBE6C,0xD742,0x783A,0x9742,0x1E8D,0xFF9D,0xFF95,0xBF6C,0x1F54,0x1C43,0x5C4B,0x9D53,0x3D43,0xBB3A,0x5B3A,0x5B32,0x3D53,0x7E6B,0xFE73,0xFF8C,0x5F8D,0x9F8D,0x5F7D,0x7E6C,0x3B3B,0x1332,0xB029,0xEF21,0xF220,0xB529,0x372A,0xB629,0xD629,0xD429,0x9319,0x9111,0x5111,0x8D21,0x8D21,0x8D29,0x2F21,0x5229,0xB531,0x5229,0xD329,0xD732,0x7B43,0xF52A,0x9319,0x521A,0x2C11,0x6A18,0x8B08,0x6A08,0xA818,0x2721,0x8729,0xE831,0xA729,0x2721,0x2729,0x2529,0x0521,0x0721,0x0819,0xC718,0x0911,0xE910,0xE818,0x0C19,0x1422,0x3422,0xF019,0x7629,0xFA21,0xFE52,0x5F74,0xDE95,0x1A6C,0x9653,0x316B,0xF884,0x8F42,0x145B,0x324B,0xBB63,0xBE9D,0xBA5B,0x7C74,0x3743,0x3F9D,0x3FAE,0x7E8D,0x3C95,0x316C,0x6C6B,0x4B63,0x2B6B,0x4B6B,0x4B63,0x6A6B,0x2B6B,0x0B63,0x4A63,0x2A63,0x2A63,0x0A63,0xEA62,0xEA5A,0xCA5A,0xEA62,0xC962,}, +{0xCBE7,0xEAE7,0xC9E7,0xC9EF,0xC9F7,0xC9F7,0xE8F7,0xC8F7,0xC9F7,0xCAF7,0xE9F7,0xC9F7,0xC9F7,0xC9F7,0xE9F7,0xC9EF,0xE9F7,0xC9F7,0xC9F7,0xC9F7,0xC9F7,0xC9F7,0xCAF7,0xCAF7,0xCAF7,0xEBEF,0xCAEF,0xEAEF,0xC9DF,0xA8D7,0xE7B6,0xE695,0x0A75,0x2D54,0xEE43,0xD343,0xD44B,0x1654,0x184C,0x773B,0xD63A,0xD642,0xD632,0x562A,0xF519,0xD519,0xB319,0x9219,0x5111,0xAF21,0x133A,0x153A,0xF229,0x9031,0xF231,0xF121,0x302A,0xF019,0xB309,0x7311,0x5401,0x9509,0xF719,0x763A,0x343A,0x1122,0x8E19,0x0C09,0xAA10,0xC708,0xC708,0x0A19,0x6E21,0xF321,0x5632,0xB832,0x9632,0x5632,0x3422,0xF621,0x5621,0x1611,0xD510,0x9510,0xB610,0xB510,0x9208,0x7000,0x4E08,0x4E08,0x2D08,0x8D00,0xAE08,0xAF08,0xD000,0x3301,0xD419,0x7521,0xD408,0x9300,0xB200,0x4F08,0x4D00,0x8900,0xC708,0x8710,0x6908,0xAA10,0xEC18,0x0C11,0x6D19,0x8A19,0x0A11,0x2819,0x2811,0x0719,0x0519,0x0E11,0x5721,0xDA21,0x7B21,0x7B21,0x9C29,0x9B21,0x7A29,0xDE6B,0xFF7C,0x7F74,0xFF84,0x7F6C,0x393B,0xF321,0xD941,0x9F84,0x1FAE,0x7FAE,0x3F96,0x1F7D,0x5E64,0x7C53,0x9D4B,0xFC3A,0xF921,0xF710,0xF818,0x5C42,0x7D5B,0xBE52,0x7F63,0x1F74,0xBF74,0xDF7C,0x5F6C,0x3A3B,0x1522,0x1322,0x0D11,0xCE18,0xD521,0xF421,0x5121,0xF118,0xF118,0x0F09,0xEF10,0x4D19,0x1222,0x322A,0xD321,0xF521,0x9219,0x0E11,0xEC10,0xAD18,0x1229,0x993A,0x3B33,0x142A,0x131A,0x4E19,0x4800,0x6908,0x6610,0x6418,0xA418,0xC520,0x6729,0xA629,0xA420,0x0521,0x0521,0xE620,0xE818,0xA810,0xCF10,0x0C11,0x0611,0xEB10,0xD629,0x772A,0xD631,0xF321,0xB819,0xFB29,0x7F4B,0xDD5B,0x9B7C,0x586C,0x9473,0x1EA6,0xD553,0xB752,0xB863,0x1E64,0x7FA5,0x1E85,0x1E8D,0xF85B,0x3FA6,0x1F8D,0x9F9D,0x7E95,0xF26B,0x8C63,0x4B6B,0x4A6B,0x4B6B,0x4B6B,0x4B6B,0x6A63,0x2B63,0x4A63,0x2A63,0x2A63,0x2A63,0x0A63,0x0A5B,0xE95A,0xEA5A,0xCA5A,}, +{0xCBDF,0xCAE7,0xCAE7,0xC9EF,0xC8EF,0xC8F7,0xE8F7,0xE9F7,0xC9FF,0xCAFF,0xEAFF,0xE9F7,0xC9F7,0xE9F7,0xEAF7,0xCAF7,0xC9F7,0xC9F7,0xC9F7,0xC9F7,0xC9F7,0xCAF7,0xCAEF,0xEAEF,0xCBF7,0xCAEF,0xC9EF,0xCBE7,0xC9E7,0x88D7,0xC7BE,0xC78D,0x6C6D,0xAE4C,0x903C,0x113C,0xB43B,0x974B,0x9A4B,0xBA4B,0x7953,0x564B,0xF64A,0x5442,0x3322,0x3322,0x3422,0xF119,0xF119,0xEF11,0xEF19,0xD121,0xF229,0xD129,0xB131,0xD231,0xF131,0x7342,0x184B,0xD942,0x792A,0x5B2A,0x7D2A,0xDC4A,0xDB52,0xB83A,0x3532,0xB221,0x2D11,0xEA08,0xC808,0x0B21,0x9229,0x1A3A,0x5C42,0x9D52,0x9D42,0x5A42,0x3832,0x9319,0xEF10,0x8E00,0x6D00,0x4D00,0x6F00,0x7000,0x4F00,0xCD08,0xAA00,0x8700,0x4808,0xAA00,0x3109,0xD619,0x7B32,0x9D32,0x9E3A,0xDB29,0x1609,0x9000,0x8C00,0x2900,0x2800,0x6600,0x6400,0x4308,0x4210,0x6508,0xEC20,0x0E19,0x0C19,0xE820,0x6A29,0x8729,0x4729,0x6721,0x4421,0xA710,0xCE18,0x3519,0xF818,0x3A19,0x9921,0xD621,0xB519,0x9921,0xFE52,0x1F74,0x5F6C,0x9F7C,0x5D64,0x9732,0xF721,0x9B29,0x9E52,0x5F8C,0xDF9D,0xBFB6,0x7F9E,0x5F7D,0xBE5B,0xDB42,0x782A,0xD619,0x5309,0xB208,0x5208,0x1210,0xB618,0x9A39,0x7D42,0x1E4B,0xDE42,0x9A2A,0x9932,0x793A,0x1622,0x1422,0x7319,0xF721,0xB421,0xD429,0x9229,0xF221,0x5522,0x7522,0x1422,0x3019,0xF621,0xFA3A,0xDB3A,0x1A33,0xD221,0x6A11,0xE910,0x6D10,0xF420,0x593A,0x9B5C,0x1233,0xD221,0x185C,0x975C,0x2C1A,0xC518,0xA418,0x6318,0x2529,0x0529,0xE420,0x0519,0xA418,0xA610,0x8708,0xAE08,0xAE10,0xC618,0xC918,0x5419,0x192A,0x172A,0x5511,0x1622,0xFA21,0xBC2A,0xF842,0x555B,0xB663,0x397C,0x7FB6,0x9E9E,0x153B,0xF54A,0xDD6B,0x1F95,0x5F9D,0x5F9D,0x5D8D,0x1FC7,0x1C75,0x5E74,0xDC53,0x555B,0x8B6B,0x2B6B,0x4B6B,0x4B63,0x4A63,0x2B6B,0x4A63,0x4A63,0x2A6B,0x2B63,0x2B63,0x2A63,0x0A5B,0xEA5A,0xEA5A,0xCB62,0xE95A,}, +{0xCAE7,0xEAEF,0xCAEF,0xC9EF,0xE8EF,0xE8EF,0xC8F7,0xC8F7,0xC9F7,0xC9FF,0xC9F7,0xC8FF,0xC9FF,0xEAF7,0xCAF7,0xCAF7,0xC9F7,0xC9EF,0xC9F7,0xC9F7,0xCAF7,0xCBF7,0xEBF7,0xCCF7,0xCBF7,0xCBEF,0xC9DF,0xC9D7,0xA7CF,0xE6AE,0x4696,0x6875,0xED74,0xEF64,0x115D,0xB25C,0x344C,0xD543,0x773B,0x9A4B,0x3B4B,0x1843,0xB83A,0x353A,0x3532,0x973A,0x9A42,0x983A,0xB83A,0xB83A,0x173B,0x1643,0xD53A,0x7442,0x312A,0xCF21,0x1022,0x5132,0x595B,0x5E7C,0xBC53,0xDB3A,0xBB42,0xBB3A,0x9C3A,0x7B3A,0xF621,0xF429,0x7119,0x0C11,0xC910,0xE908,0x8B08,0x9110,0xD510,0xD818,0xB718,0xD608,0x9508,0x9108,0x6C00,0x4B08,0x8C00,0x6B00,0x4C08,0x8D00,0x4E00,0x6D10,0x4B08,0x8808,0x2D11,0x7311,0xFA21,0xBB29,0x5C19,0x3C11,0xFB10,0xB808,0xB400,0x8F00,0xAB00,0xA808,0x8510,0x8408,0x6210,0x8108,0xA110,0x2419,0x2829,0x2821,0x2729,0x2521,0xE420,0x0321,0xC218,0xE320,0x4421,0x2421,0xC739,0xAC29,0x3021,0x1511,0x5821,0xB521,0x321A,0x521A,0xB821,0xFE31,0x9E42,0x1E53,0x7F95,0x5E85,0xB932,0xFA21,0x3B21,0x3E42,0x7F6B,0x7F84,0xBF9D,0x5FAE,0xDF8D,0x9E5C,0xDA32,0x792A,0x572A,0xD321,0x5322,0x111A,0xD119,0x7119,0x1319,0xF518,0x5619,0x9521,0xF418,0x7621,0x5932,0x9932,0x9A32,0x5932,0xF721,0x3853,0x5D85,0x3D7D,0xFD74,0x9E64,0x1D43,0x3C43,0xBA3A,0xBA3A,0x5B3A,0xBC32,0x5A2A,0x152A,0x1122,0xAE11,0x6910,0x4D18,0xB439,0x984B,0xD332,0xF639,0xBE7C,0x3E8E,0x1A6D,0x9543,0x0D2A,0x0521,0x0429,0xC310,0xE418,0xA410,0x8310,0x4608,0x4D08,0x6B10,0x8710,0xED10,0x7511,0xF931,0xD942,0xD419,0x1922,0xD311,0x9832,0x3432,0x1453,0xAF39,0xFB6A,0x3EAE,0x1FBF,0xD96C,0x924A,0xF762,0x3D74,0x3F95,0x5F95,0x1FB6,0x1FC7,0xBE85,0x1E64,0xFA5B,0xD373,0x6B63,0x6C6B,0x4B63,0x6B63,0x4B6B,0x2C6B,0x2B63,0x0C63,0x2A63,0x2A63,0x2A63,0x0A63,0x0A63,0x0A5B,0x0A63,0xEA5A,0xEA5A,}, +{0xC8E7,0xC9EF,0xE8EF,0xC8EF,0xC9F7,0xE9F7,0xC9F7,0xE9F7,0xC9F7,0xC9F7,0xC9FF,0xC9F7,0xC9F7,0xC9F7,0xC9F7,0xE9F7,0xC9F7,0xE9EF,0xC9F7,0xC9F7,0xC9EF,0xCAEF,0xCAF7,0xCBF7,0xEAEF,0xCAEF,0xCBEF,0xCADF,0xC8D7,0x47BF,0x86A6,0x466D,0x6854,0xEA3B,0x6A33,0x2A33,0x4F33,0x313B,0x343B,0x384B,0x1843,0x1643,0xB53A,0x1422,0xF619,0x182A,0x7B42,0xFB3A,0x7C4B,0xBC5B,0xFC5B,0xBC53,0x7B53,0x3A4B,0xB632,0x753A,0x3122,0x303A,0xB432,0xDE6B,0x1D64,0x9A4B,0x175B,0x3A4B,0x5C4B,0xFA32,0x9A32,0x3632,0x9119,0x2F11,0xEC18,0xED08,0xCC08,0xAB08,0x6C00,0x7000,0x9000,0x5100,0x6F00,0x4E00,0x6A00,0x6B08,0x6B00,0x6A00,0x4900,0x6A00,0x6900,0x4800,0x4808,0x6808,0x9419,0xBB32,0x7B32,0x1719,0x9500,0x7300,0x3200,0x1000,0x5000,0x6C08,0x6800,0x4308,0x8210,0x0419,0xA919,0x4719,0x6521,0x8629,0xA731,0x6529,0x2421,0xE629,0x8529,0xE629,0xE739,0x4429,0xA631,0xC739,0x0942,0x4B4A,0x0B32,0x4E21,0xF418,0x9319,0x9222,0xF02A,0xB132,0xD729,0xFA21,0x7921,0x3E7C,0xFFA5,0x7F85,0xBB3A,0x1922,0x1A22,0x1D32,0x5D42,0x7F6B,0x3F7C,0x9F95,0x7F8D,0x5D64,0x3C3B,0x1D3B,0xD832,0x1A3B,0x7632,0x9521,0x1522,0x372A,0xD631,0xD521,0xD529,0x3732,0x982A,0xF629,0x9621,0xF829,0x192A,0xD619,0x9629,0x5D63,0x7F7C,0x5F8D,0x5FA6,0x1F9E,0x5F8D,0xDF9D,0x1F9E,0xDF85,0xBF85,0xDD74,0xBD64,0xBB4B,0x5C43,0xFA53,0x5443,0xAD19,0x6B20,0x723A,0x9021,0x1121,0x1842,0x3D7C,0xBF8D,0x5D75,0xD753,0x1033,0xA410,0xC418,0x0421,0x0419,0x4408,0x2D00,0xEB08,0x8510,0x2C10,0xF919,0x3421,0x9932,0xF421,0xF619,0xD822,0x7221,0x1222,0xB442,0x4C31,0x1642,0x7E9D,0xDFB6,0xFEAE,0x6E3A,0xD352,0xF873,0x7E84,0x9E84,0x7EA5,0xDFC6,0x1F96,0xDE74,0xDD63,0x916B,0x8D6B,0x8E6B,0x4B63,0x4B6B,0x4B6B,0x4B6B,0x2B6B,0x4A63,0x4A63,0x2A63,0x2B6B,0x2B63,0x2A63,0xEA62,0xEA62,0xEA62,0xCA5A,}, +{0xC9E7,0xC9EF,0xE8E7,0xC7EF,0xC8EF,0xE8F7,0xC8F7,0xC9F7,0xEAFF,0xC9F7,0xCAF7,0xE9F7,0xC9F7,0xE9F7,0xE9F7,0xCAF7,0xC9F7,0xE9F7,0xEAF7,0xEAF7,0xCAF7,0xCBF7,0xCAF7,0xEAF7,0xCAE7,0xCAE7,0xEAEF,0xCAE7,0xC8DF,0xA8D7,0xC7AE,0xE685,0xC864,0xEA53,0xEB3B,0x8A23,0x4A23,0x2B1B,0xEF2A,0xD22A,0xD432,0xD542,0x733A,0x1222,0xD621,0x3A3A,0xDE42,0x9E4B,0x1F64,0x1F64,0x5F6C,0xFF6B,0xBD53,0x3C4B,0xF94A,0xB432,0x722A,0x1032,0xEF21,0xD842,0x7F84,0x9D7C,0xF96B,0xFB6B,0x1E64,0xFE5B,0x7C53,0xFA4A,0xB83A,0xF421,0xB219,0x9211,0x1009,0xEE08,0x6D10,0x6B08,0x8B00,0x6B00,0x8B00,0x2D01,0x3101,0x5101,0x5101,0xEF00,0xCB00,0xCA00,0xC800,0xC500,0xAA08,0x0D09,0x172A,0xDD52,0x7A21,0xB500,0x3000,0x4A00,0x4800,0x4700,0x2600,0x2300,0x4100,0x4008,0x6108,0x0521,0xAA29,0x6929,0x4619,0x8629,0x2A42,0x093A,0xAA4A,0xEE5A,0x6F63,0xF16B,0x4C4A,0x4E5B,0x2E5B,0x6E5B,0x8A42,0xA731,0xA831,0xA929,0xEE20,0x3311,0x9111,0xCE19,0x0C2A,0xB021,0xF821,0x9621,0xFA39,0xFF84,0x7F95,0xFF74,0x7A32,0xFC42,0x3D53,0xBF4B,0xDD42,0x9C42,0x9E84,0x5F8D,0x5F85,0x3F75,0x1F54,0x1D43,0x5E4B,0x1C4B,0x5C43,0x792A,0xDA42,0x5C4B,0x3B3B,0xF932,0x5732,0x9521,0xB621,0x783A,0x1B3B,0x772A,0xD521,0x9521,0x5729,0xBE42,0xFF52,0x7E6B,0xBF84,0x1F85,0x9F84,0x1F95,0xBF9D,0x5FAE,0x3FA6,0x5F9E,0x3F9E,0xBF95,0x5F85,0xBE85,0xDD5C,0xD74B,0x3343,0xF142,0xCD21,0xEE20,0x7118,0xB929,0x7D63,0xBE7C,0x7E7D,0xB74B,0xAA19,0x4719,0x6621,0xC418,0x2A08,0x0E2A,0x0A22,0xE910,0xF518,0x191A,0x1822,0x1B3B,0xDF64,0xDD43,0x1122,0x7422,0x533A,0x4E31,0xF64A,0xFC7B,0x1FA6,0xFFB6,0x956C,0x7152,0x7774,0x187C,0x7C6B,0x1F9D,0x5FBE,0x3FA6,0x7E64,0x5E85,0xD343,0x7774,0x1A7D,0xAB63,0x6A6B,0x4B6B,0x4B6B,0x4B6B,0x6B63,0x6B63,0x4B63,0x4A63,0x2A63,0x2B63,0x0A63,0x0A6B,0x0A5B,0x095B,}, +{0xC9E7,0xC9EF,0xC8EF,0xC7EF,0xC7EF,0xE7EF,0xC8F7,0xC9F7,0xC9F7,0xC8F7,0xC9F7,0xE9F7,0xEAF7,0xCAF7,0xCAF7,0xCAF7,0xC9F7,0xE9F7,0xCAF7,0xCAF7,0xCAF7,0xCAF7,0xCAF7,0xCAEF,0xEBE7,0xCAEF,0xEAEF,0xC8E7,0xC8D7,0x88CF,0x66A6,0x8685,0x686D,0x2865,0xC94C,0x2B3C,0xAB2B,0x8D33,0x2F33,0xEF32,0xD132,0xB232,0xB142,0x7232,0x353A,0x372A,0x7B3A,0xFE42,0x9F6B,0x1F64,0x3F7C,0xFF6B,0xDE63,0x9C53,0x3B53,0x174B,0x1453,0x5032,0xCE21,0xEF19,0xFA52,0x7F84,0x9D7C,0xF963,0x5D74,0x7F7C,0x1E6C,0x7D5B,0x5C53,0x993A,0x7932,0x1722,0xD619,0x5119,0xCF10,0xAC08,0xEB10,0xAD29,0xF952,0x3D6C,0xFD6B,0x5D6C,0x9D84,0xB92A,0x9211,0x0D11,0xE910,0x2B09,0xF008,0x1001,0xB108,0x7100,0x7200,0x3100,0x6E00,0x6B00,0x6900,0x6400,0x4308,0x6108,0x8110,0xA210,0xE310,0xE418,0x0621,0x2829,0x093A,0x083A,0x0942,0x4731,0x2A42,0x6931,0x4931,0x6831,0x8939,0x6D52,0xEC41,0xF47B,0x4F63,0x2D53,0x8A4A,0x8629,0xE720,0x1021,0x5111,0xEE08,0xC808,0xA808,0xCF18,0x9421,0x1511,0xBD4A,0x7F74,0x7F74,0x3D43,0x3A22,0x7B1A,0xDD3A,0x1D4B,0x1D4B,0x7E3A,0x7E4A,0x3F74,0x3F8D,0x7F85,0x1F75,0x1E5C,0xFC42,0xFB4A,0x3C4B,0x9D5B,0xBE53,0xBE4B,0xBD4B,0x7C53,0x9D4B,0x7D43,0x1B43,0x1A43,0x5832,0x5632,0xB419,0x3211,0x7519,0xBB29,0x9E42,0x7F4B,0x3E4B,0x3E53,0xBF5B,0x3F6C,0x9E63,0xBF73,0xDE84,0xDE8C,0x5F95,0x5F8D,0xFF74,0x7F6C,0x3D64,0xDC74,0x576C,0xD76C,0x4B19,0xA908,0xB010,0xF831,0xFD6B,0xBF7C,0xDF74,0x3C6D,0x513A,0x8C3A,0xEE42,0xCC21,0x934A,0x5032,0x6F19,0x3111,0x5619,0x9D2A,0xDD42,0x1F85,0x7F6D,0xBA33,0x3522,0x753A,0xAF21,0xF639,0xDB62,0xDFBE,0x7FAE,0x7985,0x2F4A,0x9A84,0xDB8C,0x397C,0xFD7B,0x7FBE,0xDF9D,0x3F85,0xBFBE,0x9D85,0xDFC6,0x9FD7,0xF16C,0x8A6B,0x6C6B,0x4C6B,0x4B6B,0x6B6B,0x4A63,0x496B,0x4A63,0x2B63,0x2A63,0x2963,0x0A63,0x0B63,0x095B,}, +{0xC8E7,0xC8E7,0xC8E7,0xC8EF,0xC8EF,0xC8EF,0xC8F7,0xC9F7,0xC9F7,0xC8EF,0xC9F7,0xC9F7,0xCAF7,0xC9F7,0xC9F7,0xCAF7,0xCAF7,0xE9F7,0xC9F7,0xCAF7,0xEAF7,0xCAF7,0xCAEF,0xCAEF,0xCAE7,0xEAEF,0xC9EF,0xC8E7,0xC8CF,0x68BF,0x469E,0x499E,0xABA6,0xE99E,0xA986,0x2A66,0x8B55,0xAD34,0x8E23,0xEF1A,0x702A,0x5132,0x703A,0x2F32,0x314A,0x944A,0x783A,0x5A2A,0xFB21,0x5C32,0xBD4A,0xFE52,0x1E5B,0x1D4B,0xFB52,0xB842,0xD442,0x724A,0x2E22,0xCB19,0xCE11,0xBB52,0x1F84,0xFC63,0x1B6C,0xDF8C,0x1F95,0x5F64,0x9E5B,0x1D53,0xFC4A,0x7932,0xF829,0x9421,0x6E11,0x0E09,0xCB08,0xEC08,0x5621,0x1C3A,0x7E4A,0xBE52,0x1B3A,0xDC21,0x1519,0xCE08,0xED10,0xF208,0xF508,0xF508,0xD208,0x6C00,0x4C00,0x2A00,0x4C00,0x2900,0x2400,0x4110,0x8208,0xC210,0x4419,0x4521,0x6629,0xE941,0x6521,0xE418,0x0629,0x8631,0xC430,0x8220,0x6228,0x2128,0x0228,0x2130,0x2228,0x6528,0xA520,0x6A39,0x0A42,0x716B,0x0A3A,0x6A4A,0x6529,0xE728,0xEC18,0x0B11,0x0811,0x0511,0xA710,0xEB10,0x0F11,0x3719,0x5C42,0x9F5B,0xDE32,0x7A11,0x7A22,0xD921,0x7F3B,0x5C2A,0xDB21,0x9821,0xBC31,0x1D3A,0x3F5B,0xDF63,0xDF63,0xFE5B,0xFE7C,0x1E7D,0x9F8D,0xBF8D,0xDF95,0xDF8D,0x1F9E,0x5F96,0xFF8D,0xBF85,0x5F7D,0x5E64,0x5C4B,0x5722,0xB311,0x4F11,0xF008,0x7410,0x5929,0x5C3A,0x3E43,0x3F6C,0x5F64,0x9F53,0x7F64,0xDB3A,0x3821,0x7931,0x5B42,0xFC5A,0x3E64,0x1C54,0x5A64,0xB242,0xAE29,0x4919,0x0711,0xE808,0x4A10,0xF328,0xDA52,0xDD63,0xFD5B,0x553A,0x354B,0xFD74,0x3B6D,0xF329,0x5432,0x9221,0x7419,0x9519,0x9A29,0xBF3A,0xFE6B,0x9F7D,0x7E54,0x141A,0x7732,0xB432,0x783A,0x9841,0x9FAD,0xBFA5,0x7B85,0x9152,0x7D7C,0xDE84,0x5A74,0x796B,0xBE8C,0x1F8D,0xBF9D,0x9FBE,0x1E6D,0xDFDE,0xDFEF,0x1AB7,0xAC6B,0x6B6B,0x6C6B,0x4B63,0x6B6B,0x4B63,0x4A63,0x4A63,0x4A63,0x2B63,0x4A63,0x0A63,0x0A5B,0x0963,}, +{0xE7E7,0xC7E7,0xC7E7,0xC8EF,0xE8EF,0xC8EF,0xC8F7,0xC8F7,0xC8F7,0xC9F7,0xC9F7,0xCAF7,0xC9F7,0xE9F7,0xE9F7,0xC9F7,0xCAFF,0xCBFF,0xCAF7,0xCAF7,0xCAF7,0xCAEF,0xC9EF,0xCBEF,0xCAE7,0xC9E7,0xC8EF,0xC8E7,0xC7DF,0xA5CF,0x05AF,0xC69E,0xA78E,0xC68E,0xA78E,0xCA86,0xAC8E,0xCD6D,0xAD54,0xAD3B,0x0E2B,0x8D1A,0xEE19,0x8B21,0xAB21,0xCE21,0x5542,0x574A,0xF629,0xD411,0x9411,0xB611,0x7721,0xD821,0xD729,0xF429,0xB121,0xF139,0x744A,0x2F22,0xAB19,0x6D11,0x5B4A,0x7C63,0x9A53,0xDE5B,0xBF8C,0x7F9D,0xBF7C,0xBE53,0xDC3A,0x9C42,0xF729,0xD329,0x966B,0xB553,0x8F22,0xAD19,0x6F19,0x3209,0x9400,0x9608,0xB500,0x9600,0x5000,0xAC00,0xF010,0xB408,0xD608,0xD600,0xB300,0x6D00,0x6800,0x4500,0x8400,0x4300,0x6108,0x8210,0xA210,0xE418,0x8729,0x8721,0x2521,0x4529,0x2519,0x4529,0x0421,0x6220,0x2028,0x0038,0x0058,0x0068,0x0068,0x2058,0x6150,0x2048,0x2040,0x2338,0x6428,0xA728,0xAA31,0x4C42,0xE731,0x4531,0xC410,0x0521,0xC418,0xE518,0x0519,0xE518,0xC918,0xEF18,0xB819,0x5B21,0xBC21,0x9711,0xF308,0xF921,0xDB21,0x1D2A,0xFA19,0x3519,0xF919,0xB921,0xDC29,0x3D3A,0x9D32,0xFE42,0xFD4A,0x5E53,0xDF73,0x7E74,0xDF84,0xFF8C,0x3F95,0x7F95,0xBF9D,0xFFA5,0x3FA6,0x3F8D,0xDF7C,0x7E4B,0xF932,0x7322,0xED11,0x2B09,0x8C10,0x4D10,0x7310,0xB831,0x3A3A,0x1932,0xDB4A,0xDD5B,0xFC3B,0x5A43,0x5B3B,0x5C53,0x1E85,0x5C6C,0x595B,0x763B,0xF319,0xAF11,0x8F11,0xAF19,0x4F22,0x8F19,0xF429,0x7732,0xD629,0x943A,0x343A,0x5C6B,0x9FB6,0x9D8D,0x1743,0x372A,0x7411,0x1611,0xD819,0xBB21,0x3F4B,0x9F6C,0x9F5C,0xB81A,0x9419,0x9A32,0xBA32,0x7B2A,0xDD6B,0x3E7C,0x3D85,0xD85A,0x3F8D,0x3E95,0xBD7C,0x5653,0x5B5B,0x3F6C,0x9F9D,0x7FB6,0xFE6C,0x7FC6,0x9FEF,0x9EE7,0xAF74,0x4C6B,0x4B63,0x6B63,0x6B63,0x4B6B,0x6A63,0x6A63,0x4A6B,0x2B63,0x2B63,0x0A63,0x0A5B,0x0A5B,}, +{0xC7E7,0xC7E7,0xC8E7,0xE8EF,0xC7EF,0xE8EF,0xC9F7,0xC9F7,0xC9F7,0xC9F7,0xC9F7,0xE9F7,0xC8F7,0xE9F7,0xE8F7,0xC8F7,0xEBFF,0xCBFF,0xCAF7,0xCBF7,0xEAF7,0xEAEF,0xCAEF,0xEBEF,0xCBEF,0xCAEF,0xC8E7,0xC7E7,0xC6E7,0xC5DF,0xC6CF,0x69C7,0x29AF,0xC69E,0x4786,0x0766,0xA965,0x2A5D,0x8B4C,0x2E4C,0x8F4B,0xCF2A,0x4D2A,0xEB21,0xCA31,0xAB21,0x6E21,0x9121,0xF531,0x5652,0x954A,0x743A,0xD319,0x7311,0x3311,0x3111,0x2E11,0x6C19,0xD141,0x1542,0xCE29,0x4809,0x2C09,0x153A,0xB84A,0x983A,0x5E5B,0x7F7C,0x3F9D,0xFF8C,0xFD5B,0x7A3A,0x7732,0x111A,0xD642,0x9E8C,0x1D8D,0x7843,0x3122,0xB319,0x7219,0xCE08,0xB010,0xB210,0xAF00,0xAC00,0xAF08,0x7208,0x9208,0x5100,0x7000,0x8C00,0xC800,0x8708,0xA408,0x6308,0xE310,0x0419,0x0419,0x8629,0x6A42,0xA729,0x2842,0xE831,0x0732,0x6529,0xA318,0x4120,0x4068,0x4098,0x40A0,0x40A0,0x6090,0x8A92,0x97C5,0x35AD,0x0F8C,0x4862,0x8148,0x2138,0x4420,0xE620,0x4A42,0x8739,0x6529,0x0421,0x4629,0xC420,0x2519,0xC618,0xA710,0x6810,0xF431,0x1822,0xF719,0xB419,0x3101,0x3419,0x5B2A,0xB921,0xBA19,0xB821,0xB719,0x7411,0x5409,0x3619,0x9721,0xF829,0xF821,0xDB29,0x5E42,0xDF4A,0x5F53,0x3F5B,0x5F5B,0x3F53,0x7F63,0xFF8C,0xFF9D,0xFF9D,0xBF95,0x9F8D,0x5F85,0xBD64,0xB843,0x5122,0x2A11,0xE908,0x0D19,0x4B11,0x8C10,0x8C08,0x4F18,0xD621,0xF719,0x9319,0xEF18,0x9020,0x375B,0x365B,0xB331,0xB632,0x142A,0x9119,0x3011,0xEF10,0x8C10,0xAD08,0x6B08,0xCF18,0x5021,0xCF29,0x3432,0xDA29,0x5D6B,0x1FAE,0xFE95,0x3A4B,0xD919,0x1A1A,0x7809,0xF911,0x3C2A,0x1F43,0x1E43,0x5922,0x9411,0x9831,0xDB32,0xD729,0x993A,0xFA4A,0xBC53,0x5B42,0xDF8C,0xBF9D,0x3E85,0x5553,0x575B,0x9E63,0xDF84,0x3F95,0xFE84,0x9FA5,0x3FB6,0xDEC6,0x5485,0x6C6B,0x4B6B,0x4B6B,0x6B6B,0x4B6B,0x6B6B,0x4B63,0x2B63,0x4A6B,0x2B6B,0x0A63,0x0B63,0x0A63,}, +{0xC7E7,0xC7E7,0xC8E7,0xC8EF,0xC8EF,0xE9F7,0xCAF7,0xCAF7,0xC9F7,0xC9F7,0xC9F7,0xC9F7,0xC9F7,0xE8F7,0xC8F7,0xC9F7,0xCBF7,0xCBF7,0xCAF7,0xCAEF,0xCAEF,0xCAE7,0xC9DF,0xCBE7,0xCADF,0xC9E7,0xE7DF,0xC7E7,0xC6E7,0xE6DF,0xC6CF,0x87BF,0x27B7,0x869E,0xA87D,0x0855,0x694C,0x2B4C,0x2E4C,0xEF4B,0x913B,0x322B,0xD022,0x2D1A,0xE919,0xA911,0x6919,0x4B19,0x4E19,0x5029,0xD339,0x9652,0x7452,0x7242,0xF021,0x6E11,0x4D11,0x0B19,0x2A11,0x4F21,0x9431,0xB031,0xCA21,0x0C22,0x343A,0x743A,0x9942,0x3D53,0xFF6B,0x5F84,0x5F7C,0x9C53,0xF83A,0x963A,0x3322,0x3E5B,0xBF84,0x3F95,0xFD5B,0xB82A,0xB521,0xD329,0x0D11,0x0D11,0x4E19,0x4D09,0xEE08,0xAC00,0x8A00,0x8A00,0x1109,0xF619,0x9211,0x0A11,0xC508,0xA410,0xC418,0x4629,0x6621,0x2832,0x2942,0x073A,0x2842,0xA731,0xED62,0x4629,0x6230,0x8098,0x80C8,0x20D0,0x80C0,0xA098,0x8078,0xD29B,0xBCBD,0x7BAD,0x39A5,0xB69C,0x9394,0xEB72,0xA238,0x4228,0xE520,0xCD4A,0x4B3A,0x0329,0x6631,0x8629,0xE318,0x4E21,0x5C43,0xD632,0x5131,0xBE53,0xBD4B,0x1922,0x7511,0xB200,0x3B32,0x3A22,0x1B22,0x7919,0x1511,0x7519,0x361A,0x1422,0x2D09,0xEE20,0x9121,0xB318,0xD520,0xF828,0xDB21,0x9C21,0xFD31,0x5E2A,0xDD29,0xDE52,0xBE84,0x5F95,0x3F85,0x1F85,0x5F8D,0x7F8D,0x9F85,0x7E7D,0xDA64,0xD753,0x3333,0x2D22,0x6C22,0x8711,0x4609,0x8808,0x2A08,0xAA18,0xE910,0x6C29,0x9353,0x6C29,0xAF42,0x4F3A,0x102A,0x9119,0x1011,0x9008,0x8D08,0x0C11,0x9009,0x6600,0x2510,0xA710,0xCD18,0xB921,0xFC19,0xDC51,0x9FA5,0xBE7D,0x7C2A,0xFB21,0x3A1A,0xB709,0x9919,0x1C22,0xFA19,0x9519,0x3319,0x7219,0xB519,0x3119,0x132A,0x162A,0x583A,0xFB31,0xFF73,0x7F9D,0x5F7D,0x985B,0x555B,0xB942,0x1F64,0xBF7C,0xDD7C,0xFC53,0x5F9D,0xDFCE,0xDB9D,0xEE6B,0x4B6B,0x6A6B,0x6A6B,0x6A6B,0x6A6B,0x4B6B,0x2B6B,0x4A63,0x2B63,0x2B63,0x0B63,0x2A63,}, +{0xC7E7,0xC7E7,0xC7E7,0xE7E7,0xE8EF,0xC9EF,0xCAF7,0xE9F7,0xC9F7,0xC9F7,0xC8F7,0xC8F7,0xC8F7,0xE8F7,0xC7EF,0xE8F7,0xC9F7,0xCAF7,0xC9EF,0xE9EF,0xE8EF,0xE8EF,0xC9EF,0xCAE7,0xCAE7,0xE8DF,0xE7D7,0xC6D7,0xA6D7,0xA6C7,0xA7C7,0x89BF,0x2BB7,0x6AA6,0x498D,0x495C,0x0C64,0xEF53,0xD24B,0xD553,0xF753,0xD853,0xB753,0x5453,0xF24A,0x8D2A,0x091A,0xA811,0x6809,0x2B19,0x0C19,0x2E11,0xB129,0xF141,0x324A,0x1042,0xCC29,0x2C21,0x2819,0x2909,0x0C11,0x1442,0xB452,0x776B,0x1A74,0xFA53,0x393B,0xDA42,0xFD4A,0x3F43,0x9F53,0x7E5B,0x5E6B,0x993A,0x7732,0x3832,0x7F5B,0x3F74,0xFF8C,0x7F6C,0xFA3A,0x194B,0x9332,0x9342,0xD64A,0x174B,0x9632,0x7011,0xC900,0xEE10,0xF718,0x1911,0xD408,0xCB08,0x8510,0x8310,0xC210,0x8629,0x4A3A,0x4F63,0xCB52,0xCC5A,0x0D5B,0xEC52,0x0A42,0xA430,0xC1A8,0xC0E0,0xC0D0,0x80C0,0x8098,0x4058,0xA228,0x5784,0x5C95,0x3B8D,0xBA8C,0xB984,0xB78C,0x9694,0xD07B,0x4449,0x4230,0xE720,0x4729,0xAA42,0x4529,0xC731,0xC731,0xEC20,0x5D53,0x7F64,0xF729,0xBD4A,0x7F74,0xDE53,0xD919,0x1309,0x5210,0xFB19,0x5A22,0x3411,0x1209,0xB108,0x8E08,0xEE08,0x8E11,0x3222,0xF221,0x7319,0xB521,0xB619,0xB919,0x7919,0xDA21,0xFA21,0x3719,0x9410,0xF618,0x9A39,0x1C53,0x5E5B,0xBF63,0x3F6C,0x9F74,0x5F6C,0x1E64,0x1C64,0x7643,0x2F32,0xEB21,0xC929,0x082A,0x0619,0x6608,0x6810,0xAD21,0x5343,0x174C,0x7553,0xF24A,0x522A,0xD421,0xD621,0x9411,0xD100,0xD110,0xB432,0x131A,0x0E11,0xE710,0xAA29,0x8D32,0xF210,0x9B21,0xBD21,0xDF6B,0x1F7D,0xDE32,0xFA19,0xF911,0x9609,0x5511,0x9409,0xD509,0x0D09,0x2D19,0x2D19,0x0D19,0x2E11,0x2F19,0x2F11,0x9229,0xD929,0x9E5B,0xBF84,0xFF7C,0xBA5B,0xD75B,0x5B5B,0xBE4B,0x7F74,0xBE7C,0x564B,0x5C7C,0x5FBE,0xBD95,0xB374,0x8B6B,0x6B63,0x4B6B,0x4B6B,0x6B6B,0x4B63,0x2B6B,0x4B63,0x2B5B,0x4B63,0x2A6B,0x0A63,}, +{0xE8E7,0xC8E7,0xE8E7,0xC7E7,0xC8E7,0xE9EF,0xCBF7,0xCAEF,0xC9EF,0xC8F7,0xC8F7,0xE8F7,0xC7F7,0xC7F7,0xC7EF,0xE8EF,0xC9F7,0xE9F7,0xC8EF,0xC8EF,0xC7EF,0xC7EF,0xE8E7,0xC8E7,0xCADF,0xC7D7,0xA6C7,0x66B7,0x26AF,0xE8AE,0xA99E,0x2D8E,0xD17D,0x347D,0x5674,0xF76B,0x1764,0xD75B,0xDA5B,0xDA63,0xFC6B,0xFD63,0xFD63,0xFC63,0xBA5B,0xD85B,0x5874,0x799D,0x967C,0x0E3B,0xC919,0x4811,0x0909,0x4B19,0x6C29,0xEE29,0x0D32,0xAA29,0x8819,0x2919,0x2809,0x4B19,0xF541,0xB84A,0xDE73,0x3F95,0xDE7C,0xFD5B,0x5C43,0x3E53,0xBD3A,0xFD4A,0x9A42,0xBB42,0x3622,0x3422,0x3B3A,0x3F4B,0xDF63,0xBF84,0xBF7C,0xFE5B,0x9C53,0x1A53,0xBC5B,0xDC63,0xFD73,0xD942,0x6C09,0x9021,0xF629,0x7411,0xEF00,0xA908,0x8508,0x8308,0x4629,0x4A42,0x8C4A,0x2F63,0x0E5B,0x8C4A,0x0B42,0xCF62,0x4831,0xA190,0x20E9,0x60E9,0x00C9,0x8088,0x4048,0x4118,0x0419,0xD87C,0x3B95,0xFA7C,0xD97C,0xB974,0x7874,0x587C,0x767C,0xD07B,0x2449,0x0128,0x8831,0x2B3A,0x2429,0xC839,0xCC4A,0x6921,0x173A,0x9E5B,0x3A32,0xBB29,0x3F53,0x5F64,0x9C32,0x3511,0x6F08,0x1309,0x5711,0x9511,0x3201,0x5309,0x3119,0xF121,0x1022,0xEF08,0xB321,0x172A,0xD721,0xF619,0x1411,0x3411,0xD411,0x9411,0xB519,0xB519,0x9711,0x1611,0xF410,0x5408,0x5410,0xD618,0x1629,0x5A32,0x5A32,0x1732,0x5332,0x3132,0x4F2A,0x0F3A,0x323B,0xB532,0x583B,0x983B,0x7A6C,0x7D85,0x7F7D,0x1C5C,0x5743,0x3A43,0x3E43,0x3D3B,0x3C22,0x7711,0xB508,0xD408,0xB200,0xCF00,0x2E11,0x8A21,0xAC21,0x7021,0xB210,0xBB21,0x1D22,0x9E32,0xDC32,0xDA21,0xB711,0x7211,0x2F09,0x6E11,0x2C09,0x0A11,0x4919,0x6C19,0xCB29,0x0911,0xEC10,0x4D09,0xF229,0x7629,0x3F53,0xBF7C,0xBF7C,0xFC6B,0xB953,0x1D6C,0x1E6C,0xBF9D,0x1E75,0xDA53,0xBA63,0xDD7C,0xFFA5,0x5CAE,0xCC6B,0x6A6B,0x6B6B,0x4B6B,0x2B6B,0x6B63,0x4B6B,0x4A63,0x2A63,0x2B63,0x0B63,0x0B63,}, +{0xC8DF,0xE8E7,0xE7EF,0xC7E7,0xC8EF,0xCAEF,0xCAF7,0xCAF7,0xC9EF,0xC8F7,0xC7F7,0xE7EF,0xC7F7,0xC7F7,0xC6F7,0xC7F7,0xC8F7,0xC8F7,0xC8EF,0xC8EF,0xC7F7,0xE7F7,0xC6EF,0xC8E7,0xC9DF,0xA8CF,0x27BF,0xC7A6,0x669E,0xC785,0x2865,0x885C,0x2A3C,0x4B2B,0xAE22,0xB022,0xB32A,0x753A,0x553A,0x563A,0x5842,0xDA52,0x3C63,0x7E63,0xBE63,0xDC63,0xBC84,0xBFBD,0xDEA4,0xB763,0x3353,0x9042,0x0C2A,0x8909,0x4919,0xCC39,0x4B3A,0x8E42,0xAE3A,0x4F32,0xEE29,0x8B19,0x6C11,0x343A,0x1C53,0xFF6B,0x1F9D,0x5FA5,0xBF74,0x9E53,0x9C3A,0xB93A,0xB942,0x5732,0x363A,0x1432,0x5632,0x5C32,0xFE42,0xDF63,0xBF9D,0xDF84,0x5F6C,0xBE5B,0xBE5B,0xFE63,0x1F7C,0x5E74,0x584B,0x7532,0xDC42,0xDC42,0x5219,0xA808,0xA318,0xC210,0xC729,0x8B52,0x8B4A,0x6B4A,0x4B52,0xEC5A,0xEE5A,0x0942,0x8358,0xA0D8,0xC0F0,0xC0D0,0x4080,0x2048,0x2118,0x6110,0xEE4A,0x7B8D,0x5C8D,0x5C85,0x3B8D,0xF97C,0x7874,0x176C,0x3764,0x1574,0xAD6A,0x6050,0x2330,0xE939,0x4842,0x6A4A,0x2A42,0xED52,0x4C29,0xD639,0xD621,0xB719,0xBC29,0x7E42,0xBE3A,0x7409,0xAC08,0xB219,0x572A,0x1209,0xD108,0xD321,0x3743,0xDC53,0x7E6C,0x5D54,0x9B43,0x973A,0x382A,0xB932,0x592A,0x181A,0xF811,0x1622,0x3422,0xD519,0xD621,0x9619,0xB409,0xB509,0x5211,0x0E09,0xCC08,0xAB08,0x2C08,0x2B10,0x4910,0x4910,0x8A18,0xCB20,0x2D29,0x5121,0x7131,0x2E19,0x8F18,0xCF20,0x5229,0xB431,0xD331,0x3419,0x7A31,0x3E4B,0xDF5B,0x5E3B,0xFC19,0x7709,0xB300,0xAF00,0x2A08,0xA810,0xC820,0xEC10,0x7211,0xF410,0x3A19,0x1C22,0xD719,0x3719,0x7409,0x4E11,0x0B09,0x6D11,0x2A09,0x4E11,0x4A21,0x2F32,0x764B,0xAF21,0xED10,0x7419,0x181A,0x5621,0x7D42,0x5F74,0xBF7C,0x1E8D,0x1A5B,0x1F95,0x5E6C,0xBFB6,0x3F9E,0x1D5C,0xF53A,0x1B3B,0x9F7C,0x1FB6,0x7074,0x6B6B,0x8B6B,0x6A6B,0x4B6B,0x6B6B,0x6A6B,0x4B63,0x4A6B,0x2A63,0x0A63,0x2A5B,}, +{0xC8DF,0xE8E7,0xC7E7,0xC8E7,0xCAEF,0xC9EF,0xC9EF,0xC9EF,0xC8EF,0xC8EF,0xC7EF,0xE7EF,0xC6F7,0xC6F7,0xC6EF,0xC6F7,0xC6F7,0xC6F7,0xE7F7,0xC7F7,0xC6EF,0xC6EF,0xC6EF,0xC6EF,0x84CF,0x65CF,0x04BF,0x63A6,0xE48D,0x057D,0x2654,0xE64B,0x673B,0xC72A,0x8622,0x6712,0x681A,0x4822,0x091A,0xEA09,0xCB09,0xAB01,0x6E11,0xB019,0xB529,0x1522,0xF64A,0x7A63,0x385B,0x1543,0xB44A,0x713A,0x2E3A,0x2E4A,0x2D3A,0x0C2A,0xCE42,0x997B,0x397C,0xD963,0x785B,0xF542,0x5132,0xAE19,0x5642,0x3C5B,0x1D7C,0xBF8C,0x3F95,0x1F85,0x7E6C,0x5B4B,0xD83A,0x583A,0xB742,0x1022,0x543A,0x5832,0x7A32,0xBE7C,0xDE7C,0x9E74,0x5F8D,0x9F7C,0xFF63,0x9F5B,0xDF6B,0x7F6C,0xDE63,0x3B5B,0xBB3A,0x3B3A,0x3319,0xEA10,0x4521,0xC729,0x893A,0x6E63,0x2A42,0xC731,0xAB52,0x4E63,0xC941,0x2631,0x81A8,0x07EA,0xC0D8,0x40A8,0x0040,0x2020,0x4208,0xE308,0xB684,0x5C85,0xDB7C,0x9B7C,0x9A7C,0x9974,0xF352,0x713A,0xF75B,0x9563,0x0821,0x8150,0x2058,0xE628,0x0F5B,0x8C52,0x4529,0xA831,0x6831,0x4A21,0xF131,0xD229,0xB829,0x9A21,0x3919,0x3309,0xEC00,0xF110,0x5D32,0xFB32,0x7209,0xD010,0xD731,0xBE5B,0xBF84,0x7F8D,0x9F8D,0x3F75,0xDA3A,0x392A,0x1922,0x9B2A,0xBC22,0xD929,0xF721,0xD719,0xB811,0xB819,0x9509,0x9611,0x9309,0x7009,0x0F12,0xCC11,0xEB11,0x6A11,0x0B09,0x6C11,0xAC19,0x2F22,0xEE21,0x2D19,0x0A19,0xE808,0x8610,0x6410,0x2508,0x0610,0x0918,0x3111,0x7709,0xF808,0x5A31,0xFD42,0x1F4B,0xDE2A,0xB809,0xB000,0xCA00,0x8600,0xA510,0x6508,0xAA10,0x5211,0x3311,0xF710,0x7609,0xD000,0x1109,0x6D11,0x2B09,0x1309,0x9101,0x7211,0x3219,0x3832,0x1E5C,0x1B3B,0x7211,0x9719,0x9E32,0x7919,0x7919,0x7D3A,0x3E6C,0xDE9D,0xDD63,0x1F8D,0x1F95,0xFFC6,0x7FAE,0x7F95,0xF122,0xD411,0x3C43,0xBE84,0x3174,0x6B6B,0x6B63,0x8A6B,0x4B6B,0x6B6B,0x6B6B,0x4C63,0x2B6B,0x2A6B,0x2B63,0x2963,}, +{0xC8DF,0xC7E7,0xC8E7,0xC9E7,0xE9EF,0xC9EF,0xEAEF,0xE8EF,0xE8EF,0xC7EF,0xC7EF,0xC7EF,0xE6EF,0xC6EF,0xE6EF,0xC6EF,0xC7EF,0xE6F7,0xC7F7,0xC8EF,0xC7EF,0xE6EF,0xC6EF,0xC5E7,0xC4D7,0x84CF,0x04B7,0x64A6,0xA595,0xE484,0x255C,0x8443,0x442B,0xC522,0x8522,0x661A,0x661A,0x871A,0x6B32,0x8F2A,0x9242,0x734A,0x7442,0x7242,0x9132,0x713A,0x3032,0x3122,0x2F2A,0x2E22,0xED29,0x0E2A,0xEC19,0xEB29,0x0F42,0x7352,0xAF52,0xF342,0xFC7B,0x3F9D,0x1E95,0x5C74,0xFB6B,0xF44A,0xEF21,0xD429,0x784A,0xBE6B,0xFF84,0xFF94,0x1F8D,0xFF84,0xFC5B,0x1943,0x9532,0x343A,0xCF21,0x5642,0xD73A,0x7EAD,0xDD8C,0xFFA5,0x9F95,0xDF7C,0x3F74,0xDF5B,0xBF5B,0xDF63,0x7F53,0x3D5B,0xFB52,0x1732,0x6F21,0x4819,0x4621,0x8B4A,0x8F63,0xCF6B,0x4842,0xAA4A,0x2E5B,0x706B,0x8A52,0xA348,0xC0D8,0x44E9,0x80C8,0x4068,0x2020,0x4108,0xE310,0xC829,0x987C,0xDA7C,0x196C,0xF452,0x5974,0x313A,0x2700,0x0919,0xF44A,0xF031,0x8608,0x6128,0x8058,0x2040,0xC620,0x4629,0x493A,0x2521,0x093A,0x6629,0x7231,0x1E54,0xB521,0x9519,0x1109,0xCD08,0xA900,0x8F08,0x3A19,0x9F2A,0x9B2A,0x1011,0xB210,0x1819,0x3D42,0x9F63,0x9F74,0xFF74,0xBF53,0xD93A,0x152A,0xB721,0x7719,0x3719,0x1509,0x5611,0x7611,0x5B22,0x9719,0x9611,0x5219,0xF319,0xD011,0x4F1A,0x701A,0x4D22,0xED29,0x6C19,0x4919,0x2919,0x0919,0xE610,0xC310,0x6310,0x8410,0xC418,0x0511,0xE410,0x4510,0x0E19,0x5621,0x1B12,0x5D22,0x3B1A,0x7B19,0xBD21,0x5D1A,0x1501,0xAE00,0xCC00,0x2B19,0xD021,0x6E21,0xCB08,0xAD18,0x7219,0xB100,0xAD00,0x2808,0xEB08,0xCF00,0x1609,0xF909,0x1411,0x7A21,0xDC29,0x1F64,0xDE53,0x1A2A,0x7A2A,0x5E2A,0xDA09,0x1411,0x7921,0xDE73,0xBF8D,0xDF84,0x5F85,0x1E8D,0x5FB6,0xDF9D,0x5F95,0xF84B,0x373B,0x1E54,0x3A43,0xB36B,0x6C73,0x6B6B,0x6B6B,0x6B6B,0x4B6B,0x4B6B,0x4B6B,0x4A6B,0x2B63,0x2B63,0x2A63,}, +{0xC7E7,0xC7E7,0xC8E7,0xC9E7,0xC9EF,0xEAEF,0xCAEF,0xE9EF,0xC7EF,0xC7EF,0xC7EF,0xC7EF,0xC6EF,0xE6EF,0xC6EF,0xC7EF,0xC8EF,0xE9F7,0xC8EF,0xC8E7,0xC8EF,0xC7EF,0xE6EF,0xC5EF,0xC5DF,0x84D7,0x04C7,0x86B6,0x07A6,0x278D,0xC764,0x4A54,0x093C,0x682B,0x4A33,0x492B,0x4B43,0x4D53,0x0C43,0xAB2A,0x8C2A,0xED29,0xCE29,0xEF39,0x1032,0x1042,0xF041,0xF029,0x0F2A,0xAD21,0xAB31,0x4E42,0x7663,0x966B,0x723B,0x8E2A,0x904A,0xD44A,0xF852,0x9E6B,0x5F7C,0x7F8C,0x5E84,0x5B84,0xF973,0x6F2A,0xAF21,0x573A,0xDE6B,0xDF8C,0x1F8D,0xFF84,0xBF84,0x1E6C,0x3A43,0x753A,0x543A,0x1532,0x773A,0xF639,0x383A,0x1C74,0xBF9D,0xFE7C,0x7F7C,0x9F5B,0x7F53,0x1F4B,0x5F53,0xBE4A,0x9B3A,0x3632,0xB121,0xAA29,0xE631,0xB06B,0x937C,0x317C,0xD073,0xEC5A,0x2C5B,0xCD5A,0x4A4A,0x6180,0x60E8,0xA0D0,0x4090,0x2128,0x2210,0xA308,0x2621,0x2B3A,0x376C,0x1664,0x6D21,0xCC29,0xB24A,0x2600,0x0200,0x2400,0x2A19,0xE608,0x6300,0x6110,0x6038,0x4050,0x2531,0xCC52,0x2942,0xA731,0xC939,0x8631,0xCD28,0x7E5B,0xFC3A,0x1009,0xEC00,0xC908,0xE600,0x4700,0xD610,0xFE19,0xFE21,0xD819,0x3119,0x3422,0x7310,0xB820,0x3C42,0x1E53,0x1F5C,0x5A4B,0xB94B,0xD842,0xB832,0x5519,0x3409,0x5619,0x171A,0xB711,0x1511,0x3311,0xB219,0x752A,0x752A,0x3122,0x302A,0xED31,0xAC29,0xAA21,0x6819,0x8619,0x0621,0xC510,0x2619,0x8B11,0x7209,0xAF19,0x8D32,0x092A,0x6621,0x2819,0x8D18,0x7208,0x9610,0x5A11,0x9A09,0x1811,0x1911,0xB811,0x4C00,0xED00,0xEA10,0xEE10,0x5219,0xB411,0xB409,0x1009,0xEE00,0x0C01,0x8400,0x2800,0xB200,0xD808,0x1E1A,0xF508,0x9A11,0xBD21,0xFF63,0x7F74,0x3D32,0x5E53,0xDE32,0x5C1A,0x1511,0x9829,0xBF6B,0x7F7D,0x9F7C,0x3F8D,0x9F9D,0x3F8D,0x7F6C,0x7F7C,0xFF7C,0x5F8D,0x1E7D,0xD62A,0xF352,0x6B6B,0x6B6B,0x4B73,0x6B73,0x2B6B,0x4B6B,0x4B63,0x6A6B,0x4A63,0x2B63,0x2A63,}, +{0xC7DF,0xC7DF,0xC8E7,0xC9E7,0xC9E7,0xCAEF,0xCAEF,0xC8EF,0xC8EF,0xC7EF,0xC7EF,0xC7EF,0xC6EF,0xC6EF,0xE6F7,0xC7F7,0xC9F7,0xE9EF,0xEAEF,0xC9F7,0xE9F7,0xE8F7,0xE9F7,0xC6F7,0xC6E7,0x45DF,0xE8C6,0x6AA6,0x8B8D,0xEB74,0x8B6C,0x2B54,0xEC43,0xCD3B,0x6D33,0x6D3B,0x6D43,0x4D53,0x2B53,0x0C53,0x6F5B,0xCF52,0x8C42,0x6D3A,0xAE3A,0x6F3A,0x2E3A,0x103A,0xF031,0xAC21,0x6A29,0xEB29,0x713A,0x7A73,0x7F8C,0x9D84,0xD763,0xD33A,0xB53A,0xDB52,0x1D63,0x5D5B,0x7C6B,0x9B5B,0xFD73,0x5C6C,0x333B,0x912A,0xBB42,0xBF6B,0xBF7C,0x5F95,0xBF84,0xDF5B,0x7D53,0x9A3A,0x5432,0x352A,0xB321,0xB529,0x9419,0xF529,0x9E9D,0xFE84,0x9E5B,0x7F32,0xFF5A,0xFF4A,0x7E42,0x3C3A,0x592A,0xB64A,0xF452,0x4D3A,0x8C4A,0x0E5B,0x527C,0x117C,0x0D63,0xCC52,0xCC52,0xCD52,0xA839,0x21A0,0x81E8,0xE0C0,0x4060,0x2118,0x6208,0x4519,0xE518,0xEF4A,0x745B,0x124B,0x4500,0xC810,0x8710,0x2200,0x0100,0x2100,0x6300,0x6521,0x8208,0x4108,0x4118,0x6050,0x4148,0x0721,0x4F5B,0x6B4A,0x0531,0xA629,0x0829,0xB631,0x1C2A,0xF110,0x0B09,0xC410,0xA410,0x8608,0x2C08,0xD710,0xDC19,0x9A11,0x1611,0x3832,0x371A,0x1B22,0x7A2A,0x192A,0x7819,0x1B3A,0x392A,0xB429,0x3832,0xB932,0x3A33,0x582A,0xB218,0x1822,0x7722,0x3622,0xB621,0xD629,0x182A,0x7419,0x3311,0x2F09,0xEA10,0xD021,0x1533,0xB22A,0x0E2A,0xAC21,0x0E19,0x3411,0x3C22,0x7B2A,0x7432,0x0F3A,0x4E32,0xEC29,0xB021,0xF110,0x1709,0x3809,0xF508,0x7100,0x5300,0xB400,0x3101,0x4800,0x8A00,0x5019,0x9A32,0x9C22,0xDA11,0x1812,0x5001,0x0D09,0xCA00,0x6D00,0xB208,0xD908,0xDD19,0x7A11,0x5C19,0xBC21,0x1F53,0x9F53,0xDF3A,0xDF5B,0x9F4B,0x7C2A,0x7621,0xB842,0xFE6B,0x5F7D,0xBF74,0xDF84,0x9D7C,0xBD63,0x7E53,0x9E53,0x1D53,0xFF6B,0xFC63,0x2F1A,0x4F4A,0x4C6B,0x4B6B,0x4B6B,0x6B6B,0x4B73,0x6B6B,0x6B5B,0x4A6B,0x6A5B,0x4B63,0x2A63,}, +{0xC7E7,0xE7E7,0xC8E7,0xE8E7,0xC9E7,0xC9E7,0xC8EF,0xC8EF,0xC7EF,0xC7EF,0xC7EF,0xE7EF,0xC6EF,0xC6EF,0xC6EF,0xC6EF,0xC6EF,0xC6EF,0xC6EF,0xE7E7,0xC6E7,0xC7EF,0xC9F7,0xC8EF,0x29C7,0x6796,0xE97D,0x4765,0xA85C,0x474C,0xEA43,0xCC43,0xCC43,0xCD3B,0xCF4B,0x6D3B,0x0B43,0xC932,0xA932,0xAA42,0x2E53,0xAF4A,0xAE42,0x4F3A,0xEF31,0xB039,0x6F29,0x2D29,0x0C21,0x0919,0x6821,0x0E3A,0x503A,0x7132,0x753A,0x1A63,0xDD83,0x3D84,0x7853,0xF842,0xFA4A,0x1A4B,0x5A6B,0x3B53,0x5B43,0x5F7C,0xBE84,0xB84B,0xB632,0x7C4A,0x3E53,0x1F74,0xBF84,0x9F74,0x5D4B,0x1C43,0x773A,0x3422,0xF429,0x9419,0x5419,0x3311,0xB973,0x9C6B,0xFA31,0x1C22,0xDC29,0x5E3A,0x5D32,0x3A2A,0xB721,0xF429,0xF431,0x0D22,0x2B42,0x6A3A,0x3284,0xF17B,0x695A,0xEC52,0x0A42,0x8831,0x0529,0x00A8,0xA1E0,0xA1B8,0x4038,0x6108,0xA308,0xA629,0x6208,0x4A21,0x2F3A,0xE918,0x2200,0x0300,0x0200,0x0100,0x0100,0x0000,0x0200,0x2519,0xC410,0x4200,0x8110,0xA148,0x6068,0x8428,0x0829,0xE428,0xE328,0xC739,0x8731,0x6B29,0x5021,0x8E08,0x8800,0xC508,0xA710,0xB321,0x1111,0x8E10,0xD510,0xD408,0x3209,0x1319,0xBA32,0x5E43,0x7D43,0x7D53,0x3D3B,0x1822,0x1922,0x172A,0x1111,0xD419,0xF621,0xBA32,0xF421,0x3219,0x5319,0xF519,0xD829,0x5A2A,0x7A2A,0x3722,0xB73A,0xD92A,0x131A,0xEC10,0x6E10,0x152A,0xDB4B,0xB94B,0xF82A,0x9619,0xD510,0x1611,0x9621,0x7419,0x3009,0xD429,0x1D43,0xBF53,0xFE53,0xFC2A,0x7A22,0xF409,0xEE00,0x2C00,0xCE00,0xEC08,0x4A00,0xB208,0xBB19,0x1F33,0x5E3B,0x5C1A,0x3912,0x5111,0x5612,0x3419,0x762A,0x1A22,0x5B11,0x3911,0x1A11,0x5A19,0x9F3A,0x1F4B,0x5E3A,0x9F5B,0x7E4B,0x1B22,0x1732,0xBD53,0x9F5B,0xFF7C,0x3F6C,0x9F95,0x1743,0x793A,0x1822,0x372A,0x6F11,0x3319,0x5019,0xAE11,0x904A,0x4C6B,0x4B6B,0x6B6B,0x6B6B,0x6B63,0x6A63,0x4A5B,0x6B73,0x6B63,0x2A63,0x4A63,}, +{0xC7E7,0xC7DF,0xC8E7,0xE8E7,0xC8E7,0xC8EF,0xE8EF,0xC8EF,0xC7EF,0xC7EF,0xC7EF,0xC8EF,0xC8EF,0xC7EF,0xC8EF,0xC8EF,0xC8EF,0xC7EF,0xC7EF,0xC7EF,0xE7EF,0xC6E7,0xC6E7,0xC5E7,0x85C7,0x47B7,0xC6A6,0x4686,0x876D,0x0865,0xCB5C,0x8B5C,0xEA53,0xAC43,0x6D4B,0xEC32,0x892A,0x892A,0xAA1A,0x4A22,0x6B2A,0x2C3A,0xEC21,0x8A19,0x4909,0x0609,0x0509,0xE410,0xE408,0x0519,0x2721,0x6A21,0xEF31,0x734A,0x9542,0xF44A,0x564B,0x7963,0xBB73,0xDB73,0xDB63,0x5953,0x3953,0x1943,0x3B53,0x5D4B,0x7F84,0x3F95,0x7E6C,0x3B3B,0xDA3A,0x3E4B,0x7F53,0x3F74,0x5F74,0xBE5B,0x3D4B,0xB932,0xF321,0x9219,0x5219,0xEF08,0x3109,0x1421,0xDB21,0xBC3A,0x7C2A,0xBB21,0xFC21,0xB821,0x7419,0xB419,0xB219,0xEF21,0x0A3A,0x8B42,0xB073,0x4D63,0x694A,0x2D5B,0xCC5A,0x293A,0x0429,0x20B0,0x81D8,0x61A0,0x4128,0x8100,0xC408,0x8629,0x2100,0x4400,0x6710,0x2400,0x2100,0x0100,0x2000,0x0100,0x0100,0x0000,0x0100,0x6308,0x2521,0xA200,0x6210,0x8128,0x2068,0x6138,0xE420,0x0331,0xE228,0x2521,0x8629,0x2729,0x6821,0xC610,0xAC00,0xCF00,0xD100,0x1811,0x9911,0xD010,0x9519,0x5411,0x0F11,0x9111,0x7619,0x3D32,0x7E53,0xBF53,0xFF63,0x3F5C,0x1B33,0x9719,0x581A,0x5109,0x1321,0xFE6C,0x9E64,0x9D64,0x1D54,0xB92A,0x1622,0xD619,0xF929,0x1C33,0x9A2A,0x5B32,0xDB32,0x1A33,0xD432,0x5011,0x7218,0x7429,0x5A32,0x5B43,0xDC4B,0x7722,0xF511,0xF208,0x5409,0x7709,0xBB29,0x5F53,0x7F64,0x9F64,0xBF5C,0x1E44,0xB72A,0xD62A,0x7111,0x9511,0x3009,0x8E08,0xF808,0x7E21,0xFF42,0x1F4C,0x3E2B,0xFB19,0x1D3B,0x1B33,0xBD53,0x9F54,0x191A,0xB911,0x1719,0x1911,0xDD29,0x3E32,0xBE6B,0xFF84,0x5F4B,0x9D2A,0xDD3A,0x7F64,0x7E4B,0xBF63,0x1E4B,0x9F95,0xB953,0xF74A,0x962A,0x5021,0x8E21,0xF221,0x9019,0xAF29,0xAF5A,0x6A63,0x6C6B,0x6B6B,0x4B6B,0x6B63,0x6A6B,0x6A63,0x6B6B,0x4A6B,0x4B63,0x4A6B,}, +{0xC7E7,0xC8EF,0xC9EF,0xC8E7,0xC8E7,0xC8EF,0xC8EF,0xE7EF,0xE7EF,0xC7EF,0xE7EF,0xE7F7,0xC7F7,0xC6EF,0xC8EF,0xC9E7,0xC8E7,0xC7EF,0xC7EF,0xC7EF,0xC7EF,0xC7E7,0xC8EF,0xC8EF,0xC8E7,0xC7E7,0xC7E7,0x67BF,0xA9A6,0x0986,0x2A7D,0xC95C,0x2844,0xEA3B,0xAC33,0xEC42,0xAB3A,0xCB32,0x4A22,0x2A1A,0x0912,0xE911,0x0712,0x081A,0x2712,0x2B32,0x0C3A,0x2C32,0x4C3A,0x4C2A,0x4B2A,0x6D3A,0x4D3A,0x0C2A,0x2F2A,0x3553,0xFB73,0x3D74,0x1B64,0x1A5C,0x1D74,0x3E6C,0xFC5B,0x594B,0x3843,0x5C53,0x3D4B,0x3F74,0xBF84,0xDE6B,0x1C43,0xDD4A,0xDE42,0xBF42,0x3E5B,0xDF6B,0x3E43,0xFC3A,0x562A,0x5221,0x2E11,0x2F19,0x1032,0xEC08,0x3619,0x3C3A,0xDF6B,0xBC63,0xD919,0x9721,0x7221,0x1011,0x6F19,0x7021,0x4C21,0xCA39,0x6A4A,0x2C63,0x0B5B,0x0D5B,0x0F63,0x2A42,0x0431,0x60B0,0x60D0,0x6088,0x6120,0x6100,0x0411,0xA629,0x2100,0x0100,0x0200,0x0200,0x0100,0x0100,0x0100,0x0100,0x0000,0x0100,0x0100,0x2100,0x2421,0xA210,0x6208,0x4118,0x6068,0x6148,0x4529,0x6A4A,0xC739,0x4529,0xA731,0x8831,0x8729,0x4521,0xAE10,0x5909,0xB510,0xF810,0x5811,0xB208,0xD410,0xD721,0xF321,0x9119,0x3311,0xF808,0x5919,0x1A19,0x5E42,0x7F53,0x9F4B,0x5D33,0xB811,0xB509,0xCF08,0x1642,0xDE5B,0xBF7C,0xDF74,0x7F54,0xDC2A,0x7519,0x7621,0xD829,0xDE32,0x7F43,0x3F64,0x7E64,0x5D54,0x1C44,0xF83A,0x762A,0xD629,0xBB43,0x582A,0x1922,0xFE2A,0x9B12,0x7609,0x3309,0x5308,0x9A21,0x1E43,0x5F53,0xBF53,0xBF53,0xFD32,0x5B2A,0x7E43,0x1E4C,0x3B33,0x9609,0x9709,0xF808,0x1A19,0x5E32,0xDF2A,0xBC11,0xDE21,0x1F3B,0x3C32,0x3F5C,0xBC3B,0x3A1A,0xF721,0x7319,0x3611,0xFA19,0x3B29,0xFE39,0xDF3A,0x7D2A,0x9D32,0x5F64,0x9C43,0x7C3A,0x9B3A,0x1F85,0x7C64,0xF94A,0x9632,0x0E19,0xEC10,0x9319,0x3332,0xEA21,0x6A52,0x6A73,0x6B6B,0x4B6B,0x4A6B,0x8A63,0x6B6B,0x4B63,0x6A6B,0x4A6B,0x6A63,0x4A63,}, +{0xC7E7,0xE9EF,0xC9EF,0xC9EF,0xC8EF,0xE9EF,0xE8EF,0xC9EF,0xE8EF,0xC7EF,0xE7EF,0xC7EF,0xE6EF,0xC7EF,0xC9E7,0xCAEF,0xC9EF,0xE8EF,0xC9EF,0xC9EF,0xE9EF,0xE8EF,0xE9EF,0xCAE7,0xCAE7,0xC9DF,0xC9D7,0x88B7,0x29A7,0xA996,0x288E,0xC775,0x0855,0x8844,0x082C,0xA81B,0x071B,0x070B,0x280B,0x2813,0x0823,0x0B3B,0x2E53,0x715B,0x9253,0x7143,0x304B,0x3353,0x9763,0xBA63,0xB95B,0x555B,0xD242,0x703A,0xD23A,0xD34A,0x584B,0xDE7B,0xDF94,0xFE94,0xDF7C,0x1E5C,0x1E64,0xBD63,0xBB5B,0x5A5B,0x1B53,0x3D4B,0x7E53,0xBF6B,0x9F53,0xDB42,0x7832,0x9D4A,0x7B32,0x5C2A,0x7E42,0x9D3A,0x3932,0x9321,0x5011,0xEF18,0xF031,0xD029,0xAD08,0x3719,0x1C32,0xDF73,0x1B4B,0xD521,0x152A,0xB119,0xB021,0x2D19,0x2B21,0x4821,0x8631,0x6F6B,0xAE73,0x0D63,0x2A4A,0xA731,0x0431,0x40A8,0x80D0,0x8098,0x6028,0x4210,0x0419,0xC731,0x0100,0x0000,0x0100,0x0100,0x2000,0x2100,0x0000,0x0100,0x0100,0x0100,0x0000,0x0100,0x2521,0x8208,0x4108,0x6018,0xA060,0x6060,0x0521,0x0B4A,0xA739,0x6531,0xE939,0xE939,0xE831,0xE731,0x6C29,0x1511,0xB510,0xF510,0x1409,0x6F00,0x5210,0x5619,0xDC32,0x7319,0x9621,0x3709,0x3611,0xF410,0x7A19,0x5C19,0x9E3A,0x9F53,0x1E33,0xF611,0xF008,0x1674,0xBF95,0x5F95,0xFF84,0xFF6C,0x5F5C,0xD93A,0x141A,0xB219,0x1611,0xBC2A,0x9E2A,0x3C32,0xBB3A,0x3B3B,0xFA4A,0x5E4B,0x5F5C,0x7F64,0x5F5C,0x5E54,0x9D43,0xBD22,0xDB11,0xB601,0xCD00,0x2C08,0x3310,0x1A3A,0x1E43,0x1F33,0x3A1A,0x1711,0x3E2A,0x5F4B,0xDF53,0xFD32,0xD811,0x3709,0x3709,0xD610,0x5909,0xB400,0x9C09,0x1E22,0x7D22,0x7D53,0x1E5C,0x1922,0xB82A,0x5211,0x3511,0xDD22,0x9809,0xFA10,0x3B21,0xBB21,0x1E2A,0xBF53,0x1933,0xB321,0x993A,0x1E64,0xBE74,0xB842,0xD73A,0x554B,0x6D11,0x0F11,0x6D21,0xC931,0xEA6A,0x4B6B,0x6B6B,0x4B6B,0x8A6B,0x4B63,0x6B63,0x6B6B,0x6A6B,0x4B63,0x4A63,0x4B63,}, +{0xC5E7,0xC6E7,0xC7E7,0xC9EF,0xE8EF,0xE8EF,0xC7EF,0xC8F7,0xC7F7,0xC6F7,0xE7EF,0xC7EF,0xC6EF,0xC6EF,0xC7E7,0xC8EF,0xC7EF,0xE8EF,0xE9EF,0xC9EF,0xC9EF,0xC9EF,0xEAEF,0xCBE7,0xCBDF,0xC8DF,0xC8C7,0xC8C7,0xC8C7,0xA8BF,0x28A7,0xA896,0x2776,0x0866,0xA855,0x4835,0xA83C,0x2824,0x0A2C,0xA933,0x6A33,0x6D43,0x904B,0x367C,0x9B84,0x9B6C,0x5B74,0x7B7C,0x5B6C,0x3B64,0x1C6C,0xDB73,0xD963,0x5853,0x554B,0x5653,0x153B,0x9632,0x1B4B,0xFE73,0xBF8C,0xDF8C,0x5E74,0xFE5B,0x7C63,0xBB63,0x194B,0xBA42,0x3B4B,0xFC63,0x1D64,0xBD5B,0x3A4B,0xD93A,0xFB42,0xDC3A,0xF819,0xD821,0x1A2A,0xB621,0x6F11,0xED08,0xCE08,0x1019,0xF020,0xCE08,0x1921,0xDC39,0x5F5B,0x3C43,0x172A,0x5832,0xD329,0xD231,0x4C19,0x2721,0x4521,0x8C52,0x4F6B,0xAA4A,0x8A52,0xA731,0x8631,0x40A0,0xA0D8,0xC1A8,0x8040,0x4208,0xE418,0xE729,0x4100,0x0000,0x0000,0x0100,0x0000,0x0000,0x0100,0x0100,0x0000,0x0000,0x0100,0x0000,0x0521,0x8208,0x4100,0x6010,0xA070,0x8078,0x8328,0x4541,0x6631,0x2529,0x8831,0xE831,0xC739,0xE831,0x6931,0x5019,0x3811,0x3501,0xAF08,0xAC00,0x2A00,0x1611,0x9A19,0xD709,0x5619,0x5609,0xF308,0x1201,0x7821,0x7C22,0xFB19,0xBC21,0x1C2A,0x9511,0x0E09,0x7031,0xD85A,0x9D6B,0xDF6B,0xFE63,0x9E53,0x5E53,0x5D43,0x1D33,0x9B22,0xB919,0xB508,0x1511,0xB821,0x5611,0xD410,0x3A21,0x1D2A,0x9D3A,0x7E3A,0x1F43,0x7F43,0xDE32,0xDA11,0x1101,0xAA00,0xA600,0x2700,0x0908,0x0E10,0x9108,0xD210,0x6E08,0x1521,0xFE3A,0xDF42,0x3D22,0xDA11,0xB511,0xD100,0x6F08,0xD000,0x6D00,0x5208,0x7B09,0x1D1A,0x7742,0xB832,0x5419,0x3019,0x5111,0xBB21,0xDF43,0xBB1A,0x1309,0xD308,0x9519,0x1C2A,0xFF4B,0x192B,0xB429,0x5E43,0xDB42,0xBC5B,0xBA4A,0x9C5B,0x9E64,0xB42A,0xB221,0x342A,0x934A,0x2C6B,0x4A73,0x6B6B,0x6A6B,0x6B6B,0x4B6B,0x6B6B,0x6A6B,0x6B6B,0x2A6B,0x2B63,0x4B63,}, +{0xC3E7,0xC5EF,0xC6EF,0xE7EF,0xC7EF,0xC6EF,0xC6F7,0xC7EF,0xC7EF,0xE7F7,0xC7EF,0xC7EF,0xC6EF,0xE6EF,0xE8EF,0xC8EF,0xC7F7,0xC7EF,0xE7EF,0xC8EF,0xC8EF,0xC8EF,0xEAEF,0xCAEF,0xEAEF,0xC9EF,0xE8E7,0xC8DF,0xC7CF,0xC6C7,0x86AF,0x469F,0x0797,0xE986,0x4A6E,0xAB3D,0xCC3C,0x0C34,0x6B2B,0xEA2A,0x6E3B,0xF563,0x5A6C,0x9B6C,0xDD7C,0xBE74,0xDE84,0xBF84,0xFF84,0xFF84,0xBF7C,0x5E74,0xFB73,0xDB6B,0x9B6B,0x996B,0x595B,0xF74A,0xB642,0xD842,0xDB4A,0x5D63,0x5D5B,0x5D5B,0x9D63,0x5C5B,0x3A4B,0xF952,0x5B7C,0x5EAD,0x3E95,0xDF7C,0x1F6C,0x5C4B,0x1B3B,0x1E53,0x1D53,0xF619,0x5421,0x9529,0xB319,0x5219,0xCB00,0xCC00,0x9018,0xD218,0xD310,0x5921,0x1E32,0x9F63,0x9C53,0x362A,0x9521,0xB429,0xD129,0x2819,0x4519,0x073A,0x6F73,0xEC52,0xAB52,0x4A4A,0x093A,0x6080,0xA0D0,0xC1C8,0x8060,0x4110,0xA310,0xA729,0x4421,0x0000,0x0000,0x0100,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2521,0x8208,0x2100,0x4010,0x8060,0x8078,0xA841,0xCD52,0x2B42,0x8731,0x4529,0xA631,0x4529,0xA731,0x0832,0x6C19,0xB508,0x3701,0xB408,0xF408,0xAD08,0xD510,0x5811,0x3809,0x1511,0x1411,0xAE08,0xCE00,0xB108,0xB708,0x5B32,0x7B2A,0x7409,0xF008,0x8A08,0x2708,0x4B08,0x9118,0x7510,0x5921,0x9B32,0x392A,0x7A2A,0x7B32,0x9C32,0x792A,0xD319,0x8A00,0x0908,0x2D08,0x4F08,0x9308,0xB500,0xD208,0x7418,0x7A19,0xFD21,0x9E2A,0xFE22,0x3A1A,0xD609,0x7309,0xEE00,0x8700,0x4400,0x0408,0x0508,0x4500,0x6908,0x7310,0x5A19,0x9A11,0xF521,0x122A,0x0F09,0x8A00,0x2900,0xCD00,0x6900,0x5000,0x1501,0xAD10,0x6F11,0x4E11,0xC918,0xEF18,0xDB21,0xFE32,0xDD22,0x3201,0x3011,0xF932,0xDC1A,0xBD2A,0x181A,0xB921,0x5F4B,0xF329,0x783A,0xDE5B,0x7F6C,0x7F64,0xB42A,0xD621,0xBA42,0x134B,0x6C63,0x6A73,0x6B6B,0x6B6B,0x6B6B,0x4A73,0x6B6B,0x4A63,0x6B6B,0x4B6B,0x4B63,0x4A63,}, +{0xC3DF,0xC4DF,0xC5E7,0xC4E7,0xC4EF,0xC5EF,0xC6EF,0xE6EF,0xE8F7,0xC8F7,0xE7F7,0xC6EF,0xC6EF,0xC6EF,0xC7EF,0xC7F7,0xE7EF,0xC8F7,0xC8EF,0xC7EF,0xC7F7,0xC8F7,0xEAEF,0xEAEF,0xE9EF,0xC8EF,0xC7E7,0xC7DF,0xC7D7,0xC6C7,0xC6B7,0x86A7,0x0897,0x2A7E,0x4C55,0x6E3C,0xCD2B,0x2C23,0xAB2A,0xCC32,0x9153,0xD963,0x3E7C,0xFF94,0x7FA5,0xBFAD,0xFFAD,0xBFA5,0x7F9D,0x5F8D,0xFF7C,0x9F7C,0x1E64,0x994B,0x574B,0x185B,0xB73A,0xD73A,0x7742,0x5842,0x363A,0x773A,0x783A,0x7732,0x9742,0xDB52,0x1B5B,0x7842,0x7632,0x996B,0xFFBD,0xDFB5,0x3F95,0xBF7C,0xDE53,0x7E43,0xBC4A,0xFD4A,0x151A,0x2E09,0x3111,0xB829,0x3009,0x8900,0xAE10,0xCF10,0x3219,0x5711,0x7B19,0x7D3A,0xDF6B,0xFA3A,0xB621,0x7321,0xB329,0x9029,0x2621,0x473A,0x1174,0x1274,0xE839,0x6B4A,0xED5A,0x0459,0x60B8,0xA0C8,0xC090,0x2030,0x4308,0x2521,0xE731,0x4000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0100,0x0100,0xA208,0x2519,0x6110,0x2000,0x4010,0x4060,0x4088,0x4330,0xE730,0xE728,0xE528,0x4529,0x8629,0xE831,0x4B21,0x0B32,0xAC29,0xB300,0x5000,0x9500,0xB500,0x9100,0xB308,0x1811,0x1711,0x7208,0xB008,0xCA00,0x8908,0x8A10,0xB108,0xD508,0xD308,0xCF08,0xEC10,0x0A09,0xEB08,0xCC08,0x4C00,0x9110,0x3409,0xCF10,0x5019,0x5211,0xF510,0x3719,0x9819,0xF921,0x1512,0x4E09,0xC708,0x6708,0x0F09,0x1311,0xB619,0xCE10,0x5511,0x5919,0x3E2A,0xDF32,0x1F33,0x9F2A,0x7D22,0x3812,0x9111,0xB111,0x9111,0x2D09,0x0A01,0xC600,0x0608,0x2D00,0x6E00,0x2A00,0x6808,0x2400,0x0300,0x0300,0x2700,0xAC08,0xAC08,0x8B08,0x4608,0x8608,0x4710,0xA518,0xEC20,0xB829,0xDE2A,0x1E1B,0x1509,0x7611,0x1D33,0xBA22,0x9611,0x3511,0x7B19,0xFE3A,0x7029,0x9B3A,0x7E53,0x1E53,0x9F53,0x7B53,0x7A32,0xFC42,0x565B,0x6B6B,0x8B6B,0x6B6B,0x6B63,0x6B6B,0x4B6B,0x6B63,0x6B6B,0x4B63,0x4A6B,0x4B63,0x4A63,}, +{0xC4E7,0xC7EF,0xC6EF,0xC6EF,0xC6EF,0xC6EF,0xC6EF,0xE7EF,0xC7EF,0xC7F7,0xC7F7,0xC6EF,0xE6EF,0xC7EF,0xE7EF,0xE7EF,0xC6EF,0xC8EF,0xC8EF,0xE7EF,0xC6EF,0xC6F7,0xC9EF,0xCAEF,0xC9EF,0xC8E7,0xC7E7,0xC8DF,0xC7D7,0x67C7,0xC6A6,0x2796,0x8A7D,0xAC5C,0xED43,0x6E33,0xAD2A,0x6A22,0x4B2A,0x8B3A,0xCF42,0xD54A,0x5A53,0xDD6B,0x7F84,0xDF8C,0x3F9D,0x3F9D,0x5F9D,0x7FA5,0xFF8C,0xDF84,0x7F7C,0x3D74,0xD963,0x1653,0xF33A,0x964A,0x3232,0xD121,0x9321,0xD431,0x363A,0x1432,0x1232,0x132A,0x163A,0x3742,0x5632,0x3432,0xDA6B,0x3FA5,0xFF84,0x9F84,0xBF84,0x3F64,0x7E4B,0xBC42,0x3E5B,0x342A,0x0C01,0xD629,0xB519,0xEA08,0x8A08,0xEE10,0x7429,0xB619,0x5711,0xBB21,0xF921,0xF931,0x9721,0x9519,0x5319,0x7129,0x6C29,0x4942,0x1174,0x127C,0x063A,0xC639,0xCE5A,0xA849,0x6090,0xA0B8,0x60A8,0x0050,0x4110,0xA310,0x6629,0x6421,0x2000,0x0000,0x0000,0x0000,0x0100,0x0100,0x0000,0x0100,0x0100,0x2311,0xA310,0x6100,0x2108,0x2010,0x2060,0x2080,0x4130,0x0421,0xE328,0xE320,0x0429,0x083A,0xED52,0x2921,0x8810,0xAB10,0x9200,0x4C00,0x6D00,0x8F00,0x2D00,0x2E00,0x9210,0xD208,0xCD00,0x6900,0xC600,0x8608,0x4608,0x4A10,0x4C00,0xEF08,0xCC08,0xEC18,0x7319,0x9711,0x1309,0xB200,0x4F00,0x2C00,0x8D08,0x5319,0x3B2A,0xFE2A,0x9C22,0xD911,0x7809,0x7511,0x5119,0x2A09,0x2A09,0xEE08,0x9321,0x7611,0x5311,0x7519,0x1D1A,0x7F2A,0x3F43,0x3F3B,0x9F32,0x3D1A,0xB719,0x1011,0x7611,0x7809,0x5509,0x0F01,0x8700,0x2200,0x0600,0x8B00,0xCC00,0xEA00,0x8500,0x4400,0x8500,0x4500,0x0400,0x2708,0xE810,0x0609,0x6108,0x4210,0xC418,0x2921,0x3411,0x7A01,0x3A0A,0x1509,0x5709,0x7D22,0xB711,0xD711,0xF611,0x7A19,0x7932,0x6D21,0xB429,0x142A,0xB619,0xBB29,0xBC3A,0xFA42,0xD83A,0x555B,0x6C6B,0x6B6B,0x6A6B,0x6A63,0x4B6B,0x6B6B,0x8A6B,0x4B63,0x4B63,0x4A6B,0x4B63,0x4B63,}, +{0xC4E7,0xC6E7,0xC6E7,0xC6E7,0xC7EF,0xC7EF,0xC7EF,0xC8EF,0xC8EF,0xE7EF,0xE7EF,0xE7F7,0xC8F7,0xC9EF,0xE9EF,0xE8EF,0xC8EF,0xC8EF,0xC7EF,0xE7EF,0xC6EF,0xC6EF,0xC8EF,0xCAEF,0xCAEF,0xC8E7,0xC6DF,0xA5BF,0x05A7,0x46A6,0xC695,0x6785,0xA96C,0xAA53,0x0B43,0xAC2A,0x0C1A,0x291A,0x091A,0x0922,0x4B22,0x6E2A,0x722A,0xD63A,0xD842,0xDB4A,0x5C53,0x5D5B,0xDE5B,0xFE6B,0xDD63,0xFD6B,0xFC73,0xFB6B,0x9A73,0x375B,0x3563,0xB54A,0x5342,0x112A,0xCF19,0xCF21,0x6E11,0x4E11,0xB031,0xD029,0xAF29,0x9021,0xD529,0x1532,0x7532,0xFD9C,0x5C6B,0x3E53,0xBF63,0x5F74,0x7F74,0x9E53,0x3D4B,0x7E53,0x7953,0xAF11,0x5532,0x101A,0x0801,0xED10,0x1121,0x9521,0x9821,0x7819,0x9921,0x7421,0x3519,0x3319,0xF218,0x4C21,0x4D21,0x2B3A,0xB06B,0x8F63,0xEB5A,0xE639,0xE941,0x6B4A,0xC270,0x60B0,0x60C8,0x2088,0x2030,0x6110,0xA218,0xA529,0x8521,0x4000,0x0100,0x0100,0x0000,0x0100,0x0000,0x2000,0xA310,0xE318,0x6208,0x4108,0x2008,0x2028,0x4078,0x0070,0x8230,0x093A,0xE731,0x6631,0x8529,0x8B4A,0xC939,0xE729,0x6408,0x8508,0x4A08,0x2A08,0x2E11,0x2A09,0x2508,0x8908,0xCC08,0x8D08,0x8910,0x8508,0x6608,0x8B00,0xCF10,0xCE00,0xCC00,0x0B09,0x5009,0xF008,0xD410,0x3811,0x3701,0x3509,0xB108,0xF000,0x8900,0x2C00,0x7610,0x3C11,0x9D21,0xBC19,0xFB11,0x7819,0xD110,0x2C09,0x3111,0x1B1A,0x3B2A,0xD811,0x5609,0x9308,0xF710,0xBD19,0x3E22,0xBD19,0x9C11,0x3709,0xAE00,0x6C08,0x181A,0x7C1A,0x5A1A,0x1309,0xCC00,0x2100,0x2108,0x6410,0x8910,0x6808,0xA500,0x4408,0x0A11,0x4D19,0xE808,0x8300,0x8310,0xC310,0xA210,0x6210,0xA318,0xA518,0x8C00,0xF100,0x2F01,0x8F08,0x1409,0x9711,0xF610,0x5C12,0x1612,0xB110,0xF329,0x6B21,0x2C19,0x5019,0x3309,0x7A2A,0x3D43,0xF742,0x7632,0xF15A,0x4C6B,0x6B6B,0x4B6B,0x4A63,0x4B6B,0x4B63,0x6A63,0x4A63,0x4B6B,0x4B63,0x4B63,0x4B63,}, +{0xC5E7,0xE8EF,0xC8E7,0xC7EF,0xE8EF,0xE7E7,0xC8EF,0xC8EF,0xE8EF,0xC7EF,0xC6EF,0xC6EF,0xC9F7,0xC9EF,0xC9EF,0xC9EF,0xC8EF,0xC8EF,0xC7EF,0xC7EF,0xC6EF,0xC6EF,0xC6EF,0xE6EF,0xE6E7,0xC5D7,0xC4D7,0x43C7,0xC4B6,0x46AE,0xA695,0x0785,0x2764,0x6A43,0xCB3A,0x6D2A,0x8C22,0x8C22,0x6B22,0xCB2A,0xCD42,0xEF3A,0xF242,0xD33A,0xD442,0x953A,0x943A,0xD642,0xD83A,0xD842,0x1743,0xF84A,0x3753,0x564B,0xF64A,0xD342,0xB24A,0x713A,0x3242,0x133A,0x322A,0x7442,0x3232,0xF029,0x303A,0x0E2A,0x313A,0xB029,0xAF21,0x8F29,0xB231,0x363A,0xF721,0xB719,0xFC31,0x1F53,0x9F5B,0x7E63,0x5F53,0xFE4A,0x5E53,0xFD5B,0x1C5C,0xBEBE,0xB77C,0x4909,0xEB08,0xF110,0x7619,0x9419,0x1319,0x1419,0x3219,0xD010,0xEF18,0xED18,0x6B19,0x8919,0xEE5A,0x727C,0x5184,0xA952,0xE741,0x4A42,0x6B5A,0x6098,0x80C0,0x60C0,0x6080,0x6030,0x6210,0xC410,0x8731,0xA631,0x4411,0x8208,0x4000,0xA208,0xE108,0x0311,0xE410,0x8208,0x4108,0x4008,0x2010,0x2048,0x4078,0x0068,0x2429,0x8629,0xE420,0xE428,0x8B4A,0x293A,0x083A,0x6942,0xE518,0x0621,0x2519,0x4408,0xAC21,0xE808,0x6300,0x2408,0xAC08,0xEA08,0x4500,0x8508,0x4808,0x8F00,0x7208,0x8F00,0xAE00,0xEF08,0x5311,0x5709,0xF508,0xD608,0x5709,0xF200,0xB200,0xF408,0x1009,0x0E01,0x1101,0x9709,0x1609,0xD608,0xF808,0xD708,0xF108,0x0E09,0x2E08,0xB400,0xF910,0x5909,0x3809,0x7701,0xF200,0x9208,0x7611,0x5811,0x3701,0x8E00,0x4700,0x0608,0xB010,0x9719,0x391A,0x7109,0xC808,0x4108,0x8018,0xE218,0xE318,0xA210,0x8110,0x2108,0x4210,0x6418,0xA410,0x8308,0x6210,0x6110,0x4108,0x8218,0xA318,0x4610,0x0D1A,0x8800,0x6800,0x8C08,0xD219,0xCC08,0xD508,0x1D12,0xF309,0x4910,0xF521,0x0711,0x2919,0xAD10,0x7411,0xBB42,0xD942,0xD132,0x934A,0x0D63,0x4B6B,0x4B6B,0x4B6B,0x6A6B,0x6A6B,0x6C6B,0x6A5B,0x6A63,0x6A6B,0x4B63,0x6A6B,0x4A6B,}, +{0xC5E7,0xE6EF,0xC7E7,0xC6E7,0xC6EF,0xE6E7,0xC7EF,0xE8EF,0xE8EF,0xC7EF,0xE6EF,0xC6EF,0xC8F7,0xC8EF,0xC9EF,0xE8EF,0xC8EF,0xC7EF,0xC7EF,0xC6EF,0xC5EF,0xC4EF,0xC4EF,0xE4EF,0xC4E7,0xC4DF,0xA3D7,0x63D7,0xE4BE,0x45AE,0x8695,0x8774,0xE853,0x6933,0x2D43,0xAE3A,0x0C33,0x2E3B,0x7043,0xB25B,0x9263,0x725B,0x7453,0x5553,0x145B,0xD44A,0xD342,0x733A,0x7332,0x3232,0x322A,0x533A,0xB54A,0xB442,0x1353,0x5563,0x334B,0xB242,0x7142,0x503A,0x712A,0x523A,0x344A,0x122A,0x112A,0xF239,0x103A,0x9021,0xB231,0x9029,0x8F29,0x2D21,0x7119,0x7421,0x7519,0x7819,0xDC39,0x3C2A,0xBD42,0x7D4A,0x7C3A,0x5F53,0xDF74,0xDFB5,0xFFB5,0x3B85,0xD132,0xEC08,0x3211,0x7621,0x7319,0x0F09,0x3209,0x0F11,0xED18,0xEC10,0x2909,0x2711,0x2721,0x9073,0x7384,0x4D63,0x2842,0x0A3A,0xB473,0x095A,0x4098,0x60B8,0x40B8,0xA070,0x6030,0x8108,0x8310,0xC520,0x6529,0x6631,0x6521,0x6729,0x2419,0xA210,0x8208,0x6008,0x4008,0x4008,0x2028,0x2060,0x0078,0x2048,0xC418,0xA739,0x6629,0x293A,0xF263,0x683A,0x093A,0x4942,0x8529,0x6410,0x0521,0xAC4A,0x8D32,0x8408,0x4400,0x6400,0x4700,0x4708,0x6500,0x2700,0x4900,0x6E00,0x7000,0x8F00,0xAE00,0x6E00,0x2F08,0x9400,0x1709,0xD608,0x5100,0x4F08,0x2D00,0x2E00,0xB021,0xF221,0xF400,0xF608,0xD600,0xB308,0x9108,0x5409,0xF811,0x9611,0x7511,0x7609,0xD610,0xB308,0xF400,0xF308,0xB100,0xAC00,0x4A11,0x8B10,0x4B00,0x4600,0x0200,0x0108,0x4408,0x4910,0x6C08,0x8B00,0xCA10,0x2719,0xE118,0xE228,0x0229,0x0219,0xC218,0xC118,0x8018,0xC220,0x2421,0x8310,0xC210,0xC110,0x8118,0xC218,0xE210,0x6810,0x6F2A,0x8500,0x4508,0x5109,0xFA2A,0x2C11,0xB410,0xB801,0x5009,0x8810,0xAC10,0xA508,0x2A21,0xEF20,0x3832,0xB842,0x723A,0xCE4A,0xCB5A,0x4B63,0x4B63,0x4A6B,0x6A6B,0x6A6B,0x4A6B,0x2B6B,0x6A63,0x4A63,0x6A6B,0x4A63,0x6B6B,0x4B63,}, +{0xC5E7,0xE5EF,0xC5EF,0xC6EF,0xE5EF,0xC6EF,0xC7EF,0xC7EF,0xC8EF,0xC6EF,0xC6EF,0xC6E7,0xC6EF,0xE7EF,0xC8EF,0xC9EF,0xE8EF,0xC7EF,0xC6EF,0xC6E7,0xC5EF,0xC4EF,0xC4EF,0xE4EF,0xC4EF,0xC5E7,0xC5DF,0x65CF,0xA5B6,0xC495,0xE574,0x485C,0xA853,0x683B,0x8B43,0x8E43,0x8F53,0x914B,0xB353,0xB563,0x935B,0x725B,0x5453,0x365B,0x144B,0x1453,0x1453,0x144B,0x5653,0x3543,0xB23A,0xB23A,0xB33A,0xB54A,0x1563,0xF973,0x9E8C,0xBC84,0x1964,0x975B,0xD33A,0x3132,0x1032,0x7442,0x723A,0xCE31,0xB029,0xAF29,0x6E29,0x4F21,0x4C21,0x8D29,0x6E29,0x5021,0x7421,0x7421,0x5519,0x9719,0xB921,0xD931,0xFA29,0xDF42,0x3D32,0xDD3A,0x3E6C,0x1F8D,0xBE7C,0xB632,0x2E09,0x3419,0x7421,0x6F11,0x5019,0x2E09,0x2D11,0x4B11,0x0709,0xE518,0xC410,0xA831,0x5484,0x327C,0xEA4A,0xCE52,0x5363,0x347C,0xE861,0x40A0,0x20C0,0x40A8,0x6070,0x6038,0x4020,0x6218,0xA310,0xA310,0x8310,0x6410,0x6210,0x4108,0x4108,0x2010,0x2010,0x4028,0x4060,0x4078,0x2060,0x2531,0x0421,0xE520,0xA939,0x6C42,0x4B42,0xCB4A,0x083A,0xE731,0x6531,0x6629,0xE618,0xEB39,0x4B3A,0x6308,0x4308,0x6600,0x2500,0x2508,0x2600,0x2700,0x4A00,0x6D00,0x4F00,0x2D00,0x2A00,0x0700,0x2B08,0x9219,0x9208,0x5100,0x8E00,0x0900,0x0500,0x0900,0x8B08,0x0F19,0x5419,0xB819,0xB911,0x7509,0xEF08,0xF408,0x1A09,0x7A11,0x3709,0x3609,0x1501,0x9000,0x8F00,0xF000,0xEE00,0x2700,0x2300,0x0300,0x0200,0x0100,0x4010,0x8010,0x8018,0x6118,0x6318,0xA318,0xE418,0xC510,0x8110,0xC228,0xA639,0xA529,0xC220,0x2329,0x2329,0xA631,0x6A42,0xE739,0x6529,0x4421,0x2329,0x6429,0xC318,0x8708,0xAA19,0xE508,0x8A08,0x791A,0xFB12,0x0B09,0xAE00,0x9000,0xCF00,0xA508,0x8508,0x0911,0x8700,0x8808,0xCC08,0xEA08,0x8F21,0x6D4A,0x095B,0x4B63,0x4B63,0x6B6B,0x6A6B,0x6A63,0x4A6B,0x4B6B,0x6B63,0x6B6B,0x4B6B,0x4A63,0x6A6B,0x2A6B,}, +{0xC6E7,0xC5E7,0xC6EF,0xC6EF,0xC7EF,0xC6EF,0xC7EF,0xC7E7,0xC7EF,0xC6EF,0xC5EF,0xC6EF,0xE6F7,0xC7F7,0xC8F7,0xC8EF,0xC7E7,0xC7EF,0xC7EF,0xC6E7,0xC6EF,0xC5EF,0xC4EF,0xC4EF,0xE4EF,0xC5E7,0x84CF,0xC3BE,0xE49D,0x057D,0x2554,0xC94B,0xC84B,0xE93B,0xEA3B,0xEC33,0xCE3B,0xAF3B,0x903B,0x3243,0x3243,0x1243,0x123B,0xD232,0xF242,0x5353,0x755B,0xB75B,0xB95B,0xBA63,0x796B,0x7853,0x3753,0xB53A,0x7232,0x174B,0x7D6B,0x3F7C,0x1F9D,0x5F9D,0xBD7C,0xDB5B,0x3743,0xD642,0xD54A,0x7142,0x7042,0x514A,0xCE31,0x6C21,0x8D21,0xCF29,0xB021,0x9131,0x5019,0x0F11,0x1219,0x5329,0x3419,0x5519,0x7719,0x3821,0xDA21,0x3C22,0x9A3A,0xDD63,0x9E5B,0xDC4A,0x5853,0x3653,0x3A4B,0x3B43,0x962A,0x542A,0xF029,0x8D21,0x0611,0xC318,0xA210,0xC410,0xA941,0x3484,0xB48C,0x8A4A,0x0C42,0x736B,0x3063,0xC759,0x0090,0x00A8,0x00A8,0x4088,0x4068,0x8050,0xE140,0x8138,0x6118,0x6118,0x4018,0x2018,0x4018,0x2020,0x4038,0x6058,0x4078,0x2070,0x6140,0xE931,0x8729,0xE320,0x6729,0x4B42,0x4A4A,0xAB4A,0x0842,0x083A,0x4421,0x4621,0xE418,0xA418,0x2621,0x4419,0xA508,0x8308,0x2200,0x2300,0x4508,0x6800,0x2800,0x4900,0x2A00,0x2A00,0x2800,0x4600,0x4A00,0xF039,0xAE31,0xAF11,0x3201,0xAE00,0xA800,0x8800,0x6900,0x2A00,0x4E10,0x6F08,0xB110,0xCF08,0x8B00,0x4E08,0x7300,0x9500,0xB500,0xF308,0xF300,0xF208,0xEF08,0x8A00,0x6600,0x6400,0x4200,0x4100,0x4108,0x2008,0x8210,0xA410,0xE410,0xA218,0x0321,0x2431,0x4431,0xA639,0xC639,0xA531,0xAC52,0x6E5B,0x4942,0x894A,0xAA4A,0xEB52,0x6F63,0xEC5A,0x6531,0xC410,0x2429,0x6531,0x4629,0xC710,0x2A32,0x4521,0xAB18,0xD609,0xB409,0x8808,0x6700,0x4A00,0x8D08,0xA308,0xC410,0xC308,0x6400,0x8908,0x0B09,0x6C11,0xD031,0xAD5A,0x4A63,0x6B6B,0x6B6B,0x6B73,0x4B73,0x6B6B,0x2B6B,0x6B6B,0x6C63,0x4B6B,0x6B6B,0x4A6B,0x4A6B,0x4A6B,}, +{0xC5E7,0xC5E7,0xC6E7,0xE6EF,0xC7EF,0xC7E7,0xC7EF,0xC7E7,0xC6EF,0xC6E7,0xC5E7,0xC5EF,0xC6F7,0xE7EF,0xC7F7,0xC8EF,0xC7EF,0xE7EF,0xC6EF,0xC5E7,0xE5E7,0xC5EF,0xE4EF,0xE4E7,0xC4E7,0xC4DF,0xE4BE,0x23A6,0x6475,0x645C,0xC543,0x0A5C,0x495C,0x694C,0x6A44,0x2E4C,0x104C,0x3144,0xB24B,0x7243,0x7143,0x9453,0x764B,0x7543,0x5553,0x9463,0x5774,0x9B7C,0x7D74,0x3A64,0xDA53,0xFD63,0x9A5B,0xBA6B,0x5753,0xB542,0x963A,0xBB42,0x7E63,0x5F7C,0xDF8C,0x1F8D,0x7D6C,0x9B53,0x173B,0xF542,0x9432,0x112A,0xF339,0xD341,0x7029,0x6D21,0x6E21,0x4F21,0x3121,0x7021,0x4E19,0xCD08,0xAF18,0xD010,0xB108,0x1419,0x3721,0x5719,0xB821,0xB921,0x9719,0xFB21,0x1822,0x3B42,0x7E5B,0x9F6C,0xFF5B,0xBE53,0x1D4B,0x792A,0xD019,0x2811,0xC310,0xA210,0xE420,0x0D5B,0x5484,0x4E63,0xA739,0x4E42,0x5163,0x7584,0x8B52,0x4070,0x00A0,0x00A8,0x20B0,0xC0B0,0xC0A0,0x2089,0x0071,0x4058,0x6050,0x6048,0x6040,0x6050,0x4068,0x0070,0x0060,0x0339,0xC731,0x8731,0x0A3A,0x4B42,0x8B42,0x8831,0x4942,0xC731,0xE739,0x2942,0x6529,0xC218,0xA318,0xC420,0x6731,0xE939,0x4519,0x6210,0x8310,0x6308,0x4300,0x4600,0x4600,0x2600,0x4900,0xC800,0x0600,0x2500,0x4800,0x0A10,0xAC4A,0xAA29,0x8F00,0xF000,0xAB00,0x6800,0xCA00,0x0B01,0xEE00,0xAC00,0xA900,0x4900,0x4808,0x2900,0x6B08,0xAF08,0xB008,0x0F11,0xF108,0x3109,0x9209,0xD511,0xF409,0xAF01,0xE800,0x8300,0xE810,0x1433,0x3933,0x5A33,0xCE19,0x0421,0xE631,0xC539,0x4431,0xEC5A,0x8F6B,0x906B,0xD273,0xF273,0xB063,0xD173,0x7384,0x9384,0xD073,0x0C5B,0xCA42,0x6529,0x6B4A,0xAA4A,0xA831,0x0521,0xA318,0xE420,0x8710,0xAB00,0x0B09,0x8310,0x4200,0x0900,0xC618,0xA621,0x0419,0xA210,0x6508,0x6808,0xEF18,0xB529,0x763A,0xCD5A,0x4A63,0x4B6B,0x4B6B,0x6B6B,0x4B6B,0x6A6B,0x4B63,0x4B63,0x6A6B,0x4B6B,0x6B63,0x4B6B,0x4B63,0x0B63,}, +{0xE5E7,0xE4E7,0xC5E7,0xC7EF,0xC7E7,0xC7E7,0xC7E7,0xC7E7,0xC6EF,0xC5E7,0xC5EF,0xC6EF,0xC7EF,0xC7F7,0xC6EF,0xC7EF,0xC6EF,0xC6EF,0xC5E7,0xC5E7,0xC4E7,0xC3EF,0xC3E7,0xC3DF,0xC3DF,0x42C7,0x82A6,0xA38D,0xC464,0x455C,0x085C,0x4A64,0xAB64,0xEB5C,0x8D54,0x2D44,0x5154,0x1364,0x1554,0xF65B,0x5864,0x3964,0x195C,0xF963,0x1964,0x197C,0x5A7C,0x3D7C,0x7E74,0x1F9D,0x3F95,0xBD84,0x1B6C,0xFB63,0xDB6B,0x995B,0xF742,0xB52A,0x763A,0xDC52,0xBE63,0x3F74,0xBF7C,0xBF8C,0x3D6C,0xFB5B,0x9A5B,0xF94A,0x332A,0x9021,0x7121,0x2F19,0x8F21,0x9231,0xB029,0xB121,0x9019,0x6F19,0x6D19,0x2E19,0x0E19,0x2E11,0xCE08,0xB010,0x3511,0x5721,0x7721,0x3611,0x1311,0x5411,0x7A11,0x7E42,0xDF73,0x9F7C,0x5F6C,0x5E43,0x9721,0x7111,0x4B09,0xE908,0xC410,0xCD5A,0x3284,0x4D5B,0x484A,0xC831,0x8F52,0x3263,0x3574,0xD16B,0x0852,0x2070,0x0090,0x40A8,0x80A8,0x40A0,0x20B0,0x2098,0x4090,0x6078,0x2078,0x4070,0x0060,0x2050,0x0531,0x346C,0x6C42,0xA629,0x8929,0xEA31,0xEE4A,0x293A,0xA731,0xA531,0x083A,0x4529,0x0219,0xA220,0xC218,0xC318,0xE418,0x2521,0xE410,0xE318,0xA318,0x8218,0x8210,0x6300,0x4200,0x2208,0x2508,0xE608,0x2500,0x4400,0x4500,0x2500,0x0300,0x0200,0x0500,0x0900,0x6C00,0x6900,0x8700,0x4800,0x8C00,0xCD00,0xAC00,0x6900,0x2608,0x6900,0x2808,0xEA10,0x8F21,0xF029,0xD511,0xB711,0x9709,0x9509,0x3309,0xCD00,0x6500,0xE418,0xD129,0x9832,0x9431,0x2F21,0x6731,0xC539,0x4942,0xEC52,0xEC52,0xEE5A,0x0F63,0xAD5A,0x4B4A,0x2C52,0x6C5A,0x6C5A,0x6C52,0xAC52,0x6C5A,0x9073,0x6F63,0x0C5B,0x4F6B,0xEB52,0xE420,0xC218,0x2429,0x4429,0x8108,0x4310,0xC418,0xC320,0x6521,0xC518,0x8A3A,0x6A3A,0x2529,0xA218,0x8508,0xC808,0xE900,0x0C11,0xCE31,0x6B4A,0x0A63,0x4B6B,0x6B6B,0x6C6B,0x6B6B,0x6A6B,0x4B63,0x4B6B,0x6A6B,0x4B6B,0x4A6B,0x2B63,0x4A6B,0x4A63,}, +{0xC3DF,0xE3E7,0xC5E7,0xC8EF,0xE9E7,0xC8E7,0xC7E7,0xC7E7,0xC6E7,0xC5E7,0xC5EF,0xC5E7,0xC6EF,0xC7F7,0xC6EF,0xC7EF,0xC5E7,0xE5E7,0xC4E7,0xC4E7,0xE3E7,0xC3DF,0xC3D7,0x82C7,0x42BF,0xA2A6,0x018E,0x826D,0x2565,0xC764,0x885C,0x8A64,0xA95C,0xA954,0x8C54,0x0E4C,0x3254,0x1364,0x576C,0x5B7C,0xBE7C,0xFE8C,0xFE7C,0xBE74,0x9E74,0x5D7C,0x3B74,0x1D74,0x3E64,0x9F84,0xFF8C,0x9F84,0xBF8C,0x9E84,0x3D6C,0x1C6C,0xBC5B,0x5B5B,0xD84A,0x152A,0x373A,0xBA4A,0x1D74,0xBF84,0xFF8C,0x9E7C,0xDB63,0x3943,0xD74A,0x974A,0xD321,0x9121,0x9321,0x0F21,0x0E19,0x7029,0xB129,0x9019,0x9029,0x7321,0x5411,0x7219,0x2F19,0x6E19,0xED10,0xD010,0xF318,0x3311,0xF010,0xCD08,0xD310,0x3A21,0x1D32,0x9F63,0x5F7C,0xDF5B,0x9C3A,0x182A,0xD211,0x4F09,0x2909,0x6821,0xF383,0xF073,0x4842,0xE639,0x2439,0x4831,0x115B,0x115B,0xD46B,0xF063,0x684A,0xA150,0x2070,0x0078,0x0080,0x0080,0x0078,0x0070,0x2068,0x6148,0xA649,0xE949,0xE528,0xF15A,0x8931,0x2A42,0x8C4A,0x8C52,0xCE4A,0xA731,0x4621,0xC739,0xA631,0x4429,0x2321,0xC220,0x2429,0xE318,0xC210,0x2419,0xE310,0x8310,0x8410,0xA318,0x0529,0x6519,0x8308,0x4108,0x4208,0x4208,0x4400,0x4500,0x6600,0x2400,0x2200,0x4200,0x4400,0x2500,0x0700,0x4900,0x4800,0x6600,0x2600,0x4900,0x6A00,0x2700,0x6608,0x4A19,0x4C2A,0x0D2A,0xCD08,0x4A00,0x2A00,0x2C00,0x2D00,0x4900,0x2700,0x4500,0x4200,0xEC10,0x9221,0x0B21,0x0A42,0xA631,0xA639,0x0842,0x0C53,0xEE52,0x916B,0xEC52,0xA739,0xA739,0x4531,0xE430,0xE530,0x4531,0x4539,0x2531,0x8739,0xEA41,0x2F63,0x127C,0xB06B,0xAA42,0xE631,0xE639,0x283A,0xE629,0xC318,0x8629,0x2429,0x6531,0xE839,0x8B4A,0xAD4A,0x8C4A,0x4529,0xE318,0xA408,0xA508,0x2921,0xA929,0x4942,0xC952,0x2A63,0x4B6B,0x6B63,0x6B63,0x6B6B,0x6B6B,0x6B6B,0x4A6B,0x4A73,0x4B63,0x4B6B,0x4A63,0x2B63,0x6A6B,}, +{0xC3E7,0xC3DF,0xC5DF,0xE8E7,0xCAE7,0xE8E7,0xC6E7,0xC7E7,0xC6E7,0xC5EF,0xC5EF,0xE5EF,0xC7E7,0xC7EF,0xC8EF,0xC7EF,0xC6E7,0xC6E7,0xC6E7,0xC4E7,0xC3DF,0xC3D7,0x83BF,0x02AF,0xC29E,0x628E,0xE285,0xA37D,0x457D,0x0775,0xC85C,0xEA6C,0xE96C,0x8854,0x4B44,0x4E3C,0x915C,0x325C,0xB55B,0xBA5B,0xFD63,0x3F7C,0x9F84,0xBF84,0xDF94,0xFF8C,0x1E7C,0xDD73,0xDD6B,0x3F7C,0x9F8C,0x5F7C,0x1F6C,0xDE63,0xDE6B,0xBB5B,0x1A53,0xF94A,0xD842,0x763A,0x132A,0x142A,0x7842,0x3D53,0x5F7C,0x1F95,0x1F95,0xBE84,0x9A53,0xB942,0x5742,0x363A,0xD221,0x5111,0x1011,0xCC08,0xAB10,0xEA10,0xAB18,0xD118,0x1619,0x7719,0x7419,0x7219,0x7219,0x5111,0xEE08,0xAD08,0x8B18,0x8A08,0xAB08,0x1409,0x5819,0x5A19,0x1F4B,0x1F64,0xFF5B,0x9E4B,0xFD42,0x592A,0xB219,0xAE19,0xAC39,0xD083,0x117C,0xCA4A,0x0842,0x0942,0x2829,0x4A29,0xF15A,0x1574,0x967C,0x1274,0xEE5A,0x0842,0x6439,0x4439,0xE338,0x8639,0x2942,0x6C4A,0xAE4A,0xEC41,0x0429,0xAE52,0x0B42,0x8C4A,0x2A42,0x8839,0x2529,0x4421,0x6529,0x4731,0x2942,0x2629,0x2431,0xE228,0x2529,0x2421,0xC210,0x6729,0x2521,0xE310,0x6310,0xA210,0xA318,0x8729,0x0419,0x6208,0x4108,0x4108,0x2208,0x4308,0x4300,0x0200,0x0100,0x2300,0x6300,0x0300,0x2300,0x0500,0x2600,0x4500,0x2200,0x0100,0x0100,0x0100,0x0208,0x2610,0x8A29,0x2A19,0x4900,0x4900,0x2800,0x0600,0x0500,0x2400,0x6F09,0x2B09,0xC610,0x9021,0x8B29,0x6531,0x8952,0x2842,0x084A,0xCC5A,0x0E5B,0x4A4A,0xE949,0xA749,0x8539,0x0231,0xE128,0xA030,0xC128,0xE228,0xE228,0x2431,0x4531,0x0942,0xCD52,0xCD62,0x4F6B,0xD073,0x6E63,0x6F6B,0xF584,0x1074,0x106C,0x4B4A,0x937C,0x4C63,0xE839,0x6731,0x4729,0x8729,0x0329,0x2429,0x0411,0xA410,0x4729,0x684A,0x884A,0xCA5A,0x2A63,0x6B6B,0x4B6B,0x4B63,0x6A6B,0x6A6B,0x6A63,0x4B6B,0x4B6B,0x4A63,0x4A5B,0x4963,0x2A6B,0x2B63,}, +{0xC4E7,0xC4DF,0xC5DF,0xC8E7,0xC9EF,0xC9E7,0xC7E7,0xC6DF,0xC6E7,0xC5E7,0xC4EF,0xC5EF,0xC7EF,0xC8EF,0xC8E7,0xC7EF,0xC7E7,0xC7EF,0xC6E7,0xC5DF,0xC4CF,0x83C7,0x42B7,0x01AF,0xC2A6,0x8296,0x2396,0xE48D,0x8585,0x0575,0xE76C,0x0B6D,0x0B6D,0xE94C,0x4A55,0x2C5D,0xB064,0xB253,0x353B,0xFA4A,0xDB42,0xBB42,0xBD42,0xDC42,0x5D5B,0x7C5B,0x3B53,0x9C6B,0x7A63,0x7A5B,0x9D6B,0xDE73,0xBF73,0x5C5B,0x1A4B,0xF94A,0xD742,0xD742,0xB73A,0x553A,0x7532,0x7642,0xB63A,0xDA42,0xFC4A,0x5E4B,0xFF73,0x9F84,0x9F7C,0x5F6C,0x7B4B,0x7832,0x773A,0xF321,0xB421,0x5119,0x2D19,0x0C11,0xE908,0xCC08,0xF110,0x1619,0x1511,0x1411,0x3311,0xF110,0x0F11,0xED10,0xCA10,0xA608,0xA608,0xAB10,0xF308,0x5921,0x5C19,0x5E32,0xDF6B,0x1F64,0xDF5B,0xDE3A,0x5C22,0x9519,0x7111,0xED31,0x1384,0x3174,0xCB52,0x6A4A,0x6529,0x0521,0xAB39,0xEC41,0x325B,0xB46B,0x1263,0x968C,0xD273,0xF263,0xEE52,0xEF52,0xE939,0x0621,0x6E4A,0xCA39,0x2529,0x0942,0x4729,0x8B4A,0x6629,0x4529,0x0429,0xE428,0xE420,0xE428,0x0521,0xE420,0x0429,0xA631,0xA731,0x8629,0x2521,0xE518,0x8410,0xE318,0x0419,0xA210,0x6210,0x6410,0x8310,0x6308,0x2108,0x2208,0x4108,0x4108,0x4008,0x2108,0x2100,0x0200,0x2100,0x2100,0x4200,0x4400,0x2300,0x0100,0x0100,0x2100,0x0100,0x0000,0x0008,0x2208,0x2300,0x4308,0x2700,0x4A00,0x2900,0x0500,0x2208,0x0B19,0x4E11,0x0621,0x4419,0x0629,0x694A,0x2C63,0x4D63,0x284A,0xE849,0x4952,0x8B52,0xAB52,0x484A,0xC639,0x8331,0xE128,0xA030,0x8030,0x8030,0x6030,0x6028,0x6028,0x8228,0x8330,0x4541,0xE849,0xAC5A,0x0E6B,0x6F73,0x506B,0xB58C,0xB173,0xEE5A,0xB173,0x1AA6,0xF384,0x8942,0xC739,0xE739,0x694A,0x4231,0x0421,0x0521,0x2621,0xC731,0x4742,0xA962,0x2A6B,0x4A63,0x6A6B,0x4B6B,0x6A6B,0x4A63,0x6A63,0x4B6B,0x4A6B,0x2A6B,0x4B63,0x2B63,0x2A6B,0x4A63,0x4B63,}, +{0xC3E7,0xC4DF,0xC4DF,0xC6E7,0xC8E7,0xC8EF,0xE6DF,0xE6E7,0xE6DF,0xC6DF,0xE6E7,0xC6E7,0xC7EF,0xC8EF,0xC8EF,0xC7EF,0xC7E7,0xC6DF,0xE5DF,0xC4DF,0xE3D7,0xC3CF,0x62BF,0x42BF,0x23BF,0x03B7,0xC4AE,0x859E,0xE68D,0x667D,0x2765,0x0865,0x8B7D,0xAB7D,0x4D75,0xCF6C,0x1054,0x5343,0x1643,0xB94A,0x783A,0x552A,0x142A,0x1522,0xF631,0x9642,0xF752,0x395B,0x5A63,0x384B,0x184B,0xF952,0xBA4A,0x784A,0x9632,0x753A,0x773A,0x974A,0x5542,0x3332,0x122A,0x3232,0x3332,0x7842,0x9A4A,0xBA3A,0x9A32,0xDC4A,0x7E53,0xBF63,0x5E53,0x3E5B,0xFC42,0x773A,0x552A,0x9319,0x5119,0x0F19,0xEE10,0xCC08,0xED18,0x7219,0x7419,0xB419,0xB519,0xB421,0xB421,0x153A,0x132A,0xAF11,0x2A09,0x0809,0xCB00,0xB208,0xD710,0x9C19,0xDD19,0xFF52,0xFF63,0x9F53,0xBE32,0xB921,0x7719,0x5009,0x6D21,0x316B,0xB48C,0x727C,0x4832,0x6529,0xE320,0x0521,0x6E4A,0x4A31,0xE828,0x2F4A,0x8A31,0x1163,0xAA39,0x8839,0x4629,0x0331,0x8839,0x6631,0xC939,0x2E5B,0x2A42,0xA731,0x4521,0x0521,0xE320,0xC228,0x0421,0x2421,0xE320,0xC631,0x6731,0xC831,0x8731,0x8731,0xE518,0xA410,0x8208,0x8218,0x8218,0x0419,0x0419,0x6210,0x6208,0x6308,0x6108,0x4110,0x4008,0x4100,0x4108,0x6210,0x6100,0x0100,0x0100,0x2100,0x2100,0x0200,0x2200,0x2300,0x6500,0x6400,0x2200,0x0000,0x2200,0x2500,0x2600,0x8408,0x8900,0x8A00,0x4600,0x4600,0xA508,0x8610,0xC420,0xA631,0x283A,0xA831,0xEF6B,0x6E6B,0x4A5A,0x284A,0x4D63,0xCC5A,0xEE62,0xD073,0x307C,0xA862,0x6139,0xA028,0x6030,0x4040,0x6038,0x4038,0x4038,0x4030,0x2038,0x4439,0x494A,0x2C5B,0xCA4A,0x274A,0x2852,0x6C52,0x0E63,0x2F6B,0xB584,0xD68C,0x958C,0xD27B,0xF16B,0x4E6B,0x8E63,0xEC5A,0x674A,0x6429,0x8629,0x8729,0x294A,0xC952,0x8952,0xEA6A,0x2B63,0x6B63,0x6B6B,0x8A6B,0x4A63,0x6A63,0x4B63,0x4B6B,0x4B63,0x6A63,0x6B63,0x2B6B,0x6A6B,0x4B6B,}, +{0xC2D7,0xC3D7,0xC3D7,0xC4D7,0xC5D7,0xC5DF,0xC7E7,0xC8E7,0xC8E7,0xC7E7,0xC6EF,0xC6EF,0xC6EF,0xE6EF,0xE6E7,0xC6E7,0xC5E7,0xC5E7,0xE5E7,0xE6E7,0xC5E7,0xC5DF,0xC4DF,0xC4D7,0xA4D7,0x64CF,0x46C7,0xE7AE,0x679E,0x258E,0xE885,0x0A8E,0xEA85,0x6C75,0xCE64,0x0F54,0x714B,0xB442,0x7432,0x753A,0x5542,0x1232,0x3242,0x3132,0xF131,0x102A,0x1032,0x3132,0xB34A,0xB652,0xB74A,0xB74A,0x974A,0x974A,0xB54A,0xB442,0x732A,0xF221,0xD129,0x9129,0xF129,0xF129,0x523A,0x3432,0x9329,0xD629,0x573A,0x994A,0xFC52,0x7B42,0x5A32,0x782A,0x7A32,0x3832,0xF621,0xD521,0x7219,0x5019,0x0F11,0x4E11,0x2E19,0x9019,0x7421,0x173A,0x3832,0xF821,0xF831,0x1832,0x5832,0xF629,0xB321,0x6F11,0xEB18,0xCC10,0xD510,0xD710,0x5B11,0x9E19,0x3E3A,0x3F4B,0x3F4B,0xBC3A,0x5832,0xD321,0x9311,0x6E09,0x8D29,0xF37B,0x3274,0x4E5B,0x6D53,0xCA52,0xE839,0x0331,0x2421,0x0529,0x0329,0x4731,0x2531,0xA631,0xA629,0x8A4A,0x8942,0xCA4A,0x6C4A,0x305B,0x2B42,0x0421,0x2521,0xE839,0xA731,0x6629,0x094A,0x093A,0xA639,0x4A42,0xE939,0x8731,0x2731,0x2431,0xC318,0xC410,0xA310,0x8118,0x6210,0xE520,0xA318,0xA210,0x6208,0x4208,0x6108,0x4100,0x4008,0x4108,0x4108,0x6208,0x6100,0x4000,0x2108,0x4100,0x2000,0x4100,0x4300,0x8700,0x6800,0x0400,0x2200,0x4300,0x2500,0x4900,0x8B00,0xEA08,0x0D01,0x6900,0x0A09,0x4C09,0xE608,0xC218,0xE320,0xA939,0x8E63,0xEB52,0xED5A,0xCB5A,0x094A,0x6E73,0x8E6B,0x0D63,0x2D63,0x0D63,0xAB6A,0x656A,0xE049,0xA038,0x4030,0x2038,0x4040,0x2040,0x2038,0x0038,0x0038,0xC350,0x4E7B,0x948C,0x5595,0x759D,0xF494,0x317C,0xCF73,0xED5A,0xB16B,0x5274,0x317C,0x4F6B,0x916B,0xB27B,0xF06B,0xED5A,0xEA52,0xC631,0xA631,0x4742,0x6742,0xEA5A,0x2A63,0x0B6B,0x4B73,0x6B6B,0x6A6B,0x4A6B,0x6B6B,0x4A6B,0x4A6B,0x6A63,0x6A63,0x6A63,0x6A6B,0x4A63,0x4A6B,0x2A63,}, +{0xA2CF,0x82C7,0xC5DF,0xC6E7,0xE6DF,0xC5E7,0xC6E7,0xC8E7,0xC7E7,0xC5E7,0xA3DF,0xA3D7,0xC4E7,0xC5E7,0xC4E7,0xE5E7,0xE4E7,0xE4E7,0xC5E7,0xC5E7,0xE6EF,0xC5E7,0xE4DF,0xE4D7,0xC4D7,0x64C7,0x26B7,0x66B7,0xA8C7,0x68BF,0x49AF,0xECB6,0x6B96,0xAC85,0x8F5C,0x9143,0xF13A,0x913A,0x312A,0x112A,0xD331,0xF229,0x1232,0xF331,0xD229,0xF131,0x1132,0x3032,0x3142,0x102A,0xF129,0x1332,0x343A,0xD331,0xF339,0x553A,0x753A,0x7442,0x523A,0x3232,0x1032,0xAF19,0xCD19,0xF131,0xD221,0xD019,0xD021,0xD119,0x9319,0xB439,0xF629,0x7832,0x393A,0x3732,0xD429,0xD321,0x5021,0x6F11,0x5332,0x9653,0xB85B,0xB953,0x994B,0xDA3A,0x3822,0xF719,0x3832,0x382A,0xF831,0x9631,0xB421,0x9021,0x0D19,0xCA08,0x6A08,0x5010,0x1611,0x5911,0xBD21,0x9F3A,0x3F53,0xFF6B,0xFE63,0x9E53,0x1C3B,0xBA32,0x161A,0xB111,0xCD31,0x8C5A,0xCD5A,0x094A,0x0842,0xC639,0xE731,0x4842,0xAB4A,0xE839,0x2A42,0x8B4A,0xCD52,0x0F5B,0x4E5B,0xED52,0x2A3A,0x2A42,0x6A42,0xEC4A,0xA731,0xA731,0x6731,0x2529,0x6729,0xC931,0x4729,0x0A3A,0x6739,0x2421,0xE620,0x0329,0xA310,0x2519,0x0319,0x8218,0xC218,0xA210,0x8108,0x8108,0x4108,0x6008,0x4000,0x4000,0x4000,0x2100,0x4108,0x4108,0x4108,0x4010,0x4110,0x6108,0x4208,0x4400,0x6800,0xA700,0x2500,0x2408,0x4700,0x4900,0x0800,0xED08,0x0F01,0xCD08,0xCC08,0xEA10,0xED42,0xA510,0xC318,0xE320,0xC520,0x8D52,0xB58C,0x6E5B,0x0E5B,0xCF73,0x2D63,0x2D63,0x117C,0xF27B,0x2D6B,0xAB62,0xA95A,0xE95A,0x244A,0xA030,0x0030,0x0038,0x4038,0x4038,0x4040,0x2038,0x0038,0xA050,0x4C83,0xB494,0xD49C,0xB594,0x548C,0x1384,0x9073,0x2E63,0x1484,0x979D,0x349D,0x4D6B,0x8F73,0xEE62,0xAB42,0x6A42,0xEC5A,0x4742,0xE841,0x685A,0xA852,0xA84A,0xEA5A,0x2A63,0x4A6B,0x4B6B,0x6A6B,0x4A6B,0x4B63,0x6A6B,0x4A6B,0x4A63,0x4A6B,0x4A63,0x4A63,0x4A63,0x6A63,0x2A63,}, +{0x22BF,0x01B7,0x64C7,0xA4CF,0xE5D7,0xC4DF,0xC4DF,0xA4D7,0xA3CF,0x62C7,0x62C7,0x83D7,0xC5E7,0xE5E7,0xE6EF,0xC6EF,0xC5E7,0xC5EF,0xC5EF,0xC5EF,0xC5EF,0xC5EF,0xC5DF,0xC5D7,0xC6DF,0xC7DF,0xE8DF,0xE8D7,0xC8D7,0xC7CF,0xC8C7,0x4CC7,0x8BAE,0x8C95,0xAE6C,0x1064,0x8F53,0x0E4B,0xB13A,0x713A,0x323A,0x944A,0xB44A,0x332A,0x122A,0x322A,0xEF19,0xD021,0xAE21,0x102A,0xF239,0xD229,0xD231,0xD231,0x9229,0xD129,0x1132,0x3232,0x543A,0x7542,0x5332,0x5432,0x3132,0x313A,0x333A,0x7232,0x133A,0x122A,0xD221,0xCF19,0xF329,0xD329,0xD329,0xB321,0xB421,0xF531,0xB429,0xB021,0xD752,0xFE6B,0x1F95,0x9FA5,0xBFA5,0xBFA5,0x9F8D,0x1E85,0x7D64,0xDD53,0xBA32,0x1832,0xB429,0xB019,0x4F21,0x0B11,0xA708,0x4708,0x6D00,0xD310,0xF810,0x3A11,0xDD29,0x5F3A,0x1F53,0xDF6B,0xFF73,0xFF63,0x3E43,0x5A22,0x7411,0x2B11,0xC508,0xC318,0x2521,0xE941,0x2B4A,0xA829,0xCA39,0x8C4A,0xAB39,0x2821,0x2729,0x8939,0x4731,0x4729,0xA931,0xA941,0x4731,0xAA39,0x2629,0x4529,0x6629,0x6721,0xE931,0x8A29,0x4829,0x4731,0x0629,0xE528,0xC518,0x0421,0x0821,0xE618,0x4629,0xC510,0xE420,0xC318,0x8208,0x2100,0x6108,0x6108,0x6108,0x4000,0x6108,0x6100,0x4108,0x4200,0x4108,0x4108,0x4308,0x6408,0x4608,0x4800,0x2600,0x2400,0x4600,0x6808,0xAF08,0xD000,0xAC00,0xAB00,0xCE00,0xEF00,0xCD19,0x6D19,0xE718,0x6218,0xA218,0x0521,0x4621,0x2C4A,0xF47B,0xCF63,0xCB52,0x494A,0xEB5A,0xAF73,0x8E6B,0x2E6B,0x2E6B,0xEE7B,0x2E7C,0x6C6B,0xAA5A,0x2241,0x0038,0x0040,0x4038,0x4038,0x4038,0x4038,0x6048,0xE060,0x4C8B,0x34A5,0x7294,0xD17B,0x7384,0xF27B,0x2D6B,0x2D6B,0x9173,0x917B,0x718C,0x4C7B,0x4D73,0x4B6B,0xEB52,0x2D5B,0x4E63,0xA94A,0x2742,0x2642,0x6742,0xC952,0x2B63,0x4C63,0x4A6B,0x4B63,0x6A63,0x4B6B,0x4B6B,0x6A63,0x4A63,0x4A6B,0x4B6B,0x6A63,0x6A6B,0x4A6B,0x6A63,0x4A63,}, +{0xE1A6,0x22B7,0x85C7,0xA5DF,0xE5DF,0xC3DF,0xC3D7,0xA3CF,0xA3D7,0xA2D7,0xC4D7,0xC4E7,0xC5EF,0xC7EF,0xC6EF,0xC6E7,0xE6EF,0xC4EF,0xC5E7,0xC5EF,0xE4EF,0xC4EF,0xC4EF,0xC6EF,0xC7E7,0xE9E7,0xE9E7,0xCADF,0xE9DF,0xE9E7,0xC9E7,0x8CD7,0xCDB6,0xCEA5,0x1095,0xB28C,0x7284,0xF273,0x5553,0xF552,0xF452,0xF442,0x9432,0x3332,0x7642,0x964A,0xB53A,0xB342,0x6F32,0x0E2A,0x0F2A,0x1332,0xF131,0xCE39,0xF039,0x1232,0x1032,0xB14A,0xB44A,0x733A,0x7332,0x753A,0x1332,0xB019,0xD121,0x9019,0x6F21,0x7229,0xB129,0xD131,0x9221,0x142A,0xD439,0xB221,0x9021,0x5011,0x5119,0x7429,0xB431,0xF639,0x9C42,0x5F63,0xDF6B,0x3F7C,0x9F84,0xDF84,0xFF8C,0xFF8C,0x1F8D,0xFD63,0xF832,0x122A,0x8F21,0x4C19,0xEA10,0xCA00,0xA800,0x6800,0x2E08,0x7308,0xB508,0xD818,0x5C19,0xDE31,0xBF4A,0x5F5B,0x9F63,0x7E3A,0x7711,0x3009,0x4B11,0x2919,0x0919,0x6F29,0x7129,0x4D21,0x2821,0x2A21,0x2B21,0xEB20,0x0819,0x0521,0xE320,0xC320,0xC418,0xC618,0xCC21,0x2611,0xE510,0xE520,0xA618,0x102A,0x2A19,0x8508,0x8410,0xC418,0xC320,0xA310,0xC318,0xE410,0x0721,0xE510,0xC620,0x6B10,0xA410,0xA618,0x6308,0x6100,0x6100,0x4208,0x4208,0x4108,0x6110,0x8208,0x8210,0x6108,0x4108,0x6410,0x8700,0x8600,0x6800,0x6A08,0xA500,0x6400,0x8A00,0xAE08,0xF308,0x3309,0xAD08,0x6C00,0x7409,0x151A,0x2D19,0xA700,0x8208,0x8110,0xA120,0xE520,0x4529,0x4639,0x0B4A,0x8A4A,0xC641,0xEB62,0xCB5A,0xCB62,0x0C63,0x0D73,0xAF73,0xCF7B,0x4D73,0xED62,0x0C63,0x685A,0x4139,0x4040,0x6040,0x6048,0x4038,0x4040,0x0048,0x4071,0x0F9C,0x55AD,0x159D,0x728C,0xB073,0x0F6B,0x0E63,0xD173,0x1184,0x0F84,0x8E8C,0xEC8B,0xEC83,0x6D7B,0x149D,0xCF73,0x8F6B,0x4C5B,0x8A4A,0xC95A,0x0A6B,0x2A6B,0x4B63,0x2A63,0x4A6B,0x2B63,0x6A63,0x6A63,0x6A63,0x4A63,0x4B6B,0x4B63,0x4A6B,0x4A6B,0x4A6B,0x4A6B,0x4A63,0x4A6B,}, +{0x03BF,0x42BF,0x63C7,0xA5D7,0xC4D7,0xA3D7,0xC3D7,0xC4DF,0xC4DF,0xC4DF,0xC4DF,0xC4DF,0xC5E7,0xC8EF,0xC8EF,0xC7E7,0xC6EF,0xC5EF,0xE5E7,0xC5EF,0xC4EF,0xE4EF,0xC4E7,0xC6EF,0xE8E7,0xE9DF,0xC9E7,0xC8E7,0xC8E7,0xEAEF,0xCAEF,0xCDE7,0x51D7,0x73C6,0xB5B5,0x78AD,0x38A5,0xDA94,0x5984,0xF763,0xB763,0xD85B,0xB75B,0x3853,0xD64A,0x953A,0x9542,0x964A,0xD84A,0xB442,0x732A,0xAF19,0x4D19,0x6F31,0xAF31,0xEF29,0x102A,0x5242,0x944A,0xB342,0xB64A,0xB64A,0x5432,0x722A,0x323A,0x6F21,0x9029,0xCE29,0xCF29,0xD121,0xB019,0x9011,0x7021,0x2E19,0x9229,0x7329,0x2E19,0xA910,0xCF10,0x3219,0x1321,0xD518,0xD931,0xBD52,0x3E63,0x9F63,0x1F74,0x9F7C,0x1F74,0xFD6B,0x1C64,0xD963,0x775B,0xB23A,0x4F2A,0x6C09,0x0A01,0xA700,0x6600,0x2700,0x0A00,0x4E00,0xD410,0x5919,0xBD21,0x1E32,0x5E3A,0xDC29,0x5619,0x342A,0x183B,0x1A3B,0xB932,0xF729,0x9319,0x5111,0xB219,0xF421,0x9021,0x2C19,0xE718,0xC320,0xE428,0x4621,0xC821,0x0F32,0x963A,0x0811,0xA608,0x8910,0x6608,0x2B19,0xCB10,0xA808,0x8310,0xA310,0x8518,0x2911,0x2B09,0x4D09,0xA510,0x0A09,0x6708,0x4508,0x6210,0x6310,0xC318,0xC410,0x8308,0x6308,0x8510,0xA410,0xA510,0x6710,0x6510,0x4108,0x4108,0x6518,0x8510,0x8408,0x8810,0x6808,0xA710,0xEA08,0x6F11,0x0E11,0xF008,0x3001,0xAF00,0xF008,0x3311,0x6A08,0x4508,0xA308,0xC210,0xA118,0xA220,0xA428,0xA631,0xC531,0xC639,0xE639,0x8539,0x8B62,0xA952,0x6952,0x6952,0xCD6A,0x0D63,0x0D6B,0x4E6B,0x8F6B,0xED62,0x2D6B,0xCC73,0x4552,0x6149,0x2049,0xC048,0xC048,0x6259,0x2A83,0x929C,0x939C,0x7394,0x518C,0x7384,0xB17B,0x958C,0xF594,0x9394,0x908C,0xAE94,0x2D8C,0x0D84,0x308C,0x39B6,0x1395,0x8E73,0xAE63,0xA94A,0x4842,0xC95A,0x0A5B,0x2B63,0x4B63,0x4B6B,0x4B6B,0x4B63,0x4A63,0x4A6B,0x4A63,0x4A63,0x4B63,0x4A6B,0x2B63,0x4A63,0x2B63,0x2A63,0x4A63,}, +{0xE2A6,0x01AF,0x63BF,0xC5D7,0xC5DF,0xA4DF,0xC4D7,0xA5DF,0xA4D7,0xA4D7,0xC4DF,0xE4DF,0xE6EF,0xE8EF,0xC7EF,0xC5EF,0xE4EF,0xC5E7,0xE5E7,0xC5E7,0xC4E7,0xC4EF,0xE5E7,0xC7E7,0xE9EF,0xC9EF,0xC8E7,0xE6EF,0xC9F7,0xCCF7,0xD0EF,0x94E7,0x38E7,0xDBD6,0x7CCE,0x1DBE,0xFEA5,0xBE9D,0x5D9D,0x3D8D,0xFC94,0x5E8D,0xFE8C,0x7C6C,0xD95B,0x574B,0x985B,0x574B,0x5743,0x5653,0x575B,0x1553,0x7132,0x6F2A,0xF13A,0x535B,0xF242,0xB33A,0xD542,0x364B,0xB63A,0x763A,0x7742,0x343A,0x1232,0xF129,0x323A,0x954A,0x963A,0x763A,0x973A,0x363A,0x7742,0xB942,0x553A,0x3522,0xB219,0x7121,0x2C19,0xE910,0xEE18,0x0D11,0xCC08,0x6D08,0x5008,0x7408,0x3729,0x9839,0x9729,0x1732,0x5842,0xFB4A,0x9B63,0x1A6C,0x1C85,0x7953,0xF611,0x5009,0x0C01,0xCA00,0x6700,0x6500,0x4800,0xF008,0x5619,0xB921,0x5B2A,0x192A,0x792A,0xFB52,0xBF63,0x1F6C,0xDF63,0xDF63,0x5E53,0x3E4B,0x1E6C,0x1E64,0x5C53,0x352A,0xAC21,0x4629,0x8931,0x9552,0x585B,0x342A,0x8D10,0x8810,0xF008,0x1001,0xAB00,0xC910,0xEB08,0x6808,0xAA08,0xC910,0xC808,0x0E09,0x3822,0x1109,0x0D09,0xB419,0x0D01,0x8408,0x6108,0xA310,0x4629,0xE418,0xC510,0xC608,0x6708,0xA808,0xCB08,0xAE08,0x8908,0x8308,0x6108,0x6318,0xA418,0xA410,0x8710,0xE908,0x2E11,0xD229,0xF121,0xCE08,0x1209,0x3409,0x9609,0xCF00,0x6808,0x4308,0x6208,0x8210,0xC118,0x8120,0x0329,0x2529,0x4A3A,0x2742,0x6439,0xC641,0x083A,0xCB52,0x4852,0x295A,0x0C73,0x2D73,0xAF73,0xD07B,0x6E6B,0xED62,0xAC62,0xCD72,0xF183,0xF39C,0xD19C,0xAF8C,0x8B73,0xAF94,0x93AD,0x129D,0x3084,0x6F83,0xCF83,0x118C,0x1284,0x5173,0x1484,0x16A5,0x349D,0x918C,0xAD73,0x0B6B,0x8F83,0xB9BD,0x3DD7,0x79BE,0x507C,0x6E73,0x8D6B,0x0963,0x4A6B,0x6A63,0x2A63,0x4A6B,0x6A63,0x4A63,0x4A63,0x4B6B,0x4A63,0x4A6B,0x4A63,0x4A6B,0x4963,0x2A63,0x2A63,0x4B63,0x4A63,0x4A63,}, +{0x02AF,0xE1B6,0x22BF,0x44CF,0x84CF,0x63CF,0x83C7,0x83CF,0xA4CF,0xC4D7,0xC5E7,0xE6E7,0xC8E7,0xC8E7,0xE7E7,0xC5EF,0xC5E7,0xE4E7,0xC6E7,0xC5E7,0xC3E7,0xC4E7,0xC5E7,0xE8E7,0xC9EF,0xC9EF,0xC8EF,0xE7F7,0xC9FF,0xCDFF,0xB2EF,0x58E7,0xDCDE,0x7FCE,0x3FC6,0x3FBE,0x5FBE,0x3FB6,0x1FB6,0xDFAD,0xFFB5,0xFFB5,0xFFB5,0xFFAD,0xDEA5,0x9E95,0x7E8D,0xDE84,0x7B74,0xFA63,0x574B,0xD552,0xD44A,0xB66B,0x5974,0x7B7C,0x9C6C,0x5C6C,0x5C64,0x5C64,0xD853,0xD532,0x9532,0x9632,0xB642,0x785B,0x7653,0x9A5B,0x7A4B,0xDD5B,0xDD63,0x1B4B,0x193B,0xD83A,0x373A,0x993A,0x393A,0xB419,0x2F19,0x4F21,0x4D11,0x946B,0xF66B,0xF13A,0x6F32,0x6E22,0x8C09,0xAC09,0x0E22,0x2F22,0x301A,0x922A,0x1964,0x5B6C,0x3C7C,0xBA4A,0xD919,0x1309,0x3419,0x5311,0xEF08,0xCB08,0xA808,0x0C11,0xD329,0x782A,0x5E53,0x3E43,0xDD32,0xFA29,0x5B21,0xBD19,0xDE31,0x3E3A,0x9C31,0x9B21,0xBC29,0x1D32,0xFB31,0x3319,0xEA10,0xE920,0x6E19,0x5319,0x3219,0xEF08,0xC908,0x8710,0xF018,0xB621,0xD621,0x5019,0x6900,0xEE08,0xD421,0x5111,0xEA08,0x0D11,0x1219,0xD010,0x1011,0x3411,0x0F09,0x8610,0xA308,0xC518,0xE918,0x2A11,0xEA10,0xCB10,0x8A08,0xCC08,0xCE10,0x8E08,0xAC00,0xC600,0x8208,0x8208,0x6310,0xA510,0xA818,0xF008,0x3822,0x7011,0xCD00,0xED10,0x3509,0x3A12,0xF501,0xAB00,0x8400,0x6408,0x8208,0x6208,0xA110,0xA210,0xE320,0x2429,0x8731,0xA531,0x4231,0xA749,0xCC5A,0x8A5A,0xE649,0x4952,0x695A,0xAA5A,0xEC6A,0x8A6A,0xEC62,0x4D6B,0xEC62,0x2E73,0x9073,0x7494,0x16A5,0x36AD,0xF394,0xD49C,0xD39C,0xEF83,0x4D73,0xEC72,0x4C83,0x0D7B,0x2C6B,0x6F73,0x328C,0x7294,0x718C,0xCF7B,0x8A5A,0x696A,0xAB72,0xB18A,0x97AC,0x5CCE,0xD7AD,0x0F7C,0x8E73,0xC962,0x0A63,0x4A63,0x4A63,0x6A6B,0x4B63,0x4B63,0x4B6B,0x6A63,0x4B63,0x6A63,0x4B6B,0x4A6B,0x4A63,0x2A6B,0x2A63,0x4A63,0x4A5B,0x2A63,}, +{0xE2AE,0xC1AE,0xC1AE,0x03BF,0x44C7,0x44C7,0x85CF,0xA5D7,0xC6DF,0xE5E7,0xE6E7,0xC7E7,0xC9E7,0xC9E7,0xC7E7,0xC7EF,0xE6EF,0xC5E7,0xC5E7,0xC5E7,0xC4E7,0xC5E7,0xC5DF,0xC9E7,0xC9EF,0xE8EF,0xE8EF,0xC7F7,0xC9F7,0xCBEF,0xAFF7,0x14EF,0x58C6,0x7CA5,0xFE84,0xBE7C,0xDF7C,0xFF8C,0x3F9D,0x3F9D,0x1F8D,0x5F9D,0x5F9D,0x7F95,0xDFAD,0xDFAD,0xDFAD,0xBFAD,0x5F9D,0xDE8C,0x1B6C,0xB953,0x774B,0xD75B,0xDA63,0x1E74,0xFF84,0x1F9D,0x5F9D,0x7F9D,0x7F95,0x3E8D,0xDC7C,0xDB4B,0x9A53,0x5E7C,0x9E84,0x1F95,0x3F95,0x1F8D,0xFF84,0xBF7C,0x5E64,0x1E64,0xDD53,0x5A4B,0xB93A,0x782A,0xF521,0x9121,0x4D09,0xAF31,0xD562,0x3863,0x9E84,0x7F95,0x7E9D,0xDE9D,0xFF9D,0x7F8D,0x1F7D,0xDF74,0x5E64,0x7E6C,0x9922,0xB511,0x7619,0x3219,0x7519,0x3311,0xD110,0xAD08,0xA908,0xA808,0x0E11,0x1611,0x1D3A,0xFF52,0x1F4B,0x5C2A,0x7711,0x1809,0x3809,0xFA10,0xD808,0xD508,0xB310,0xB310,0x1111,0x4D09,0xB219,0xF421,0xF511,0x9519,0x5219,0xED00,0xA800,0xA610,0x2F19,0x5419,0x5619,0x5219,0xED10,0x9429,0x9721,0x5511,0xEE10,0xEF10,0xD621,0x7319,0xF008,0x1722,0xB521,0xEC08,0x0611,0xC918,0xAA18,0x4E11,0x7119,0x1111,0x5219,0x1009,0xAE08,0xAE08,0xAD10,0xE908,0xA408,0x8210,0x2308,0x8510,0x6F19,0xB819,0x1822,0x9311,0x8A00,0xCC10,0x1411,0x1509,0x1111,0xAB08,0xA700,0xA608,0xA310,0x6208,0xA318,0x0411,0xC320,0x6529,0x6531,0xC539,0xC531,0x6531,0x4631,0xA741,0xE749,0x8551,0x8549,0xC551,0x285A,0x8D73,0x6E73,0x4D6B,0xAF73,0x1184,0x518C,0x1184,0x6F7B,0x0C73,0xCB6A,0xCB62,0x696A,0x2862,0xC659,0x2762,0x8A6A,0xAD6A,0xF083,0x308C,0x518C,0xF18B,0xAB72,0x2B62,0x3294,0xD8C5,0xB6C5,0x73AC,0x76AD,0xCE6A,0x4D73,0x4C6B,0x0C63,0x2A73,0x4A63,0x4A63,0x6A6B,0x4B6B,0x4B6B,0x4A6B,0x4A6B,0x4B6B,0x4A63,0x6A63,0x4A63,0x2B63,0x4B63,0x2A63,0x4A63,0x4A5B,0x4A63,0x2A63,}, +{0xC2A6,0xA1A6,0xA1AE,0xC3AE,0x06C7,0x65CF,0xA5D7,0xA5CF,0xE5D7,0xC5DF,0xC6DF,0xC8E7,0xE8E7,0xC8EF,0xC8E7,0xC7E7,0xC7E7,0xC6E7,0xC6E7,0xC5E7,0xC5E7,0xC4DF,0xA4D7,0xC9DF,0xCAEF,0xC8E7,0xC7DF,0xC8EF,0xCAF7,0xCBEF,0x8DE7,0xB0C6,0x93A5,0x9484,0xB863,0x795B,0x7A4B,0x5C53,0xBD6B,0xDD7B,0xBD6B,0x1E74,0x3F7C,0x3F6C,0x7F84,0x9E7C,0xFF8C,0x3F9D,0x1F8D,0xBF84,0x3E74,0x5D6C,0x5D74,0xBC73,0x5963,0x3A5B,0x5C5B,0xBE63,0xFF73,0x5F7C,0xBF84,0xDF8C,0xDF8C,0x9F84,0x1F6C,0xDD63,0x3C53,0xBE63,0x1F74,0x7F7C,0xBF84,0x1F8D,0x3F8D,0x5F95,0xFF8C,0x1F6C,0x5F53,0x1C43,0x3622,0xD521,0xB421,0x7119,0x3019,0x0D09,0x1419,0x5C4A,0x7F6B,0x3F7C,0xFF94,0x5F8D,0x7F95,0x9F95,0xFF84,0x9F6C,0x5E4B,0x3B22,0x7511,0xD000,0xD008,0xD210,0xD110,0x8D08,0xA900,0x8700,0xC708,0xAD10,0xF610,0x1B21,0x7D21,0x7D21,0x9B19,0x9B11,0x1609,0xD400,0x1309,0x3219,0xB521,0x7529,0x3632,0xFB3A,0xBE53,0xBE5B,0x9E53,0x1A2A,0x3311,0xEC00,0xC900,0x8510,0x0B19,0x1219,0x1311,0x1209,0x0E19,0x3211,0xF410,0xF210,0x1019,0xF721,0xB721,0x3511,0x3A2A,0xBC3A,0x7919,0xB010,0xC908,0x0C11,0xD329,0xD821,0x7621,0x191A,0xD829,0x7411,0xD108,0xEF08,0xCE10,0x0A11,0xC708,0xC510,0xE820,0xEB18,0xF221,0xF621,0x9B2A,0xF210,0x8A00,0xE908,0x6D00,0x4E08,0x8C10,0xCD08,0x0D09,0xC908,0x8408,0x4310,0x0911,0xC310,0xE428,0x2429,0x0331,0x6539,0x2331,0xE230,0xE338,0x0339,0xA549,0x0542,0x8349,0xE449,0x675A,0x8A62,0x2E6B,0xD07B,0xB073,0x1084,0xD08B,0x1084,0xA96A,0x4962,0x485A,0xC659,0x6451,0x2349,0x4449,0xE751,0x6A52,0xCD5A,0x4E7B,0x4C7B,0x8A7A,0x2B92,0x6E9B,0x1394,0x75A4,0xBAD5,0x1BEE,0x7CF6,0xBCEE,0x79C6,0x2C63,0xEA62,0x2C63,0x2B73,0x4A63,0x4A63,0x4A6B,0x4B63,0x4B63,0x4A6B,0x496B,0x4B63,0x6A63,0x6A63,0x4A63,0x2B63,0x4B63,0x4B63,0x4B63,0x4A63,0x4A63,0x4A6B,}, +{0x23BF,0x22B7,0x03B7,0x03B7,0x47CF,0xA7D7,0xC7D7,0xC7C7,0xC6CF,0xC5C7,0xE7DF,0xC8E7,0xC8E7,0xC7E7,0xC8EF,0xE8E7,0xC7E7,0xC7E7,0xC6E7,0xE5DF,0xC4D7,0xC3CF,0x45BF,0x48BF,0x68C7,0xC7D7,0xC9DF,0xCAEF,0xE9F7,0xE9EF,0x8ADF,0xABB6,0x4B7D,0x0C54,0x0C43,0xEE32,0x8E2A,0x4E1A,0x3022,0x9232,0xF63A,0xD742,0xB83A,0x5843,0x9A63,0xDC63,0xDC63,0x3C74,0x3E74,0x5E74,0xFE6B,0xFD5B,0x9C53,0xB542,0x9132,0x7232,0x522A,0x3532,0x7942,0xBA42,0xBB4A,0xDC42,0xFD52,0xDD4A,0xDB42,0xDA42,0x1A5B,0xFA52,0xFD42,0x9D3A,0x1E4B,0x7E5B,0xBE5B,0xDF63,0xFF6B,0xBE5B,0x7F53,0xDC42,0x7942,0x7932,0x5632,0x1422,0x9311,0x3011,0x0D09,0xEF00,0xB308,0x5819,0x5D42,0x1F4B,0x9F63,0x1F74,0x3F6C,0x5F64,0x1F6C,0x3E43,0xFA21,0x3309,0xCC00,0x8B00,0xAA00,0xC910,0xC908,0xE808,0xA608,0xA810,0xF008,0xB410,0x3811,0x5819,0x7A19,0x5B11,0x5711,0xD821,0x5A22,0xBB2A,0x1922,0x5519,0x7321,0x9919,0x9E42,0x1F53,0x5F5B,0x5D32,0xD719,0x5019,0x0911,0x2721,0x2D19,0x7311,0x1722,0x161A,0xB211,0x5211,0xB419,0xD93A,0x583A,0x9519,0x3519,0xD721,0x3B2A,0x5919,0x7709,0xCF18,0x2E11,0x9321,0x3932,0xDA21,0x182A,0x9611,0xD518,0x5619,0x3311,0x3211,0x3011,0x0E11,0x0B09,0x4911,0x0D19,0x4E11,0xB019,0xB521,0x9321,0xAF10,0x4B08,0xAC08,0x8E00,0xCC08,0x0D11,0x1011,0xF200,0xEE08,0x4508,0x8B19,0x2A11,0x8218,0x2429,0x8531,0x6431,0xE228,0xE228,0x0229,0x4431,0x6541,0xE641,0x6962,0x485A,0x2752,0x275A,0xCA62,0x4A62,0xE851,0x8B62,0xEC72,0x8D83,0x2D7B,0xAE7B,0x4D6B,0xCB62,0x685A,0x695A,0xA95A,0xCB62,0x8B5A,0x2A52,0xC751,0x6561,0x6571,0x8CA2,0x73DC,0xF5DC,0xD1A3,0xB1A3,0xD2D3,0x75EC,0xFBF5,0xDAF5,0xDEEE,0x58BE,0x096B,0x2C73,0x4B6B,0x4A6B,0x4A63,0x4A6B,0x4A6B,0x4B63,0x4B6B,0x6A63,0x4B6B,0x4A63,0x4A63,0x4A63,0x4A6B,0x4963,0x4A6B,0x2A63,0x4963,0x6A63,0x2A63,}, +{0xC3DF,0xC3DF,0xA4D7,0xA4D7,0xA6D7,0xC8DF,0xC9DF,0xE9DF,0xE7E7,0xE7DF,0xC9E7,0xC9E7,0xC9E7,0xC9E7,0xC8E7,0xC7EF,0xE6EF,0xE6EF,0xC5DF,0xE6D7,0xC5C7,0xC5BF,0x64AF,0xA9C7,0xCCDF,0xCCEF,0xCBEF,0xC9E7,0xC9DF,0xC9CF,0x4ABF,0x6C96,0x6D7D,0xAF6C,0xEF53,0xD063,0x535B,0xD242,0x134B,0xB66B,0x995B,0xF85A,0xF752,0x1853,0x184B,0x1853,0x585B,0x595B,0x9B5B,0x9B5B,0xBB63,0x9B53,0x1A53,0x5853,0x5853,0xF74A,0x7342,0x9242,0xF64A,0x3753,0x184B,0xF852,0xD84A,0xB93A,0x983A,0xB93A,0x9842,0xDA42,0xBA42,0xBA42,0x783A,0x9A3A,0xBB32,0xFC3A,0xBE5B,0x3F6C,0x1F64,0xBE4B,0x5C4B,0xDE4B,0x5C4B,0x3C3B,0xDA32,0x3622,0xD221,0x5211,0x7211,0x7211,0x7311,0x5511,0x9A21,0x1C32,0x5D32,0xDE42,0xFF42,0x5E32,0xD921,0x9419,0x7019,0x7019,0x4E11,0x2B19,0x0C09,0xEB08,0xE910,0x0911,0x8E19,0x9429,0x7821,0xD829,0x9521,0xF631,0x1A4B,0x7E6C,0x7F74,0x9F7C,0x1F64,0x5E53,0x191A,0x1409,0xD718,0x1A11,0x9B29,0x1C2A,0xD921,0x7319,0xAF21,0x9442,0xDE6B,0x7F7C,0x5F64,0x3E4B,0x182A,0x792A,0x7D53,0xFE42,0x7729,0x1311,0xF218,0x7621,0xB719,0xF721,0xD719,0xB521,0x7632,0xF531,0x7529,0x7611,0x5419,0x1211,0xB210,0x7519,0xB521,0x7519,0xD821,0x1522,0x2F11,0x2E11,0x1019,0x3019,0x0D09,0x7011,0xED10,0xEA08,0x8C08,0xD110,0xB411,0x4E11,0x0F11,0x1309,0xB609,0xCD00,0x6708,0x6C11,0x6520,0x0421,0xA639,0x8631,0xA639,0xE739,0xC631,0x8631,0x4539,0xA741,0x4541,0x6439,0x8541,0x4449,0x2449,0x6651,0xA649,0x6649,0x8649,0xC649,0x2862,0xCA6A,0x2D73,0x4E83,0xCA62,0x8A62,0xCB62,0x8B6A,0x4A5A,0x0852,0x2551,0xE360,0x078A,0xCBB2,0x73EC,0x19FE,0x5AFE,0xF8F5,0x34ED,0xB3F4,0xAFF3,0xF3FB,0xD5FC,0x5DFE,0x5EF7,0x6F8C,0xEA6A,0x4B63,0x4A63,0x4B63,0x4B6B,0x4A6B,0x4A6B,0x4A6B,0x496B,0x4A63,0x4A63,0x4A63,0x495B,0x4A63,0x4A63,0x2B6B,0x2A63,0x4A63,0x4A63,0x4A63,}, +{0xC5E7,0xC4EF,0xE5E7,0xC7E7,0xC7E7,0xC8E7,0xC9DF,0xC9DF,0xC9E7,0xC9E7,0xC9E7,0xE9EF,0xC9EF,0xC8E7,0xC7E7,0xE6EF,0xC6EF,0xC6E7,0xC7E7,0xE8DF,0xC6D7,0xC6CF,0xC8CF,0xCCDF,0xCEDF,0xCEE7,0xCBDF,0xEBDF,0xCAD7,0xC8CF,0x48B7,0x6986,0x8B75,0xEB5C,0x2B5C,0xAC4B,0x2F53,0xD042,0xF03A,0xD142,0xB23A,0x9232,0x9232,0x933A,0x943A,0xD442,0x1653,0xF54A,0x364B,0xF642,0x184B,0x594B,0x5753,0x153B,0x184B,0x3753,0x743A,0x733A,0x5432,0x963A,0xB632,0x973A,0xBA3A,0x9942,0x7832,0x793A,0x783A,0x7832,0x7732,0x7A3A,0xBA42,0xB942,0x1B53,0xBC5B,0x5F74,0x7F7C,0xBF84,0xFF84,0xDF84,0xFF84,0xBF7C,0x9F74,0x5F6C,0x9E4B,0xDB3A,0x1622,0x5311,0xB519,0x5309,0x7519,0x7819,0x7719,0x9821,0xBB21,0x9A19,0x7921,0xB721,0x3622,0x9219,0x9221,0xB321,0x8F11,0x2D09,0x6E19,0xAF21,0xB229,0xF429,0xD629,0xB621,0x7621,0x7219,0x9221,0x5521,0xDC31,0x5E42,0xDF4A,0xFF4A,0xFF4A,0x1C2A,0x7611,0xF008,0x1419,0xD931,0xFB29,0xF921,0x7211,0xD129,0xB329,0x9A31,0xFE31,0x5D2A,0xB929,0x9521,0xF829,0xDB29,0x9A21,0x1519,0x7511,0xBA32,0x9D53,0xFE63,0x9B32,0xDD3A,0xDE53,0x5E53,0xF731,0x7721,0xF821,0x9721,0xF719,0xD719,0x1311,0xB621,0x9B2A,0x1E43,0x392A,0xF108,0xEE18,0x9321,0xCE39,0x4E21,0x0E11,0xAF19,0x6B11,0xAD08,0xB719,0xD619,0x5019,0x3211,0xD821,0x1309,0x8A00,0xC710,0x0811,0x6210,0x2621,0xE528,0x8739,0x8739,0x8739,0x8839,0x2531,0xC328,0xC228,0x8228,0xE130,0xE130,0xE240,0xE340,0xE240,0x2339,0xA641,0x6649,0x8651,0x2862,0xCA6A,0x6A6A,0xEB72,0xCA6A,0x2862,0x8651,0xC448,0x6250,0x6260,0x8671,0xEDA2,0x92D4,0xF4F4,0x56FD,0xBCFE,0xBCFE,0x9BFE,0xD8FD,0x97FD,0x71FC,0xB0FB,0x32FC,0x18FD,0xBAF5,0xF6BD,0x2B63,0x4A63,0x2A63,0x2A63,0x2B6B,0x2A6B,0x4A6B,0x4A63,0x4A63,0x4A63,0x6A5B,0x4963,0x2A63,0x2A63,0x4A63,0x2A63,0x2A6B,0x2A63,0x2963,0x495B,}, +{0xE4E7,0xC5EF,0xC7E7,0xC8EF,0xC9EF,0xC8E7,0xC9DF,0xCAE7,0xC9E7,0xC9E7,0xC8E7,0xE8E7,0xC8E7,0xC7E7,0xC6E7,0xE7EF,0xC6EF,0xC5F7,0xC5E7,0xA5E7,0x87CF,0x87BF,0xABCF,0xCEE7,0xCFDF,0xEED7,0xEBC7,0xCBC7,0xAABF,0xA8B7,0x2AA7,0x6B86,0xCB7D,0x2C6D,0xAD64,0x0F54,0x105C,0xF263,0x924B,0x3153,0x545B,0x7553,0x344B,0xB66B,0xD76B,0x1964,0x7C7C,0xDC7C,0x1D85,0x3D7D,0xBC74,0xBC6C,0x9C6C,0x5B6C,0xFA53,0xDA5B,0x584B,0x164B,0x975B,0x9C7C,0xFD84,0x5D8D,0x5E8D,0x3D85,0xDD74,0x9E6C,0xFC5B,0x7A3B,0xF83A,0x9832,0x3732,0x1532,0x1632,0x373A,0x9B4A,0xDE42,0x1F53,0x7F53,0xBF63,0xFF73,0x1F74,0x3F74,0x7F7C,0xFF6B,0x7F5B,0x5B32,0xD719,0x5411,0x3109,0x1009,0xF308,0x3209,0x9319,0xD729,0xF631,0xF631,0x182A,0x3722,0x342A,0x3722,0x161A,0xF419,0x3122,0xD231,0x783A,0x9A3A,0xBB3A,0x182A,0x182A,0xB521,0x7119,0x0F11,0xCC08,0xD218,0xF818,0x7B19,0x7C19,0x3B19,0x5811,0xF310,0x9019,0x7411,0x5922,0x9D2A,0xBB32,0xD521,0x6F21,0x2D21,0x1121,0xB210,0x1421,0x7521,0x5321,0x3319,0x1519,0x3519,0x7721,0x5D4B,0x5F6C,0x7E5B,0x7D3A,0x9D3A,0xBF5B,0x5E53,0x1C32,0x3619,0x7621,0x7A32,0x7E43,0xDF4B,0x5C2A,0x7721,0x7C3A,0xBF53,0x3C3A,0xB719,0xAF00,0xAE08,0xB319,0x4F4A,0xF339,0x792A,0x162A,0x6F11,0xAE08,0x7519,0x3111,0xD010,0x7519,0xF208,0x6C00,0x6608,0x8C19,0x0711,0x8210,0xA420,0x2629,0x2531,0x0539,0xC338,0xE440,0xC240,0xC238,0x8038,0x6038,0x6030,0x6038,0x8040,0xA148,0x8140,0x6038,0x8130,0x4148,0x8140,0x0351,0x4459,0x0461,0xE350,0xE350,0x8050,0x2060,0xA268,0x4479,0x2A9A,0x4DBB,0x31DC,0xB3F4,0x56FD,0x5BFE,0x7CFE,0x7BFE,0x7BFE,0xB9FD,0x98FD,0x35FD,0x92FC,0xF1FB,0x75FC,0xBAFD,0x39DE,0xAB6B,0x4A6B,0x2A63,0x6A63,0x2B63,0x4A6B,0x2A63,0x2A63,0x4A63,0x4A63,0x4A63,0x2A63,0x4A63,0x2A63,0x4B6B,0x2A63,0x2A6B,0x2A6B,0x2A63,0x2A63,}, +{0xC5E7,0xC5E7,0xC8E7,0xCAEF,0xCAEF,0xC8E7,0xC9E7,0xC9E7,0xEAE7,0xCAE7,0xEAEF,0xE9EF,0xC8EF,0xC7E7,0xE6DF,0xC4DF,0xC3D7,0x81C7,0x82BF,0xA4C7,0xC7CF,0xC8CF,0xC9D7,0xCDE7,0xCCDF,0xCAC7,0xC9BF,0xC9BF,0xA9AF,0x49A7,0x0A97,0xE97D,0x6975,0xEB64,0xAD54,0x0E54,0x0F5C,0x536C,0x3564,0x3764,0x3864,0xB863,0xD86B,0x7984,0xBB94,0xDE8C,0x3FAD,0x9FAD,0xDFAD,0xFFB5,0xDFB5,0xBFAD,0xDFAD,0x7FA5,0x1F95,0xDF8C,0xFB63,0x375B,0x395B,0x1B5B,0xBE63,0x3F84,0xFF94,0x5FA5,0xBFA5,0xDFAD,0x7FA5,0x3F8D,0xBF7C,0x1D64,0x5C4B,0xB832,0x552A,0x122A,0x1632,0x1932,0xFA29,0x7C32,0x1D32,0x5D3A,0x5D3A,0x7E3A,0x9E3A,0x3D3A,0x1D2A,0x1922,0x182A,0xB429,0xD321,0xB321,0x9419,0xF429,0x1632,0xF829,0x382A,0xF529,0x5A32,0x9B32,0x7832,0x7932,0x372A,0x7742,0x9632,0x563A,0xB94A,0xFA42,0x9A42,0x5A32,0xF929,0x9621,0x9219,0x2E11,0x4B09,0x2E19,0xD110,0x1409,0x3509,0x7619,0xB529,0x5532,0x9B53,0x1E6C,0x9F74,0xBF74,0x3F64,0x3C43,0x1532,0x6C19,0x2911,0xC918,0xAE18,0x3311,0x5319,0x9519,0x1A2A,0x5D4B,0xDE5B,0xFD4A,0xFC29,0x9A19,0x7721,0xBC42,0x5C3A,0x7B21,0x7919,0xF518,0x5A32,0xFF5B,0x1F5C,0xDE3A,0x9919,0x7519,0x9B3A,0xFB21,0x5721,0x3119,0xAE00,0x3111,0x3419,0xB34A,0xB93A,0x3E3B,0x1B22,0x5311,0xCD08,0xF018,0xD010,0xB619,0xEE10,0xCC08,0x6700,0x8708,0xEA10,0xA310,0x8120,0xE330,0x8541,0xA348,0x8248,0x0351,0xA258,0xC260,0xE260,0x8160,0xC160,0x6050,0x4058,0x4068,0x6070,0xA068,0xC070,0x2269,0x0271,0xE170,0xA070,0x8070,0x2379,0x8479,0xA581,0x499A,0x0CAB,0x4DB3,0xEFC3,0x72DC,0xD4F4,0x92FC,0xD4FC,0x19FE,0x3BFE,0xFAFD,0xF9FD,0xFAFD,0x3CFE,0xFAFD,0x97FD,0x53FD,0x70FC,0xF0FB,0x96FC,0xD8ED,0x8B7B,0x4A63,0x4A63,0x4A6B,0x4963,0x4A63,0x4963,0x2A6B,0x4A63,0x4963,0x2A63,0x2B63,0x2A6B,0x4A63,0x2A63,0x4963,0x4A63,0x2A63,0x4A63,0x2A63,}, +{0xC6E7,0xC6E7,0xC7E7,0xEAEF,0xCAEF,0xEAE7,0xCAE7,0xEBE7,0xCBE7,0xC9EF,0xC9E7,0xC9E7,0xC7DF,0xC6D7,0xC5CF,0xC4CF,0xC5DF,0xC5DF,0xC6E7,0xE7E7,0xC7E7,0xE8DF,0xC8DF,0xC8DF,0xCACF,0xCACF,0xCAD7,0x68BF,0xE796,0x8686,0xE555,0x2755,0x285D,0x2C6D,0xEF64,0x915C,0x1575,0x398D,0xDA7C,0xDC84,0x5D6C,0xFB5B,0xDB63,0xDA5B,0xFA63,0xDC5B,0xDE6B,0x1E6C,0xFE6B,0xBE6B,0xFE73,0x1E74,0x1E6C,0xDE63,0x7E4B,0x5C53,0xF94A,0xB542,0x3432,0xB219,0xB419,0x1932,0x9C42,0x3D53,0x1F7C,0xFF6B,0x1F6C,0x1F74,0x1F74,0x1F74,0xDF63,0x7E53,0xBB42,0x383A,0x173A,0x9729,0x5521,0x1521,0x1611,0xF610,0x5619,0x9911,0x7719,0x7821,0x9929,0x9719,0xD621,0x9629,0xB421,0x9419,0x5632,0x5732,0x7832,0x593A,0x9A3A,0x393A,0xFB4A,0x1B43,0xBA3A,0x1B43,0x9932,0x783A,0xF93A,0x983A,0x7A42,0xDB42,0xBB42,0xBB3A,0x7A32,0xB521,0x7111,0x2D11,0x2B11,0x5019,0x1021,0xEF08,0x3411,0x9301,0xB621,0xBD6B,0x1F74,0x1F74,0x5F7C,0x1F64,0x9F5B,0x7D32,0x9629,0x2C19,0x6C19,0x4E21,0x7021,0x9219,0xB321,0xDB42,0xFF7C,0xBF7C,0xBF63,0xF921,0x3519,0x5519,0x9519,0x9521,0x7711,0x5719,0xF308,0x9621,0xDA3A,0x7C42,0x9C29,0x7A19,0xF310,0x5219,0x5519,0xF508,0xB208,0xD000,0x8F00,0xF108,0x7621,0x1732,0x7F53,0x9F4B,0xDC19,0xB110,0xAC08,0x8B08,0x9311,0xD310,0x0E09,0xA908,0x6500,0x8600,0x6508,0x8020,0x8238,0xC248,0x4150,0x6160,0x6170,0xA278,0xE380,0xE290,0x0491,0x0391,0xE288,0x0389,0x4491,0x22A1,0x64B1,0x84B9,0x68C2,0xEAC2,0x0BCB,0x8DD3,0xAED3,0x0FCC,0x10D4,0x14E5,0xF4E4,0xD3EC,0xB8F5,0x35F5,0x35FD,0x15FD,0x14FD,0xF5FC,0xF8FD,0xD8FD,0xF5FC,0x37FD,0xB9FD,0x5BFE,0x9CFE,0xF9FD,0x93FC,0x31FC,0xAEFB,0xF1FB,0x31FC,0x77F5,0x50A4,0x2A6B,0x2A63,0x496B,0x696B,0x6963,0x4963,0x2A6B,0x4A63,0x4963,0x4963,0x2A63,0x2B63,0x2A63,0x2A63,0x6963,0x4A63,0x2A63,0x4963,0x4A63,}, +{0xC6E7,0xC7E7,0xC9E7,0xEBEF,0xCBEF,0xEAE7,0xCAE7,0xCAEF,0xCAE7,0xE9E7,0xC7E7,0xC8E7,0xC9E7,0xC9E7,0xC8E7,0xE7E7,0xC8EF,0xE8EF,0xC7E7,0xC8DF,0xE8DF,0xC9DF,0xCBE7,0xCEE7,0xCECF,0xACC7,0x8AA7,0x6B97,0x4B87,0x0B8F,0x0B77,0x0B7F,0xCA76,0xCF7D,0x9575,0x7A7D,0xFD8D,0x1E9E,0x1FA6,0xFFA5,0x9F8D,0x3E7D,0x1E85,0xBE7C,0xFB63,0x9963,0x7C63,0x7B5B,0x5C5B,0xFA4A,0xBB4A,0xBA3A,0xFB4A,0xDA42,0xFB42,0xBA4A,0x9742,0x552A,0xD331,0xD229,0xB221,0x9111,0x9211,0x7411,0x9719,0xD819,0x1A22,0x3A2A,0x3B32,0x7B32,0x5C32,0x1A2A,0xD819,0x7511,0x3211,0x0F11,0xF008,0x1109,0x5419,0x3411,0x1319,0x5619,0x1411,0x1211,0x5421,0x5521,0x9521,0x7311,0x9419,0x9329,0xB529,0xD721,0xD821,0xF931,0x7A3A,0x593A,0xFB42,0xFB4A,0xDA3A,0x9D53,0x9C4B,0x7C53,0xBC5B,0x3E6C,0x5E6C,0x3D5C,0x3E5C,0x5D4B,0xFD32,0x1822,0xB321,0x752A,0x1222,0x362A,0x1522,0xB021,0xB321,0x362A,0x3832,0x9921,0x1D32,0xFD31,0xDC39,0xFB29,0x7B21,0x3511,0xEF10,0x0C19,0xF129,0x563A,0x7A32,0x582A,0xF942,0xFE6B,0xBF6B,0xDE4A,0xDA29,0x5511,0x9519,0xF821,0x392A,0x1B3B,0x1822,0x9619,0xD619,0x5A2A,0x5822,0x5511,0x1509,0x6E08,0xD010,0x3211,0xCF08,0x8D08,0x6C08,0x9108,0x1409,0xF819,0xB721,0x9D3A,0x5F4B,0x5D2A,0x3709,0x8F08,0xCB00,0xCE00,0x0F09,0x5009,0xCD08,0x4A00,0x2708,0x6500,0x6410,0x4030,0x0040,0x4058,0x0479,0x0892,0xAAA2,0x8BB2,0x08AA,0x86A9,0x86A9,0x64A9,0x23A9,0x65A9,0xC6A9,0x85B1,0x22B9,0x63C1,0xC7C9,0x6BD2,0x2DE3,0x4CEB,0x4EEB,0x8FEB,0x32F4,0x94FC,0x16FD,0xF6FC,0x17FD,0xD5FC,0x73FC,0x52FC,0x10FC,0x52FC,0x53FC,0x52FC,0xB5FC,0xB9FD,0x3AFE,0x1BFE,0x5DFE,0xB8FD,0x12FC,0x8FFB,0x2EFB,0x70FB,0xD0FB,0x91E3,0x8EB3,0x2B6B,0x4A63,0x2A63,0x2A63,0x4A63,0x2963,0x4A63,0x4963,0x2A63,0x4A5B,0x6963,0x2A63,0x2A63,0x2A6B,0x2A63,0x2A5B,0x2B63,0x4A63,0x4A63,}, +{0xC6E7,0xC7E7,0xCAEF,0xCBEF,0xCAF7,0xE9EF,0xEAEF,0xCBE7,0xCAE7,0xC9E7,0xCAEF,0xE9EF,0xCAEF,0xCAEF,0xC9E7,0xC8E7,0xE8E7,0xC9E7,0xCAE7,0xCDE7,0xEBE7,0xCBE7,0xAACF,0x8CBF,0x6EB7,0x0B9F,0xC876,0x886E,0xA956,0xE976,0x0B7F,0x497F,0x2B87,0x938E,0x5C86,0x3F96,0x7FAE,0x7FBE,0x7FC6,0x9FC6,0x7FBE,0x5FB6,0x5FAE,0xBF9D,0xFE7C,0x9C64,0x3E64,0x9D53,0x1A3B,0xD942,0x393A,0x162A,0xF521,0xD521,0xF419,0xF329,0x1222,0x1222,0xF229,0xD229,0x5021,0x2F19,0xEF18,0x1119,0x7729,0xB921,0xF931,0xF829,0xD821,0xD821,0xB721,0x7621,0x5519,0x3411,0x3211,0x5019,0x9119,0x5219,0x5221,0x7319,0x1119,0x3311,0x5211,0x1019,0x9421,0x9321,0xB421,0x132A,0x9329,0xB331,0xF629,0xF721,0x362A,0x1A43,0x7C4B,0x9B53,0xF942,0xB73A,0xDC5B,0x5F7C,0x9F7C,0x9F7C,0x9F7C,0xDF7C,0x1F85,0xDF7C,0xDF7C,0x1F6C,0xDF53,0x9C32,0x793A,0x3832,0x7832,0x592A,0x1932,0x9529,0xD421,0xBB32,0xFC42,0x7B32,0xD919,0x5811,0x5619,0x3711,0xF408,0xAC08,0x0C09,0x8F19,0xB83A,0xFB42,0x9E53,0x9D53,0x1D4B,0xF829,0x7829,0x5719,0xD919,0x9511,0xB619,0xBD3A,0x9F6C,0x3F64,0x7C2A,0x7C32,0xBC3A,0x9E53,0x3A1A,0xF108,0x4D00,0xCF08,0xCE10,0xCE10,0x2C09,0xC910,0xA810,0x1111,0x7719,0xDE3A,0xFD3A,0x1C2A,0xDD42,0x5911,0xF308,0x8D08,0x8D00,0x4A00,0x8A08,0xED08,0x8C00,0x2500,0x4608,0x4508,0x2318,0x0038,0x2058,0x8380,0xE598,0x87A1,0x67B1,0x27B1,0xC4A8,0x04B1,0x04B1,0xE3B0,0x04B9,0x26C1,0xA6B9,0x85C1,0xC5C9,0x68D2,0x07D2,0x29D2,0x2DE3,0x8EF3,0x2DF3,0x0DF3,0xCDF2,0xCDF2,0xADF2,0x4BF2,0xC9F1,0x4BF2,0x4DF3,0x4DFB,0x8EFB,0x6FFB,0xB0FB,0x52FC,0x36FD,0x9AFD,0xDCFE,0xD5FC,0x34FC,0x74FC,0x32FC,0x12FC,0x4FFB,0x0EFB,0x90FB,0x95F4,0xF0C3,0x0B83,0x2A63,0x4A63,0x2A63,0x2A63,0x4963,0x2A5B,0x4A6B,0x2B63,0x4A63,0x4A63,0x2A5B,0x4A63,0x2A63,0x2A5B,0x0A63,0x2963,0x4A63,0x2A6B,}, +{0xC6DF,0xC7E7,0xE8E7,0xCAEF,0xEAEF,0xEBEF,0xCBEF,0xCBE7,0xEAE7,0xC9E7,0xEAEF,0xC9EF,0xCAEF,0xC9EF,0xE9EF,0xC8E7,0xC9E7,0xCBEF,0xCAE7,0xCBD7,0xA9C7,0x07A7,0xC896,0xEC9E,0xCC96,0xCA86,0x8A76,0x4A6E,0x8B66,0x0B87,0x0C8F,0x2987,0xEB86,0x4D7E,0xD36D,0x766D,0x9A5C,0x5C5C,0xBE6C,0xFF74,0xFF8C,0x5F9D,0x5F9D,0x1F9D,0x1F8D,0x1F8D,0xDF8C,0x5F7C,0xFE63,0x5B4B,0xDA42,0x763A,0x7332,0x753A,0x7532,0x533A,0x3332,0x1232,0xD021,0xAE19,0x6E19,0x2D11,0xEC10,0xEA08,0xEC08,0x0D09,0xEC08,0xED08,0xCC08,0x0F09,0x2E19,0x7119,0x7211,0xB529,0x9421,0x3119,0x0F11,0x8E08,0x8D08,0xAD00,0xCF08,0x2F09,0x9219,0x9129,0xF531,0xF729,0x162A,0x9421,0xD329,0xB63A,0x7C53,0xBD5B,0x9C5B,0x1E5C,0x9F74,0x5F6C,0x1E64,0xDD53,0xBE63,0xDF6B,0x7F5B,0xBF42,0x9E42,0x3F53,0x5F5B,0x7F5B,0xBF63,0x7F63,0x5F4B,0x1D43,0x993A,0x7A3A,0x1C53,0x1E43,0x3D4B,0x3E64,0x7C43,0x1F64,0x3F74,0x5F6C,0x1E43,0x5E2A,0x7511,0x1409,0x1309,0x9219,0x1211,0xF221,0x7C4B,0xFF7C,0xDF84,0x3F74,0x9E32,0x7419,0x5019,0x7209,0x7519,0xB519,0xFC3A,0x7F6C,0xDF6B,0x1C22,0xFB21,0x5E32,0x7F5B,0x5E3A,0x5609,0x8E08,0x6C08,0xAE08,0xCF10,0x0F11,0xAE11,0x4C19,0x6D19,0x5119,0x5B32,0x7F4B,0x7B2A,0xD829,0xF418,0xAF10,0xCF08,0x6B08,0x8C00,0x4800,0x6908,0x6C00,0x4B00,0x2508,0x4510,0x0418,0x0328,0x0048,0x0068,0x0180,0x2198,0x63A0,0x83A8,0x62A8,0x61A8,0xA2B0,0x04B1,0x45B9,0xA3C0,0xC3C0,0x67C9,0xC7C9,0x67C9,0xC7C9,0xC7D1,0xABE2,0xB0F3,0x31F4,0xF0F3,0x10EC,0x0CE3,0x0CEB,0x4DF3,0xEAF2,0x4CF3,0x8EFB,0xAFFB,0x51FC,0x72FC,0xB3FC,0xB4FC,0x16FD,0xF5FC,0x37FD,0xF5FC,0x50FB,0xB1FB,0xF2FB,0xB5FC,0xD4FC,0xD1FB,0xEDFA,0x2FFB,0x71FB,0x11D4,0xEA9A,0x2A63,0x4A6B,0x2A6B,0x2963,0x4963,0x496B,0x4A63,0x2A5B,0x2A63,0x2A63,0x2A63,0x4A63,0x4B63,0x4A5B,0x2A6B,0x4963,0x2A63,0x2A63,}, +{0xE7DF,0xE7E7,0xCADF,0xEAE7,0xCBE7,0xECE7,0xCBE7,0xCBE7,0xC9E7,0xCAE7,0xC9E7,0xC9E7,0xC8E7,0xC8E7,0xC7E7,0xC7E7,0xC8E7,0xC7E7,0xC8D7,0xC8C7,0xA8B7,0x289F,0xC896,0x688E,0xC875,0xA75D,0xA75D,0x474D,0x8955,0xEA75,0x097E,0xE875,0xC86D,0x2865,0x8A44,0xAC33,0xB133,0x943B,0xB73B,0x5833,0x3933,0xBB3B,0x5B3B,0x7D43,0x9D3B,0x5C4B,0x5D53,0x5D4B,0x7C4B,0x1A4B,0xDA4A,0x763A,0x7342,0x5442,0x3342,0xEF31,0xCF21,0xF131,0xD231,0xAF29,0x4E19,0x4F19,0xB021,0xF331,0xF431,0xD629,0x9431,0x9321,0xD321,0xD621,0x7429,0x7319,0x5311,0x1109,0xAF08,0xCD08,0xCB08,0xC910,0xED08,0xEF18,0xAE08,0xCD10,0x4F11,0x9119,0x9221,0xB311,0x5219,0xB219,0x963A,0x1C4B,0xFF6B,0x3F6C,0x3F95,0x5F8D,0xBF7C,0xDF84,0xBF7C,0x7F6C,0xDF63,0x3F53,0xBE42,0xFB29,0xDB21,0xDC29,0xBC29,0xFB29,0x3B32,0xFB29,0xDB21,0x9C3A,0x7C4B,0x1D54,0x7E64,0x9F74,0x5F74,0x9F7C,0x7F5B,0x7F63,0x5F5B,0x3F53,0x5E32,0xBD21,0x3611,0xF208,0x7419,0x3411,0x5319,0x1B4B,0x3F74,0x5E6B,0x9E42,0xFC31,0x7919,0x9521,0xF431,0xF321,0xB429,0xB521,0x1B43,0xDE4A,0x7B21,0xF510,0x5719,0x7D32,0xDB21,0xD810,0xD200,0xAD00,0x6D00,0xCE08,0x3009,0xD519,0xB219,0x7129,0x542A,0x7221,0x5C32,0x7F4B,0xF721,0xF218,0x8F08,0xCC08,0xEC10,0x8A00,0x6B00,0x2700,0x9000,0xD300,0x6E00,0x2810,0x2518,0x0328,0x0130,0x0050,0x0070,0x0078,0x2088,0x2198,0x83A8,0xC2A8,0xE4B0,0xA4B0,0xE4B0,0xC4B8,0x83C0,0xC3C0,0xA4C0,0xE4C0,0xE5C8,0x06D1,0x27D1,0x25D9,0x67E1,0x2BF2,0x0EFB,0x75FC,0x57FD,0x35FD,0xF4FC,0x35FD,0x15FD,0x94FC,0x73FC,0x94FC,0x94FC,0x74FC,0x33FC,0x54FC,0x33FC,0x92FB,0x93FC,0x90FB,0x6CFA,0xD2FB,0x75FC,0x74FC,0xD1FB,0x0EFB,0xEEFA,0xEEFA,0x53F4,0xCBB2,0x4A63,0x6A63,0x2A63,0x2A5B,0x4963,0x2A63,0x2A63,0x4A63,0x2963,0x4A6B,0x4963,0x4A63,0x4A63,0x4963,0x2A63,0x4A63,0x2A63,0x0A63,}, +{0xC7D7,0xE8DF,0xE9D7,0xCADF,0xCBE7,0xECE7,0xCCE7,0xCCEF,0xCAEF,0xE9EF,0xC9EF,0xE9EF,0xE8EF,0xC7EF,0xE7EF,0xC8EF,0xE9EF,0xCAE7,0xC9DF,0xEADF,0xC9CF,0xA9BF,0x489F,0x877E,0x0776,0x665D,0x2555,0x0645,0xA665,0xE775,0xA865,0x8855,0x4645,0xA74C,0x6D4C,0xD043,0x9343,0x5643,0x784B,0xBA53,0x7B53,0x9B4B,0x3C4B,0x1C4B,0x7B4B,0x7B5B,0x5B5B,0xFA52,0xD742,0x553A,0x7542,0x7442,0xF339,0xF431,0xD329,0xD121,0xAF29,0x7129,0x5021,0xD129,0x1232,0xB229,0x5221,0xCF18,0x8D08,0xAD08,0x8F10,0xD118,0x1219,0x3419,0xF318,0xD110,0xD010,0x8E08,0x8A08,0xCC08,0xAB10,0xA808,0x6808,0xC908,0x0C11,0xB231,0xB221,0xF629,0xF639,0x773A,0x1432,0x583A,0x983A,0xBB4A,0xFE52,0x3F53,0xDF63,0x1F6C,0xDF6B,0xBF5B,0xBF5B,0x5F53,0xBE3A,0x5D32,0x1C2A,0x7619,0xF208,0x5419,0xB619,0x9721,0x9719,0xB619,0xDC3A,0xFF63,0x5F74,0x1F6C,0xBF5B,0x1F53,0x1F4B,0x5D42,0x3A21,0x7B29,0x7B19,0x5B21,0x1719,0x1719,0x3109,0x3001,0x9419,0x7922,0x5922,0xFA21,0x7A19,0xB608,0xD508,0x7619,0x9619,0xB719,0x3732,0xB319,0xD421,0x5832,0x5E43,0x3B22,0x1511,0x3111,0x1219,0x3411,0xF210,0xB108,0x6D00,0x4B08,0x522A,0xB22A,0x7519,0xD821,0xF621,0xDA3A,0xFA3A,0xD329,0x1A2A,0x3B3A,0xB219,0xAA10,0xCD10,0xCD08,0x8C08,0x8C08,0x6C00,0x4A00,0xD600,0xF700,0x9108,0x2718,0x0520,0x0230,0x0040,0x0058,0x0078,0x2188,0x4290,0x6290,0x61A0,0x61A8,0x22B0,0x63B8,0xC4C0,0x63C0,0xA3C8,0xE4C0,0x05C1,0x46C9,0x45C9,0xC4C8,0xC4C8,0xE4D0,0xC4D0,0xC5D8,0x07E9,0x49F1,0x2CFA,0xAEFA,0xEEFA,0x50FB,0x30FB,0xEFFA,0xB2FB,0xD1FB,0x90FB,0x90FB,0xF2FB,0xB1FB,0x2FFB,0x0EFB,0x4FFB,0xADFA,0x90FB,0xF3FB,0xD2FB,0xF2FB,0x53FC,0x2EFB,0xADFA,0xEEFA,0x11FC,0x4DD3,0x6B7B,0x2963,0x2A63,0x2A6B,0x2A6B,0x2A63,0x2A63,0x2A63,0x2963,0x2A63,0x2A5B,0x2A63,0x4A63,0x4963,0x4A63,0x4963,0x2A63,0x2A63,}, +{0xE7D7,0xC7D7,0xE7DF,0xC9DF,0xEBE7,0xCBE7,0xCCE7,0xCBE7,0xCAE7,0xC9E7,0xC9EF,0xC8EF,0xC8EF,0xC8EF,0xC8EF,0xC9EF,0xCBEF,0xCCE7,0xCDE7,0xCCE7,0xCBDF,0xEBD7,0xA9BF,0x2AAF,0x8986,0x286E,0xA665,0x6755,0xC665,0xE765,0x484D,0x274D,0x0855,0x474C,0x8733,0xE822,0x692A,0xEC32,0xEE32,0xF03A,0xF13A,0x133B,0x933A,0xB53A,0xF542,0xB642,0xB642,0x7442,0x5132,0x5142,0x0F32,0xAF29,0xCE19,0xF119,0x121A,0x3422,0x743A,0x5332,0x342A,0x1532,0x9221,0x2E19,0xEB08,0xEA08,0xE908,0xA908,0xC800,0xE808,0xA800,0xA700,0xC900,0x0D09,0x2F09,0xEE08,0x0D09,0xEC08,0xAB10,0xE910,0x8A10,0xAA08,0xAC10,0xD010,0xB429,0xF629,0x773A,0x583A,0xB842,0xFA3A,0x1B43,0x9A3A,0x1D3B,0xFE42,0x7E3A,0xFC29,0xDC29,0x5D32,0xFC31,0xBB29,0x5921,0x5821,0x1511,0xF100,0xCC00,0x2F11,0xB219,0x7521,0xD729,0x7421,0x1A2A,0x1D2A,0xFE29,0x3E3A,0xFD31,0x9C21,0x3A11,0xB208,0x6B00,0x6E00,0xD210,0xB100,0x1209,0x5609,0x7409,0x582A,0x5E53,0xDF53,0xBE53,0x1E33,0xDC19,0x1509,0x1309,0x5619,0xD921,0x7511,0x7319,0xB93A,0xBC53,0xFE7C,0x1F5C,0x5B2A,0x3311,0x2F09,0xEF10,0xEC10,0xAB08,0x6908,0x4800,0x2B29,0xFC9D,0xFB7C,0xD429,0xB621,0xD521,0x1F5C,0x3D43,0xF321,0x9519,0x3211,0x0B09,0xA708,0xCC10,0x5009,0x8E08,0x8F08,0x9000,0x6E08,0xB608,0xD908,0x7010,0x2620,0x0328,0x0138,0x0040,0x0058,0x0088,0x0188,0x2198,0x0198,0x00A0,0x00A0,0x22A8,0x22B0,0x42B8,0x22B8,0x42C0,0x42C0,0x83C0,0xA4C8,0xA4C8,0xC4D0,0xE4C8,0x05D1,0x25D1,0x05D9,0xC4D8,0x47E9,0xE5E8,0x47E1,0xC9F1,0xEAF9,0xEAF1,0xEAF1,0xCEFA,0xEFFA,0x30FB,0x0EFB,0x8DFA,0x0AFA,0xCDFA,0x0EFB,0x8CFA,0x12FC,0x94FC,0x70FB,0x4FFB,0x13FC,0xF2FB,0x0EFB,0x2BFA,0x6CFA,0x6CFA,0xEAE1,0xCF9B,0x0A63,0x2A63,0x2A63,0x2A63,0x2A6B,0x4A6B,0x2A63,0x4963,0x2A63,0x2A63,0x695B,0x2A6B,0x2A5B,0x2A5B,0x4A63,0x4963,0x2A5B,}, +{0xC6DF,0xE7D7,0xC6D7,0xC7D7,0xEAD7,0xEBDF,0xCCE7,0xCCEF,0xCAE7,0xCAEF,0xC9EF,0xE9EF,0xE8EF,0xC8EF,0xE8EF,0xCBEF,0xCCEF,0xCCDF,0xECDF,0xEBE7,0xCBDF,0xCACF,0xA8B7,0x68B7,0x89BF,0x69A7,0x289F,0xE78E,0xA786,0xE765,0x6855,0x065D,0x2634,0xA533,0x673B,0xE932,0x0A33,0x4D33,0xB14B,0x935B,0xF34A,0xF542,0x964A,0x9542,0x742A,0x5432,0x143A,0x3332,0x7332,0x713A,0x912A,0xD33A,0x164B,0x194B,0x5B53,0x7D53,0x3C53,0xDA52,0xFA42,0xB83A,0x342A,0x9021,0xB021,0xB531,0xF529,0x153A,0x363A,0xD631,0xB319,0xB321,0x9221,0x1111,0xCF08,0xCE08,0xED08,0xCB10,0xAB18,0xAC10,0xA908,0xC900,0x2C11,0x9221,0x763A,0xFB4A,0x5D4B,0x9D5B,0xBE53,0xDF53,0xDF5B,0x5E5B,0x1E4B,0xFF42,0x7D3A,0xDA29,0xF919,0xF721,0xD831,0x7621,0x1319,0xF210,0x7019,0xEC10,0x2C11,0x5119,0x9419,0x7319,0x7719,0x7519,0x3521,0x7821,0xF710,0xF508,0x9310,0x5008,0x8D00,0xAC08,0x4F11,0xCE10,0xCC08,0x3311,0xD819,0x7811,0x782A,0x3C43,0x9F7C,0xDF84,0x3F6C,0xDF42,0x9C11,0xF500,0x1011,0x9421,0xD929,0x7521,0x5932,0xDE5B,0x5F8D,0x9F7C,0x5C32,0xD929,0x1111,0x3009,0x3011,0x2C19,0x0C11,0x0911,0x8610,0xEB28,0x5B84,0xD231,0x0E19,0xEF18,0xFA42,0x7F74,0xDD53,0xD219,0xCE10,0xD419,0xEB10,0xEB08,0xEE10,0xED08,0x8D08,0xD408,0xD508,0x8D08,0x9218,0xD810,0x4C20,0x0428,0x0030,0x0040,0x0048,0x0060,0x0080,0x0080,0x0088,0x00A0,0x01A0,0x21B0,0x42B0,0x22B8,0x42B8,0x62B8,0x62C0,0xC5C8,0xE5C8,0xE5C8,0xE5C8,0x05C9,0xA3C0,0xA5D0,0x05D1,0x67D9,0x87D9,0x46D9,0xA4D8,0x26E1,0x26E1,0x67E9,0x66F1,0xC5E8,0x47F1,0x47F1,0x89F1,0xE9F9,0x2AF2,0x2AFA,0x8DFA,0xCDFA,0x12FC,0x53FC,0xF3FB,0x91FB,0x91FB,0xF2FB,0x70FB,0xACFA,0x2AFA,0x2BFA,0xCAF9,0xE9E9,0xEB9A,0x0A63,0x4A63,0x2A63,0x4A63,0x2A63,0x4A63,0x2A5B,0x2A63,0x4A63,0x2A63,0x4963,0x4A63,0x4A63,0x2A63,0x2A5B,0x495B,0x0A63,}, +{0xC6D7,0xC7DF,0xC6D7,0xC8CF,0xCAD7,0xEADF,0xCAE7,0xCAE7,0xC9E7,0xCAEF,0xE9EF,0xE9EF,0xE8EF,0xE8EF,0xC8EF,0xCBEF,0xCBEF,0xCBE7,0xCCE7,0xCBE7,0xCBE7,0xCADF,0xC9D7,0xC8CF,0xC7D7,0xA8BF,0x47AF,0xE796,0x8776,0x2A76,0x6965,0x8644,0xA423,0x442B,0x662B,0x6833,0x2933,0x6E43,0x914B,0xF14A,0xB33A,0x923A,0x312A,0x0F22,0x0E22,0xCE29,0x1142,0x1453,0x5653,0x795B,0xBD63,0xBD5B,0x5D5B,0x5E53,0x9E5B,0xBE5B,0x9E5B,0x9D5B,0x9D53,0x5D4B,0x5B3B,0xB732,0x762A,0xF721,0xD621,0x5321,0x3521,0x5521,0xB521,0xB621,0x7421,0x5119,0x7021,0x4F19,0xED10,0xCC08,0x8A08,0x8B10,0xAA10,0x6E19,0x753A,0x5A4B,0x1D6C,0x9F7C,0xBF7C,0xFF84,0xFF8C,0xDF7C,0xBF7C,0x1F64,0xFE42,0x7D2A,0xD921,0x5511,0x3209,0x9119,0xD521,0xD411,0xB419,0x9421,0x5111,0x2E11,0x7019,0x3011,0x7419,0x9419,0xB821,0x9821,0x9429,0x3209,0xAE10,0x0F11,0x1011,0x2F11,0xF429,0x3732,0x9311,0x3019,0x4D11,0xD719,0x7C2A,0x7932,0xBC4B,0xFF63,0x9F63,0xFE52,0x9E3A,0xFC21,0x3911,0xB300,0x7211,0x7521,0xB721,0xB721,0x5A3A,0x1E6C,0xDF6B,0x7C3A,0x9911,0xF210,0x1119,0x9519,0x9319,0xD021,0xCF21,0xCD21,0x8A21,0x8C19,0x713A,0xA808,0xA608,0x8D10,0xBD5B,0x9F74,0xFB4A,0x0E19,0xB319,0x5119,0x5011,0xF210,0x7411,0xCE08,0x4E08,0xD100,0x3511,0xAB10,0x4B20,0x6F18,0x0528,0x0030,0x0038,0x0048,0x0048,0x0060,0x0070,0x0080,0x0088,0x01A0,0x0098,0x00A8,0x22B0,0x63B0,0xA4B8,0x84B8,0x63C0,0x84C0,0x43C0,0x01C8,0x43C8,0x84C8,0xC5D0,0xC8D1,0xE4D0,0xE5D8,0x47E1,0x67E1,0xC8E1,0x86D9,0x25D9,0x46D9,0x05E1,0xA3E0,0xA2D8,0x26E9,0xE9F1,0x8CFA,0xEFFA,0xEDFA,0x4FFB,0x90FB,0xB1FB,0x71FB,0xD2FB,0xD3FB,0xB2FB,0xD2FB,0xB1FB,0x0EFB,0x8CFA,0x2BFA,0xC9F9,0x4BF2,0x48AA,0x2A63,0x2A63,0x0A63,0x2A63,0x2B63,0x2A63,0x4A5B,0x0A5B,0x4963,0x495B,0x2963,0x295B,0x295B,0x495B,0x4963,0x2A63,0x0963,}, +{0xC7C7,0xC7D7,0xC7CF,0xA8C7,0xAAC7,0xEBCF,0xEBDF,0xCAE7,0xC9E7,0xC9EF,0xC9EF,0xC8EF,0xE8EF,0xC8EF,0xC9EF,0xCBEF,0xCCE7,0xCCE7,0xCBE7,0xCAE7,0xCAE7,0xC9DF,0xC9D7,0xE8D7,0xC7CF,0xA7BF,0x27B7,0x8596,0x066E,0x865D,0x4745,0x0645,0x0534,0x2423,0xE522,0x072B,0x2733,0xE932,0xCA2A,0xAB2A,0xAD32,0x8D2A,0xB042,0x7232,0x9132,0xB342,0x924A,0x943A,0x7532,0x763A,0xBA42,0x3B3B,0x9B43,0x5C5C,0xFD74,0x3D85,0xBE7D,0x9F95,0x9E95,0x3E95,0xFF84,0x3E74,0x9C53,0xFA4A,0x3532,0x9021,0x6F21,0x6E21,0x4D11,0x0F11,0x1121,0x1019,0xF118,0x3109,0x1011,0x2F09,0xEF18,0xED18,0x2D21,0x364A,0xFD4A,0x1E4B,0x5F63,0x9E63,0x1F64,0x1F74,0x1F74,0xDF63,0x9F5B,0xDE42,0x5C2A,0x191A,0x3932,0x1722,0xD621,0xB721,0x7721,0xB821,0x9721,0x5511,0x3219,0x5119,0x7119,0x7119,0x9721,0x9619,0x5719,0x7821,0x3411,0x1311,0x2D19,0xB219,0x1632,0xB529,0x1219,0x7519,0x132A,0x554B,0x1943,0x7B3A,0xBE53,0x7E5C,0xFE63,0x1B2A,0x9A21,0x7919,0x7A19,0x9819,0x1519,0x8D08,0x3319,0x7721,0x582A,0xDC32,0xDC32,0xBE5B,0x5B3A,0xB821,0x3411,0x4F09,0x5219,0x7219,0x9221,0x3332,0x112A,0x3232,0x923A,0xF229,0xCE29,0x2911,0xA710,0xF018,0x3E4B,0x3F6C,0x3832,0x8A10,0x9219,0x5011,0xCF10,0x3721,0xD921,0x1301,0x6C08,0x4908,0x1319,0x6918,0x0428,0x2428,0x0028,0x0030,0x0038,0x0048,0x0050,0x0060,0x0068,0x0078,0x0088,0x0198,0x0198,0x01A0,0x01A8,0x02A0,0x01A0,0x01B0,0x01B8,0x22C0,0x42C0,0x63C8,0x63C0,0x42C0,0x43C8,0xE6C8,0x67C9,0xE4C8,0x43D0,0xC6D8,0xEAE1,0x8BEA,0x4AEA,0xABEA,0x8BEA,0x2AF2,0x08EA,0x2AF2,0xCCFA,0xEEFA,0x0EFB,0x2EFB,0xEDFA,0x2BFA,0x2BFA,0x6DFA,0x30FB,0xB2FB,0xB2FB,0xD3FB,0x13FC,0x91FB,0xCDFA,0x0BFA,0x0AFA,0x88F1,0xE7B9,0x4A6B,0x0A63,0x2A63,0x2A63,0x2A63,0x2A63,0x2A63,0x2A63,0x4A5B,0x2A5B,0x2A63,0x2963,0x495B,0x495B,0x2A5B,0x2A5B,0x2A63,}, +{0xA5B7,0x85B7,0x67B7,0xE8A6,0x2AB7,0xCBC7,0xCBD7,0xEBE7,0xCAE7,0xC9E7,0xC9E7,0xC8E7,0xC8EF,0xC8EF,0xCAEF,0xECE7,0xCCE7,0xCBDF,0xEBD7,0xEADF,0xC9DF,0xC9DF,0xC9D7,0xC8CF,0xC6BF,0x86B7,0x06A7,0xC58E,0x6786,0x665D,0xC52C,0x642C,0xC423,0x273C,0x294C,0xC94B,0xA94B,0x4A4B,0x0B3B,0xCD42,0x3153,0xB242,0xD242,0x743A,0xB43A,0xD752,0x7642,0xB73A,0x594B,0x5B64,0x5E85,0x1FA6,0x5FB6,0x5FB6,0x3FBE,0x3FB6,0x1FAE,0xBFA5,0x7F95,0x9F84,0x1F74,0x3D5B,0x9A42,0x5942,0xF631,0xB429,0xD531,0xD531,0xD421,0x1532,0x132A,0xAF11,0x4E11,0xB421,0x5221,0x3019,0x8F19,0x5019,0x0D11,0xB421,0x1A32,0xF931,0x5B32,0x9D32,0x9E32,0x9E42,0x7D3A,0x1D32,0x1C32,0xB921,0x7619,0xB531,0xB621,0xB729,0x7529,0x7519,0x9419,0x7419,0x7611,0x5719,0x7419,0x3211,0x9319,0xB319,0x1522,0x152A,0xB53A,0x9A53,0x973A,0x142A,0x3119,0xF010,0x1009,0x7211,0xD529,0x795B,0x995B,0x5D6C,0x5E6C,0x7F95,0x7F95,0x1F85,0xBF63,0x5B32,0x9619,0xB621,0x3419,0xF210,0x2F19,0x0B11,0x9221,0x7B32,0xBD42,0x7F64,0xFF74,0x9E53,0x9719,0x1319,0xEE10,0xB119,0x3019,0x9119,0xF631,0x363A,0xB83A,0x5A53,0xD742,0xF329,0x4F19,0x2C11,0xCA10,0x7129,0xBC4A,0xBF53,0x7319,0x4708,0x6E00,0x9311,0xD210,0x1819,0x1D2A,0x3509,0x4908,0x4610,0xF020,0x8428,0x2028,0x0030,0x0030,0x0040,0x0038,0x0050,0x0058,0x0060,0x0078,0x0078,0x0088,0x0190,0x0098,0x0098,0x01A0,0x01A0,0x01A0,0x00B0,0x00A8,0x01B8,0x01B8,0x02C0,0x43C0,0xE5C0,0x42B8,0x84C8,0x47C9,0x25C9,0x62D0,0xC5D0,0xC5D8,0x07E1,0x27E9,0x88F1,0xEAF1,0xEAF9,0xC9F9,0x0AFA,0xC9F9,0xC9F9,0xCAF9,0xCAF9,0x68F9,0x67F9,0x88F9,0xADFA,0x30FB,0xEFFA,0x91FB,0xD3FB,0xF3FB,0xD2FB,0xEEFA,0x2BFA,0xADFA,0x67F1,0x46C9,0x0973,0x0A63,0x4963,0x2A63,0x2A5B,0x2A63,0x2963,0x295B,0x2A63,0x4963,0x4963,0x2A5B,0x2963,0x2A63,0x2963,0x4963,0x295B,}, +{0x25AF,0x05A7,0xC69E,0x477E,0xCA9E,0x6BB7,0xCBD7,0xCADF,0xCAE7,0xE8EF,0xE8EF,0xE7EF,0xC7E7,0xC9E7,0xC9E7,0xCBDF,0xCBDF,0xCBD7,0xEBCF,0xCBD7,0xCAD7,0xC8CF,0xE8CF,0xC8C7,0xC7BF,0x46AF,0xA59E,0x457E,0x4666,0xA655,0x8845,0x4845,0xA734,0x283C,0xE93B,0x6733,0x692B,0x072B,0x0933,0xEB32,0xCE32,0xD032,0xF13A,0xB342,0xB432,0x3553,0xF96B,0x9D7C,0x3F8D,0x7F9D,0x7F95,0x3F8D,0xFF84,0x3F8D,0x3F85,0xFF74,0x1F85,0x9F74,0xDE5B,0xFD42,0x9A2A,0xD942,0x7953,0xDB5B,0xDB5B,0xFC63,0x3C64,0x3D64,0x3C64,0x3D6C,0xBC4B,0x5A4B,0x5732,0xD521,0x9121,0xB219,0x8F19,0x2F11,0x0E11,0x0E11,0x1121,0x5219,0x9729,0xB621,0x7821,0x7619,0x5319,0x5519,0xD829,0xB521,0x9311,0x9421,0x7421,0x9519,0xB621,0x392A,0x1A22,0xD821,0x182A,0xF829,0x182A,0x7A2A,0x7C3A,0x3932,0x3A32,0xF829,0xF94A,0x593A,0x7419,0xB321,0x7119,0xF621,0x1722,0x1B4B,0x1A4B,0xF84A,0xDB5B,0xFF8C,0x5F95,0xDF8C,0x1F6C,0x3E53,0x1D32,0x9919,0x3109,0xF508,0xF108,0x0D11,0x2B09,0xAF19,0x7632,0x9E5B,0xBF7C,0xBF9D,0x7F74,0xFE3A,0xB619,0x5319,0x7011,0x3011,0x2E21,0xF619,0x1932,0x9B3A,0xBE53,0xBF74,0x1A43,0xB219,0x0F19,0x2C11,0xEC10,0x4D19,0xB521,0x7942,0xAE10,0x2900,0x9100,0xF600,0xD610,0x1919,0xBE42,0x5719,0x4510,0x8320,0xE728,0xC130,0xC030,0x2030,0x0038,0x0040,0x0048,0x0058,0x0058,0x0060,0x0070,0x0078,0x0080,0x0190,0x0088,0x0088,0x0088,0x0190,0x0098,0x0098,0x00A0,0x00B0,0x01B0,0x00B0,0x00B0,0x01B8,0x01B8,0x02C0,0x84C0,0x63C0,0x62C8,0x42D0,0x42D0,0xA5E0,0xE5D8,0x62E0,0x84E0,0xE6E8,0xE5E8,0x05F1,0xC5E8,0x88F1,0xE9F9,0x0AFA,0xC9F9,0x87F9,0x68F9,0x2BFA,0x6DFA,0xADFA,0x2DFA,0x30FB,0xD3FB,0x54FC,0x4FFB,0x2BFA,0x8CFA,0x68F1,0xE5C8,0xEA7A,0x0A63,0x2A63,0x2A63,0x2A63,0x0A63,0x0A5B,0x2A5B,0x2A63,0x2963,0x2A63,0x2A63,0x2963,0x2A5B,0x295B,0x495B,0x2A63,}, +{0xC486,0x848E,0x067E,0x087E,0x8B9E,0x4CBF,0xCAD7,0xCBDF,0xAAD7,0xC7D7,0xC5DF,0xE6E7,0xC8E7,0xCAE7,0xCAE7,0xCBDF,0xCAE7,0xC9DF,0xC9D7,0xC9CF,0xE9D7,0xC8D7,0xC9CF,0xC8CF,0xA7B7,0xC58E,0x2676,0x6876,0x6A66,0xA85D,0x894D,0x0945,0xC734,0xAA3C,0x093C,0x2A44,0xAB3B,0x2C3B,0x6E3B,0x7043,0x323B,0x134B,0xF43A,0x943A,0x765B,0x3B84,0xFC7B,0xDD73,0x9D63,0x5D63,0x5D63,0xDD63,0xDE6B,0x5E84,0xDD63,0xDD6B,0x1E74,0xBE63,0xFD4A,0xBC4A,0x9D5B,0x7C63,0xDD63,0x3E64,0xBE6C,0x3F85,0x7F8D,0x9F8D,0x7F8D,0x3F8D,0xFF7C,0x1F6C,0xFD4A,0x793A,0x352A,0x1422,0x9021,0x6F19,0x4F19,0x0D19,0xED18,0xEC10,0xCE10,0xCD08,0xCF18,0x7019,0x7321,0x9219,0xD719,0x172A,0xF519,0x1522,0x562A,0x782A,0xDC42,0x5E53,0x5E4B,0xFD42,0xBC32,0x9B3A,0x7A2A,0x7B32,0x7C3A,0x7932,0xBA3A,0x5A32,0xF829,0x1A2A,0x1922,0x1822,0x7A32,0x7C32,0x3A32,0x1832,0x162A,0x184B,0x3E6C,0x1F6C,0xDF63,0xDE6B,0x5D32,0xBD29,0xDD21,0x9919,0x7319,0x3211,0x9521,0x9019,0xAE19,0x1232,0xD842,0x3E74,0x5F8D,0x3F7C,0x5F4B,0xB919,0xD719,0x9419,0x9319,0xB211,0xB421,0x572A,0x7B3A,0x5E53,0x3F8D,0x3E85,0x7D53,0x7321,0x7219,0xAC10,0xEE18,0x2D09,0x4F21,0x4F31,0xEE08,0x6A00,0x9508,0x1809,0xF610,0xDA18,0xDE29,0xF318,0x2210,0x4120,0x4120,0xC130,0x2149,0x2038,0x0040,0x0048,0x0058,0x0058,0x0060,0x0060,0x0070,0x0078,0x0078,0x0188,0x0080,0x0080,0x0088,0x0090,0x0090,0x0098,0x0098,0x01A0,0x01A8,0x01B0,0x00B0,0x00B8,0x01B0,0x01B8,0x02B8,0x02C0,0x22C0,0xC5C8,0x05D1,0x05D1,0xC3D8,0xA2D8,0xC3D8,0x06E1,0x46E1,0x05E9,0x06E9,0x47F1,0xA9F9,0xC9F9,0xA8F9,0x05F9,0x88F9,0x88F9,0xC9F9,0xA8F9,0xABF9,0xEFFA,0x72FB,0x54FC,0x90FB,0x2BFA,0x0AFA,0xA9F1,0xE6D8,0xA98A,0x4A63,0x0A63,0x2A63,0x4A5B,0x2A63,0x2A5B,0x2A63,0x2963,0x2963,0x2A63,0x2A63,0x295B,0x295B,0x2963,0x2953,0x0A63,}, +{0x8476,0x045E,0xC565,0xE885,0xABA6,0xCAAE,0x09AF,0x29A7,0x48B7,0xC7CF,0xC7E7,0xCAE7,0xCBE7,0xCBE7,0xCBE7,0xEADF,0xCAE7,0xE9DF,0xE8D7,0xC8C7,0xC7CF,0xE9CF,0xC9C7,0xA8B7,0xA9B7,0x489F,0xC886,0xE765,0x484D,0x493D,0xE73C,0x8734,0x8934,0xEB4C,0x2A3C,0x8933,0xCD43,0x8D43,0x8F4B,0x104B,0xD04A,0x7032,0x532A,0x942A,0x7532,0x553A,0xB219,0xB111,0xB411,0x9319,0x5219,0x5111,0xF110,0xCF10,0xED00,0xCD00,0x2F09,0xF121,0xF542,0xFA63,0x1D85,0xBF9D,0xFFAD,0xDFAD,0xDFA5,0xFFAD,0xDFAD,0xBFA5,0x7F95,0xDF8C,0x1F7C,0x3E53,0x5B32,0x5722,0xF319,0xEF19,0xCD21,0xED21,0xCE19,0x0F1A,0x0F1A,0xCE19,0x9011,0x8F11,0xB321,0x1522,0x172A,0xF631,0xB621,0x5742,0xB742,0xFC42,0x3E53,0xBE3A,0x7E42,0x9E42,0x5E32,0x7E32,0x7D3A,0x9C32,0xBC3A,0xDC3A,0x9C3A,0x3B43,0xDC53,0x1E64,0x5E64,0x9F74,0x1F64,0x3E43,0xD929,0xD929,0x3932,0xD73A,0x5A64,0xDD5B,0x3C43,0x393A,0xD721,0x5942,0xDA29,0x9921,0xBA29,0xD931,0xF731,0x3832,0xF829,0xF221,0xF229,0x343A,0xFB52,0x7F74,0x1D5B,0xBE42,0x5C2A,0x1922,0x7619,0x7319,0x5211,0x9211,0xF519,0xF731,0xFD4A,0x1F6C,0xDF9D,0x1C6C,0x5B53,0xEE10,0x3019,0xEA08,0x2F19,0x2F11,0x0C11,0x2E11,0x0E01,0x6C00,0x9508,0x7B11,0x1501,0x1911,0xBB21,0x4D18,0x2018,0x4028,0x4030,0x6038,0x8048,0x2038,0x0048,0x0050,0x0058,0x0058,0x0060,0x0068,0x0070,0x0078,0x0078,0x0188,0x0088,0x0088,0x0088,0x0090,0x0088,0x0090,0x0098,0x0098,0x00A0,0x83B0,0x21B0,0x00C0,0x00B8,0x01B8,0x02C0,0x02C0,0x01C0,0xC5C8,0x67D1,0x2BDA,0xE5D0,0xC4D0,0x42D8,0x84E0,0xE4E0,0x84E0,0xE4E8,0x84E8,0xE4E8,0x06F1,0x27F9,0xE4F8,0x88F9,0xA8F9,0x47F9,0x68F9,0x6AF9,0x4DFA,0x72FB,0xB2FB,0x2FFB,0x2BFA,0x0AFA,0xE9F9,0xC4D8,0x699A,0x0A5B,0x0A63,0x295B,0x2A5B,0x2A63,0x4963,0x0A5B,0x2963,0x0963,0x2963,0x2A63,0x4A63,0x2A63,0x2A6B,0x2963,0x2A63,}, +{0xC486,0x4566,0x046E,0x657E,0x868E,0xA896,0x09AF,0x49AF,0xC7CF,0xC8DF,0xC9E7,0xCBE7,0xCCEF,0xCBE7,0xCBDF,0xCACF,0xEAD7,0xC8C7,0xCAB7,0xCAB7,0xA9BF,0xABC7,0xABBF,0xA9AF,0x8AA7,0x2997,0xA77E,0x6876,0xC855,0x2845,0xA83C,0x072C,0x061C,0x292C,0xEB3B,0xEC43,0x6B43,0x2B3B,0x2D33,0x4F43,0x324B,0xB74B,0x9C63,0xFA52,0x5632,0x152A,0x352A,0x1522,0xD421,0x9219,0x7019,0x4F11,0x2E11,0xEF18,0x0C11,0x2C11,0x723A,0xDC73,0xDE7B,0x1F7C,0x3F7C,0xFE7B,0xBE73,0xBE6B,0x9E63,0xBE6B,0x7D5B,0x5D5B,0xDC52,0x5B3A,0xDA29,0x191A,0xD819,0x1612,0xF532,0x773B,0xFB53,0x5D64,0x5E6C,0x7E5B,0x5C4B,0x7932,0x572A,0xB429,0xB429,0x9521,0x5421,0x3219,0xAD00,0xB021,0xF321,0x9821,0x5A19,0x5A19,0x5B21,0x7B19,0x7A19,0x9919,0x3A42,0x7B32,0xFB3A,0xFD63,0xFF74,0x3F85,0x5F8D,0x1F85,0x7F6C,0x3F6C,0x3F53,0x3C3A,0x192A,0x9832,0x9C74,0x9F95,0xDF7C,0xBE4B,0x7922,0x7221,0x9021,0x9119,0x3311,0x3319,0x3111,0x5221,0x3622,0xD421,0x3832,0x362A,0x5632,0xF531,0x3B4B,0x5E5B,0x3D53,0x1E3B,0x9E32,0x5611,0xD108,0x7419,0x3119,0x3119,0x7319,0xF519,0x3A32,0x9F84,0x9F95,0x783A,0xF229,0x0B09,0x0D19,0x8B10,0x972A,0x0F11,0x2E19,0x5211,0x3109,0x6D08,0x9408,0x7B11,0xF600,0x3819,0xB110,0x0418,0x0020,0x6028,0xA040,0x2040,0x0050,0x0048,0x0048,0x0058,0x0058,0x0058,0x0058,0x0068,0x0070,0x0068,0x0078,0x0078,0x0078,0x0080,0x0080,0x0088,0x0090,0x0098,0x0098,0x0098,0x00A8,0x42B0,0x22B0,0x00B0,0x00B0,0x01B8,0x44C0,0x06C1,0x83C0,0x64C0,0x22C8,0x43C8,0x21C0,0x42D0,0x01D8,0x43E0,0x05E1,0x63E0,0x63E0,0x63E0,0x83E8,0xC4F0,0xE6F0,0xA3F0,0x83F0,0xA4F0,0xE5F0,0x27F9,0x29F9,0xCBF9,0x2DFA,0x6EFA,0x6CFA,0x0BFA,0x8AF9,0xC9F9,0xC5E0,0xC7A9,0x2A63,0x2A63,0x2A63,0x2963,0x2A5B,0x295B,0x2963,0x295B,0x0A5B,0x2963,0x0A5B,0x095B,0x2963,0x0963,0x0A5B,0x2A5B,}, +{0xE48E,0x0597,0x459F,0x47BF,0x48C7,0x6BCF,0x49B7,0x4AB7,0xC7CF,0xC8D7,0xE9DF,0xC9DF,0xE9DF,0xCADF,0xCCD7,0xEBCF,0xE9BF,0xCAB7,0x6AAF,0x4AAF,0xACBF,0x0BB7,0x888E,0xE98E,0x098F,0x0A87,0xA876,0xC85D,0x884D,0xE944,0x4634,0xA62B,0x0744,0x4B44,0x4C44,0x703C,0xB55C,0x1B7D,0x3C64,0xBC5B,0x7C53,0x7B3B,0x5B43,0x5A43,0x393B,0xFA42,0x3B53,0xDA4A,0x9832,0x573A,0x152A,0x152A,0xD319,0x9121,0xB029,0xF021,0x5232,0xB421,0x5319,0x5411,0x1311,0xF210,0xD010,0xCE08,0xCE00,0xEF00,0xCF00,0x4F11,0x152A,0x592A,0x392A,0xF92A,0x1C54,0xDE7C,0x3F85,0x1F75,0x5F8D,0x5F95,0xFF84,0xFF63,0x7E5B,0x5932,0x7219,0x2F19,0x2D19,0x0B01,0x6C11,0xD119,0xB421,0xD519,0x3111,0x1111,0x1209,0xD408,0xD300,0xD208,0xB208,0x9119,0xF942,0x1F74,0xBF74,0x5F74,0x7F74,0x1F74,0xDF5B,0x3F7C,0x9F53,0xBD42,0x5921,0xD619,0x7C6C,0xDF95,0x9F9D,0xDF7C,0x9F5B,0x5D2A,0x7619,0x7211,0x5219,0x5219,0x7311,0x5321,0xD421,0xD629,0x573A,0x793A,0x7A32,0xFC3A,0x3C43,0xD83A,0x1C4B,0xDE5B,0x5F6C,0xDE42,0x9A19,0xD110,0xF110,0x1009,0xAD10,0xB519,0x3622,0xB321,0xF521,0x5E74,0x9E7C,0xD421,0x2E11,0xCB08,0xE810,0x4A10,0xBA3A,0x1011,0x7419,0xD919,0x5722,0x8E00,0x8F18,0xF710,0x9308,0xF610,0xAC08,0x2010,0x0018,0x6030,0xA048,0x2040,0x0048,0x0058,0x0050,0x0058,0x0058,0x0060,0x0060,0x0068,0x0070,0x0068,0x0078,0x0078,0x0080,0x0080,0x0088,0x0088,0x0090,0x0098,0x00A0,0x01A0,0x00A0,0x01A8,0x01A8,0x01A8,0x00B0,0x01B0,0x44B8,0xC5B8,0xA4C0,0x22C0,0x00C0,0x01C8,0x01C8,0x01D0,0x01D0,0x02D8,0x23D8,0x02D8,0x02E0,0x63E0,0x22E8,0x42E8,0x83E8,0x83F0,0xC4F0,0xA4F0,0xC6F0,0xE6F8,0x07F9,0x8AF9,0xAAF9,0x0CFA,0x8EFA,0x4CFA,0x68F9,0xA8F9,0xE4E0,0x67A9,0x0A63,0x2A63,0x2963,0x2A63,0x295B,0x0963,0x2963,0x495B,0x295B,0x2A63,0x2963,0x2A63,0x095B,0x295B,0x095B,0x095B,}, +{0xE4A6,0x45BF,0x46B7,0x66B7,0xA7B7,0xC8CF,0xCACF,0xC9CF,0xC7CF,0xE8DF,0xE8D7,0xC8D7,0xCADF,0xEAD7,0xC9C7,0xAABF,0xA8BF,0xAAAF,0x2BAF,0x0CB7,0x0CAF,0x6A8E,0x2966,0x0C7F,0x2B97,0xCA86,0x6A76,0x484D,0x8734,0x6734,0x6634,0xA62B,0xC83B,0x2B44,0x8F3C,0xD644,0xB84C,0x7B5C,0x5E64,0x5F6C,0x9C53,0xBD63,0x3F74,0x1E74,0x9E63,0x3D53,0xFB52,0x7B42,0x593A,0x3732,0x563A,0x963A,0x9742,0x1532,0xF431,0xF429,0xD221,0x9221,0x7119,0x7011,0x4D09,0x2C11,0xEB10,0x4C11,0x6E11,0x742A,0xD932,0xBC4A,0x9B3A,0x3D4B,0xFE5B,0xDF9D,0xDF9D,0xFFA5,0x1FA6,0xFF9D,0xBF9D,0x3F8D,0x9F7C,0xBF5B,0xBC3A,0x9729,0x5111,0x8F11,0xD432,0x5A43,0x7C4B,0x5D3B,0x3D43,0xBB2A,0x371A,0x9321,0x5219,0x3111,0xF208,0xD108,0xF210,0x563A,0x5B42,0x7E3A,0x5F42,0x5E42,0x5D2A,0x7F32,0xBF32,0xDD52,0xDB63,0x363B,0x3A64,0x9E95,0x3F8D,0xFF84,0x5F74,0x5E5B,0x3D32,0x7719,0x7519,0xB321,0xD429,0x9421,0xD621,0xD629,0xF621,0x9A3A,0x7832,0x7832,0xFE5B,0xBF74,0xBF74,0x5C53,0xDD63,0xFF7C,0xFE42,0xFC21,0x5711,0xD010,0x1211,0xEF08,0xB221,0xF621,0x362A,0x5532,0x363A,0x7A42,0xBC3A,0xF421,0xEF18,0x6C11,0xE708,0xAB10,0xD84A,0x5319,0xD218,0x9B19,0x9D32,0xD200,0x4B00,0x6E10,0x8B10,0xAD10,0xA910,0x4010,0x2010,0x2020,0x0030,0x0038,0x0050,0x0060,0x0068,0x4160,0x0060,0x0060,0x0068,0x0068,0x0078,0x0070,0x0078,0x0080,0x0080,0x0088,0x0088,0x0188,0x0090,0x0098,0x0098,0x0098,0x00A0,0x01A8,0x00B0,0x00B0,0x01B0,0x22B0,0x84B8,0x44C0,0x24C0,0x01C0,0x01B8,0x42C8,0x01C0,0x21C8,0x21D0,0x01D8,0x01D0,0x01D8,0x43D8,0x43E0,0x22E0,0x43E8,0x63E8,0x82E8,0xC4F0,0xA3F0,0xA5F0,0x47F9,0xE6F8,0xE6F8,0x27F9,0xABF9,0x4CFA,0xEAF9,0x06F9,0xA7F9,0x05E9,0x26B9,0x096B,0x0A63,0x296B,0x2A63,0x2963,0x2A63,0x2963,0x2A63,0x2A63,0x0A5B,0x295B,0x2963,0x2963,0x2A63,0x0A63,0x2A63,}, +{0x056E,0x6676,0x0997,0xCBCF,0xCCD7,0xCAD7,0xCBD7,0xCAD7,0xC8D7,0xC8D7,0xC8C7,0xC9C7,0xCACF,0xCAD7,0xC9BF,0x48A7,0x28A7,0x0997,0xCB96,0xEA7D,0xCB75,0x8D96,0xCC96,0xAB7E,0x4A6E,0x0A6E,0x0A5E,0x6855,0x8744,0x282C,0x6834,0xA623,0xE933,0x6D4C,0xD244,0x3855,0xFC5C,0xDE5C,0x5F5C,0xFF53,0x9E4B,0x1C4B,0xFB3A,0x5C4B,0xBD63,0x5B53,0x7B53,0x3B4B,0x5C53,0x7C53,0x5943,0x194B,0x3853,0x1843,0x552A,0x9532,0x542A,0xB321,0x5121,0x7019,0x6F11,0x5019,0x7019,0x772A,0x9D53,0xDF63,0x1F43,0x1C3B,0x1D5C,0xDF7C,0x7FA5,0xDFA5,0x9F9D,0x7F9D,0xFF8C,0x7E84,0x7D6B,0xDC52,0x1A3A,0xB621,0x1522,0x173B,0x3B64,0xFF84,0x5F95,0x5F8D,0x1F85,0xDF7C,0x5F74,0x5F53,0x7C32,0x9521,0x5219,0x3111,0xCF10,0x8F10,0x8D08,0x0F19,0x5411,0x5921,0x3911,0x5A11,0x7B19,0xDB29,0x1611,0xB542,0x5DB6,0x5EA6,0xFEAD,0x7E74,0xBF5B,0xDD4A,0xBB21,0x7921,0x5619,0x5419,0x5211,0x9119,0xF629,0xD731,0xB721,0x173A,0x5832,0x592A,0x5D4B,0x9E74,0x5F85,0xFF7C,0xDF63,0xBD4B,0x1E6C,0xDE52,0xBB21,0x5719,0xF110,0x7319,0x7119,0x2E19,0x2F21,0x6F21,0x6E21,0x9121,0x1522,0x1A43,0x7D4B,0x792A,0x9319,0xD019,0x0809,0x0C11,0xEE10,0xEF10,0x8C08,0x1711,0x3E43,0x3509,0x8C00,0x2600,0x6608,0x6510,0x6210,0x6010,0x6010,0x4018,0x0028,0x0038,0x0048,0x0058,0x0060,0x4160,0x0060,0x0068,0x0070,0x0070,0x0070,0x0078,0x0070,0x0070,0x0078,0x0088,0x0088,0x0088,0x0090,0x0098,0x0098,0x0098,0x00A0,0x00A0,0x00A8,0x01A8,0x00A0,0x49BA,0x43B8,0x02C0,0x02B8,0x01C0,0x01C0,0x00C0,0x00C0,0x82C0,0x01D0,0x00D0,0x00D0,0x02D8,0x43E0,0x63E0,0x43E0,0x43E8,0xA4E8,0x42E0,0x83E8,0xA4F0,0x64F0,0x64F0,0x85F8,0x85F0,0xC5F0,0x48F9,0x69F9,0x06F9,0xE5F0,0x06F1,0x05E1,0xC4B8,0xE97A,0x0A5B,0x0A63,0x0A63,0x0A63,0x0A63,0x2963,0x0A5B,0x2963,0x0963,0x0963,0x0A63,0x2A63,0x2A63,0x2A63,0x0A63,}, +{0xA96D,0x2976,0xCB96,0x6CAF,0xCDBF,0xECCF,0xCCD7,0xECD7,0xCAD7,0x88C7,0xA8B7,0x89BF,0xABBF,0xCBBF,0xCAB7,0x4AA7,0x8886,0x697E,0x4B7E,0x6A6D,0x8D85,0xED85,0x0A7E,0x2A76,0xA95D,0xAA65,0x6B55,0xA955,0xC94C,0x4834,0x672C,0x882C,0xEE5C,0x1165,0xF44C,0x984C,0x5B44,0xFC43,0x1E64,0x7F6C,0x5E74,0x5B5B,0xBC53,0x9F74,0x3E74,0xDE63,0x5E74,0x5F6C,0x5E64,0x7F6C,0x5E6C,0x3E6C,0xFD63,0x9D4B,0x1943,0xB73A,0x743A,0xF021,0xCE19,0xCE21,0x5332,0x7632,0xFC3A,0x3F4B,0x7F5B,0xBF53,0x3F6C,0x9F84,0x9F7C,0xDE73,0x5E6B,0x3E53,0xDE3A,0x9C32,0x9922,0x3622,0x962A,0xF83A,0xBA5B,0x7D7C,0xDF8C,0x1F9D,0x1F95,0x3FA5,0x3F9D,0x9F84,0xDE6B,0xFD5A,0x3B42,0xB929,0x1509,0x3311,0xEE10,0xAA08,0xC910,0xAC08,0xAD08,0xAD10,0xED08,0x1209,0x3309,0x1311,0x1309,0x1311,0xF518,0x7763,0xFEBD,0xBD84,0x5A5B,0xB831,0xD610,0x1619,0xD310,0x9711,0x3619,0x9519,0x5319,0x9521,0xF829,0x7932,0x5A3A,0xF831,0x172A,0x1C4B,0x7F6C,0x7F95,0x5F8D,0xBE5B,0xFE42,0x9942,0x382A,0x5721,0x1619,0xF208,0x5119,0xB319,0xCF21,0xCD31,0xCC29,0x6B29,0x2921,0x5232,0x3432,0x7E74,0x3F75,0x1D43,0x9753,0x9011,0xE908,0x4F11,0x2F19,0xEA10,0x8C10,0xF718,0x1E53,0xD821,0xB008,0x6A00,0x4308,0x4210,0x4010,0x8010,0x8118,0x8018,0x4020,0x2020,0x0038,0x0050,0x0060,0x4270,0xE270,0x0070,0x0070,0x0068,0x0070,0x0078,0x0481,0x0068,0x0080,0x0080,0x0088,0x0090,0x0090,0x0090,0x0098,0x0098,0x00A0,0x00A8,0x00A8,0x01A8,0x01B0,0xC4A8,0x43B0,0x01B8,0x01B8,0x23C0,0x22C0,0x01C8,0x66C9,0xABDA,0x01C8,0x00D0,0x00D0,0x01D0,0x01D8,0x02E0,0x02E0,0x02E0,0xC5E8,0xA3E8,0x83E8,0x42F0,0x23F0,0x63F0,0x63F0,0xC6F0,0x26F9,0x47F9,0x26F9,0x05F9,0x06F1,0xE6F0,0xA4E8,0x05C1,0xA97A,0x0A63,0x2A63,0x0A63,0x2963,0x0963,0x485B,0x2963,0x2863,0x085B,0x0963,0x2A63,0x2A5B,0x0A63,0x0963,0x0A5B,}, +{0x283D,0x8A45,0x6C7E,0x4EA7,0xCEC7,0xCCC7,0xCBBF,0x4AA7,0xEA9E,0x689E,0xA686,0xA88E,0x0BA7,0x4A9F,0x6AA7,0xE996,0x487E,0xC96D,0xAC65,0x8D6D,0x8E6D,0xAE7D,0x0E86,0x2D8E,0x4965,0xEB4C,0x4D55,0xCB65,0x4A55,0x2D4D,0xB065,0x716D,0x105D,0xD264,0x723C,0xB33B,0xD633,0x984B,0xFA4B,0x3D64,0xBD5B,0x7B53,0x3E6C,0xBF74,0xBF7C,0xFF84,0x7F95,0x5F95,0x5F95,0x3F8D,0x5F85,0x3F95,0xBF84,0x1F6C,0x5B4B,0x953A,0xF63A,0xF96B,0x7C84,0x3A5B,0x5832,0x982A,0x3C43,0xDE5B,0x1F6C,0x3F6C,0x5E5B,0xB921,0x3409,0x7100,0x9008,0x9621,0xBC52,0x1D6B,0x5D6B,0x5D63,0x7D63,0x3D63,0x1E53,0xDE52,0x1C42,0x7A29,0x1821,0x1719,0xD410,0x7200,0xD208,0x5311,0x9619,0x9719,0xF208,0xAB00,0x6700,0xA800,0xC808,0x8800,0xC908,0xED10,0xF010,0xCE08,0x8B08,0xEF08,0x5311,0x3321,0x9821,0xF439,0xF041,0x1011,0x9108,0x1209,0xD110,0xD010,0xD819,0xF408,0x1311,0x1411,0x5419,0x3932,0x3A3A,0x7832,0xBA3A,0x593A,0x9842,0x5E74,0x3F8D,0x7F74,0x9F63,0x1D32,0xB921,0x7419,0xF108,0x3011,0x5011,0x2F11,0x7019,0x112A,0x3032,0x2D42,0x4B42,0xC931,0x6829,0x1132,0xDA6B,0xFE84,0x3F7D,0xBB42,0x5219,0x0F11,0x5019,0xF621,0x9419,0xB121,0xEF10,0x7819,0xBE4A,0xF821,0xB000,0xAD00,0xAA08,0x6108,0x2010,0x4018,0x6018,0x8020,0x4028,0x2020,0x0028,0x0048,0x0060,0x2170,0x2479,0x2070,0x0070,0x0070,0x0068,0x0070,0x0070,0x0078,0x0080,0x0088,0x0088,0x0088,0x0090,0x0098,0x01A0,0x0098,0x0098,0x00A0,0x00A0,0x00A8,0x01B0,0x05B1,0x83B0,0x01B0,0x21B8,0x23C0,0x02C0,0x01C0,0x01C8,0x01C8,0x01C8,0x00C8,0x00C8,0x00D0,0x00D8,0x01D8,0x01E0,0x01E0,0x02E8,0x22E8,0x63E8,0x42E8,0x83F0,0x22F0,0x84F0,0x64F0,0x48F1,0xA9F1,0x27F9,0x06F9,0x26F9,0x06F1,0xA6D9,0x63C0,0x687A,0x2963,0x0A63,0x0A63,0x0963,0x095B,0x295B,0x2963,0x295B,0x295B,0x295B,0x2A5B,0x2A5B,0x295B,0x0963,0x095B,}, +{0x093D,0x6B55,0x6D75,0x2C7E,0xAB8E,0x4CA7,0x2B97,0x6876,0x475D,0xA875,0x0886,0x266E,0xAA8E,0xAB96,0xCA86,0x2BA7,0xAA86,0xAA5D,0x0B4D,0xCC4C,0x2D55,0x7075,0xAF85,0xEE85,0xED7D,0x4B55,0x5066,0x7176,0xF06D,0xEF64,0xAF44,0x6D4C,0x6D44,0x504C,0x0F4C,0x6D33,0xB443,0x385C,0xFD84,0x9E74,0x1E5C,0x7F6C,0x7F7C,0xDF84,0x1F8D,0x1F8D,0x3F8D,0x5F8D,0x5F8D,0x1F85,0x1F85,0x9F84,0x9E6B,0xBB42,0xD93A,0x9C63,0x5C63,0x3742,0xB229,0x531A,0xB843,0x1D5C,0xDE74,0xDF7C,0x5F6C,0xBF5B,0x1F4B,0xDA21,0xF200,0x8D08,0x4908,0x6700,0x2A00,0x0C00,0x4C00,0x2B00,0x2B00,0x2B00,0x6D00,0x8D00,0x4C00,0x2A00,0x6800,0xED10,0xD229,0x1622,0x1932,0x5621,0xF210,0x6D00,0x8700,0xC908,0xCD08,0xCC00,0xEB08,0x0909,0x6A11,0x6E19,0xAF19,0x341A,0xF421,0xB521,0x5411,0xAF08,0x3111,0x9319,0x7319,0xD308,0xB210,0x8E00,0x3111,0x5611,0xB208,0xCF00,0xF210,0xD410,0x9519,0xF929,0x1832,0xD629,0xDB3A,0x3D53,0xDD5B,0x9F74,0x5F74,0xFE4A,0xDB29,0x9A19,0x1511,0x1311,0xF210,0x0F11,0x3011,0x7119,0x8E21,0xCF29,0x713A,0x8E42,0xAD3A,0x8C3A,0xE939,0x4B29,0x574A,0x3E95,0x1D64,0x5A3A,0xAB08,0xCD08,0x7421,0x3D4B,0x1732,0xD521,0x3219,0x9419,0x5819,0x5711,0xB308,0x3311,0xF010,0xCA08,0x4108,0x0018,0x2020,0x2020,0x0028,0x2020,0x0020,0x0030,0x0058,0x0068,0xC380,0xC178,0x0070,0x0078,0x0070,0x0070,0x0078,0x0080,0x0080,0x0088,0x0090,0x0090,0x0090,0x0098,0x00A0,0x00A0,0x20A8,0x00A0,0x00A8,0x01A8,0xA4B0,0x46B1,0x61B0,0x01B8,0x01B0,0x01B8,0x01B0,0x00B8,0x00C8,0x01C8,0x01C8,0x00D0,0x01D0,0x01D0,0x01D8,0x22D8,0x01D8,0x63E0,0x43E0,0x43E0,0x41E8,0x42E8,0x64E8,0x43F0,0x63F0,0x43F0,0xA7F0,0x8CF2,0x27F9,0xE6F8,0xC4F0,0x26F1,0xCBEA,0x42C8,0x678A,0x4963,0x2963,0x4963,0x0953,0x2A5B,0x2A5B,0x295B,0x295B,0x295B,0x295B,0x2A63,0x2A5B,0x2963,0x095B,0x095B,}, +{0xE73C,0xA944,0x494C,0xE84C,0xCA5D,0x6A6E,0x8976,0x0866,0x674D,0x8655,0xC765,0xC55D,0xA765,0x496E,0x8976,0x896E,0x696E,0xCA55,0x8C55,0x2D55,0x0D55,0x2F5D,0x2E5D,0xCF6D,0x116E,0xF26D,0x1066,0x8F65,0xEF4C,0x4E3C,0x0D44,0x2C4C,0xCB3B,0x2A23,0x0A2B,0x0D3B,0x333B,0x176C,0x3C6C,0xFE5B,0xFE53,0xDF63,0x1E64,0x9F7C,0xBF7C,0xBF74,0xDF84,0xDF84,0x3F7C,0x7D63,0xFB4A,0xBA32,0xD83A,0xB43A,0xB63A,0x142A,0x721A,0x185C,0xFD84,0x5F8D,0x7F95,0x5F95,0x3F95,0xDF84,0x1F74,0x3E63,0x5C4A,0x9709,0x5211,0xD010,0x8B08,0x6608,0x6300,0x4300,0x4200,0x2200,0x2100,0x2200,0x8200,0xA600,0x0B11,0x9429,0xF739,0x9629,0x3521,0xD108,0x8D08,0x4810,0x4608,0xC908,0xB009,0xD211,0x1422,0xB63A,0x5953,0x3C6C,0x7B7C,0x5D7C,0xFE6B,0x9F5B,0xDE32,0x9819,0x7311,0xF010,0x1111,0xAF08,0x6C00,0xAD00,0xCF00,0xCF00,0xAE08,0x8B00,0xCC00,0xCD08,0xED08,0x3119,0x9A32,0xF821,0x1732,0x9A42,0xFE5B,0x9F74,0x3F85,0x7F5B,0xBE3A,0xB919,0x7819,0x5719,0x7719,0x7311,0x1511,0x5219,0x7221,0x0F19,0xAE19,0xD029,0x3032,0x6F3A,0x2B3A,0x4C42,0x8929,0x8A21,0xB131,0x3E7C,0xB331,0x3121,0x4500,0x6908,0xF429,0xFD63,0x373A,0x9321,0x8F18,0xB210,0x7621,0x5B2A,0x9510,0x1509,0xB621,0x8F18,0xA918,0x8510,0x6128,0x0028,0x0020,0x2028,0x2028,0x0028,0x0040,0x0058,0x2078,0xE180,0x4070,0x0070,0x0078,0x0078,0x0078,0x0080,0x0090,0x0088,0x0090,0x0090,0x0090,0x0098,0xA2A8,0x41A0,0x00A8,0x00A0,0x00A8,0x00A8,0xC4B0,0xA3A8,0x00B0,0x01B0,0x00B0,0x00B8,0x01B8,0x00B8,0x01C8,0x01C8,0x01D0,0x01D0,0x00D0,0x00D0,0x01D8,0x02D8,0x43E0,0x01D8,0x43E0,0x22E0,0x01E0,0xE6E8,0x63E8,0x62F0,0x42E8,0x43E8,0xA5F0,0xA5F0,0xC5F0,0xC5F0,0xA3F0,0xE5E8,0x63E0,0x43C8,0x478A,0x096B,0x2A63,0x2963,0x295B,0x0A5B,0x295B,0x0A5B,0x095B,0x095B,0x0A63,0x0A5B,0x0A5B,0x0963,0xE95A,0x295B,}, +{0xC72C,0xC94C,0xE84C,0x695D,0xAA5D,0xEA65,0x6B7E,0x0A66,0x8755,0x2445,0xC444,0xC444,0x265D,0x8755,0x6A6E,0xAA76,0x0B6E,0x8A55,0x4945,0x8A55,0xEB4C,0xCF85,0xD07D,0x0D5D,0x2B45,0x6E65,0xEE64,0xCF4C,0xF044,0x6F54,0x8C43,0x493B,0x0A3B,0xE92A,0x8D5B,0xCB3A,0x8C2A,0xF45B,0xBA7C,0xDC63,0xFD5B,0xBE63,0x3F64,0x7F7C,0x5E84,0x9E6B,0xDC4A,0xF929,0x1622,0x1964,0xFD84,0x7F84,0x3B53,0x394B,0x794B,0x5C6C,0xFE7C,0x3F95,0x3F95,0x3F9D,0xBF8C,0xDF73,0x5E63,0x9C4A,0x7721,0xB619,0x3A32,0xF821,0x5321,0x1019,0x8A08,0x6608,0xA600,0x8500,0x8500,0x8400,0xC400,0xE810,0x4C11,0x7111,0x3219,0x1111,0x8F10,0x8A00,0x8800,0x6608,0x6608,0xA908,0x6F11,0x5822,0xFA32,0x3C4B,0x7C53,0x3C5B,0x7A52,0xF839,0xF218,0x2F21,0x3521,0xF839,0x5519,0x1209,0xCE10,0xAB08,0xA900,0xE900,0x5019,0xB511,0x9711,0x3209,0x0D01,0xCB00,0x8900,0x8908,0x2C19,0x9331,0xD421,0x9519,0xD721,0x9D4B,0xBF74,0x5F95,0xDF5B,0x3C2A,0x7819,0x3309,0x9721,0x5411,0x7711,0x191A,0x591A,0xF721,0x5019,0x4D11,0x7029,0xB229,0xD029,0x703A,0xF04A,0x6E42,0xCA29,0xEA29,0xED29,0xD239,0x2B21,0x0811,0x4308,0x2400,0xCC18,0x1C6C,0x364B,0xCB08,0x4D08,0x9208,0xF620,0x7C3A,0xD208,0xF310,0xD618,0xF210,0x2510,0x0318,0x0028,0x0030,0x0030,0x0030,0x2038,0x2038,0x2038,0x0050,0x0070,0x4080,0xA080,0x4078,0x0080,0x0078,0x0080,0x0080,0x0088,0x0088,0x0090,0x0090,0x0098,0x01A0,0x01A8,0x42A0,0x00A0,0x00A8,0x00A8,0x22B0,0x63B8,0x02B0,0x02B8,0x01A8,0x00B0,0x00B8,0x00B8,0x00B8,0x00C0,0x01C0,0x00C8,0x00C0,0x00C8,0x01D0,0x01D0,0x02E0,0x22E0,0x00D8,0x01E0,0x22E8,0x22E8,0x07E9,0xC4E8,0x62E8,0x84E8,0x84E8,0x84F0,0xA4F0,0xA5F0,0xE6F0,0x84F0,0xE5E8,0xA4E0,0xC4D0,0x278A,0x095B,0x295B,0x495B,0x0A5B,0x2A5B,0x295B,0x0A63,0x0A63,0x0963,0xEA62,0x2A5B,0x295B,0x2A5B,0x0963,0x0A5B,}, +{0x0845,0x6B6D,0xCB65,0x0B66,0x4955,0xE95D,0x0A76,0xA955,0x274D,0xA534,0x843C,0x6334,0xC544,0x296D,0xAA6D,0x096E,0xA965,0xA955,0x4635,0xE72C,0xC93C,0x4A4C,0xEB54,0xAB54,0x0834,0x6934,0xCD3C,0xCF44,0x2E44,0x4A33,0x8C43,0x2A3B,0xCA2A,0x882A,0x0B33,0x0B33,0x8B32,0xEE32,0x5774,0xBB63,0x7C53,0x1B53,0x9C42,0xFA29,0x7719,0xD511,0xF83A,0xFC63,0x1F8D,0xFE94,0xFD7B,0x9952,0x7532,0x9A5B,0x5F84,0x7F84,0x3E7C,0x7D6B,0x9C4A,0x1A42,0x1621,0x7208,0x1009,0x772A,0x9B32,0x1A3A,0xD931,0x3421,0xCD10,0x6700,0xA600,0xEC08,0xE810,0x2A21,0x8E21,0xF229,0x9321,0x5329,0x5221,0xF010,0x8C08,0x6800,0xA700,0xAA21,0xEC31,0x8C21,0xF129,0x7832,0xFD42,0xFF52,0xBD42,0x393A,0xD331,0xB129,0x1532,0x373A,0xF741,0x7842,0x182A,0x1722,0xF721,0xD511,0x7209,0xB009,0x9732,0x7D43,0x3D4B,0x5F4B,0xDF32,0x1B1A,0x7611,0x1109,0xC900,0xEC08,0x0D11,0x152A,0x993A,0x1B4B,0xDC42,0xFF84,0x3F8D,0x5F5B,0x5E3A,0x7719,0x7719,0x7411,0x5519,0xB929,0x9B32,0xDE53,0x1D33,0x191A,0x4E11,0x8F19,0xF531,0x2F21,0x5332,0x7342,0xB242,0xCF29,0xCD29,0x6A21,0x4821,0x4819,0x2919,0x0709,0xC308,0x4300,0x2700,0xFD6B,0x9953,0xA900,0x8B08,0x8D08,0x9010,0x7731,0x8C00,0x4C10,0xB208,0x9110,0x6410,0x0020,0x0028,0x0030,0x0038,0x0030,0x0038,0x2048,0x4040,0x2048,0x0060,0x0080,0x4088,0x4080,0x4080,0x0080,0x0080,0x0080,0x0088,0x0088,0x0090,0x0090,0x0098,0x0098,0x42A8,0x2098,0x00A0,0x21A8,0x00B0,0x02B8,0x23B0,0x22B0,0x21B0,0x00B0,0x00B0,0x00B8,0x00B0,0x00B8,0x01C0,0x22C8,0x00C8,0x01C8,0x01D0,0x00D0,0x00D0,0x02D8,0x02D8,0x01D8,0x00E0,0x00E0,0x21E0,0x23E0,0x43E8,0x01E8,0x43F0,0x63E8,0x23E8,0xA4F0,0x84F0,0xA5F0,0xA4F0,0xE5F0,0xC5E0,0xA4D0,0x2792,0x0A63,0x295B,0x2A63,0x0A63,0x0A63,0x2A63,0x0A63,0x0963,0x2963,0x0963,0x095B,0x0963,0x095B,0x2963,0xEA5A,}, +{0xE844,0x2B5D,0x0D6E,0x8B6D,0x284D,0xE955,0xCA65,0x2855,0xA63C,0x852C,0x6434,0x4334,0x222C,0x442C,0xE75C,0xC74C,0x6655,0xA64D,0x4755,0x462C,0x662C,0x893C,0x283C,0x4A4C,0x8944,0xCA3C,0x4A3C,0x0823,0xEB33,0xAC43,0x2B2B,0x2B33,0x8922,0x6922,0xCA32,0xA932,0x2922,0x4C2A,0xB032,0x5232,0xB011,0xB211,0x9311,0x5532,0xBB63,0x5F7C,0x1F7C,0x5D63,0x5A42,0xF310,0x8D00,0xA900,0xAD29,0x133A,0x5529,0xF208,0xB000,0x6D00,0x6A00,0xC900,0xD121,0xD83A,0xDD52,0x9E42,0xB831,0x5329,0x4D29,0x4A21,0x2719,0x6A19,0x6D19,0x4C09,0x0D11,0x2C19,0x0C11,0xEC08,0xCC08,0xCC00,0xAA08,0xA800,0xC810,0x4C11,0x4C19,0x2C21,0x6D21,0x3232,0xB542,0x9842,0xD839,0x1521,0xD110,0xEF18,0x5021,0xEF18,0xCE08,0x732A,0x9753,0x1B64,0x3E6C,0xDE53,0x9F53,0x3E3B,0x9D53,0xBE6C,0xBF7C,0x9F74,0x3F6C,0xDF5B,0xBF5B,0x7E32,0x3711,0x6D00,0x4800,0x0D09,0x9319,0xD829,0x7A2A,0x7C42,0x3E6C,0xDF84,0x1E53,0xBC21,0x3819,0x7821,0x5609,0xB719,0xB921,0xBD3A,0xBF6C,0x3F6C,0x7C22,0x9511,0x5111,0xB221,0x3219,0xD321,0x8F19,0xB73A,0xD642,0x1222,0x4D19,0x2919,0xE610,0xC610,0xE810,0xC710,0xC508,0x8400,0x2908,0xBE5B,0xBD53,0x3109,0x1009,0xCC00,0x6C00,0xEE10,0x4A08,0x4708,0x6C08,0x8810,0x4210,0x0018,0x0020,0x0028,0x0030,0x0038,0x0040,0x0040,0x2048,0x4050,0x2058,0x0070,0x0088,0x0080,0x0080,0x2090,0x4090,0x0088,0x0088,0x0090,0x0090,0x0090,0x0098,0x0098,0x0098,0x20A0,0x00B0,0x00A0,0x01A8,0x00A8,0x02B0,0x02B0,0x20A0,0x00A8,0x00B0,0x01B8,0x01B8,0x00B8,0x00B8,0x01C0,0x01C8,0x01C8,0x01D0,0x01D0,0x21D0,0x02D8,0x01D8,0x01D8,0x01E0,0x00E0,0x00E8,0x01E8,0x22E0,0x21E8,0x01E8,0x01E8,0x83E8,0x84F0,0x64F0,0xC4F0,0xC4F0,0xC4F0,0x83E0,0x63D0,0x289A,0x0963,0x295B,0x2A5B,0x2A63,0x2A63,0x0963,0x2A5B,0x0963,0x095B,0xE95A,0x295B,0x0A5B,0x095B,0x095B,0xE962,}, +{0x485D,0x6B65,0x8B65,0xC854,0x4945,0x8A5D,0x0845,0xA52C,0x6734,0x862C,0x232C,0xE323,0x021C,0x2324,0x0434,0xA65C,0xC644,0xC544,0xC644,0xA63C,0x2624,0x6944,0x094C,0x8B54,0x0954,0x0723,0x4523,0x082C,0xEB2B,0xEC33,0xCA22,0xEB22,0xEB2A,0x8C22,0x6A22,0x2E53,0x8B32,0x2C32,0xAB19,0x6E3A,0x1363,0xF84A,0x5842,0x3942,0x1B32,0x7919,0xF608,0xB400,0xAE00,0xAB00,0x2D09,0x5019,0x3019,0x4F19,0x0E11,0xA900,0xE900,0x4D19,0x142A,0x5B32,0x9C4A,0xB831,0x1319,0x0F09,0x4A21,0x8921,0xEC29,0x4F22,0x5332,0xD331,0x4D11,0x6D19,0x6F21,0x0C09,0x2C11,0x8D19,0xAE19,0x8E21,0x2D19,0x0B11,0x0911,0xC808,0xE918,0x2D19,0x4E19,0x2D19,0x0B19,0xCA18,0x4708,0x4300,0x2300,0xA808,0xF34A,0x5A74,0xDE84,0x1F85,0xFF7C,0x7F7C,0x5F74,0xFF63,0x1F6C,0xFF7C,0x5F9D,0xFFA5,0x3F8D,0x1F95,0xFE6B,0xDC4A,0xB731,0x6F00,0x4700,0x8600,0xCD08,0x2F21,0x5629,0x1A2A,0x9A32,0x5C53,0x1F74,0xDE42,0xDC21,0x9919,0x7619,0x3409,0x5511,0xDA21,0xDD42,0x7F7C,0x7F74,0xDE3A,0xDB21,0x1011,0x7221,0x0F11,0x7832,0x3011,0x372A,0x3A4B,0x1933,0x141A,0xE908,0x8608,0xC500,0xA508,0xA508,0xA710,0xC808,0x6600,0x2B08,0xDD52,0x7C53,0x3411,0xF819,0x3111,0xAC00,0x8C08,0x4900,0x8600,0x4608,0x6410,0x4110,0x2110,0x0018,0x0028,0x0030,0x0038,0x0038,0x0048,0x0048,0x0050,0x2058,0x2060,0x0070,0x0080,0x0088,0x0088,0x0088,0x0090,0x0090,0x0090,0x0090,0x0090,0x0098,0x00A0,0x00A0,0x00A0,0x00A8,0x00A0,0x00A0,0x00A8,0x00B0,0x01B0,0x00B0,0x00B0,0x00B0,0x00B8,0x00B8,0x01C0,0x00B8,0x02C0,0x01C8,0x01D0,0x01C8,0x01C8,0x00D0,0x01D8,0x00D8,0x00D8,0x01D8,0x00E0,0x01E0,0x83E0,0x83E0,0x21E0,0x02E0,0x62E8,0x22E8,0x62E8,0x63E8,0x83F0,0xA5F0,0xC3F0,0x41E0,0x23D0,0xE799,0x2963,0x095B,0x295B,0x095B,0x295B,0x295B,0x295B,0x095B,0x095B,0x095B,0x295B,0x295B,0x0A5B,0x095B,0x095B,}, +{0x274D,0x8A65,0x685D,0xE844,0x694D,0x4945,0xE93C,0x863C,0x662C,0xC534,0x852C,0x432C,0xE32B,0xA223,0x221B,0x2323,0xA433,0xA42B,0xC52B,0x883C,0x272C,0xA723,0xCA3B,0x2833,0xC52A,0x253B,0x672B,0x6B44,0x0B3C,0x6A1B,0xEC33,0x6D2B,0xEB32,0x8A22,0x6A22,0x2B2A,0x0922,0xE921,0x6819,0xA821,0xAB29,0x9019,0x6E09,0x3011,0x1309,0x1209,0xB100,0xCF00,0x1009,0x7211,0x9411,0xD829,0x5529,0xEE10,0x0A21,0xCE29,0xD439,0xB639,0x3421,0xD220,0xAC08,0xAA10,0xE708,0x6819,0x1032,0xB73A,0xD73A,0xD842,0x5932,0x3522,0x5522,0xD221,0xF119,0xF121,0xB321,0xB129,0xB019,0x6F19,0x4E19,0x0B11,0xEA10,0x0819,0x2A21,0xCA18,0xE708,0xA508,0x8400,0x6508,0xA608,0x4921,0x7342,0x395B,0x5D5B,0xDF63,0xBF53,0x1F64,0x5F6C,0xDF63,0x9E63,0x5F74,0x7F74,0xBF8C,0x9D94,0x1B7C,0x5842,0x9418,0x2F00,0x2A00,0x0600,0x6400,0x0D09,0xEB00,0xED10,0x1019,0xDA31,0x3B32,0xDE63,0x7E4B,0x3B3A,0xB919,0x3C22,0xBB21,0x5819,0x1209,0xF821,0x5A2A,0xDF63,0xDF6B,0x7E42,0x9A19,0xF510,0x3311,0xF110,0x5832,0xD008,0xF821,0x3B2A,0xFC5B,0xFA3A,0xD121,0x8608,0x6508,0x8508,0x8508,0x6508,0x8608,0x8700,0x8B08,0x4A00,0xBA29,0x993A,0xF210,0x3C2A,0xF821,0xF210,0xAB08,0x8A00,0x6700,0x4500,0x4510,0x6310,0x4110,0x2118,0x0020,0x0028,0x0030,0x0038,0x0048,0x0050,0x2058,0x2060,0x2068,0x2070,0x0080,0x0088,0x0090,0x0090,0x0090,0x0090,0x0090,0x0098,0x0098,0x00A0,0x0098,0x0098,0x00A0,0x01A8,0x00A8,0x00A8,0x01B0,0x00A8,0x22B0,0x21B0,0x00B0,0x00B8,0x00B8,0x01B8,0x21C0,0x00B8,0x01B8,0x01C0,0x00C8,0x00C8,0x00C8,0x00D0,0x00D0,0x00D8,0x01D8,0x00D8,0x00D8,0x00E0,0x05E9,0x84E8,0x62E0,0x63E8,0x01E8,0x01E8,0x83F0,0x63E8,0x63F0,0x63F0,0x63E8,0x21D8,0x23D0,0x489A,0x0A63,0x095B,0x285B,0x295B,0x2A5B,0x095B,0x2A5B,0x295B,0x0A5B,0x0963,0x0A5B,0x2963,0x095B,0x2953,0xEA5A,}, +{0x273D,0x6955,0x8A5D,0xCB55,0x8C55,0x693D,0x2945,0xE844,0x6634,0x642C,0x453C,0xA32B,0xE21A,0x810A,0x411B,0x032B,0x6433,0xE53B,0x2533,0x0734,0x492C,0x8823,0xA612,0x4412,0xE62A,0xEA4B,0xEA43,0x8933,0x2A3C,0x6C34,0x0D2C,0x2A1B,0x0A2B,0x8922,0xAB2A,0x4C2A,0x2812,0xA709,0xA711,0xA919,0x6A21,0xAC21,0x8F19,0x4F11,0x0F09,0x5111,0x7419,0x7319,0xB511,0x182A,0xF829,0xD318,0xCD08,0x4F21,0x2E21,0x2E19,0xED18,0xEC18,0xA908,0xA608,0xE718,0x2819,0x0F2A,0xF83A,0x1C43,0xBE4B,0x9D43,0xDD3A,0x3D4B,0xBD42,0x372A,0x1232,0x5432,0x142A,0x9329,0x9121,0x8F11,0xAE11,0xCF11,0x6D11,0x2A19,0xE710,0xC610,0xA610,0xC610,0xA410,0xC710,0xA708,0x8608,0x0811,0x7342,0x793A,0x5D5B,0x5D5B,0xDC4A,0xBE42,0x7D3A,0xFE42,0x5D53,0xBB4A,0x5619,0x5108,0x6D00,0x8B00,0x8800,0x6600,0x2400,0x2100,0xA800,0x3111,0xCF10,0x3311,0x3011,0x3111,0x5519,0x3A3A,0x1D4B,0x5932,0xB93A,0xFE3A,0x5C2A,0xF710,0x1611,0x8D08,0xD210,0xDD7C,0x1F74,0xDD31,0x5919,0x3611,0x1109,0xB108,0xD308,0xD400,0x362A,0xDB29,0x1E64,0xBE53,0x7B2A,0x7119,0x4600,0x6400,0x4508,0x4700,0x8900,0x6908,0x8B00,0xAC08,0x8C00,0xD108,0x5219,0x1109,0xDC31,0x7C2A,0x1309,0xED00,0xAB00,0xA800,0x8608,0x6408,0x6408,0x2310,0x2218,0x0028,0x0030,0x0038,0x0040,0x0050,0x0050,0x0058,0x2068,0x0070,0x0068,0x0070,0x0080,0x0088,0x0098,0x00A0,0x0098,0x0098,0x0098,0x0098,0x0098,0x00A0,0x00A8,0x00A8,0x00A0,0x00A8,0x01B0,0x01B0,0x00A8,0x01B0,0x00B0,0x00B0,0x00B8,0x20C0,0x00B8,0x00C0,0x01C0,0x42C0,0x01C8,0x00C0,0x00C0,0x00C0,0x00D0,0x01D0,0x00D8,0x01D8,0x00D8,0x00D0,0x21E0,0x01E0,0x42E0,0x42E0,0x42E8,0x01E8,0x01E8,0x22E8,0x22F0,0x21E8,0x22F0,0x21E8,0x00E0,0x22D0,0x0792,0x2A63,0x2963,0x495B,0x2A5B,0x2963,0x2A5B,0x0A5B,0x0A63,0x095B,0x0A5B,0x095B,0x495B,0x095B,0x0A5B,0xE95A,}, +{0x0745,0x2A5D,0x8A55,0xAA55,0x8A45,0x0D5E,0xEE55,0x2B4D,0x272C,0x642B,0xE31A,0x0313,0x832B,0xE333,0x4243,0x031B,0xE42A,0xC322,0x8533,0xA72B,0x071B,0xE50A,0xE50A,0x6823,0xE822,0x0833,0x893B,0xE93B,0xE933,0x0B24,0xCC1B,0xAD2B,0x4B23,0x6B23,0x0C2B,0x6B22,0x4912,0x4A22,0x091A,0x6709,0x8819,0x6921,0x8C21,0x4F11,0x7219,0xD521,0x7419,0x9419,0x9721,0xD310,0xAC00,0x3119,0x5419,0x7219,0x3019,0xCB08,0x0B11,0x6808,0xC508,0x2911,0x5332,0x3B4B,0x7D4B,0x3F64,0xBF74,0x7F74,0xFF5B,0x3E4B,0x5C32,0x5832,0x573A,0xF429,0xB229,0xF221,0x7432,0x984A,0x5942,0x1532,0xF021,0x4D19,0x2919,0x0711,0x0611,0xE718,0xA610,0xC518,0xA508,0xE810,0x0C11,0x0D21,0x2E19,0x1111,0x7411,0x3722,0xFD3A,0x3E5B,0x7B3A,0x3519,0x5008,0x4B00,0x8800,0x0E09,0xF010,0xCC00,0x6800,0x2400,0x2300,0x0E09,0x3311,0xAC08,0x5019,0x1411,0x5519,0x5321,0x7419,0xBA3A,0xD729,0x5B4B,0xFF5B,0x1E4B,0x7A11,0x7719,0xAE08,0xAD08,0x3211,0x1A32,0x9921,0x3511,0xD208,0x6E08,0xD100,0xD000,0x6E00,0x1211,0xD821,0xBC4A,0xDF7C,0x9F4B,0xB511,0x0F09,0x2908,0x4600,0x6600,0x4B00,0xD008,0xAE00,0x6B08,0xEE08,0x8B08,0xAD08,0x1011,0xF108,0x5819,0x9E2A,0x9619,0x1011,0xCC08,0xCB00,0x8900,0x8608,0x6408,0x6310,0x2218,0x0120,0x0030,0x0030,0x0040,0x0048,0x0050,0x0058,0x0068,0x2070,0x2070,0x2070,0x2078,0x2088,0x0090,0x0098,0x00A0,0x0098,0x0098,0x00A0,0x00A0,0x00A0,0x00A8,0x00A0,0x00A0,0x00A0,0x02B0,0x01B0,0x00A8,0x00B0,0x00B0,0x00B8,0x00B0,0x01B8,0x00B8,0x01C0,0x01C0,0x44C8,0x86D1,0x20C8,0x00C8,0x00C8,0x00C8,0x00D8,0x00D8,0x63D8,0x45E1,0x21E0,0x41D8,0x02E0,0x63E0,0x01E0,0x01E0,0x00E8,0x00E8,0x42E8,0x21F0,0x01E8,0x01E8,0x20E0,0x00D8,0x01D0,0xC799,0x0963,0x0963,0x295B,0x295B,0x296B,0x2963,0x295B,0x0A63,0x295B,0x095B,0x095B,0x0A5B,0x095B,0x095B,0x0A5B,}, +{0xC84C,0x6C75,0xCE7D,0x2B5D,0xCA34,0x0B35,0xE94C,0xE733,0xC41A,0x8322,0x221B,0x653C,0xC533,0x454C,0x644B,0x6212,0x2002,0x4433,0x642B,0x672B,0x2723,0xC82B,0xA923,0x4A23,0x4923,0xE92A,0x6B4B,0x6A33,0x8933,0x6C44,0x0C2C,0xCC2B,0xCD2B,0x8B2B,0x4C23,0x2C23,0x4A1A,0xE811,0xA709,0x6611,0x4509,0x2511,0x6A19,0x6E21,0x8D19,0x7019,0x7419,0x3311,0xEF08,0x5111,0x3019,0x3211,0x3321,0xAF08,0xAB10,0xCB10,0x8600,0x4911,0x722A,0xB82A,0x5D43,0x9F74,0x1F95,0x5F95,0x7F74,0x9F6B,0xBE52,0x3A3A,0x9629,0x5219,0xEF00,0xB219,0x783A,0x1832,0xF529,0x5219,0xB019,0xF121,0xD029,0x6D21,0x4A21,0x2919,0x2619,0x2611,0xE618,0xE710,0x0A11,0x4E21,0x2F21,0x0E19,0x6F29,0x7121,0x172A,0xDD42,0x3A2A,0x7511,0x5109,0xED00,0x0D09,0x352A,0x5A2A,0x9821,0xF210,0x4900,0x4400,0x2300,0xEE10,0xB108,0xAE08,0x3119,0x3011,0x5411,0x5619,0x162A,0x5A42,0xB821,0x7C53,0x9F7C,0x9E5B,0x7B21,0xDB19,0x1311,0x8D08,0xAE00,0x6E00,0xD008,0xCF00,0xAF08,0x4A00,0x8D08,0x8E08,0x2800,0x6B00,0xD410,0x9819,0xDD63,0xFE63,0x7D2A,0xAE00,0x8B00,0x6700,0x6900,0x4800,0x4F08,0x3611,0xD308,0x8D00,0xAE10,0x8B08,0xAB08,0xD010,0xF208,0xB408,0x9C21,0xB719,0xD008,0xCD08,0x6A00,0x6C08,0xCB08,0x8410,0x6410,0x2320,0x2220,0x0028,0x0030,0x0040,0x0048,0x0050,0x0060,0x0068,0x2070,0x2078,0x8078,0x4078,0x4088,0x2090,0x0090,0x0098,0x00A0,0x00A8,0x00A0,0x0098,0x00A0,0x00A8,0x00A0,0x00A0,0x00A0,0x01B0,0x01B0,0x63B0,0x05B9,0x62B0,0x00B8,0x01C0,0x01C0,0x00B0,0x00C0,0x00B8,0x02C0,0x23C8,0x01C8,0x00C8,0x00C0,0x00C8,0x01D8,0x02D8,0x63D8,0x22D8,0x22D8,0x62D8,0x01D8,0x00D8,0x01D8,0x00D8,0x00E0,0x00E8,0x01E8,0x41E8,0x20E0,0x20E8,0x00E0,0x00D8,0x01C8,0x08A2,0x096B,0x0A63,0x0A5B,0x295B,0x0A63,0x0963,0x2A5B,0x0A63,0x095B,0x085B,0x095B,0x0963,0x095B,0xE962,0xEA62,}, +{0xC53B,0x2744,0x073C,0xA523,0xC51B,0xE533,0x2323,0xC21A,0xA11A,0xE223,0xE43C,0x053D,0x6634,0xA423,0x610A,0xE102,0x6313,0x8523,0x4623,0x0A44,0xEA3B,0xC933,0xAA2B,0xE922,0x0923,0xC922,0x6822,0xC832,0x4933,0xEB33,0x6E44,0x2D34,0x8C23,0x6C23,0xAB23,0xAF3B,0xCD2A,0x4A12,0xC811,0xA609,0x6509,0x4509,0x6711,0x8921,0xCC19,0x4E11,0xED10,0x4E11,0x3119,0x0F09,0x5119,0x1109,0xCB08,0xED18,0x8B08,0xE700,0x8F32,0x5953,0x1D64,0xBE7C,0x1F95,0x5E74,0x7D6B,0x7C6B,0xD831,0xF420,0x4E08,0x2900,0x6700,0x4800,0xC908,0xF029,0x1132,0xF329,0x3432,0x353A,0xF429,0xD221,0xF229,0xB121,0x6E21,0x4B11,0x2821,0x0719,0x4719,0x4A19,0x6C11,0x4E19,0x8E19,0xB119,0x7219,0x7732,0xDD4A,0xF729,0x772A,0xB832,0x1A3B,0x5C53,0x1D4B,0xD931,0xB208,0x6B00,0x4600,0x2300,0x4300,0xCD08,0xF008,0x2F19,0x3111,0xF218,0x1311,0xB519,0x7721,0x3B32,0x7529,0x3732,0x7F7C,0xDF63,0x3E32,0x3C22,0xDA11,0xAF00,0x9008,0xD008,0xAE08,0x8E00,0x8D08,0x4900,0x6800,0x4808,0x4600,0x2500,0x6C10,0xAE08,0x573A,0x3F64,0xDE3A,0xB721,0x8B08,0xAA00,0x4800,0x4500,0x6A00,0x9010,0x7919,0xF408,0xAF08,0xAE00,0xAE00,0xAA00,0xAD08,0x1109,0xD310,0x3719,0x7519,0xCE08,0xAC08,0xAE10,0xAE08,0xF008,0xC910,0xA610,0x6518,0x2220,0x0028,0x0030,0x0040,0x0048,0x0058,0x0060,0x0068,0x0068,0x0080,0xC288,0xE288,0x8080,0xA098,0x4098,0x0098,0x00A0,0x00A8,0x00A8,0x00A0,0x00A0,0x00A0,0x00A8,0x00A8,0x00A8,0x00A8,0x01A8,0x42B8,0x64B8,0x21B8,0x00B8,0x21C0,0x00B8,0x00B0,0x00B0,0x00B8,0x01C8,0x00C0,0x01C8,0x00C8,0x00C8,0x01D0,0x01D0,0x01D8,0x01D0,0x01D8,0x22E0,0x22D8,0x00E0,0x00D8,0x00E0,0x00D8,0x00D8,0x22E0,0xA3E8,0x00E8,0x00E8,0x20E8,0x00E0,0x00D8,0x02C8,0x0CB3,0x2A63,0x295B,0x2A63,0x095B,0x0A63,0x0A5B,0x0A63,0x095B,0x095B,0x095B,0x285B,0x0963,0x085B,0x095B,0x085B,}, +{0x4223,0x852B,0xA52B,0x842B,0xA42B,0x642B,0x0213,0xC21B,0xE63C,0x8745,0x6755,0xA644,0x031B,0x0102,0xC10A,0x031C,0xE51B,0xA62B,0xA72B,0xA92B,0xCB2B,0x8C33,0x4B2B,0x4C2B,0x881A,0x060A,0x6612,0xE822,0x8B2B,0x0E44,0xEE43,0xCE33,0x8E33,0xAF33,0xEA22,0x2D2B,0x6C22,0x2C1A,0xAE32,0x6D1A,0x2912,0xC711,0xA611,0x8711,0x4709,0x2701,0x0809,0x2B09,0x5211,0x5111,0x0D09,0x2F19,0x3019,0xAC00,0x6B11,0x5753,0x1C5B,0xFC52,0xFA5A,0x3842,0xF420,0x8F00,0x4B00,0x4800,0x4500,0x2400,0x2300,0x4300,0x4300,0x8400,0x2F2A,0xF442,0x754A,0xD431,0x9119,0x542A,0xB83A,0xB93A,0x162A,0x9221,0x4E19,0x2B19,0x0919,0x2911,0x6819,0x8C21,0xCE31,0xD221,0xD321,0xD321,0x362A,0x3832,0x3A4B,0xDD6B,0x1B5B,0x3A5B,0x9B42,0x7821,0xD308,0xAD00,0x8900,0xA508,0x8400,0x4400,0x3011,0xD621,0x5311,0xF018,0xCE10,0xD018,0x3529,0x7319,0x9529,0xD308,0xB73A,0x5E6C,0x9F63,0xBE42,0xFB21,0xBD22,0xF608,0xB208,0x1209,0xB108,0xF208,0xCE00,0xCD08,0x6708,0x6600,0x6400,0x6400,0x6A00,0x8910,0x8908,0xF929,0xBC3A,0xDA21,0xCD08,0xEE08,0xCA00,0x6700,0x2400,0x8908,0x8C08,0xB721,0x5611,0xB210,0x8C00,0xF000,0xED08,0xD018,0x5411,0x5411,0x1311,0x0F19,0xAE08,0xCD08,0x8E08,0x1211,0x1011,0xED10,0xA610,0x6520,0x4728,0x0228,0x0030,0x0038,0x0050,0x0050,0x0058,0x0068,0x0070,0x4180,0x0992,0x4589,0xA190,0x6088,0xC0A0,0x4098,0x0098,0x00A0,0x00A8,0x00A8,0x00A0,0x00A0,0x00A0,0x00A0,0x00A8,0x00A8,0x87C1,0xC4C0,0x02C0,0x00C0,0x00B0,0x00B8,0x00B8,0x00B8,0x00B8,0x00B8,0x01C0,0x00C8,0x00C8,0x00D0,0x00D0,0x01D0,0x01D0,0x00D8,0x02E0,0x02E0,0x01E0,0x00E0,0x00E0,0x01E0,0x00E0,0x00D8,0x00E0,0x43E0,0xE5E8,0x01E8,0x01E0,0x41E8,0x20E0,0x20D8,0x63C8,0xAA9A,0x2A63,0x0963,0x096B,0x295B,0x0963,0x295B,0x095B,0x085B,0x285B,0x095B,0x095B,0x0963,0xE962,0x095B,0x095B,}, +{0x8443,0xA63B,0xC633,0x8523,0xC41B,0x252C,0x2A35,0xEC5D,0xAB4D,0xC734,0xE433,0x811A,0xA009,0x210B,0xC424,0x862C,0x8523,0x872B,0x883B,0x2A2B,0xEA1A,0xEA22,0xA922,0x691A,0xE711,0x6822,0xC822,0x4A33,0x2B1B,0x0B2B,0x6E33,0x3043,0xAD2A,0xCD2A,0xAB2A,0x8F2A,0x9032,0x1143,0xD13A,0xB122,0x8F22,0x0C1A,0xE811,0xE719,0x8719,0x6A09,0x4C11,0x9019,0x3211,0x7119,0xD221,0x5019,0x2C21,0xCF31,0x6E21,0xAB10,0x8B00,0x6A00,0x6900,0x2700,0x4500,0x4600,0x6A00,0x4900,0x4700,0x4700,0x8708,0xC808,0xE910,0xF029,0x9642,0xF532,0x173B,0x3A53,0x1C4B,0x7A3A,0xF631,0xB219,0xF321,0xF129,0xCF31,0x8C19,0x6B21,0x8B19,0xEE29,0x3132,0xB221,0xF221,0x3632,0x593A,0x9632,0x5D74,0x9C5B,0xB621,0xF621,0xF721,0x9619,0x9619,0x5411,0x3009,0xEA00,0xC700,0xA700,0x7011,0xD929,0xD110,0x6808,0xCB10,0x6D10,0x8C08,0x5219,0x1119,0x1119,0x173A,0x1E4B,0xFE4A,0x9E32,0xBE3A,0xBE32,0xBA11,0x3611,0x9100,0xD308,0x1201,0xD200,0xF108,0x8800,0x6608,0x6508,0x6500,0x4708,0x8810,0x6910,0xEC10,0x7511,0xD008,0x3311,0x0F11,0x7511,0x9111,0xAA00,0x4300,0x6600,0x8E08,0xB921,0xF510,0x1309,0x8B00,0x8D08,0xCD10,0xEF10,0x7521,0x5932,0x7211,0x1011,0x8C08,0xCF08,0xB000,0xD108,0x0F09,0xEF18,0xE918,0xC518,0x2418,0x2320,0x0038,0x0038,0x0048,0x0058,0x0060,0x0068,0x0078,0x0180,0x6699,0xA380,0x4090,0xA498,0xE490,0xC0A8,0x2098,0x0098,0x0098,0x00A8,0x00A8,0x00A8,0x00A8,0x00A0,0x00A8,0x00A8,0x01A8,0x01B8,0x02C0,0x00B8,0x00B8,0x00B8,0x00B0,0x00B8,0x00C8,0x00C0,0x00C0,0x00C0,0x00C8,0x01D0,0x00D0,0x00D0,0x01D8,0x00D8,0x01D8,0x01D8,0x00D8,0x00E0,0x00E0,0x01E0,0x00D8,0x00D8,0x00E0,0x00D8,0x01E0,0x00E8,0x00E0,0x00E0,0x20E0,0x00D8,0x22C8,0x488A,0x0A63,0x0963,0x296B,0x295B,0x2963,0x295B,0x095B,0x295B,0x095B,0x095B,0x095B,0x095B,0x0953,0x095B,0xEA5A,}, +{0xA53A,0x0523,0xC72B,0x8734,0x2A3D,0xAE5D,0xCE5D,0x2945,0x672C,0x231B,0x6012,0x000A,0x2314,0xA72D,0xC734,0x2624,0xE833,0x062B,0xA512,0xA81A,0xC71A,0xC922,0x881A,0xAB1A,0x4A1A,0xAA2A,0x6832,0x882A,0x6C3B,0x8F3B,0x0E23,0xAD22,0xF02A,0x122B,0x333B,0xF532,0x153B,0xF63A,0xF442,0xB232,0x902A,0x6C22,0x0922,0xC821,0xA819,0xAC11,0xB021,0xB019,0xB019,0x6E19,0xEC10,0x4A11,0x8D29,0x0B21,0xA708,0xC508,0x8400,0x6508,0xA500,0xCB00,0x9010,0x8F08,0xAE00,0xCF08,0xCD00,0xAC00,0xEC10,0x2C19,0xCE19,0xF742,0x5A43,0xBD53,0x7D53,0x794A,0x3321,0x4E11,0x753A,0x194B,0x9932,0xF539,0xD121,0xD019,0xEF19,0x302A,0x102A,0xB221,0xD229,0x7221,0x162A,0x7C53,0x1E6C,0x5B42,0xBA32,0x9B3A,0x1932,0xD829,0x5A2A,0x9B32,0x3A2A,0x7311,0xEE08,0xAA08,0x9319,0x7419,0xED10,0x6708,0x6508,0x6708,0xAD08,0xED08,0xAA00,0x5119,0x5319,0x5632,0xFD42,0x9B3A,0x3E4B,0xBE42,0xFD11,0x7811,0xD408,0xF408,0xD110,0x3309,0x1101,0xAC08,0x8800,0x8608,0x8600,0xA700,0x8800,0x8800,0xEE10,0x0F19,0x7211,0xCE10,0xEC08,0xD719,0x3B2A,0xD519,0xEE00,0x4400,0x8800,0xB308,0x9C19,0x3711,0x5519,0x1011,0xEF10,0xCF10,0xEF10,0x3721,0xBE3A,0x5822,0xB008,0x8F10,0x8F08,0x9000,0xF108,0x5111,0xCB08,0xAA10,0xC718,0x2518,0x0220,0x0038,0x0038,0x0040,0x0058,0x0060,0x0068,0x0078,0x0078,0x0080,0x2188,0x0090,0x0190,0x4298,0x6198,0x80A0,0x0090,0x0098,0x00A0,0x00A8,0x00B0,0x00A8,0x00B0,0x00B0,0x00A8,0x00A8,0x00B0,0x00B0,0x00B0,0x00B0,0x00B0,0x00B8,0x00C8,0x00C0,0x00C0,0x00C0,0x00C0,0x00C8,0x01C8,0x00C8,0x00D0,0x00D8,0x00D8,0x01D8,0x22D8,0x01E0,0x01D8,0x00D8,0x00D8,0x00D8,0x00D0,0x00D8,0x20D8,0x00D8,0x00E0,0x00E0,0x60E8,0x40D8,0x00D8,0x22C0,0x4982,0x2963,0x0A63,0x0A63,0x0963,0x0963,0x0963,0x295B,0x0A5B,0x095B,0x095B,0x295B,0x095B,0x095B,0x0A5B,0xE95A,}, +{0x2633,0x4944,0x2C55,0xAC55,0x2C55,0x2C5D,0xE854,0x2544,0x8323,0x4223,0x2313,0x693D,0x6B56,0x2935,0xE924,0x6934,0x0623,0x241B,0x883B,0x282B,0x081B,0xEA22,0x8A1A,0xCB2A,0x4B1A,0x691A,0xAB2A,0xEA3A,0x2C33,0x0D2B,0x5033,0x702B,0x7343,0xB63B,0x963B,0x573B,0x583B,0xB532,0x1133,0x3443,0xD23A,0x6D22,0xEB19,0xEA19,0xEB19,0xAF19,0xB119,0x6D19,0x2D09,0x4B09,0x0A11,0x2B19,0x0911,0xE610,0x0611,0x0409,0xE508,0xE810,0xEC10,0x9010,0xD008,0x1111,0x5211,0x5419,0x9411,0x5119,0x4F11,0x102A,0x9A4B,0x9C53,0xDB5B,0x7C5B,0xB742,0xD119,0x362A,0xFC42,0xBC4A,0x373A,0x3732,0x9842,0x983A,0x982A,0x7532,0x9432,0xD121,0x4F19,0xD021,0x352A,0xBB42,0xFB52,0xFA3A,0xDE6B,0xFC42,0x3932,0x9B3A,0x5E4B,0xDF53,0x3E43,0xDB19,0x7509,0x3111,0xB221,0x3011,0x2C09,0xE708,0x6500,0x6400,0x8708,0x8900,0x7119,0xD529,0x3521,0x3932,0x5932,0x172A,0xFE63,0xBD3A,0x3D2A,0x9811,0x1509,0xB208,0x1409,0x1319,0xB108,0xCD00,0x8A00,0x8908,0xA908,0xA910,0xCA00,0xCA00,0xCB08,0xAE08,0x7521,0x2E11,0x6908,0x9419,0x3C2A,0x1E3B,0xFA21,0x3109,0x4500,0x8A08,0xD408,0x5C11,0x5A19,0x9308,0x3419,0x1111,0xCF08,0xD010,0x3821,0x9E42,0x9D53,0xF208,0xAF08,0x4908,0x6F08,0x6D08,0xB218,0xEC10,0x8908,0xAB18,0x4618,0x2430,0x0030,0x0038,0x0040,0x0048,0x0060,0x0060,0x0070,0x0078,0x0078,0x0080,0x0090,0x0098,0x0098,0x0080,0x0098,0x20A8,0x0098,0x0098,0x00A0,0x00A8,0x00B0,0x00B0,0x00B8,0x00B0,0x00A8,0x00B8,0x00B0,0x00A8,0x00B0,0x00B8,0x00B8,0x00C0,0x00B8,0x00B8,0x00C0,0x01C8,0x01C8,0x00C0,0x00C8,0x00D0,0x00D0,0x00D8,0x00D0,0x02D8,0x00D8,0x00D8,0x00D0,0x00D8,0x20D0,0x00D0,0x00E0,0x00E0,0x20D8,0x00E0,0x00E0,0x20E0,0x20E0,0x20D0,0x43C0,0x6882,0x095B,0x0A63,0x0A63,0xE962,0x0963,0x2863,0x095B,0x095B,0x0963,0x0953,0x0953,0x095B,0x095B,0x0953,0x095B,}, +{0x6D54,0xCE64,0xEF5C,0xEC54,0xCB54,0x673C,0x252C,0xC423,0x042C,0xC423,0xCC45,0x8F66,0x2A3D,0x6935,0x682C,0xE40A,0xA71B,0xA723,0x472B,0x4823,0xAA2B,0x4C2B,0x0A1B,0xCF3B,0x9043,0x103B,0xAE3A,0xAC2A,0x0C33,0x0E2B,0x502B,0xD343,0xD343,0x963B,0xB93B,0x163B,0xF31A,0x974B,0x9953,0x943A,0x3232,0x6F32,0x4F32,0x9032,0x712A,0xCF19,0xAF19,0x7029,0x9021,0x4E21,0x4D19,0x6D11,0x2B19,0x2819,0x2711,0x2609,0x2611,0x0811,0x2A09,0x3119,0xB419,0x9519,0x3429,0x5319,0xB329,0x9431,0xB211,0xDB5B,0xDF94,0x7D5B,0x363A,0x5119,0x362A,0xBC42,0x5A3A,0x9721,0x962A,0x9C5B,0x3D53,0x3C4B,0xDF63,0x5E4B,0x5622,0xF219,0xCF21,0x1022,0x983A,0xFA42,0x9421,0x7C63,0xDD6B,0x9A42,0xFC4A,0x7E4B,0x1F6C,0x5F6C,0xBF5B,0x7D32,0x7719,0xF719,0x3321,0x3011,0x6D19,0xAB21,0xC708,0x8808,0x8700,0x0B09,0xF621,0xFA29,0xB721,0x7221,0xB721,0xD729,0x3D4B,0x1C2A,0x9E3A,0xDA21,0x3311,0xF008,0xF318,0x6E08,0xB110,0xD008,0xAE00,0xAE00,0xAD08,0x8A00,0xAA08,0x0D09,0xEF10,0xCE10,0x7119,0xEE08,0x0B11,0xCD08,0x3B3A,0xBE3A,0x1F43,0xFA21,0x7111,0x4900,0x8D00,0xB010,0x3819,0x7829,0x0B00,0x3419,0x1311,0xF110,0xD110,0x3829,0x3E42,0x9F5B,0x7319,0xD108,0x4C00,0x4800,0x6C08,0x4C08,0xCC10,0xAA18,0x4910,0x6818,0x2220,0x0130,0x0040,0x0048,0x0048,0x0060,0x0068,0x0070,0x0078,0x0078,0x0080,0x0088,0x0088,0x0088,0x0088,0x0090,0x2098,0x60A0,0x40A0,0x00A8,0x00A0,0x00A8,0x00B0,0x00B8,0x00B8,0x00B0,0x00B8,0x00B0,0x00B0,0x00B8,0x00B0,0x00B8,0x00B8,0x00C0,0x00C0,0x00C0,0x00C0,0x00C8,0x00C8,0x00C8,0x00C8,0x00C8,0x00C8,0x00D0,0x00D0,0x00D0,0x00D0,0x00D8,0x20D0,0x00D0,0x00D8,0x00D8,0xA4E0,0x04E9,0x00E0,0x00E0,0x00E8,0x00E0,0x20D0,0x63B8,0x897A,0x0963,0x0963,0x0963,0xEA62,0x095B,0x2863,0x0963,0x0A5B,0x095B,0x0963,0x095B,0x0953,0x0853,0x0953,0x085B,}, +{0x2E5C,0xED4B,0x0C44,0x083C,0x272C,0x6634,0x242C,0x6323,0xA51B,0x4C3D,0x8F4D,0xAC2C,0xCA2C,0xA723,0x0403,0x2714,0x0724,0xA723,0xC83B,0x671B,0xA81B,0x2E44,0x113C,0xD13B,0xED2A,0xED32,0xEC22,0xEB3A,0x2C43,0x503B,0x5023,0x512B,0xF543,0x7643,0xD222,0x723B,0xF95B,0x394B,0xD52A,0x7322,0x5332,0x3022,0x5032,0xB232,0x5222,0x532A,0xF221,0xB119,0xD221,0x9121,0xB021,0x6F19,0x6E21,0x4B11,0x6919,0x6811,0xA919,0x2D1A,0xF129,0xF421,0xB211,0xB421,0xF741,0x9631,0xEF18,0xCE19,0xFA3A,0xFD7B,0x7752,0xCE08,0x132A,0x7A3A,0x1A32,0xF310,0xD019,0xBB5B,0xFF63,0x9F63,0x9F5B,0x1F6C,0x7E5B,0x9C32,0x172A,0xB321,0x332A,0xF431,0x7219,0x9842,0x9A3A,0x3A3A,0xFC4A,0x5C4B,0xDE5B,0x5F6C,0x5F6C,0x9F53,0x7E3A,0xDA21,0xD821,0x7621,0xB219,0x332A,0xB029,0x0809,0xCC08,0x8B08,0x9021,0x3732,0x1932,0xB729,0x5321,0xF521,0xD719,0xDA29,0x7711,0x9D32,0xDB21,0x3609,0xF308,0xAD00,0xAF08,0xD010,0x8F08,0xAF00,0xB108,0xD008,0xAE08,0x8C08,0x8B08,0x0B11,0x3211,0xAB08,0x7319,0x2F09,0xEC08,0xB521,0xFD42,0xDF5B,0xFF4A,0x5C32,0xF108,0x6D00,0xB100,0xAC00,0xB010,0xD010,0x2900,0xF008,0x3411,0xB108,0xB008,0xF618,0x9C21,0x3F53,0x7732,0x9108,0x6D08,0x4700,0x6908,0x8D08,0x6B08,0x6A10,0x4918,0x4910,0x4520,0x0028,0x0038,0x0040,0x0048,0x0050,0x0060,0x0068,0x0070,0x0078,0x0080,0x0088,0x0088,0x0090,0x0090,0x0090,0x0090,0x2098,0x60A8,0x20A8,0x20A8,0x00A0,0x00A0,0x00A8,0x00B0,0x00B8,0x00B8,0x00B8,0x00B0,0x00B8,0x00B8,0x00B8,0x00B8,0x00C0,0x82C0,0x20C0,0x01C8,0x00C0,0x00C8,0x00C0,0x00C8,0x00C8,0x00D0,0x00D0,0x00D0,0x00D0,0x00D0,0x00E0,0x00D0,0x00D8,0x00D8,0x00D8,0x01E0,0x00E0,0x00D8,0x20E0,0x40E0,0x20E0,0x00D8,0xC3B0,0xC872,0x095B,0x0963,0x2A63,0xEA62,0x0963,0x0963,0x0963,0x0A63,0x0963,0x0963,0x095B,0x085B,0x095B,0x0853,0x085B,}, +{0x063B,0x4623,0xA733,0x2954,0x293C,0xE52B,0xA223,0x0424,0x2F55,0xCE3C,0x0A34,0x8723,0x0513,0x4613,0x2724,0x692C,0xE82B,0xC823,0xA82B,0xA823,0xC91B,0x8A23,0xED2B,0x4F34,0xED3B,0x8E33,0x2B2B,0x0D33,0x2D3B,0x8E3B,0xB33B,0x5433,0x9022,0x8D1A,0x385C,0xDA53,0xD532,0xD32A,0xB222,0x752A,0x5332,0x5222,0x513A,0xEF21,0x532A,0x5322,0x342A,0xF321,0xD429,0x1322,0xF229,0xB129,0xB121,0xAE19,0xAD19,0xC911,0x0C2A,0x1022,0xCF19,0x732A,0x352A,0x7429,0xCE10,0x8D11,0x174B,0xBE73,0x9731,0xAC00,0x8E21,0x7842,0x3B3A,0x9711,0x7319,0x583B,0xFE5B,0x7F5B,0xDF63,0x7F63,0xDF6B,0xFD4A,0xDE32,0x7C3A,0xD421,0x3019,0x0D11,0x9229,0x974A,0xF729,0x993A,0x1D43,0x5D5B,0x3F6C,0x5F74,0x5F74,0xBF6B,0xBE3A,0xBB21,0xB919,0x5721,0x7209,0x361A,0x5632,0x7119,0xAA08,0xCB08,0x0C11,0xB542,0x7A32,0x7619,0xB311,0x7B2A,0x3A2A,0x9419,0xB621,0x7E32,0x1D22,0xB819,0x5611,0x8C00,0xB208,0xAD00,0xAF08,0xD110,0xAE00,0xD208,0xD108,0xCD08,0xEC10,0xCA10,0x4C21,0xC900,0x0C11,0x3011,0x2F11,0x5219,0x9B42,0xBF5B,0xBF5B,0x9F42,0x392A,0x3201,0x8E08,0xD100,0x6A00,0x4B00,0x4900,0x2A08,0x8E10,0x9308,0xB108,0xD008,0xF610,0x3919,0x7E32,0x5A2A,0x6D08,0x4A08,0x4900,0x4800,0x4C10,0x4F18,0xAE10,0x6910,0x2610,0x0228,0x0030,0x0030,0x0040,0x0048,0x0058,0x0068,0x0068,0x0070,0x0078,0x0080,0x0088,0x0088,0x0098,0x0098,0x0098,0x0098,0x0098,0x20A0,0x80B8,0x60A8,0x20A8,0x00A0,0x00A8,0x00B0,0x00B0,0x00B8,0x00C0,0x00B8,0x00B8,0x00B8,0x00B8,0x00B8,0x42C0,0x05C9,0x20C0,0x00C0,0x00C0,0x00C8,0x00C0,0x00C8,0x00C8,0x00D0,0x00D8,0x00C8,0x00D0,0x00D0,0x00D0,0x00D8,0x42D8,0x00D8,0x00D8,0x00E0,0x00E0,0x00E0,0x00E0,0x60E0,0x20E0,0x00D0,0x45A1,0x0963,0x295B,0x0A63,0x0A63,0x0A63,0x0A63,0x295B,0x2A5B,0x0963,0x095B,0xE962,0x095B,0xE95A,0x085B,0x095B,0xE95A,}, +{0xE532,0x262B,0x4833,0xC73B,0x0734,0xC533,0x4624,0xEE45,0x9245,0x4E34,0x292B,0xE51A,0xA82B,0x0A34,0x2A34,0xC823,0x8823,0xA71B,0x2623,0x8823,0x2A2C,0x6A24,0x2C34,0x2D34,0x4D3C,0x0F3C,0x8E33,0xCE32,0x4F3B,0x2F4B,0xD032,0xEC11,0x5033,0x3A5C,0x374B,0xB532,0x512A,0xB332,0x532A,0xB52A,0x752A,0x1322,0xEF21,0xAE21,0x0E1A,0xD632,0xB732,0x5432,0x1322,0xF329,0x342A,0x333A,0x132A,0xF329,0xD021,0x8C21,0xCB21,0xEE21,0x3232,0xF321,0x6C09,0x6A09,0x364B,0x5E7C,0x7E6B,0x3419,0x2C09,0x352A,0xBA3A,0xDC3A,0x7B32,0x192A,0xFC4A,0x5E4B,0x5F5B,0x1E4B,0xDE5B,0xDE63,0xDD3A,0x3E4B,0x7C32,0x5219,0xB119,0x6E19,0xF429,0x7129,0xD129,0x5842,0x9C42,0xBE5B,0xDE63,0x3F74,0xFF6B,0x7F53,0x9F42,0xFC21,0xB911,0x7721,0x0F09,0xBC32,0xBD32,0x7419,0x6B08,0x8A00,0x0C09,0xD321,0x7C42,0xF929,0xDB42,0x7C3A,0x9621,0xB621,0xF621,0x5B32,0x7E32,0xBC21,0xB811,0x8F00,0xF008,0x4B08,0x1209,0x8F08,0x8E08,0xF208,0xD008,0xD010,0xEE10,0x2C11,0xEB10,0xCA20,0xEB10,0x0E19,0xB411,0x5219,0xF629,0x1B3A,0xFF52,0x3E53,0x5E32,0x1C2A,0x3709,0xEE08,0xCF00,0x8C00,0x6F00,0x4D08,0x4C00,0x4B00,0x7008,0xD108,0xF208,0xD508,0xD510,0x9B21,0x3919,0x4900,0x2900,0x6800,0x4808,0x0908,0x2E10,0xB210,0xAF18,0x2820,0x0420,0x0028,0x0038,0x0040,0x0048,0x0050,0x0068,0x0068,0x0068,0x0070,0x0080,0x0080,0x0088,0x0098,0x0098,0x00A0,0x0098,0x0098,0x0098,0x20A0,0xA0B8,0x60B8,0x40A8,0x20A8,0x00A8,0x00A8,0x00A8,0x00B0,0x00B8,0x00C0,0x00B8,0x00B8,0x00B8,0x43C8,0x20C0,0x00C8,0x00C8,0x00C8,0x00C8,0x00C8,0x00D0,0x00C8,0x00C8,0x00C8,0x00D0,0x00C8,0x00C8,0x00D0,0x01E0,0x01E0,0x00D8,0x00D8,0x00E0,0x00E0,0x20E0,0x00E0,0x40E0,0x00E0,0x20D0,0x29B2,0x2A63,0x095B,0x0A63,0x0A63,0x095B,0x095B,0x2863,0x0A63,0x0963,0xE962,0xE962,0x0953,0xE95A,0x095B,0xE95A,0x085B,}, +{0xE63A,0x072B,0x2833,0x873B,0xC62B,0x0935,0xB266,0x134E,0xF034,0x4B23,0x271B,0x8833,0x6B3B,0x6A2B,0x881B,0x4623,0x261B,0xC50A,0xE51A,0x061B,0xA82B,0x2A1C,0x0B24,0x2B34,0x4C3C,0xAE3B,0x8D2B,0x6922,0xC709,0x0822,0xAA12,0xB243,0x964B,0x722A,0x932A,0x9032,0x933A,0x301A,0xB432,0xB73A,0x122A,0xD119,0x8F19,0xEF21,0x0F22,0x5332,0x9742,0x562A,0x3422,0x5432,0x7532,0x773A,0x5532,0x342A,0x1422,0xB019,0x702A,0x1022,0xEF21,0x6C19,0x9332,0x7C5B,0x1D53,0x393A,0x1109,0x5122,0x7C53,0xBE5B,0xFF5B,0x5F53,0xFD42,0xBA42,0xBA42,0x9C3A,0xBC3A,0xDE63,0xBB42,0x3D43,0xFF6B,0x3942,0x1009,0x3121,0x4D11,0x9221,0xD018,0xB021,0x372A,0xBA3A,0xFD4A,0x1E4B,0x1F6C,0xBF5B,0x7E3A,0x7F3A,0xBA21,0xBA19,0x5919,0xCD08,0xB953,0xDD63,0x7619,0x2800,0x8A00,0xAB00,0x5011,0x3B22,0x7E42,0x7C42,0x9629,0xF110,0x9421,0xF829,0x3D4B,0x7E4B,0x3B2A,0x5919,0xB008,0x8F00,0x6C00,0xAE08,0x6C08,0x7010,0xAF08,0xF310,0xCE18,0xCD08,0x4E11,0x2D09,0xEB10,0xEB10,0x4F19,0x6F19,0x5211,0x172A,0xD629,0x7519,0xDD42,0x3A2A,0x1C2A,0x3D2A,0x7711,0x8A00,0x8F00,0xCF08,0x9008,0x3008,0x6B00,0x4A00,0xAE00,0xAF00,0xF400,0xB108,0xB210,0xD408,0xF308,0x4B00,0x0800,0x2908,0x0708,0x0708,0x0810,0x2E10,0x7318,0x6E18,0x0420,0x0030,0x0030,0x0038,0x0048,0x0050,0x0060,0x0060,0x0068,0x0070,0x0080,0x0080,0x0088,0x0090,0x0090,0x0098,0x0098,0x0098,0x0098,0x0098,0x20A0,0x80B8,0xA0B0,0x60B0,0x20B0,0x81B8,0x00A8,0x00A8,0x00A8,0x00B0,0x00B0,0x00B8,0x00B0,0x00B8,0x00B8,0x00C8,0x00C8,0x00D0,0x00C8,0x00C8,0x00C8,0x00C0,0x00C8,0x00D0,0x00D0,0x00C8,0x00D0,0x00D8,0x00E0,0x00E0,0x00E0,0x00D8,0x00E0,0x00E0,0x20E0,0x20E0,0x20E0,0x40D8,0x61D0,0xC799,0x0A5B,0xEA5A,0x095B,0xE95A,0x295B,0x095B,0xE962,0x0863,0x0963,0x095B,0x095B,0x095B,0xE95A,0xEA5A,0x095B,0x085B,}, +{0x073B,0x0633,0x483B,0xA83B,0xEC54,0x5376,0x314D,0xCC23,0xE712,0xA612,0xE71A,0xE822,0xEA1A,0x2A2B,0x092B,0xC61A,0x6612,0x861A,0x6412,0x430A,0x0623,0x2A2C,0x2B24,0x2B2C,0x8B2B,0x8812,0x250A,0x6612,0xCB32,0xCC32,0x9253,0x1143,0xB02A,0x1022,0x4F2A,0x7132,0x8F22,0xF222,0xD532,0x3222,0x1122,0xB011,0x331A,0x122A,0x3022,0xD121,0x541A,0x5832,0x552A,0x7632,0x562A,0x3732,0x3532,0x3532,0x5532,0x352A,0x7532,0x7532,0x5122,0xB942,0xFB52,0xB421,0xB119,0xAE21,0x154B,0x9E74,0x7F7C,0x7F7C,0x3D63,0x9A32,0x3E4B,0xF929,0x3722,0x5B4B,0x5D5B,0xF729,0xDD5B,0x5D5B,0x3621,0x3211,0x1311,0x4D11,0xF621,0x3219,0xEE18,0x9221,0x983A,0x9A32,0x1C43,0x3F6C,0x5E5B,0x3D22,0x7E22,0xBA19,0xFB21,0x5921,0x8E00,0xD93A,0x9B5B,0x3111,0x4800,0xAC00,0xEF10,0x3932,0x9621,0x3519,0x1419,0x2C00,0x3111,0x7429,0x7832,0x9F5B,0xBF5B,0x9D32,0x9819,0xD310,0xCF08,0x4E08,0x4900,0x4908,0xAB08,0x8C08,0xCE08,0xAF08,0xF110,0xD331,0x9021,0x5111,0x7111,0x2F19,0x0D19,0x4E19,0xD421,0xF729,0x5119,0xD521,0xDC42,0x5819,0x1D32,0x3E2A,0x9919,0xAB00,0xB010,0xB010,0x9100,0x5008,0x2D00,0x4F00,0x4E00,0x8F00,0xF708,0xD208,0x9008,0xAD08,0xCF08,0x4800,0x2B00,0x0608,0x0908,0x0508,0x0610,0x0818,0x0E18,0x3018,0x2920,0x0028,0x0038,0x0040,0x0040,0x0048,0x0058,0x0058,0x0060,0x0068,0x0078,0x0088,0x0090,0x0098,0x0090,0x0090,0x0098,0x0098,0x0098,0x00A0,0x0098,0x0098,0xC0B8,0xE0B8,0xA0B0,0x60B0,0x40B0,0x00A8,0x00A8,0x00A8,0x00A8,0x00A8,0x00B0,0x00B8,0x00B8,0x00C0,0x00C0,0x00C8,0x00C0,0x00C8,0x00D0,0x00C0,0x00C8,0x00C8,0x00C8,0x00C8,0x00D0,0x00D8,0x01D8,0x00E8,0x00E8,0x00E0,0x20D8,0x00E0,0x00E8,0x20E8,0x60E0,0x60D8,0x42D0,0x478A,0x2863,0x0A63,0x0A5B,0x0963,0x0A5B,0xE962,0xEA62,0x095B,0x095B,0x095B,0xE95A,0x0853,0xE95A,0xEA5A,0x095B,0x0963,}, +{0x4543,0x673B,0xC93B,0xF07C,0x8F64,0xEA3B,0x2723,0x831A,0x061B,0x692B,0x692B,0x8A23,0x4B23,0xC922,0x671A,0xE712,0x471A,0x2412,0xE211,0x031A,0x441A,0xA71A,0x0823,0x4512,0x0302,0x440A,0xE92A,0x2B33,0x4E33,0xEF32,0x8B22,0xAC2A,0xCA21,0x0A22,0xAB19,0x8D32,0x6F2A,0xD232,0x1222,0x3322,0xD019,0x131A,0x1322,0x322A,0x742A,0x343A,0xF419,0xF321,0x351A,0x9742,0x362A,0xB732,0x3632,0x973A,0x982A,0x3832,0xF842,0xF83A,0x773A,0xB321,0x8E19,0x6B19,0xAA11,0x964B,0xDF84,0xDF84,0x3F7C,0xF831,0xD219,0x9B42,0x7729,0xF321,0x1C4B,0x7B32,0x383A,0x9D53,0x3A3A,0xB308,0x3309,0xF618,0xEF08,0xD721,0x3411,0x0C11,0x6F19,0xB429,0xB119,0x9A4B,0x5F7C,0xBC4A,0x5D22,0x5D32,0x9919,0x5D2A,0x5A21,0x6E00,0xB921,0xDA21,0xD200,0xAC00,0xEF08,0x3119,0x5521,0x9210,0x4908,0x0600,0x6600,0xB621,0xB711,0x1B3B,0xDF5B,0xDE42,0xFC21,0xFD21,0xF510,0xEF00,0x8D08,0x6E08,0xAC08,0x8900,0x8A08,0xCD08,0xAB08,0xD010,0x1319,0x1111,0x7419,0x7219,0x3419,0x1119,0x5221,0x3211,0x172A,0x9621,0x1622,0xCF08,0x3832,0x7711,0x5D3A,0x3E32,0x9A19,0x3211,0xD310,0xB310,0x9010,0xB100,0x6F00,0x4F00,0x2D00,0xAF00,0xB908,0xF708,0x6E00,0xAE00,0x4B08,0x4A00,0x0B08,0x0A08,0x0710,0x0608,0x0510,0x0710,0x0420,0x0818,0x0520,0x0028,0x0030,0x0040,0x0040,0x0048,0x0050,0x0058,0x0170,0x0178,0x0080,0x0180,0x0080,0x0088,0x0090,0x0098,0x0098,0x0098,0x0098,0x00A0,0x00A0,0x0098,0x0098,0xA0B0,0x00C1,0xE0B8,0x80B0,0x40B0,0x00A8,0x00A8,0x00A8,0x00A0,0x00A8,0x00A8,0x00B8,0x00C0,0x00B8,0x00C0,0x00C8,0x00C8,0x00C8,0x00C8,0x00C8,0x00C8,0x00D0,0x00D0,0x00D8,0x00E0,0x42E0,0x21E8,0x01E0,0x20E0,0x00E0,0x40E8,0x00E8,0xC1E8,0xA0E0,0x60D8,0x41C0,0x687A,0x2863,0x0A5B,0x095B,0x0963,0x0963,0x095B,0xE962,0x0863,0xE95A,0x095B,0x095B,0x0953,0xE95A,0x095B,0xE95A,0x085B,}, +{0x6753,0xA843,0xE83B,0xA943,0xA72B,0x293C,0x6C44,0xCD43,0xAD3B,0x2A33,0x2933,0x6A23,0x6A1B,0x0713,0xA712,0xC822,0x061A,0xE411,0x031A,0x0312,0xE211,0x2512,0xC309,0x0312,0xE92A,0xEB32,0xA922,0x0D33,0x6B22,0x4C33,0x6B2A,0x6A22,0xEA21,0x092A,0x8C32,0x8E32,0xEC29,0x0C1A,0x2F22,0x301A,0xB632,0xD329,0xF011,0x122A,0x5322,0xF221,0xF219,0xD119,0x541A,0xB93A,0x372A,0x773A,0x793A,0x5842,0xF521,0xD842,0x9842,0x362A,0xB121,0xD021,0x2B19,0x4909,0x764B,0xDF84,0x9F7C,0x3D5B,0x1411,0x532A,0x7D63,0x5321,0xF121,0xDB3A,0x5A32,0xF921,0x1C3A,0x1509,0xB008,0x9721,0x3511,0x0E09,0x5B32,0x1519,0x8A08,0x0911,0xB529,0x2E09,0x394B,0x7F7C,0xFC52,0xFD32,0x7D3A,0xFA21,0xFE4A,0xD931,0x4C00,0x1521,0x1911,0xF608,0xB100,0x8F00,0x5321,0xD010,0x4C08,0x0600,0x2200,0x8500,0xD519,0x3C22,0x5E53,0x7F53,0xBE32,0xFC19,0x3C2A,0xD410,0xAF08,0xAF00,0x8F08,0x6C08,0x4A00,0x8B00,0x6C00,0x8B00,0xAF10,0x7411,0x1111,0x9621,0xD629,0x7419,0x3419,0xB531,0x9419,0x3A2A,0x7932,0x3411,0xB619,0x1111,0xF310,0xDA29,0xDC21,0xDE39,0x7A19,0x1111,0xD308,0x9108,0x6C00,0x9200,0x5008,0x4E00,0x6D00,0x7000,0xB908,0x5A11,0xAC00,0x8F08,0x4B00,0x6C00,0x0708,0x0808,0x0310,0x0618,0x0210,0x0118,0x0220,0x0120,0x0028,0x0030,0x0030,0x0038,0x0040,0x0040,0x0050,0x0060,0x0060,0x0070,0x0070,0x0078,0x0078,0x0080,0x0088,0x0098,0x0098,0x0090,0x0098,0x00A0,0x00A8,0x00A8,0x00A0,0x0098,0xA0B0,0x01C9,0x00B9,0xA0B8,0x40B0,0x20B0,0x00A8,0x00A8,0x00A8,0x00B0,0x00B0,0x00B0,0x00B0,0x00B8,0x00C0,0x20C8,0x20C0,0x00C8,0x00C8,0x00D0,0x00D0,0x00D0,0x00E0,0x00E0,0x01E8,0x01E8,0x01E0,0x40E0,0x00E8,0x20E8,0x20E8,0x80E8,0x80E0,0x61E0,0xC3B8,0xE972,0x095B,0x0A5B,0x095B,0x0A5B,0x095B,0x095B,0x0863,0x0963,0x0963,0x095B,0xE95A,0x095B,0x0A53,0x085B,0x095B,0x0953,}, +{0x254B,0x873B,0xC843,0x0A54,0x8C64,0x4C5C,0x0C4C,0xA933,0xA833,0xA933,0x492B,0x281B,0xC91B,0x4923,0xA612,0x8522,0xA51A,0x6412,0x231A,0x0312,0x0422,0x030A,0xE311,0xA622,0xC92A,0x2A23,0xCA22,0x2812,0xEC2A,0x0712,0xCB2A,0x6922,0x6A22,0x2A2A,0x6B32,0x2A32,0xAB32,0x6D2A,0xAE1A,0x952A,0xF221,0xF019,0x341A,0x132A,0xF229,0xD019,0x9422,0x7632,0x572A,0xD419,0x773A,0x163A,0x1832,0x9219,0xF742,0x153A,0x3332,0xF319,0x3632,0x5121,0x2809,0xD742,0x3F74,0x7E63,0x5B32,0x3409,0xB43A,0xDE73,0x5629,0x2C01,0xDA42,0x9A42,0xF629,0x3511,0xB010,0xEE10,0x1219,0xB108,0xD119,0xBC4A,0x3719,0x6A00,0x6500,0x9021,0x4F11,0xF842,0x7E5B,0x7D3A,0x1D43,0x7E53,0x3B2A,0x3B3A,0x1521,0x6A00,0xCE08,0xF108,0x5909,0x9108,0x4900,0x4900,0x6A00,0xAC08,0x2900,0x2400,0x6500,0x3622,0xFE4A,0x3F53,0x3F4B,0xDE42,0xFB29,0x9919,0x9008,0x8C00,0xAF08,0xB008,0x6B08,0x8E08,0x8C00,0x4C00,0x4B08,0xD008,0x1111,0xF210,0xB629,0xF631,0xB521,0xD629,0xF631,0x9421,0x9C3A,0x3E4B,0x7A3A,0x5519,0xB008,0x3219,0xD110,0x9929,0x1C2A,0xFD29,0x7919,0xF110,0xD308,0x9010,0x8900,0x9010,0x6F08,0x4B00,0x6C00,0x6D00,0x9808,0x1B09,0xD000,0x8E00,0x4F00,0x4900,0x2908,0x4408,0x2508,0x4210,0x2118,0x0018,0x0020,0x0028,0x0028,0x0028,0x0038,0x0038,0x0040,0x0048,0x0050,0x0058,0x0060,0x0068,0x0070,0x0080,0x0078,0x0088,0x0088,0x0090,0x0090,0x0090,0x00A0,0x00A0,0x00A8,0x00A8,0x20A8,0x00A8,0x00A0,0x00A0,0x80B0,0x00B9,0xA0B8,0x80B8,0x40B0,0x00B0,0x00B0,0x00A8,0x00B0,0x00B0,0x00B8,0x00B8,0x00C0,0x00C8,0x20C8,0x20C8,0x20C8,0x00D0,0x00D0,0x00D8,0x00E0,0x20E0,0x01E0,0x00E0,0x00E0,0x00E8,0x20E8,0x20E8,0x00E8,0x60E8,0xA0E0,0xA2E0,0x65A9,0x0963,0x095B,0x095B,0x0A63,0x095B,0x095B,0x0963,0x0963,0x095B,0x295B,0x095B,0xEA5A,0x0963,0x0A5B,0xE95A,0x0963,0x095B,}, +{0x4653,0x8853,0xA95B,0xE863,0xA86B,0x6653,0x4944,0xAB44,0x2A44,0x6A44,0x4B4C,0x682B,0x6923,0x271B,0xE612,0x851A,0xE51A,0xC51A,0x620A,0x430A,0x4412,0x230A,0x6212,0x241A,0x0A33,0x661A,0xA82A,0x681A,0x2612,0xCB22,0x491A,0x0B2B,0x091A,0x6C22,0x6821,0xC821,0x8C2A,0x6D32,0xAD1A,0x9232,0x902A,0xAD19,0x3222,0xD019,0xAE11,0xB42A,0x733A,0xF329,0xD219,0x5632,0x5622,0xD629,0xD019,0xF842,0xB429,0x753A,0x3532,0x194B,0xB529,0xA900,0xD84A,0xDD5A,0xD829,0x392A,0xB411,0xF73A,0xDE6B,0x7719,0xED00,0x1943,0x3D63,0x7319,0x1109,0xAE08,0x2F11,0x1319,0xEE08,0x5732,0xBD4A,0xD410,0x4800,0x4300,0x4E09,0x172A,0xB63A,0x7942,0x3A22,0x1C4B,0x5E5B,0x7E3A,0x9829,0x4D10,0x6700,0x6900,0xAD00,0x5719,0x6D00,0x4500,0x4500,0x6608,0x6800,0x4700,0x4600,0x6700,0x1522,0xDB3A,0xBC42,0xBE42,0x5C32,0x5711,0x5729,0x6C08,0x8B00,0xCE08,0x8E08,0x8E08,0x8F00,0x6B00,0x8D00,0x2C00,0x8C00,0xCF08,0xCE10,0x9621,0x7421,0x7521,0xF729,0x3021,0xB631,0x3932,0x7E53,0xFF63,0xD829,0x5519,0xB008,0xF108,0xD418,0x7A19,0xBB29,0x5A21,0x1611,0x8E08,0xB108,0xAE00,0xA900,0x6C08,0x4A08,0x4900,0x4B00,0x4D00,0x7508,0xFA08,0xD408,0x6E00,0x2D00,0x6800,0x4708,0x6408,0x4208,0x4108,0x4118,0x0020,0x0020,0x0020,0x0028,0x0028,0x0038,0x0038,0x0040,0x0048,0x0048,0x0058,0x0060,0x0068,0x0070,0x0070,0x0080,0x0080,0x0080,0x0088,0x0088,0x0090,0x0098,0x00A0,0x00A0,0x00A8,0x00A8,0x00B0,0x00B0,0x00A0,0x0098,0x20A0,0x60B8,0xC0B8,0xC0C0,0xA0B8,0x60B8,0x40B0,0x20A8,0x00A8,0x00B0,0x00B8,0x00B8,0x00C8,0x20C8,0x00C8,0x00C8,0x00D0,0x00D8,0x00D8,0x00E0,0x00E8,0x01E8,0x00E0,0x00E0,0x00E8,0x40E8,0x40D8,0x40E0,0x60E8,0x80E8,0x24D9,0xC699,0x0A63,0x0963,0x095B,0x0963,0x0A5B,0x295B,0x295B,0x0A63,0x095B,0x095B,0x095B,0xEA5A,0xE95A,0x095B,0x095B,0xE95A,0x085B,}, +{0xE44A,0x644B,0xC66B,0x0884,0x0A84,0xC97B,0x6B6C,0x0B5C,0x8843,0x084C,0xCA4B,0x062B,0x0523,0x2723,0xC412,0x8412,0x830A,0x6212,0xC51A,0x061B,0xA412,0xC622,0x441A,0x4412,0x6312,0x872A,0x251A,0xE91A,0xC92A,0x681A,0x0D2B,0x6912,0xCE2A,0x6811,0x0912,0xF132,0x8E3A,0xCE2A,0x8E1A,0x4F22,0xB132,0xEF29,0xEF19,0x101A,0x512A,0x111A,0x7019,0xAF11,0xF319,0x5632,0x9219,0x5222,0xD94A,0x3011,0x342A,0xF629,0x9C53,0xB731,0x8800,0x6A11,0x1221,0xAB00,0x7632,0x9B22,0x7C53,0x9F5B,0x9A29,0xF000,0x1843,0x5E6B,0xF210,0xCA00,0xEE08,0x2C09,0x5211,0xD519,0x5B2A,0x5C42,0x7008,0x2400,0x2300,0x6E19,0xDB3A,0xDA3A,0xDC42,0x592A,0xDC42,0x3F7C,0x3C3A,0xF518,0x8900,0x6508,0x8408,0xCB00,0x1511,0x2B08,0x2300,0x2200,0x4408,0x6810,0x4700,0x6700,0x9021,0x9A42,0x9A29,0x9929,0x3511,0xD308,0xD408,0xB100,0x8D08,0xAE08,0xD310,0xAB00,0x8F08,0x4C00,0x6B00,0x6C00,0x6D00,0x4A00,0x6A00,0x4900,0xCD10,0xF108,0x5421,0xB521,0xAD08,0xF739,0xD431,0xDD42,0x1F64,0x7F5B,0x7519,0x5619,0xF110,0xCF08,0xD518,0x5A11,0x3919,0x3919,0xD308,0x8E00,0x8F00,0x8B08,0x8A08,0x4A08,0x6A08,0x8A00,0x4A00,0x4F08,0x7300,0xFB08,0xD708,0xAC00,0x8D00,0x6800,0x6700,0x6308,0x6308,0x2110,0x2120,0x0018,0x0020,0x0020,0x0028,0x0030,0x0038,0x0038,0x0040,0x0048,0x0048,0x0058,0x0060,0x0068,0x0070,0x0070,0x0078,0x0080,0x0080,0x0088,0x0088,0x0090,0x0098,0x0098,0x00A0,0x00A0,0x00A8,0x20A8,0x20B0,0x20A8,0x40A8,0x40A8,0x20A0,0x2098,0x60B0,0x00C1,0x00C9,0xA0B8,0x60B8,0x40B0,0x00B0,0x00B0,0x00C0,0x40C8,0x20C8,0x00C8,0x00D0,0x00D0,0x00D0,0x00D8,0x00D8,0x00E0,0x00E0,0x00E0,0x00E8,0x20E8,0x40E0,0x60E0,0xA0E0,0xA0E0,0xA0E0,0x65D9,0x6782,0x295B,0x0963,0x2853,0x0A5B,0x0A5B,0x095B,0x0963,0xE962,0x085B,0x0A5B,0xEA5A,0x0A5B,0xC95A,0xE95A,0xE85A,0xE95A,0xE95A,}, +{0x4563,0x8473,0x838B,0x239B,0xA39A,0x8382,0x0673,0x8863,0xC853,0x0844,0x873B,0xC52A,0x842A,0x2412,0x6212,0x831A,0x821A,0xC212,0x051B,0x0513,0xC51A,0x2512,0x6412,0x4212,0x8312,0xE311,0xC51A,0x6822,0x8722,0x8822,0xC81A,0x4A22,0x4509,0x691A,0xF23A,0x2F1A,0x6B2A,0x2E3B,0xD143,0x7533,0xD32A,0x153B,0xF221,0x4A09,0xCF19,0x9011,0x2901,0x2E22,0x522A,0x4D09,0xB432,0xBB42,0x3009,0x1222,0xF521,0xFA3A,0xB729,0x6800,0x6E19,0xAA08,0x6300,0x722A,0xFE53,0x5F6C,0x9E63,0x5821,0x2E00,0xD442,0x5D63,0x9210,0x6600,0x2F11,0xCB10,0x8F11,0x193A,0xB821,0xF510,0x4B00,0x2300,0x4200,0x6C09,0x5D53,0x1E4B,0x3E4B,0x9C3A,0xF94A,0x9642,0x9529,0xAD08,0x6708,0x6500,0x6200,0xA908,0x1311,0x8A00,0x4400,0x2100,0x6200,0x6500,0x6600,0x9021,0xFB4A,0xFD52,0x1419,0x7008,0x2D00,0xAB00,0x2F09,0x8D08,0x8C08,0xAE08,0x1411,0xAE00,0xD000,0x6B00,0x8D00,0x8B00,0x4D00,0x6B00,0x6A00,0x4800,0x6400,0xA900,0xEF10,0x3319,0x8E08,0xD621,0xB010,0x3A3A,0x7F5B,0xFF63,0x9D42,0x1619,0x3611,0xF210,0xB210,0x1319,0x1619,0x3711,0xD210,0xF108,0xF108,0xAF08,0xAA08,0x8800,0x8B08,0x4808,0x8A00,0x8C08,0x4E00,0x9200,0xFA08,0xF808,0xEE08,0x6E08,0x8600,0x4710,0x6408,0x6310,0x4218,0x0118,0x0018,0x0018,0x0020,0x0030,0x0030,0x0030,0x0038,0x0040,0x0048,0x0048,0x0050,0x0058,0x0060,0x0060,0x0078,0x0078,0x0078,0x0078,0x0080,0x0090,0x0088,0x0090,0x0090,0x0098,0x00A8,0x00B0,0x00A8,0x00B0,0x20B0,0x60A8,0x60A8,0x60A8,0x60A0,0x20A0,0x20A0,0x4098,0x80A8,0x21C9,0xA0B8,0x40B0,0x20B0,0x00B8,0x40C0,0x20C8,0x20D0,0x20D8,0x00D0,0x00D0,0x00D0,0x00D0,0x00D0,0x00D8,0x00E0,0x20E8,0x80E0,0x40E0,0x40E0,0x60E8,0xE0E0,0xA0E0,0xA2C8,0xC96A,0x0A5B,0x0A63,0x095B,0x095B,0x0963,0x0A63,0x0963,0xEA5A,0xEA5A,0xE95A,0x0A63,0xE95A,0xE95A,0xE95A,0xE95A,0xC95A,0xC95A,}, +{0x225B,0x627B,0xA293,0x42A3,0x249B,0x2793,0x486B,0xCA6B,0xA963,0x8853,0xE43A,0xA41A,0xA422,0xA31A,0x611A,0x2112,0xA322,0x041B,0x451B,0xC51A,0x4512,0x4412,0x830A,0xC42A,0x8312,0xE31A,0xA412,0x672A,0xE519,0xA71A,0x471A,0x6309,0xCA32,0x913B,0xCB19,0x8B22,0xCC42,0x8E4B,0xB343,0xF32A,0x0F2A,0x2901,0xED21,0x3332,0x8D19,0xCA11,0x6F22,0xCD19,0xAB09,0x1633,0xFC3A,0x9411,0xCF11,0x3522,0x9A2A,0x3419,0x8900,0x2C11,0x3321,0x4500,0x2F22,0x5E74,0x9F7C,0x7B4A,0x6F00,0x2600,0xB121,0xFC62,0x7010,0x4500,0x2F11,0xCC08,0x6E19,0xF831,0xD210,0xAB00,0x4600,0x2300,0x4200,0x0909,0xDC53,0xDF63,0xBF63,0x1E43,0x5B2A,0x362A,0x5011,0xCB08,0x6608,0x6310,0x8300,0xEB10,0x1319,0x6B08,0x4400,0x6200,0x6300,0x6300,0x6600,0x0C19,0x3521,0x3629,0xD110,0x8D00,0xAE00,0x7511,0xF308,0x6D00,0x1109,0xAF08,0x1109,0x6C00,0xD108,0xAE00,0xB008,0x6A00,0xAB00,0x8B08,0x6A00,0x8900,0x4600,0x4300,0xC808,0x6808,0xAC08,0xED10,0x3219,0x7421,0x7C2A,0x5F4B,0x3E4B,0xD829,0x7819,0x5511,0xD510,0xB210,0xB108,0xF310,0x3211,0x1109,0xF010,0x1411,0xEF08,0xAB00,0x8900,0x8F10,0x6600,0x6800,0xCE08,0xAC00,0xB008,0x1619,0x7819,0x5211,0xAE08,0x6408,0x4408,0x8508,0x6308,0x4210,0x2118,0x0018,0x0018,0x0020,0x0020,0x0030,0x0030,0x0038,0x0040,0x0040,0x0048,0x0050,0x0058,0x0058,0x0068,0x0070,0x0078,0x0078,0x0080,0x0080,0x0080,0x0090,0x0090,0x0088,0x0098,0x00A0,0x20A0,0x00B0,0x00B0,0x20B0,0x60A8,0x60A8,0x60A0,0x60A8,0x60A8,0x60A0,0x4098,0x4090,0x40A0,0xA0C0,0xA0C0,0x60B8,0x20B8,0x40C0,0x20C8,0x00D0,0x20D0,0x00D0,0x00D8,0x00D8,0x20D8,0x00D8,0x20D8,0x20D8,0x40E0,0x60E0,0x60E0,0x80E0,0xA0E8,0xE0E0,0xC0E0,0x44B1,0xEA62,0x095B,0x0A63,0x0A5B,0x095B,0x0963,0xEA62,0xEA62,0xEA5A,0xEA5A,0xEA62,0xEA5A,0xE95A,0x095B,0xEA5A,0x095B,0xE95A,0xC95A,}, +{0xA373,0x2494,0x249C,0x64A3,0xA39A,0x2492,0x857A,0x666A,0xC45A,0x0854,0x2A54,0xC83B,0x6433,0xC222,0xA112,0x251B,0xC422,0xE522,0x8312,0x431A,0x6412,0xC41A,0x462B,0xA522,0xC41A,0x830A,0xC31A,0xE319,0xE311,0xC309,0xE209,0xE321,0xCA42,0xE811,0x8712,0xA511,0x2C33,0xAE22,0xEB19,0x2812,0x091A,0xF02A,0x5132,0xA911,0x902A,0x122A,0x4909,0x0C12,0xD94B,0xDE43,0x1812,0xAC09,0x8E32,0xB832,0x5419,0xEA00,0x0901,0x7221,0x8800,0xCD11,0x9C53,0x1C53,0x5521,0x6B00,0x4400,0x4C11,0xDA31,0x4E08,0xA500,0x7011,0x5011,0x8E11,0x3842,0xCF08,0x6600,0x2400,0x4200,0x4200,0xC700,0xBA5B,0x3F6C,0x3F6C,0x5F4B,0xFE32,0x5B32,0xB419,0xAB08,0x4708,0x4408,0x8310,0x0821,0xEC10,0x4900,0x4400,0x6508,0x6508,0x6400,0x6508,0x4708,0x4A00,0xAB08,0x6D08,0xAD00,0x3419,0x7819,0xF510,0x8F08,0x3619,0xD308,0xF208,0xEF00,0xCD00,0xCE00,0xCE08,0x6F08,0xAC08,0x8B00,0x6900,0x6700,0x8500,0x4400,0x4300,0x4300,0x2400,0x4500,0x2F11,0x6A00,0x7721,0x7E32,0x5E32,0x5E32,0x3411,0x9919,0xF308,0xF510,0xD110,0xB008,0xD408,0xD108,0x3511,0xD210,0x7619,0xF108,0x8D08,0xAE08,0x9110,0xCD08,0x8808,0xD018,0xEE08,0xF108,0x7719,0xD921,0xB819,0x5109,0x8400,0x4308,0x8410,0x8410,0x6108,0x2110,0x2118,0x0018,0x0020,0x0020,0x0030,0x0028,0x0038,0x0038,0x0040,0x0048,0x0048,0x0060,0x0068,0x0068,0x0068,0x0070,0x0070,0x0078,0x0080,0x0080,0x0088,0x0090,0x0088,0x0098,0x0098,0x00A0,0x00A8,0x00A0,0x20A8,0x20A8,0x40A8,0x60A8,0x60A8,0x60A8,0x80A0,0x60A0,0x6098,0x2090,0x2098,0x01B9,0x22B9,0x80B8,0x20C0,0x20D0,0x40D0,0x20C8,0x00D0,0x00E0,0x00E0,0x00E0,0x00E0,0x20E0,0x40D0,0x60D0,0x60D8,0x80D8,0xC0E0,0x00E1,0xA0E0,0xE0D8,0xE699,0xE962,0x0A5B,0xEA62,0xE962,0x0953,0x095B,0xEA5A,0xE95A,0xE95A,0x0A5B,0x095B,0x095B,0x095B,0x095B,0xE95A,0xE95A,0xE952,0xC952,}, +{0x229C,0x02AC,0x81B3,0x80AA,0xC0A1,0x8189,0xA47A,0x4874,0x0B6D,0xCB5C,0x2854,0x8543,0x2333,0xA633,0xE53B,0x852B,0x2523,0xC41A,0x631A,0xA212,0xE522,0xE62A,0xC622,0xC722,0x6512,0xA52A,0x641A,0x441A,0xE311,0x020A,0xE219,0x8319,0x8319,0x8311,0x6319,0x6732,0x0822,0xA411,0x071A,0x481A,0xAE22,0x6C1A,0x2A12,0x5122,0x5021,0x6700,0xCE22,0x7C5C,0x3F54,0xB91A,0xAC09,0xAB3A,0xD573,0x331A,0x4D11,0xEB00,0x7019,0xCA08,0xEC19,0xBC4B,0x172A,0xAE00,0x8900,0x4600,0xC600,0x4F21,0x0B08,0xE708,0x772A,0x5922,0x351A,0x973A,0x3119,0xAA08,0x6500,0x4408,0x4200,0x8400,0x3843,0x3F6C,0x5F74,0xFF63,0xBF63,0x7C3A,0xF310,0x6900,0x2600,0x0400,0x2300,0x8408,0xC808,0xA708,0x4508,0x8808,0x6608,0x6600,0xA910,0x8708,0x6700,0x8A08,0x8B00,0x8D00,0xCF10,0x1419,0xB208,0x3311,0x5411,0xD108,0x5409,0x1309,0x3411,0x1309,0xB008,0xCF08,0xAB08,0xC900,0x8900,0x6A00,0x4800,0x6700,0x4500,0x6300,0x4300,0x4300,0x4508,0x2700,0x0E11,0x7719,0xBC21,0xDB21,0x9A21,0x1411,0x7819,0xB210,0x6F08,0xD310,0xD108,0x9308,0x8E08,0xD208,0xF308,0xBB21,0x3409,0xAE08,0x9008,0x8D00,0xF308,0xA908,0xF110,0xEF08,0xF308,0xBA19,0x1C32,0x9721,0xB721,0xC900,0x6300,0x4308,0x6208,0x6310,0x4208,0x2110,0x0018,0x0018,0x0020,0x0028,0x0028,0x0038,0x0038,0x0040,0x0048,0x0048,0x0050,0x0058,0x0060,0x0068,0x0070,0x0070,0x0078,0x0078,0x0080,0x0080,0x0088,0x0090,0x0090,0x0098,0x0098,0x0098,0x00A0,0x00A0,0x00A0,0x40B0,0x20A8,0x40A0,0x40A8,0x40A8,0x60A0,0x40A0,0x6098,0x4090,0x81A0,0x06CA,0xA0C0,0x40C0,0x40C8,0x40C8,0x20D0,0x20D0,0x00D8,0x00E0,0x20D8,0x40E0,0x00D8,0x60E0,0x60E0,0xA0D8,0xA0D8,0xC0E0,0x20E9,0x00D9,0xE0D0,0x6882,0x0963,0xEA5A,0x295B,0x095B,0x095B,0x2863,0x095B,0x095B,0x095B,0x095B,0x0853,0x095B,0xEA5A,0xE95A,0x0963,0xE95A,0xE95A,0xC952,}, +{0xA1A4,0x01AC,0x60AB,0xA0A2,0xA58A,0x8A8B,0x2F8D,0x2E7D,0x4A64,0x4753,0xA542,0xC43A,0x873B,0x8833,0xC943,0xA73B,0x8633,0xC422,0xC522,0xC41A,0x8622,0x8522,0x872A,0x861A,0x8622,0x452A,0x0422,0xE319,0x431A,0xC319,0x6119,0x2219,0x2219,0x0109,0xA429,0x6421,0x2209,0x0111,0x0622,0xAA3A,0x8719,0x6811,0xAE19,0xA908,0xC300,0xF23B,0xDE8D,0x9E74,0xF92A,0x8F1A,0x2A12,0xF22A,0x952A,0xB109,0x2B01,0x9011,0x2C09,0x502A,0x1743,0x7411,0x2D01,0xCC00,0x8900,0x4700,0x6608,0x6400,0x4A09,0x394B,0xBF4B,0xFD3A,0xDC42,0xD521,0x2D09,0xC910,0x8500,0x6300,0x6208,0x953A,0xFF63,0x7F7C,0xDE6B,0x7A42,0xB308,0x4900,0x8608,0x4400,0x2300,0x0100,0x4500,0x0C11,0xEC00,0x8600,0xA900,0x8800,0xAC08,0xAB00,0x8908,0xAA08,0xAA08,0xAD08,0xAE08,0x8D08,0xAD08,0xF218,0x9819,0x7819,0x7411,0x9619,0x1201,0x7611,0xF308,0xD208,0xD108,0xB008,0xAF08,0xEE00,0xCC00,0x6A00,0x6A00,0x6600,0x4600,0x6300,0x4300,0x6300,0x4400,0x4608,0xD118,0x5919,0x7A29,0x7911,0xF210,0x1509,0xF410,0xD308,0x8F08,0xD310,0xD300,0x9108,0xAD00,0xAC08,0xD410,0x9D21,0x3609,0x8B00,0x6D08,0xAB00,0xD618,0x0E01,0x1219,0x3209,0xF308,0xBA19,0x3D3A,0x9819,0x7821,0x0B09,0xA500,0x6308,0x6208,0x4210,0x6210,0x6310,0x2110,0x0018,0x0020,0x0028,0x0028,0x0030,0x0038,0x0038,0x0048,0x0048,0x0048,0x0058,0x0060,0x0060,0x0070,0x0068,0x0078,0x0078,0x0080,0x0080,0x0080,0x0090,0x0090,0x0090,0x0098,0x0098,0x00A0,0x0098,0x0098,0x00A0,0x20A0,0x20A0,0x20A0,0x4098,0x4098,0x20A0,0x4098,0x2098,0x4090,0x80A8,0xA0C0,0x02C9,0x60C8,0x40C8,0x40D0,0x40D0,0x40D0,0x20D8,0x20E0,0x40E0,0x20E0,0x60E0,0x80D8,0xA0D8,0xC0E0,0xE0E0,0x60E1,0x20D9,0x84C9,0xC96A,0x0963,0x095B,0x2853,0x095B,0x0963,0x0963,0x0963,0xE95A,0x0963,0x0953,0x095B,0xE95A,0xE95A,0x0953,0x095B,0xE95A,0xE952,0xE952,}, +{0xC3A4,0x43A4,0xE4A3,0x85A3,0xCC93,0x0D8B,0xE972,0x445A,0xC251,0x8342,0xA953,0x2853,0x6833,0x6A2B,0x6A3B,0x8833,0xA632,0x2723,0x062B,0x8522,0x4522,0x4522,0x4722,0x4622,0x2522,0x262A,0xE519,0xE521,0x2322,0xC319,0xA319,0x6121,0x2111,0x6011,0x6109,0x2111,0x0111,0xA321,0x8419,0xC110,0x4521,0x4B19,0x6408,0xE911,0x5865,0x1F8E,0xBF6C,0x5A33,0xB41A,0xB122,0xB72A,0x9922,0xF311,0x2B09,0x8809,0xAC19,0x6F2A,0xF94A,0x7019,0xED00,0xED08,0x8D00,0x6700,0x6500,0xA500,0xCE19,0x1C5C,0x7F74,0x3F5C,0xBF53,0xDD3A,0xD529,0x3019,0xEB08,0xC600,0x6508,0xF029,0xDE63,0x1F64,0xBB52,0xD310,0x4B00,0x2600,0x4300,0x4400,0x2200,0x4300,0x4700,0xCD08,0xAF10,0xAA00,0xCA08,0xCB00,0xED08,0x8A08,0xEC00,0xF118,0xCD18,0xAD08,0x8D00,0xED00,0x1119,0xF010,0xF108,0x5711,0x9919,0xDB29,0x3711,0x7719,0x3611,0x3611,0x1401,0xF208,0xD208,0xF308,0xD108,0xAC00,0x8A08,0x8700,0x4600,0x6400,0x4308,0x4308,0x6400,0x4500,0x6708,0xB010,0x5619,0x3611,0x3509,0x4D00,0xF408,0xD108,0xF408,0x6F00,0xF408,0xB308,0x9120,0xEF10,0xEF00,0x9310,0xBE29,0x5911,0xAE08,0x8B00,0xF110,0xB510,0x7619,0x7519,0x7711,0x3219,0x7A21,0x3D32,0x1B2A,0x3519,0x2F19,0xE708,0xA808,0x8510,0x6208,0x4010,0x2210,0x4310,0x0218,0x0020,0x0028,0x0028,0x0030,0x0030,0x0038,0x0040,0x0050,0x0050,0x0058,0x0060,0x0060,0x0068,0x0068,0x0070,0x0080,0x0080,0x0080,0x0080,0x0080,0x0088,0x0088,0x0090,0x0090,0x0090,0x0098,0x0098,0x0098,0x0098,0x0098,0x0098,0x0098,0x4090,0x2098,0x4098,0x2098,0x4090,0x4098,0xA0B8,0x80C0,0xC0C0,0x60C8,0x60D0,0x40D0,0x40D0,0x40D0,0x60D8,0x60D8,0x20E0,0x60E0,0x80D8,0xC0D8,0x00D9,0x20E1,0x20E1,0x20D9,0xE6A9,0x0963,0x095B,0x095B,0x085B,0xEA5A,0x095B,0x095B,0x0A5B,0xE95A,0x095B,0xE95A,0xE95A,0x0953,0x095B,0x0853,0xC95A,0xC95A,0xC95A,0xE952,}, +{0x86A4,0xA5B4,0x04AC,0x429B,0x828A,0xC281,0x8379,0xC571,0x6562,0xA75B,0xAA5B,0xAA53,0xAA43,0x093B,0xA832,0x882A,0xEA3A,0x2933,0xA92A,0x472A,0x062A,0x2522,0x2622,0xE629,0x262A,0xE529,0x0622,0x0522,0x051A,0xE421,0x0522,0x6319,0xC121,0xC011,0x6019,0x4011,0x2009,0x0011,0xE018,0xE018,0xA110,0xA110,0x4E33,0x3D8E,0x1F8E,0xFF64,0x3E4C,0xBB43,0xDC3B,0x7D33,0x7A22,0xD319,0x4C09,0x4709,0xA709,0x0D22,0x7432,0xB111,0x6D09,0x0C09,0xC900,0xE700,0x2D01,0xF000,0x3322,0xBE74,0x1F85,0xFF7C,0xDF74,0x1F64,0x1E43,0xD929,0xD010,0x4700,0x4300,0xED29,0x5C53,0x9B4A,0x3319,0x8C00,0x6A00,0x4800,0x4400,0x2200,0x2200,0x6500,0x6500,0x4D11,0xF110,0xAF10,0xED10,0xC900,0xAB00,0xAD08,0xD010,0xB110,0xAC08,0xAC08,0xED08,0x1011,0xAF08,0xAC08,0xEF18,0x5411,0x7621,0x7921,0x1609,0x5819,0x5821,0x5409,0x1609,0x3611,0x7719,0xB709,0x1409,0xD210,0xAD00,0x6A00,0x6600,0x8600,0x6308,0x6300,0x4300,0x6600,0x6700,0x6600,0xAD10,0xB108,0xD210,0xD008,0xAE08,0x9118,0x8F08,0x9010,0x8E08,0xD210,0xB208,0x8F08,0xF118,0xD110,0xF508,0xBE29,0xF600,0xAE08,0x4C00,0xF710,0xD308,0x7921,0x183A,0x5621,0x5521,0x7A29,0xDE29,0x3C2A,0xCE10,0xF010,0xAA08,0x8D10,0x8810,0x6310,0x6218,0x2110,0x0118,0x2318,0x0020,0x0028,0x0030,0x0038,0x0038,0x0038,0x0040,0x0048,0x0048,0x0050,0x0058,0x0060,0x0060,0x0068,0x0070,0x0078,0x0070,0x0078,0x0080,0x0080,0x0080,0x0088,0x0088,0x0090,0x0090,0x0090,0x0090,0x0090,0x0090,0x0090,0x0090,0x0090,0x2090,0x2090,0x2088,0x2090,0x4090,0x2090,0x43B9,0xC0C0,0xE0C8,0x80C8,0x80D0,0x80D0,0x40D8,0x80E0,0x60E8,0xA0E0,0x80D8,0xA0D8,0xA0D8,0xC0D8,0x20D9,0x40D9,0x40D9,0x41D1,0x6882,0x0A63,0x0A5B,0xEA5A,0x095B,0xEB5A,0x0A5B,0xE95A,0xEA62,0xE85A,0x0953,0xEA5A,0xE952,0x0953,0xC95A,0xE95A,0xE952,0xEA52,0xCA5A,0x095B,}, +{0x459C,0x83AC,0x81BC,0x82AB,0xE39A,0x448A,0xC481,0xE579,0xE772,0x8773,0xA96B,0xEB5B,0xEC5B,0x2943,0x0943,0xC932,0x2B3B,0x0A33,0x692A,0x2622,0xE521,0x2622,0x0522,0x062A,0xC521,0xE629,0xE519,0xE521,0xC529,0x2532,0xC621,0x0422,0xC221,0xC221,0xA119,0x4111,0x2111,0x0021,0xE018,0xC010,0xC519,0xB44C,0xBD7D,0x7F7D,0x1F75,0xBF6C,0x5F5C,0xBE4B,0x1C33,0xF521,0x0E11,0xE810,0xE408,0xA609,0x9012,0x9522,0x331A,0xF411,0x8F01,0xEE01,0x110A,0xB401,0x7601,0x193B,0x1E7D,0x5F85,0x5F95,0x1F8D,0x1E74,0xBB4A,0x1419,0x4B00,0x4400,0x4300,0xC708,0xB039,0xAE10,0x8800,0xA800,0x6800,0x6600,0x6400,0x6500,0x4400,0x4400,0x8700,0x0E11,0xCF08,0xCD08,0xF218,0x3019,0x0C09,0x0D01,0xCE08,0x6A08,0xAC08,0xCE10,0xF010,0xF118,0xAB00,0xF010,0xF218,0x7121,0x3619,0x1411,0x5611,0x7921,0xF710,0x9819,0x9719,0x9819,0xBA11,0xBB21,0xDA21,0x1509,0xB000,0xAD00,0x6800,0x6600,0x6500,0x8400,0x6400,0x8500,0x6608,0x6708,0x8B08,0x6A08,0xAE08,0xCD10,0xAA08,0x0F09,0xAD10,0xAE08,0x6B00,0x2F11,0xAF08,0xB108,0x8B00,0x8E10,0x4C08,0x5819,0xBC29,0xF408,0xAE08,0x4C00,0xD610,0xF208,0x5919,0x7C42,0xB419,0x5731,0x3819,0x7B11,0x7B19,0xA900,0xAD10,0xAD10,0xF008,0xCC10,0xA610,0x8310,0x4308,0x2218,0x0018,0x0020,0x0020,0x0028,0x0030,0x0030,0x0038,0x0040,0x0040,0x0050,0x0050,0x0050,0x0058,0x0060,0x0068,0x0068,0x0078,0x0068,0x0078,0x0078,0x0078,0x0078,0x0080,0x0080,0x0088,0x0088,0x0080,0x0088,0x0090,0x0088,0x0088,0x0090,0x0090,0x2088,0x2090,0x4090,0x2090,0x2088,0x4090,0x42B1,0xE0C8,0x00D9,0xC0D0,0x80D0,0x60D8,0x60D8,0x60D8,0x60E0,0xA0E0,0x80D8,0xA0D8,0xC0D8,0x00D9,0x60D9,0x80D9,0x40E1,0x64C1,0xCA72,0x0963,0x0A5B,0xE95A,0x095B,0xEA5A,0x095B,0xEA5A,0xE962,0x095B,0xE95A,0xE95A,0x0853,0xE952,0xC95A,0x095B,0xE95A,0xE852,0xE952,0xE852,}, +{0xE48B,0x83A4,0x41AC,0xC3AB,0x02A3,0x448A,0x2572,0x066A,0xA96A,0x2763,0x8953,0x8B4B,0xE842,0x2A43,0x0B3B,0xEB3A,0x2D33,0xEC3A,0xA932,0x472A,0x282A,0xC621,0xE629,0xE519,0xA529,0xC419,0xC521,0xC629,0xC529,0xC539,0xE521,0x0322,0xC329,0xC121,0xC119,0x6221,0x4119,0x0019,0xE018,0x4B4B,0x786D,0x3D65,0x7D5C,0x9C53,0xDA42,0x172A,0xB321,0xCE08,0x4900,0x6400,0x2100,0x4000,0xA701,0x511A,0xB52A,0x941A,0x1412,0xF219,0x731A,0xF922,0x381A,0x7509,0x3B3B,0x3F85,0x5F95,0x7F84,0x5C5B,0xD831,0x9000,0x4900,0x4300,0x6400,0xC808,0xCD10,0x6908,0x0408,0x4200,0x6500,0x8500,0x6700,0x8700,0x6600,0x4800,0x4700,0xC708,0x0D19,0xAD08,0xCB00,0x2F19,0xF008,0x5019,0x3011,0xCD00,0xCB00,0x1019,0xF010,0x3219,0xCF10,0xCC10,0xEF10,0xD110,0x1419,0xD110,0x5311,0x5819,0x1819,0x7811,0x7B21,0x9919,0xDB19,0x1B1A,0x1C2A,0xDC21,0x5819,0xF308,0xAE00,0x8D00,0x6A00,0x8800,0x6600,0x8500,0x8500,0x6600,0x8800,0x8808,0xAA00,0xCD08,0xAD08,0xAC08,0xB010,0xAE10,0x8C08,0xAC10,0xCF00,0xEF08,0x8B00,0x6C08,0x8A00,0x6B00,0x4C08,0x3919,0xBB21,0xF408,0x8D08,0x6B00,0x9310,0xD218,0x3721,0x5C42,0xB421,0xB218,0x3411,0x1709,0xD208,0xA710,0x6B10,0xAE08,0x1211,0xF118,0xA710,0x6410,0x4308,0x4308,0x2110,0x0010,0x0020,0x0020,0x0030,0x0028,0x0038,0x0038,0x0038,0x0040,0x0048,0x0048,0x0050,0x0058,0x0060,0x0060,0x0070,0x0070,0x0070,0x0070,0x0070,0x0070,0x0078,0x0078,0x0080,0x0080,0x0080,0x0088,0x0080,0x0088,0x0088,0x0080,0x2080,0x2088,0x2088,0x4080,0x6080,0x8080,0xE170,0xA389,0x61C9,0x62E1,0x00D1,0xA0D0,0x80D0,0x60D8,0x40D8,0x80D8,0xA0E8,0xA0E0,0xC0D8,0xE0D8,0x20D9,0xA0D9,0xA0D9,0x60E1,0x06A2,0xEA62,0xEA5A,0x0A63,0x095B,0xE95A,0xEA5A,0x0953,0xCA5A,0xE95A,0xE95A,0x085B,0xE95A,0x0A5B,0xE95A,0xE95A,0xE85A,0xC95A,0xE85A,0xC95A,0xE952,}, +{0x48A4,0x47A4,0x06A4,0x468B,0xC57A,0x446A,0x4562,0x065A,0xE641,0x474A,0x674A,0xA732,0x4B43,0x4C53,0x8A3A,0xAA52,0xAC32,0xAA3A,0x2832,0x6932,0x082A,0x062A,0xC621,0xC519,0xA419,0xC429,0xC431,0xC421,0xA631,0xC529,0x8429,0x8429,0x8329,0xC221,0x8221,0x6129,0x2119,0x0019,0xA842,0x5374,0x4E3A,0x2C11,0x8908,0x4610,0x2510,0x4308,0x2210,0x4100,0x2000,0x0000,0x6000,0x491A,0x3133,0xD322,0xB31A,0xB51A,0x341A,0xF321,0x121A,0xF311,0xCF11,0xB853,0x5E74,0x9C5B,0x383A,0xF208,0xAB00,0x6800,0x4700,0x6700,0x0D09,0xD008,0x8B08,0x2600,0x4200,0x2100,0x6500,0x8600,0xA708,0x8800,0x8900,0x6900,0x4900,0xAB08,0xAC10,0xC908,0xCC08,0xED08,0xAE08,0xEE00,0xEF08,0xCF10,0x3011,0xCE08,0xAD08,0xD218,0xCF08,0x5019,0xED10,0x1019,0xB010,0x3419,0x3611,0x3611,0x5709,0x5919,0x7A19,0x1E32,0xFB19,0x1D22,0xFE21,0xDC21,0x3811,0xF410,0xD308,0xB000,0xAE00,0xAB00,0x8A00,0x8A00,0x6708,0x6700,0x8800,0x8700,0x8A08,0xAD08,0xAC08,0xCF10,0xD010,0xAF08,0xAE08,0xCD08,0xED00,0x3309,0xF000,0x8B00,0x6900,0x6A08,0x6B08,0x2D08,0xF610,0x5511,0xB000,0x6F08,0x6B08,0x6D08,0xCF10,0x6C10,0x5921,0xD519,0x6708,0xEE00,0xD000,0xCC10,0x6810,0x6A08,0x8C08,0xB010,0x1621,0xE908,0x8608,0x6400,0x2308,0x4100,0x0000,0x0008,0x0008,0x0028,0x0020,0x0028,0x0038,0x0038,0x0040,0x0040,0x0048,0x0050,0x0050,0x0058,0x0058,0x0060,0x0068,0x0068,0x0070,0x0068,0x0070,0x0078,0x0078,0x0078,0x0078,0x0078,0x0080,0x0080,0x0080,0x0080,0x2080,0x4078,0x6078,0xA078,0x0071,0x4269,0xE669,0xA862,0x087B,0x03BA,0x40D9,0x00D9,0xC0D8,0x80D0,0x60D8,0x80E0,0xA0E0,0xC0E8,0xE0E0,0x00D9,0x20D9,0x80D9,0xC0D9,0xA0D9,0x61D1,0xA982,0x095B,0x095B,0x095B,0xEA52,0xEA5A,0xE95A,0xCA52,0xE952,0xE95A,0x095B,0x0953,0xC95A,0xE95A,0xC95A,0xC95A,0xE852,0xE95A,0xC952,0xE952,0xE852,}, +{0xAEDC,0x8ECC,0x2DB4,0x8B9B,0xC982,0x4772,0xE571,0x2762,0xC851,0x8641,0x4842,0x8F6B,0xEB52,0x2842,0xE949,0xE739,0x093A,0xE839,0x493A,0x4732,0x6832,0x2932,0xE521,0xC521,0xC521,0xC529,0x6529,0xC421,0xC529,0xA231,0x2329,0x8329,0x4229,0x4229,0x2221,0xC128,0xE020,0xC018,0xC120,0x8218,0x4110,0x4010,0x2018,0x0018,0x0010,0x0008,0x0008,0x0008,0x2000,0x6000,0x4A23,0x933B,0xF33A,0xF23A,0x9322,0x3312,0x101A,0x5522,0x5322,0x331A,0x3132,0x1632,0x7511,0x3309,0xD108,0x8C08,0x6708,0xE700,0x5019,0x5419,0xB010,0x6800,0x8400,0x6300,0x6300,0xC708,0xA808,0xC608,0xA600,0xAA08,0x8800,0x8A00,0x4D00,0x4B00,0x8B08,0xAA10,0x0D11,0xEE08,0x8D10,0xF010,0xD308,0x3219,0xEF08,0xAA00,0xCB00,0x3219,0xF310,0xF110,0x5211,0x0D09,0x3311,0x1511,0x5919,0x9921,0x9911,0x7911,0xBB19,0x1D2A,0xBC29,0xDA19,0x1D22,0x7B19,0x1611,0xF610,0xD408,0xF208,0xB110,0xD008,0x8C08,0x8C08,0x6A00,0x6A00,0x8900,0xAA08,0x8B00,0x8D08,0x1019,0xCC08,0xEE10,0xD010,0xAE10,0xCF08,0x1511,0x7911,0xF208,0x8C00,0x6A00,0x4808,0x2800,0x4D00,0xAF08,0xAE00,0x4D00,0x6E00,0x6A08,0x6C08,0xCF10,0x6908,0xF420,0x7529,0x6708,0x4808,0x8B08,0x6A10,0x6800,0x6C08,0x8E10,0x8F08,0xB110,0xCF08,0x6808,0x8500,0x2408,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0010,0x0020,0x0030,0x0030,0x0038,0x0040,0x0048,0x0048,0x0050,0x0050,0x0060,0x0058,0x0060,0x0068,0x0060,0x0060,0x0068,0x0070,0x0070,0x2070,0x2068,0x4078,0x2078,0x4070,0x8070,0xC160,0x2369,0xC569,0x666A,0xC96A,0xA85A,0xC962,0x0A63,0x296B,0x42B2,0x40D1,0x00D1,0xC0D8,0x80D8,0x80E0,0x23E9,0xC0E0,0xC0E0,0x00D9,0x20D9,0x60D9,0xA0D9,0xE0D9,0xA0D9,0xA3B9,0xC962,0x0A5B,0xE95A,0xEA62,0x0A5B,0xE952,0xEA52,0xE952,0x095B,0x095B,0xE85A,0x085B,0xE95A,0x095B,0xCA5A,0xC952,0xE85A,0xE952,0xC94A,0xE952,0xC952,}, +{0x8FEC,0x6FDC,0x0EBC,0x8C9B,0xEA7A,0x486A,0xC759,0xC651,0xA749,0x6639,0x6629,0x8731,0x2421,0x6431,0xA631,0xE739,0x0842,0xC739,0x082A,0x8A3A,0x8A32,0x282A,0x672A,0x682A,0xE721,0xA621,0x8421,0x052A,0xC431,0x6141,0x8339,0x6331,0xC238,0xC230,0xA028,0xC028,0xC020,0xA020,0x4020,0x2010,0x2010,0x2010,0x0018,0x0010,0x0008,0x0008,0x0000,0x2008,0xC200,0x6E23,0x9844,0xD93B,0x563B,0x5733,0xD833,0x572B,0x5532,0xF219,0x1012,0xEF11,0x6B11,0xEA00,0xEA10,0xA600,0x8400,0x0701,0x6D19,0x7219,0x1111,0x8B00,0x8600,0xC808,0xA600,0xC700,0x0B09,0xEB10,0xEA10,0xE808,0xE808,0xE908,0xCA00,0x6A00,0x8C08,0x6E08,0xAA00,0x4E21,0x2E11,0xCD08,0xCC08,0x1211,0xD108,0x1111,0x0F09,0x7321,0x7521,0xF210,0x5619,0x1519,0x5011,0x2F01,0x5311,0x3619,0xFB21,0xFC29,0x1B22,0xDB21,0x7E42,0x3D32,0xFC21,0xFD29,0x7A19,0x3719,0x3709,0xF608,0xF410,0x1209,0xB000,0x9008,0xD000,0xAE08,0x8C00,0x8C00,0x8A00,0x8A00,0xAF00,0x8B08,0x8D08,0xF010,0xCF08,0xAE08,0xD008,0xB308,0x7919,0xBC19,0xF408,0x8F00,0x4D00,0x4900,0x4700,0x4A00,0x4E08,0x6900,0x2D08,0x6D08,0x4B10,0x6C10,0x8D10,0x8708,0x8D08,0xCF18,0x8700,0x4608,0x4708,0x4700,0x4800,0x6D08,0xAF08,0x8F10,0x8C08,0xF010,0xA908,0x8600,0x4508,0x2200,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0008,0x0010,0x0018,0x0020,0x0028,0x0030,0x0040,0x0048,0x0048,0x0050,0x0050,0x0050,0x0050,0x2058,0x2060,0x2060,0x4060,0x8058,0xA250,0xA350,0xC550,0xE840,0x4D39,0xAB39,0x6952,0x0B6B,0x4B6B,0x2B6B,0x2A63,0xEA72,0x2A6B,0x2973,0x63B2,0x40C1,0x00D1,0xE0E0,0xC0E0,0xC0E0,0xC0E8,0xE0E0,0x00D9,0x40D9,0x60E1,0xA0D9,0x00DA,0x00DA,0xC0D9,0x469A,0xE95A,0xEA5A,0xEA5A,0xE95A,0xEA5A,0xE95A,0xEA52,0xEA52,0xE952,0xE95A,0xE952,0xE95A,0xC85A,0xE852,0xC952,0xC95A,0xC95A,0xE852,0xC952,0xE952,0xC952,}, +{0xCCDB,0xEDC3,0xABB3,0x6A9B,0xC87A,0x6872,0xE759,0xA549,0x6531,0x2531,0x2429,0x6431,0x6431,0xC641,0xA739,0xE841,0xC639,0xCA3A,0xAB3A,0x4A3A,0xE729,0x8922,0x6B32,0xA92A,0x4722,0x0622,0x4732,0xC529,0xA229,0xE431,0x8439,0xE228,0xA138,0x8130,0xA030,0xA128,0xA028,0x6020,0x2010,0x2018,0x2010,0x0018,0x0018,0x0008,0x0008,0x0000,0x0008,0x4509,0xF43B,0x1D65,0x3F6D,0xFF6C,0x5D54,0xB72B,0xF52B,0x2E23,0x2C12,0xE81A,0x280A,0x0A12,0x0B1A,0x6911,0x0909,0x0809,0x6F11,0xB411,0x3319,0xCC08,0xA700,0xEA10,0x0B01,0x0B09,0xEB08,0x0C09,0x0D11,0x0D19,0xC908,0x2909,0x4A19,0xCA10,0xC900,0xAB08,0x8A00,0x8C08,0xAA00,0xCE08,0x3019,0xF010,0xF010,0x1009,0x5411,0x1109,0xF619,0x3419,0x5619,0x3619,0x1311,0x7619,0x7511,0x9621,0x5419,0xB719,0x3C22,0x3C22,0xDB21,0xFA19,0xBC19,0x9B19,0x9B21,0x1719,0xF610,0xD408,0x3509,0x3609,0x5609,0xF308,0xF208,0xAF08,0xF408,0xAF00,0xAE00,0xAD00,0x8B00,0x8908,0x8B00,0x8C08,0xAB08,0xAC08,0xD010,0xB010,0x9000,0x3709,0x9A19,0x9A11,0xD200,0x8D00,0x6E00,0x6A00,0x4700,0x4800,0x4900,0x4800,0x4E08,0x6E10,0x4C08,0x8C08,0x4600,0x4708,0x8800,0x8900,0x6608,0x4608,0x4900,0x4400,0x2600,0x4D08,0x8F00,0x6F08,0x8B08,0xAA08,0x8908,0x6908,0x4900,0x2608,0x2100,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0008,0x0008,0x0008,0x0010,0x2018,0x2020,0x2018,0x2018,0x4020,0x6228,0xA220,0xE220,0xE520,0xE820,0x0921,0x4A21,0x6C21,0xAF31,0x0D4A,0xAA6A,0x4A6B,0x4B63,0x4A6B,0x2B73,0x4A6B,0x4B6B,0x296B,0xA4AA,0x80C9,0x00D1,0xE0E0,0xC0E0,0x01E9,0x20E1,0x20E1,0x40D9,0x60E1,0x80E9,0x20E2,0x60E2,0x20DA,0xE3C9,0x897A,0xE952,0x0953,0xE95A,0xE952,0xE95A,0xE95A,0xE952,0xE95A,0xE952,0xC952,0x095B,0xC952,0xE95A,0xC852,0xCA52,0xC95A,0xC952,0xE952,0xC952,0xC95A,0xC852,}, +{0x28CB,0x4ACB,0xAABB,0xCAAB,0x8A9B,0xEA7A,0x4962,0xE759,0xA541,0x6541,0x6551,0x8549,0x8651,0x8541,0xA541,0xA449,0x0752,0xAA52,0xAA4A,0x893A,0xCB3A,0xAC32,0x2A2A,0x892A,0xEA3A,0x8C32,0xA519,0x8319,0xC629,0x6421,0x4229,0xE230,0xC040,0xE138,0xE230,0x8130,0x2028,0x4020,0x4020,0x4010,0x4018,0x2020,0x2010,0x0008,0x0008,0x2000,0x0E33,0x5B6D,0x7F75,0x3F85,0xDE74,0x9953,0xB22A,0x4C22,0x4A2A,0x8A2A,0x2C2B,0x2E33,0x6F32,0xCC11,0x0C1A,0xAD11,0x121A,0x3522,0x7419,0x1009,0xC910,0x2A09,0x7019,0x2E11,0x2F21,0x2C11,0x4C11,0x2C11,0x0A09,0xEA00,0x0A11,0x2C19,0xCA10,0xE810,0xCA10,0xAA08,0xAE08,0xCD08,0xF110,0xCF10,0x5219,0x1211,0x3519,0xF408,0x3511,0x1611,0x7411,0x9419,0x3209,0xD719,0xD819,0x7709,0xB921,0x1822,0xB729,0x1822,0x7D2A,0x5611,0xD711,0xB921,0x9819,0x5709,0x3919,0x3509,0xF308,0x1419,0xF410,0x1709,0x1811,0xB408,0xCF00,0xD510,0xB208,0xB008,0xAF08,0xAD00,0xAC08,0xAA00,0xAA08,0x8A00,0x8C08,0xAB08,0x8C08,0xD108,0x9208,0x3811,0x7C19,0x3911,0xB208,0xAE00,0x6D08,0x4B00,0x4700,0x4800,0x2A00,0x4900,0x4D00,0x4D00,0x2B00,0x4B08,0x4508,0x6408,0x4700,0x6800,0x6600,0x2608,0x4508,0x4300,0x4408,0x4E08,0x9100,0x9208,0x8A00,0x8708,0x8800,0x8A00,0x4C08,0x6900,0x6300,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x2008,0x4000,0x4008,0x6208,0x8418,0xA410,0xE310,0x0719,0x0921,0x4921,0x8D21,0xCB31,0x0D32,0x4A4A,0xEB62,0x6A63,0x4B6B,0x6A63,0x4A63,0x4963,0x2B63,0x2963,0xC5AA,0xA0C9,0x40D1,0x20D9,0xE0E0,0xE0E0,0x00D9,0x40E1,0x40D9,0x80E1,0xC0D9,0x20DA,0x80E2,0x00DA,0x27A2,0x0A63,0xE95A,0xE95A,0xE95A,0xE952,0xE95A,0xEA5A,0xCA5A,0xE952,0xE952,0xEA5A,0xE95A,0xE95A,0xC95A,0xC952,0xA852,0xC962,0xC85A,0xC95A,0xE952,0xC95A,0xC952,}, +{0x89EB,0x0BEC,0x4EEC,0x6FDC,0x2ECC,0x8DB3,0xCA9A,0x289A,0xA691,0x6589,0x4471,0x6561,0x8571,0x4461,0x4361,0xA471,0x4672,0xA87A,0xC962,0xAB62,0xAA4A,0x6A3A,0x8A32,0x0C3B,0x492A,0x6411,0xA519,0x6729,0x4419,0x6221,0x4229,0x4149,0x6241,0x4339,0xC130,0x4030,0x4028,0x6020,0x2018,0xA010,0x8018,0x4010,0x2010,0x2008,0xC619,0xF35B,0x1C6D,0x7D64,0x7953,0x1332,0x2B09,0x8500,0x8300,0xE308,0x0722,0xCB32,0xCD2A,0x2B1A,0x0F1A,0x7222,0x5222,0x5022,0x1222,0xB321,0x3029,0xEA08,0x9119,0xF521,0xB311,0x5119,0xEA18,0x4B11,0x6E21,0x2C19,0x0A11,0x2901,0x2B11,0xC908,0xE910,0xE918,0x0A19,0xCB18,0xEC10,0x0F11,0xF318,0xF008,0x1111,0x3319,0x5411,0x7711,0x3409,0x7411,0x5511,0x3111,0xF829,0x1B32,0x5B2A,0x1A22,0xFA21,0xFB29,0xFB29,0xD929,0x5819,0xFA21,0xFA21,0x5619,0x7519,0x1411,0xD500,0xF608,0xF608,0xCF08,0xB310,0xF710,0xB100,0xD400,0x1811,0xF618,0xCD00,0xB008,0xAF08,0xCE00,0xCC00,0xCC00,0xC908,0x8800,0x4808,0x6C00,0x8D08,0x8D00,0x9310,0x1919,0x3A19,0xF708,0xB200,0x9008,0x4F00,0x4C00,0x8800,0x6A00,0x4A00,0x8A00,0x8B00,0x4C08,0x4900,0x4A08,0x4508,0x4600,0x4700,0x4708,0x4608,0x2508,0x4408,0x4208,0x6300,0x4C08,0x9208,0x9208,0x8C08,0x6608,0x4800,0x6908,0x4908,0x6A00,0x6400,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4008,0x4010,0x4008,0x4108,0x4308,0x8410,0xC508,0xE510,0x2819,0x4A31,0x8A29,0xAD29,0x0B42,0x6B42,0xAA5A,0x2B6B,0x4B6B,0x4B73,0x4B63,0x4A63,0x4B6B,0x2B63,0x2963,0xC4A2,0xE0C9,0x60D9,0x40E1,0x20E1,0x40E1,0x40D9,0x60E1,0x80E1,0xC0D9,0xE0D9,0x40DA,0x80D2,0x02CA,0x8872,0xEA5A,0x095B,0x095B,0xEA5A,0xE95A,0xE95A,0xE95A,0xE95A,0xE952,0xE95A,0xE962,0xC85A,0xC852,0xC952,0xC95A,0xC952,0xEA5A,0xE952,0xC952,0xC852,0xC852,0xC952,}, +{0x6FFC,0xB0FC,0xD0FC,0x8FFC,0x6FEC,0xADD3,0xCAC2,0x28B2,0x86A1,0x6491,0x2289,0x4399,0x83A1,0xA4A1,0xC699,0xC599,0x0592,0x2592,0x877A,0x8862,0xA84A,0x273A,0x2632,0xC621,0x6311,0x0522,0x8521,0x2311,0xC219,0xA219,0xA129,0x8239,0x4231,0xA120,0x6020,0x6020,0xA110,0x8218,0xC308,0xC310,0xC118,0xA000,0x2311,0xCA32,0xB153,0x1253,0x4C11,0x6700,0x4400,0x2100,0x2100,0x4200,0xE608,0x6721,0xE919,0x0B2A,0x6F22,0xB122,0x7522,0x342A,0x2F12,0xCE11,0xD121,0x4F19,0x8C11,0x762A,0x582A,0xD629,0x5119,0x0A09,0x6D11,0x6F21,0x8D19,0x4E19,0x0811,0x0A19,0xC708,0xE910,0x0709,0x0811,0xE818,0x2B11,0x0F11,0x3111,0xD010,0x1519,0xF108,0x3309,0x7519,0x1609,0x5509,0x3109,0x7311,0x7621,0xFA29,0x3C3A,0x3C32,0x3B22,0xD921,0xD921,0xFC29,0xD919,0xB819,0xB921,0x7711,0x3719,0xD308,0xD008,0xF310,0xB308,0xB208,0x3409,0xF510,0x8F00,0xF708,0x3509,0xF708,0xF200,0xF418,0xF208,0xD000,0xB008,0xF108,0x3109,0x8B08,0x8800,0x6808,0x6900,0xAD08,0xAC00,0xD508,0x1911,0xD818,0xD208,0xB100,0xB000,0x8D08,0x6F00,0x4B00,0x4A00,0x6C00,0xAE08,0xCF00,0x8B00,0x6800,0x4808,0x4608,0x2608,0x4400,0x2700,0x2600,0x2300,0x0400,0x2200,0x4300,0x2900,0x6D08,0xAF08,0x9110,0x6B08,0x6800,0x4810,0x4608,0x6500,0x4300,0x0100,0x2000,0x0000,0x0000,0x0000,0x0008,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4008,0x4010,0x4008,0x4108,0x6308,0x6610,0xC808,0x0709,0x2929,0x8A39,0xAA31,0xCC31,0x2A52,0xAB52,0xCB6A,0x4B6B,0x4B6B,0x4B63,0x4A6B,0x4B6B,0x2B63,0x2B6B,0x296B,0xE4A2,0x00CA,0xA0D1,0x80E1,0x60E1,0x40E1,0x60D9,0xA0E1,0xA0D9,0xC0D9,0x40DA,0xA0DA,0x40DA,0x26AA,0xC962,0xEA5A,0xE95A,0xE95A,0xE95A,0xC95A,0xE95A,0xC952,0xE95A,0xC95A,0xE952,0xC95A,0xC852,0xE85A,0xC95A,0xC952,0xCA52,0xCA52,0xE94A,0xC952,0xA952,0xC952,0xA952,}, +{0xD1FC,0x11FD,0x11FD,0xCFF4,0x4EDC,0x8BC3,0xA8B2,0x27BA,0xA5C9,0x84D1,0x84D9,0xC6E1,0x05E2,0x26EA,0xC5E1,0xC4C9,0x06BA,0x459A,0x6682,0x2672,0x0452,0xC439,0x8331,0x8221,0x6329,0x8119,0x6121,0x8221,0x8019,0x6019,0x0119,0xA010,0x6008,0x4008,0x4008,0x4008,0x4100,0x8110,0x8208,0x8210,0xA210,0xA529,0x6E6B,0xA621,0xA308,0x8200,0x4100,0x4000,0x4000,0x8200,0x0511,0x2709,0xE918,0x0719,0x6911,0x2B2A,0x2E2A,0x8D11,0x8B09,0x701A,0xB42A,0x9129,0x0A09,0xCE21,0x773A,0xDA32,0x7832,0x7019,0x4C19,0x9129,0x9019,0x8C21,0xD121,0x0A09,0x6F19,0xEB10,0x0D19,0xC910,0xC710,0xC710,0x0819,0x6D19,0x3211,0x5011,0x1211,0x1011,0x1419,0x7411,0x5511,0x1409,0x3409,0xB821,0xD921,0xB929,0x9819,0xF821,0x9D42,0x1B32,0xB921,0x1A1A,0xFB19,0x7519,0x7619,0x1111,0x3611,0x1309,0xB410,0x8F08,0xCF00,0x1009,0xF008,0x3509,0xAF00,0x1511,0x3919,0x5819,0xF308,0xF408,0xF508,0x1411,0xF208,0xF208,0x7519,0x1209,0xAC00,0xAA08,0xA908,0xC900,0xAA00,0xCF00,0x1611,0x1911,0xF818,0xD008,0x9008,0x9100,0x6E00,0x7208,0x4C08,0x8B08,0xB000,0xF210,0xF110,0x6C00,0x2A00,0x4808,0x2808,0x2600,0x4700,0x2808,0x0708,0x2500,0x4400,0x4400,0x4300,0x2700,0x4608,0x4B08,0x8F08,0xAF08,0x6B08,0x6608,0x4408,0x4300,0x4100,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0108,0x2008,0x4100,0x4008,0x6008,0x4008,0x6210,0x6508,0x6710,0xAB08,0xE918,0x4A29,0xCB41,0xEB31,0x2A42,0x8A5A,0x2B63,0x4B6B,0x4B73,0x6B6B,0x2B6B,0x4A73,0x2B6B,0x4B6B,0x4A63,0x2963,0x04A3,0x20D2,0xC0D1,0xA0E1,0x80E1,0x80E1,0xA0E1,0xC0D9,0xC0D9,0x00DA,0x80DA,0xE0E2,0x21D2,0x897A,0x0A5B,0x095B,0x0953,0x095B,0x095B,0xC95A,0xCA62,0xE962,0xE95A,0xC95A,0xE952,0xC952,0xE852,0xA952,0xE95A,0xE852,0xE852,0xA952,0xC95A,0xC852,0xC952,0xA952,0xC852,}, +{0x73FD,0x73FD,0x32FD,0xD0FC,0x4EFC,0x6BFB,0xC8F2,0x26FA,0x06FA,0x05FA,0x47FA,0x48FA,0x47FA,0x27F2,0xA5E9,0x63D9,0x63C1,0x82A9,0xC399,0x8489,0x6379,0x8361,0xA251,0xC239,0x6139,0x4029,0x4029,0xE028,0xA020,0x6018,0x2008,0x2000,0x2000,0x0000,0x0008,0x0000,0x2000,0x4000,0x0000,0x0000,0x2000,0x2008,0x4208,0x4108,0x6000,0x6110,0x6110,0xA100,0x2409,0x8619,0x6919,0x6911,0x4911,0xCD21,0x8C19,0x4719,0xE500,0xA821,0xB02A,0x9432,0x8E19,0x6B11,0x1022,0x1232,0x5532,0x7732,0xF429,0xF121,0xD221,0x2F19,0xB029,0xD231,0x4D19,0x9121,0x0E19,0x5019,0xCD10,0xED18,0xC908,0xC810,0x0A11,0x2A11,0x1019,0x3111,0x1119,0xEF10,0x3419,0x7721,0x7519,0x1411,0xB621,0x3B2A,0x1D32,0xB721,0x9619,0x5A2A,0x1A32,0xFB21,0x5D3A,0x3B2A,0x9719,0x7511,0x3211,0xF010,0xF210,0xD108,0x8F08,0xB008,0xB010,0xD108,0xD008,0xCF00,0xEC10,0x1419,0xF410,0x1311,0x1411,0x3411,0x5311,0x1211,0x5511,0xDA31,0x9721,0x1109,0xCE00,0xCD08,0xAB00,0xCA00,0x8900,0xAE00,0xD510,0xF500,0xD410,0x8E00,0x9100,0x8E00,0x4F08,0x7210,0x8E10,0xAC08,0xD210,0x3611,0xF208,0xAC00,0x4B00,0x6B08,0x4900,0x4600,0x2808,0x2600,0x2608,0x0808,0x4400,0x2700,0x2500,0x0700,0x2700,0x2708,0x4A08,0x6E08,0x6C08,0x6600,0x4408,0x4100,0x2100,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0008,0x2000,0x0000,0x0000,0x2000,0x2100,0x4100,0x4000,0x6008,0x6010,0x6008,0x6308,0x6500,0x8808,0xAC08,0x0B11,0x6A21,0xEA41,0x0A3A,0x4942,0xAA5A,0x6B6B,0x8B6B,0x6B73,0x6B73,0x6B73,0x4B6B,0x4A63,0x4A6B,0x4A63,0x4963,0x03B3,0x40D2,0x00DA,0xE0E1,0xC0E1,0xC0E1,0xE0D9,0x00E2,0x00DA,0x60DA,0xA0DA,0x80D2,0x45A2,0xEA5A,0x0A5B,0x095B,0xE95A,0xC95A,0xE95A,0xC95A,0xCA5A,0xC85A,0xC95A,0xC95A,0xCA5A,0xC952,0xE95A,0xA95A,0xC95A,0xC952,0xC852,0xA95A,0xA95A,0xC852,0xA952,0xC95A,0xC85A,}, +{0x74FD,0x33FD,0xB1FC,0x6FFC,0xECFB,0x29FB,0xE8FA,0xA8FA,0xA9FA,0xC8FA,0xE9FA,0x87FA,0x47FA,0xC6F9,0x83E9,0x01D9,0xE0C0,0x00C1,0x00B9,0xE0B0,0xC1A0,0xE298,0xE080,0xC068,0x6058,0x4048,0x2048,0x2048,0x0038,0x0028,0x0018,0x0010,0x0008,0x0008,0x0008,0x2000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0008,0x0000,0x0000,0x8110,0xC410,0xA308,0x2419,0x2511,0x8819,0xAD21,0x0911,0xC408,0x2709,0x2809,0xCB21,0x8C21,0x2911,0xCC21,0xD229,0x1232,0x342A,0x3332,0xF221,0x332A,0x1432,0x6F19,0x532A,0xD331,0x6C19,0xF531,0x2F19,0x6F21,0x4F19,0x4F19,0x0B09,0x0C19,0x0C09,0xA700,0x2B21,0xEB08,0x3111,0xEE10,0xB519,0x5621,0x7621,0x9619,0x7519,0x7319,0xD829,0xB929,0xD621,0x9819,0x7519,0xD621,0x1B2A,0x7719,0x7811,0x7709,0x3511,0x1519,0xF110,0xAE00,0x1211,0x8F08,0xD308,0xAD00,0x9108,0x9010,0x8D00,0x1019,0xED10,0xEF10,0x1511,0x5619,0x1519,0xF110,0x7711,0xFC29,0xFD31,0x7719,0x1211,0xF008,0xED08,0xAD08,0x8D08,0x8C08,0xEE00,0xD210,0x9110,0x8E08,0x8D00,0x7008,0x8F00,0x6D00,0x6F08,0x8F10,0xAE00,0xD208,0x3711,0xF308,0x6F00,0x6C08,0x6A00,0x6800,0x4800,0x2900,0x4400,0x2800,0x2508,0x4400,0x2700,0x2308,0x2700,0x2800,0x4300,0x4508,0x4608,0x6C08,0x6A00,0x4200,0x2100,0x2100,0x2000,0x0100,0x0000,0x0000,0x0008,0x0000,0x2000,0x0000,0x2000,0x0000,0x0000,0x2100,0x2108,0x4100,0x4100,0x4108,0x6008,0x6108,0x8308,0x6500,0x6808,0xAC10,0x4C11,0xCA29,0x2942,0x6942,0x895A,0x0B63,0x6C6B,0x6B6B,0x8B73,0x4B6B,0x4B6B,0x4A63,0x4B6B,0x4A63,0x4B63,0x4963,0x43B3,0x60D2,0x40DA,0x20EA,0xE0E1,0xE0E1,0x20DA,0x20DA,0x60DA,0xC0DA,0xC0DA,0x42C2,0x8872,0xEA5A,0xE952,0xE95A,0xE952,0xE95A,0xE85A,0xEA52,0xC952,0xC952,0xC862,0xA95A,0xCA52,0xC952,0xC952,0xC95A,0xA95A,0xC95A,0xA94A,0xA95A,0xA95A,0xA952,0xA952,0xC952,0xA952,}, +{0x13FD,0xB1FC,0x4EFC,0xCCFB,0x6BFB,0x49FB,0x29FB,0x0AFB,0x29FB,0x2AFB,0x0AFB,0xC9FA,0x05FA,0xA3F9,0x61F1,0x00D9,0x02D9,0xE1D0,0xC0D0,0x80B0,0x40B0,0x60A8,0x4098,0x0090,0x2078,0x0070,0x0060,0x0050,0x0040,0x0038,0x0030,0x0028,0x0010,0x0010,0x0010,0x0008,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0008,0x0000,0x0008,0x0008,0x0010,0x0008,0x4108,0xC418,0x8310,0xA308,0xC508,0x2711,0x6C11,0x2919,0xA808,0x8408,0x6809,0xAD19,0xF321,0xD329,0x1432,0xF131,0x302A,0x532A,0x8F19,0x9542,0x5732,0x8D19,0x352A,0x7119,0xD229,0x6F21,0x6F19,0x4E11,0x2F21,0x0E11,0xCE08,0x0B09,0xA808,0xE910,0xC908,0x5221,0x5419,0x5421,0xB521,0xB419,0x7719,0x5411,0xF418,0x3019,0xB929,0x7619,0xEF10,0x1211,0x3211,0x5419,0x5411,0x5719,0x3311,0xF508,0xF308,0xD108,0xAF00,0xF010,0xD108,0xF008,0x8D08,0x8E00,0xAE08,0xCC08,0xEB10,0x0F11,0x3219,0x5611,0xF208,0x5519,0xDB21,0x3E32,0x9921,0x5519,0x3519,0xF210,0xEF08,0x8D08,0x8C10,0x8C08,0xAC08,0xAC08,0xCC10,0xAB00,0x6A00,0x6B08,0x8E08,0xAD10,0x6B08,0x8E08,0x8F00,0xB500,0x1811,0xD508,0x5008,0x4D00,0x2A00,0x4B00,0x4A00,0x4800,0x4700,0x2608,0x4408,0x4408,0x2700,0x4108,0x0608,0x2908,0x4400,0x2508,0x6508,0x8A08,0x8D08,0x6400,0x2100,0x2100,0x4100,0x0100,0x0000,0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2108,0x0210,0x2100,0x6100,0x4100,0x4108,0x6110,0x6208,0x8408,0x8608,0x6910,0xCD10,0x4C19,0xCA31,0x4A4A,0xAA5A,0xEA62,0x4C6B,0x6C6B,0x6B73,0x6B6B,0x4B6B,0x6B6B,0x6B6B,0x2B6B,0x2B6B,0x2A63,0x4973,0x41BB,0xA0DA,0x60E2,0x60EA,0x20E2,0x00E2,0x60E2,0x60E2,0xA0DA,0x00E3,0xC0D2,0xA59A,0xE962,0xEA5A,0x095B,0xE95A,0xE95A,0xE95A,0xEA52,0xE952,0xE95A,0xC95A,0xC952,0xC952,0xCA5A,0xCA5A,0xC952,0xA95A,0xA95A,0xC952,0xA952,0xA952,0xA952,0xA952,0xA852,0xA852,0xA952,}, +{0xB0FC,0x2EFC,0xCCFB,0x6AFB,0x4AFB,0x4AFB,0x4AFB,0x2BFB,0x6BFB,0x4BFB,0xE8FA,0x67FA,0xE4F9,0xC4F9,0x62F1,0x21E9,0x01F1,0x80E0,0xA0C8,0xA0B0,0x80B8,0xA0B0,0x20B0,0x40A0,0x4090,0x0080,0x0068,0x0058,0x0050,0x0048,0x0040,0x0038,0x0028,0x0020,0x0018,0x2008,0x0008,0x0000,0x0000,0x0000,0x0008,0x0000,0x0000,0x0000,0x0008,0x0008,0x0008,0x0010,0x0000,0x0008,0x0000,0x0000,0x2108,0x6310,0x8408,0x2200,0x2100,0xA300,0x4609,0x2909,0xCE11,0x111A,0x3222,0x1332,0xD029,0x1532,0x4F19,0x722A,0x943A,0x6F19,0x3232,0xB321,0xB121,0x4E21,0xAE19,0x9121,0x8F19,0x2E19,0x0F19,0x0D19,0xCC08,0xEA08,0xA708,0x0C21,0x0F19,0xD018,0x3021,0x7319,0xD621,0xD719,0x7511,0xAD08,0x7329,0x9721,0xEF08,0x1109,0x3411,0x1011,0xCE08,0x3619,0x3411,0x1309,0x1511,0xD208,0xD108,0xD008,0xAF08,0xD108,0x1211,0xAF08,0x8F08,0x8E00,0xAA00,0xAA10,0xF110,0x3419,0xF108,0x3511,0xDA29,0x3E2A,0x9A19,0x3719,0x3619,0x3619,0xF418,0xF108,0xCF08,0x8E10,0x8B00,0x6B00,0x6A00,0x6900,0x8700,0x6900,0x8808,0x4A08,0x6C08,0x6800,0x8D08,0x9108,0xB508,0x1911,0xB608,0x7000,0x4C00,0x4800,0x2C00,0x2900,0x2500,0x2700,0x2508,0x2608,0x4400,0x2400,0x2100,0x2400,0x2A00,0x2508,0x2500,0x4508,0x2708,0x2B08,0x2800,0x2200,0x2200,0x2000,0x2000,0x2000,0x2008,0x2000,0x4000,0x2000,0x2000,0x2000,0x4000,0x0308,0x2308,0x2100,0x4100,0x4300,0x6208,0x8310,0x8410,0xA508,0x8608,0x8A10,0xCE10,0x6B21,0xEA31,0x4A52,0xCA62,0x2B6B,0x4C73,0x6B73,0x6B73,0x6B6B,0x4B6B,0x4B73,0x4B6B,0x4B6B,0x4B63,0x6A6B,0x4973,0x81C3,0xE0D2,0xA0E2,0xC0EA,0x40E2,0x40E2,0x80E2,0xA0DA,0xE0DA,0x00D3,0xA3BA,0xE972,0x0A63,0xEA5A,0x095B,0x095B,0xE95A,0xE952,0xE95A,0xE95A,0xC95A,0xC95A,0xE952,0xE95A,0xC952,0xC95A,0xE852,0xC95A,0xC952,0xA952,0x895A,0xC952,0xC852,0xC952,0x8952,0xA852,0xC852,}, +{0x4FFC,0xEDFB,0x8BFB,0x69FB,0x6AFB,0x69FB,0x8AFB,0x6BFB,0x6BFB,0x0AFB,0xE8FA,0xE8FA,0xA9FA,0xE4F9,0x63F9,0xE1F8,0xC0F0,0x80E0,0x80D0,0x80D0,0xA0C8,0xA0C0,0x80B8,0x60A8,0x2098,0x0090,0x2080,0x0070,0x0060,0x0058,0x0058,0x0048,0x0040,0x0040,0x2020,0x2010,0x2008,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0008,0x0008,0x0000,0x0008,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x6108,0x4200,0xC410,0xAA21,0xCE19,0x2F22,0x4D11,0xD119,0x0E11,0x1322,0x5432,0xAD21,0x8E29,0xB129,0xD129,0x9231,0xAD21,0xCE29,0x6E11,0xF219,0x9221,0x5121,0x2F19,0x0D11,0x8908,0xC708,0xA908,0x0B19,0x0C11,0x1019,0x9429,0xB629,0x7311,0x3109,0x3211,0x1009,0xF208,0x0F11,0x3109,0x1209,0x1009,0x3109,0xF110,0xD008,0xF110,0xB008,0x1411,0xCF00,0xF108,0xF210,0x9108,0xCD00,0xCF00,0x4D08,0x6E00,0x8C00,0xAC08,0x5519,0xF210,0x1209,0x7809,0xFD29,0xFB21,0x7719,0xF418,0x1511,0xF510,0xF310,0xF008,0xB100,0xAE00,0x8C00,0x6D00,0x6A00,0x2900,0x4700,0x4600,0x4808,0x2908,0x6D08,0x8E00,0x8E00,0x9108,0xD508,0xD610,0xD408,0x6F00,0x4B00,0x4900,0x2B10,0x2700,0x2408,0x2600,0x4308,0x2508,0x4308,0x2200,0x0300,0x2400,0x4800,0x4400,0x2500,0x2608,0x4400,0x4500,0x2500,0x4200,0x2200,0x2100,0x2100,0x0000,0x2000,0x4000,0x2008,0x2008,0x2000,0x2000,0x4100,0x4308,0x4308,0x4000,0x2200,0x4300,0x6300,0x8408,0xA510,0xC600,0x8610,0xAA08,0xED10,0x6A29,0x0942,0x8952,0x0B63,0x4C6B,0x6C6B,0x6B6B,0x6B6B,0x6B6B,0x6B6B,0x4B6B,0x4A63,0x4B63,0x4B6B,0x6A6B,0x698B,0xA0CB,0x00DB,0xE0E2,0xE0EA,0xA0E2,0xA0E2,0xE0E2,0x00D3,0x40D3,0xC1D2,0x878A,0x0A5B,0xE95A,0x095B,0xE95A,0xE952,0xEA5A,0xE85A,0xE952,0xC95A,0xC952,0xC952,0xC952,0xC95A,0xC952,0xC95A,0xC952,0xA952,0xA94A,0xA95A,0xA95A,0xC952,0xA852,0xA852,0xA952,0xA952,0xA852,}, +{0xECFB,0x8BFB,0x69FB,0x69FB,0x6AFB,0x6AFB,0x8BFB,0xACFB,0x2AFB,0x0AFB,0x0AFB,0x4BFB,0x88FA,0x25FA,0x83F9,0x01F9,0xE0F0,0xE0F0,0xC0E0,0xA0E0,0xA0E0,0x80D0,0x80C8,0x80B0,0x60A8,0x20A0,0x4098,0x2080,0x0078,0x2070,0x0060,0x0050,0x0058,0x0048,0x2030,0x4018,0x2008,0x4008,0x2008,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x8308,0xA618,0x8608,0x2B11,0x0A01,0xF221,0x542A,0xAD19,0xF021,0x7021,0x0D11,0x5019,0x6D21,0x4E21,0xD021,0xD031,0xF029,0x7011,0x7221,0x0E11,0xEE10,0xEC08,0xCD10,0xC908,0x8708,0xEA10,0x0B21,0x3019,0x0F19,0x5221,0x4F01,0x3419,0x3209,0x8B08,0xCA08,0x3109,0x3211,0x0F11,0xF110,0xAE08,0xAB00,0xCE08,0x0F11,0xCF00,0x0F11,0x5211,0x1219,0xD008,0x8E00,0xAD00,0x8B00,0xAD00,0x9000,0xB308,0x1411,0xD010,0x5611,0xDA19,0x7B21,0xF310,0x1619,0xF510,0x1311,0xD210,0x9310,0xB108,0xAF08,0x8F00,0xAF00,0x6B00,0x6B00,0x4900,0x2500,0x4600,0x6608,0x4908,0x4900,0x6F08,0x8E00,0x9008,0xB610,0xF508,0xB200,0x6F00,0x4B00,0x4900,0x2800,0x2500,0x4400,0x4308,0x2308,0x2308,0x2200,0x2100,0x0308,0x2510,0x4400,0x4400,0x2300,0x2408,0x2500,0x2400,0x2200,0x2200,0x2200,0x0100,0x2100,0x2100,0x4100,0x4000,0x2008,0x4100,0x2000,0x4000,0x4200,0x4308,0x4208,0x2100,0x4300,0x4400,0x6300,0x8308,0x8610,0xC508,0xC610,0xC808,0x2B11,0xA831,0x2842,0xAA5A,0x0B6B,0x4C73,0x6C73,0x8B6B,0x6B6B,0x8C6B,0x6B6B,0x6B6B,0x6A6B,0x2B6B,0x6B6B,0x4A63,0xA79B,0xA0D3,0x40D3,0x00E3,0x20E3,0x00E3,0xE0DA,0x00DB,0x40D3,0x20CB,0xA6AA,0xEA62,0x0A5B,0x095B,0xEA5A,0xCA62,0xE952,0xE95A,0xE95A,0xE95A,0xC85A,0xE952,0xC952,0xC952,0xC952,0xC952,0xC952,0xA962,0xA952,0xA94A,0xC852,0xC952,0xA852,0xA95A,0xA952,0x8852,0xC952,0xA952,}, +{0xCBFB,0x8AFB,0x49FB,0x29FB,0x4AFB,0xABFB,0xACFB,0x2AFB,0x4AFB,0x6BFB,0x6BFB,0x4CFB,0xC8FA,0x47FA,0xE3F9,0x83F9,0x22F9,0x00F9,0xE0F8,0xC0F8,0xA0F0,0xA0E0,0x60D8,0xA0C8,0x80C0,0x60B8,0x60A8,0x6098,0x2090,0x4088,0x2080,0x2078,0x2070,0x4058,0x4048,0x4028,0x4018,0x4010,0x2110,0x2108,0x2000,0x0000,0x0008,0x0100,0x0100,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x4308,0xA510,0xAB21,0xCE21,0xAA11,0xCF21,0x4F11,0xEB08,0x0E11,0xCA10,0x0D21,0x8F29,0x2F21,0x2D19,0xCF21,0x4F21,0xAB08,0x2D19,0xCF10,0xEE20,0xAA08,0xA808,0x8800,0x8708,0xC718,0xC918,0x0C19,0xCA10,0xB019,0x7219,0xCB00,0xA900,0xAA00,0xF108,0xCF08,0xAD08,0xCC08,0xEB10,0xCD08,0x0F11,0xAC08,0xCC08,0xCD08,0xCD10,0xCE18,0x8E08,0x6C00,0x8F00,0xCE00,0xD208,0xD400,0xF708,0x9208,0xF210,0x3511,0x3411,0xD108,0xF510,0xF418,0xF510,0xD410,0xB210,0x9108,0xB208,0xB008,0x8F08,0x8E08,0x8B00,0xAB00,0x4908,0x4608,0x4700,0x4600,0x6900,0x4900,0x8F00,0x6F08,0x5000,0xB300,0x9400,0x7000,0x4E00,0x2A00,0x0900,0x2700,0x4200,0x4200,0x4100,0x2100,0x2100,0x4100,0x2200,0x0300,0x2500,0x4300,0x4508,0x2300,0x0400,0x0500,0x4400,0x2200,0x2100,0x0100,0x2300,0x2200,0x0300,0x2300,0x4100,0x2108,0x2208,0x4100,0x4100,0x4208,0x4308,0x4100,0x2108,0x2300,0x2600,0x6400,0x6510,0xA710,0xE508,0xE610,0xE910,0x4919,0xC939,0x4952,0xCA5A,0x2B6B,0x4B73,0x6C73,0x8B6B,0x8C6B,0x6B6B,0x4B6B,0x8B6B,0x4B6B,0x4A6B,0x2A73,0x0A6B,0xE5B3,0xC0D3,0x60DB,0x40DB,0x40E3,0x20DB,0x00DB,0x00DB,0x40CB,0xE4B2,0xA97A,0xE962,0x0A5B,0xE95A,0xCA62,0xEA52,0xE952,0xE95A,0xE852,0xE952,0xE952,0xC852,0xC952,0xA952,0xA952,0xA95A,0xA952,0xC952,0xA952,0xA952,0xA952,0xA952,0xA952,0xA852,0x8952,0xA94A,0xA952,0xA84A,}, +{0xCBFB,0x69FB,0x49FB,0x49FB,0x8BFB,0xADFB,0x6BFB,0x4AFB,0x6BFB,0x6BFB,0x4AFB,0x2BFB,0x2AFB,0xC9FA,0x46FA,0xA4F9,0x42F9,0x21F9,0x01F9,0xE0F8,0xA0F8,0xA0F0,0x80E8,0xA0E8,0x80D8,0xC0C8,0x80C8,0x60B8,0x40B8,0x40A8,0x6098,0x4090,0x4080,0x6070,0x4068,0x4048,0x8028,0x6110,0x4110,0x4108,0x4108,0x2200,0x2200,0x2108,0x2100,0x0100,0x0100,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x4200,0xA410,0xA410,0x2919,0x2A11,0xC808,0xEB18,0xA910,0xEC18,0x4E21,0x0D21,0xC708,0x5021,0x0D19,0xC908,0x0E19,0xAD18,0xCF18,0x6908,0xAA08,0x6908,0x8708,0x8800,0x6608,0x8408,0x8508,0xE718,0x2B21,0x0C19,0xEA00,0xAA00,0xCD18,0xAD08,0x6D08,0x8C00,0xC900,0xA708,0xE910,0xCB10,0xEA08,0xCD08,0x8C08,0x6C00,0x8B08,0x6D00,0x8E08,0x8F00,0xD408,0xF408,0x1709,0xB608,0x9000,0xD108,0xF108,0xD110,0xF018,0xB310,0xF510,0x1711,0xB208,0x9008,0x8F08,0x9008,0xB108,0x8F00,0x8D08,0x6C08,0xAA08,0x4500,0x4608,0x2700,0x2600,0x2800,0x4C00,0x7000,0x6E08,0x4F08,0x9008,0x9100,0x6D00,0x2C00,0x2800,0x2800,0x2500,0x2300,0x2100,0x4000,0x2100,0x2000,0x2000,0x2100,0x4100,0x2200,0x4200,0x2300,0x2200,0x2300,0x2300,0x4400,0x4200,0x2200,0x2200,0x2200,0x0300,0x0400,0x2400,0x4100,0x4208,0x2210,0x2200,0x4200,0x4208,0x2200,0x4100,0x4200,0x2400,0x4600,0x6600,0x8610,0xC700,0xC610,0xE618,0x0921,0x6929,0xCB39,0x8A4A,0xCA62,0x4C63,0x6C6B,0x6C73,0x6C6B,0x8B6B,0x8B6B,0x4B6B,0x6B6B,0x6B6B,0x2B6B,0x4A6B,0x4A73,0x23C4,0x00D4,0xC0DB,0x80DB,0x80DB,0x60DB,0x40D3,0x20CB,0x21CB,0xC882,0xEA62,0x0A63,0x0963,0xE95A,0xEA5A,0xE95A,0xE95A,0xE95A,0xE95A,0xC952,0xC95A,0xC95A,0xC95A,0xC852,0xA952,0xC95A,0x895A,0xA952,0x8952,0xA95A,0xA952,0xC852,0xC852,0xA952,0xA952,0xA852,0x884A,0x884A,}, +{0xAAFB,0x4AFB,0x49FB,0x6AFB,0xACFB,0x8BFB,0x6AFB,0x8AFB,0x8CFB,0x8CFB,0x4CFB,0x2BFB,0xE9FA,0xA8FA,0x46FA,0x05FA,0xC4F9,0x83F9,0x83F9,0x22F9,0x21F9,0xE1F8,0xE1F8,0xE0F8,0xE0F0,0xE0E8,0xA0E0,0xA0C8,0x60C8,0x80C0,0x80B0,0x60B0,0x60A8,0x40A0,0x6090,0x8160,0xA130,0xA110,0x8110,0x6210,0x6318,0x6318,0x2318,0x2218,0x2210,0x0110,0x0108,0x0108,0x0100,0x0000,0x2000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0008,0x2110,0x0110,0x8518,0x0210,0x8618,0xC818,0xED20,0x6610,0x8A29,0x8B18,0x4200,0xA910,0x0E19,0xCE18,0x8808,0xAF18,0x6918,0x8B10,0xA908,0x6900,0x6508,0x6408,0x6300,0x8408,0xA410,0x0611,0xEA00,0x0D21,0xEB10,0x0F09,0xAB08,0x8808,0xA808,0x8608,0xEA08,0xCD08,0xF000,0xAE08,0x8F08,0x8F00,0x6F08,0xAC00,0xAD00,0x0F09,0xB010,0xD410,0xF508,0xB408,0x9308,0xAF08,0xAF08,0x6E08,0x8F08,0xF418,0xF408,0xD410,0xB208,0x8E08,0x9008,0x9008,0x8F08,0x6D08,0x8C08,0x6C00,0x4608,0x2600,0x2600,0x2700,0x2908,0x2B00,0x6D00,0x4E00,0x4B08,0x2A00,0x4B00,0x8D00,0x8A00,0x4908,0x0708,0x2400,0x0300,0x2200,0x2100,0x2100,0x2100,0x2000,0x2000,0x2100,0x2100,0x2200,0x2200,0x2200,0x2200,0x2300,0x2200,0x4308,0x2200,0x2200,0x2200,0x2200,0x2300,0x0600,0x2500,0x2300,0x4208,0x2208,0x2108,0x4100,0x4100,0x2200,0x2300,0x2300,0x2400,0x4600,0x6608,0xA808,0xC800,0xE710,0x0621,0x6821,0xCB31,0x0C42,0xAB4A,0xEB5A,0x4B63,0x8C6B,0x6B73,0x6C73,0x6C73,0x6B73,0x4C6B,0x4B73,0x6A6B,0x4A6B,0x4A6B,0x697B,0x82D4,0x40D4,0xE0D3,0xE0D3,0xE0D3,0x80D3,0x60CB,0x40CB,0xE59A,0xEA5A,0x0963,0x095B,0x0963,0x0953,0xEA52,0xEA5A,0xE95A,0xE95A,0xE95A,0xE852,0xC952,0xC952,0xC95A,0xC95A,0xC952,0xA95A,0xC952,0xA94A,0x8852,0xA85A,0xA952,0x895A,0x8952,0xA952,0xA84A,0x884A,0x8852,0x8952,}, +{0xAAFB,0x6AFB,0x49FB,0x6AFB,0x6AFB,0x89FB,0x8AFB,0x8AFB,0x8BFB,0x8CFB,0x4BFB,0x0AFB,0xE9FA,0xC8FA,0x87FA,0x47FA,0x05FA,0xC4F9,0xC4F9,0xA4F9,0xA4F9,0x83F9,0x42F9,0x42F9,0x64F9,0x22F9,0xC0F0,0xC0E0,0xC0E0,0xC0D0,0xA0D8,0xA0D0,0x80C8,0x80B8,0xC090,0xC250,0xC230,0xE320,0xE330,0xC328,0x8440,0x6438,0x6320,0x2228,0x0228,0x2218,0x2108,0x0010,0x2000,0x0100,0x2000,0x0000,0x2000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0008,0x0000,0x0008,0x0010,0x0010,0x0010,0x0018,0x0008,0x0010,0x2118,0x2118,0xC520,0x6418,0x4108,0x6210,0x8718,0x6810,0x8808,0xAF18,0x6908,0xAE18,0xAD08,0xAC10,0xAA08,0x6708,0x6708,0x6508,0x8400,0x6300,0xA410,0xEA10,0xA810,0x2D11,0xED08,0xAD10,0xAA08,0x6908,0x8B08,0xED08,0xEE08,0x0F01,0xF208,0xB000,0xD408,0x4E08,0x8C08,0xF108,0xCD08,0xCD08,0xF310,0xD408,0x9210,0x9108,0xB008,0x9108,0x6F08,0x8E08,0xB008,0xB310,0xD308,0xB108,0x8D00,0x8F08,0xAF08,0x6B08,0x6808,0x4708,0x4700,0x4400,0x0800,0x4700,0x4800,0x2A00,0x6E00,0x7100,0x8D00,0x4B00,0x2900,0x2700,0x2900,0x4800,0x2700,0x2600,0x0400,0x0400,0x2200,0x2100,0x2100,0x0100,0x0200,0x2100,0x2100,0x2100,0x2100,0x0200,0x4100,0x0300,0x2300,0x0300,0x2300,0x2200,0x2200,0x2200,0x2200,0x2300,0x0600,0x4500,0x4300,0x2208,0x2100,0x2100,0x4100,0x2200,0x2200,0x2400,0x2300,0x6400,0x4600,0x6700,0xAA00,0xC908,0xE710,0x2721,0x8829,0xCB31,0x4B42,0xAB52,0xEB5A,0x2B63,0x8C73,0x8B73,0x8C6B,0x8C6B,0x6B6B,0x4B6B,0x4B6B,0x2B6B,0x2B6B,0x4A63,0xC893,0xA1DC,0x40CC,0x20CC,0x00D4,0xE0D3,0xA0CB,0x80CB,0x06A3,0xE96A,0x0A5B,0xE962,0x095B,0x095B,0x0853,0x0A53,0xEA5A,0xC95A,0xE95A,0xC95A,0xC952,0xC95A,0xC952,0xC95A,0xA95A,0xA952,0xA952,0xC852,0xA952,0xA952,0xA852,0xA952,0x8952,0x895A,0xA952,0xA952,0xA952,0xA852,0x695A,}, +{0x8AFB,0x69FB,0x49FB,0x49FB,0x4AFB,0x8AFB,0x8BFB,0x8BFB,0xABFB,0x8CFB,0x6BFB,0x0BFB,0x0AFB,0x0AFB,0x87FA,0x46FA,0x05FA,0xE4F9,0x05FA,0x25FA,0x06FA,0x04FA,0x06FA,0x06FA,0x84F9,0x61F9,0x41F9,0xE0F8,0x01F1,0xE1F0,0xE1F0,0x00E1,0xC1D8,0xE0C8,0xE1A8,0xE280,0x2369,0xA461,0x2479,0xE370,0xA370,0x8358,0x6248,0x4240,0x0238,0x0228,0x4118,0x2110,0x2108,0x2100,0x2000,0x2000,0x0008,0x0000,0x0000,0x0008,0x2000,0x0008,0x0000,0x0000,0x0008,0x0008,0x0010,0x0018,0x0020,0x0018,0x0020,0x0020,0x0020,0x0010,0x0010,0x0018,0x0018,0x0010,0x0010,0x0008,0x0010,0x0118,0x8418,0x8918,0x4608,0xCD20,0x8C10,0x8F20,0x8B10,0xAA08,0x8A10,0x6500,0x6608,0x8600,0x6600,0x8400,0x8400,0xC610,0xED08,0xCE00,0xCC00,0xAE10,0xAD08,0xCE08,0x2E09,0xEE10,0x1111,0xCE00,0xD410,0x6F08,0x9110,0x6C08,0xAE00,0x8B00,0xAF08,0xB010,0x8F08,0x9110,0xB108,0xB008,0xAF00,0x8F08,0x8F08,0x6F00,0x6F08,0x8F08,0x8C08,0x8C08,0x8C08,0x6A00,0x4600,0x4400,0x2400,0x2300,0x0700,0x2600,0x6500,0x4900,0x2C08,0x5008,0x6F00,0x6D00,0x4D00,0x2B00,0x2600,0x0700,0x2900,0x2800,0x2500,0x2400,0x2400,0x2300,0x0300,0x0200,0x2100,0x0200,0x2100,0x2008,0x2008,0x2100,0x2100,0x0200,0x0200,0x2200,0x0300,0x0400,0x2300,0x2200,0x2200,0x2200,0x0500,0x2700,0x4600,0x4400,0x0300,0x2200,0x2100,0x2200,0x2300,0x2400,0x2500,0x2500,0x6500,0x8500,0x8800,0x8A08,0xEA08,0x2811,0x4821,0x8A31,0xEB39,0x8B4A,0xAB52,0x0B63,0x2B63,0x6C73,0x8C6B,0x8B6B,0x6C6B,0x6C73,0x6B73,0x6B6B,0x4C6B,0x6A63,0x2B6B,0x28A4,0xC1DC,0x80D4,0x40CC,0x40CC,0x00CC,0x00CC,0x64B3,0xC96A,0xEA5A,0xE95A,0x0A63,0x0A63,0xEA5A,0x0A63,0xE95A,0xE95A,0xEA5A,0xCA5A,0xE95A,0xC952,0xC952,0xC952,0xC952,0xA952,0xA95A,0xC852,0x8852,0x8852,0xA852,0xA852,0xA952,0xA952,0xA952,0xC94A,0xA952,0xA952,0xA852,0x8852,}, +{0x8AFB,0x49FB,0x29FB,0x48FB,0x6AFB,0x8AFB,0x8BFB,0x8CFB,0xABFB,0xABFB,0x6BFB,0x4BFB,0x2BFB,0xA9FA,0x87FA,0x85FA,0x26FA,0x25FA,0x05FA,0x26FA,0x46FA,0x87FA,0x47FA,0xE6F9,0xE5F9,0xC5F9,0xA4F9,0x82F9,0x42F9,0x43F9,0x42F9,0x41F1,0x01F1,0x21E1,0x22D1,0x42C9,0x45C2,0x45BA,0x44B1,0x03A1,0xC388,0xA380,0x8568,0x6458,0x2350,0x0138,0x2230,0x2218,0x2208,0x2210,0x2010,0x2000,0x2000,0x2000,0x2008,0x2008,0x2008,0x0010,0x0010,0x0008,0x0008,0x0020,0x0030,0x0028,0x0028,0x0028,0x0020,0x0020,0x0020,0x0020,0x0020,0x0020,0x0020,0x0010,0x0010,0x0008,0x0018,0x0018,0x2118,0x4318,0xCC30,0x8B10,0xAC18,0x8820,0xCD18,0xCC18,0x6810,0x8A10,0x8808,0x8700,0x6600,0x4500,0x4500,0x6510,0xAC10,0xA800,0xF010,0xAC08,0xD110,0x3109,0x1109,0xF010,0xCD08,0x3611,0xD000,0x9008,0x6E00,0x8E08,0x8E00,0x6D08,0x6A08,0x6C10,0x7010,0x8E08,0x9008,0xAF00,0x8F00,0xAE00,0x8E00,0x4D00,0x6E00,0x4900,0x4700,0x4B08,0x4B00,0x4800,0x2400,0x0400,0x0300,0x0400,0x2508,0x2600,0x4700,0x2900,0x4D08,0x4F08,0x4C00,0x2C00,0x4C00,0x2900,0x0800,0x0600,0x2700,0x2600,0x2500,0x0500,0x2400,0x2200,0x2100,0x2100,0x0100,0x0100,0x0100,0x0100,0x0000,0x2000,0x2100,0x0100,0x2200,0x0200,0x2200,0x2300,0x2300,0x2300,0x4200,0x4300,0x0500,0x0600,0x2600,0x2400,0x0300,0x2200,0x0200,0x2200,0x2300,0x4400,0x2700,0x2608,0x4600,0x6708,0x8800,0xAA00,0xE910,0x2811,0x4921,0xAA39,0x2A42,0x8C52,0xEB52,0x2B63,0x2B6B,0x8C6B,0x8C73,0x8C6B,0x8B6B,0x8B6B,0x8B6B,0x6B6B,0x4B6B,0x4B6B,0x4B6B,0xA6BC,0x01DD,0xC0D4,0xC0D4,0x60C4,0x20CC,0xC5BB,0x297B,0xEA5A,0xEA5A,0x0A63,0x0A63,0xE95A,0xEA5A,0xC95A,0x095B,0xCA5A,0xEA52,0xE95A,0xE952,0xCA5A,0xC952,0xA952,0xC952,0xC952,0xA95A,0xC952,0xA952,0x8952,0xA84A,0xA852,0xA852,0x8852,0xA952,0xA84A,0xA952,0x894A,0x8952,0x884A,}, +{0x8AFB,0x29FB,0x28FB,0x49FB,0x69FB,0x6AFB,0x8BFB,0x8BFB,0x8BFB,0xABFB,0x8CFB,0x8CFB,0x0CFB,0x68FA,0x88FA,0x87FA,0x66FA,0x26FA,0xE5F9,0x67FA,0xA8FA,0x88FA,0x45FA,0x46FA,0x46FA,0x47FA,0x25FA,0x05FA,0xE5F9,0xA4F9,0x84F9,0x62F9,0x42F9,0x62F1,0x82F1,0x44F2,0xC6EA,0x06E2,0x64D1,0x63B9,0x04A9,0xA498,0xA488,0xA468,0x6460,0x4350,0x2338,0x2330,0x4218,0x2218,0x0020,0x0118,0x2110,0x0010,0x0008,0x0010,0x2010,0x2008,0x0018,0x0010,0x0018,0x0030,0x0040,0x0038,0x0040,0x0038,0x0030,0x0028,0x0030,0x0028,0x0028,0x0030,0x0028,0x0020,0x0020,0x0018,0x0028,0x0020,0x0020,0x4230,0x8628,0xAB28,0x4710,0xAB20,0xEC18,0x6B10,0xAD10,0xAA10,0xAA08,0x8900,0x8900,0x4700,0x4600,0x2408,0x4400,0xCC10,0x6600,0xD218,0x0F11,0x3211,0x3109,0xEF00,0xAF08,0xAD00,0xAB00,0x8E00,0xCE08,0x8C08,0x8B00,0x6F00,0x6B00,0x4A00,0x6800,0xAE10,0x8F10,0xCF00,0x8A00,0x8D00,0xAD08,0x6900,0x4B00,0x4908,0x2900,0x2800,0x2800,0x2500,0x2400,0x0500,0x0300,0x0400,0x0400,0x2400,0x2700,0x2B00,0x4E08,0x2E00,0x4A00,0x2C00,0x2C00,0x2700,0x2800,0x0600,0x0700,0x2600,0x4400,0x0500,0x2400,0x2300,0x4200,0x2200,0x2200,0x0100,0x0100,0x0100,0x0000,0x0000,0x2000,0x2100,0x0200,0x0200,0x2200,0x2300,0x2308,0x2308,0x4200,0x2300,0x2400,0x0600,0x2500,0x2300,0x2300,0x2300,0x0400,0x2300,0x2500,0x2600,0x4800,0x4708,0x6508,0x6708,0x8908,0xA910,0x0911,0x4821,0xA831,0x093A,0x8B4A,0xAB52,0x0B5B,0x0B63,0x4C73,0x6C73,0x8C73,0x8C6B,0x6C6B,0x8B6B,0x6B6B,0x6B6B,0x6A63,0x6A6B,0x4A6B,0xA7C4,0x02DD,0xE1DC,0xC0CC,0x80CC,0xE5BB,0x086B,0x2A63,0x0A63,0xE962,0x0A63,0x0A63,0x0A5B,0xEA52,0xCA52,0xE95A,0xE95A,0xC95A,0xE952,0xC952,0xC952,0xA95A,0xC952,0xC952,0xA952,0xA952,0xC952,0xA952,0xA852,0xA852,0xA952,0xC85A,0x8952,0xA952,0xA84A,0x6952,0xA84A,0xA952,0x884A,}, +{0x89FB,0x69FB,0x28FB,0x49FB,0x6AFB,0x6BFB,0x8AFB,0x8AFB,0x8BFB,0xABFB,0xACFB,0x8CFB,0x2CFB,0xCBFA,0x69FA,0x27FA,0x87FA,0x66FA,0x46FA,0x89FA,0x67FA,0x66FA,0x67FA,0x87FA,0x89FA,0x87FA,0x66FA,0x45FA,0x46FA,0x04FA,0x05FA,0x04FA,0x04FA,0xC5F9,0xE4F9,0xE6FA,0x86FA,0xE6F1,0xC5E9,0x85D9,0x44C9,0x05B9,0x04A1,0x0699,0xC678,0x8758,0x2550,0x4340,0x4228,0x2148,0x2038,0x0120,0x0118,0x0010,0x2010,0x2010,0x2010,0x0010,0x0018,0x0020,0x0030,0x0050,0x0050,0x0050,0x0050,0x0040,0x0040,0x0038,0x0038,0x0030,0x0040,0x0038,0x0028,0x0020,0x0028,0x0028,0x0030,0x0028,0x0028,0x0030,0x4238,0x0128,0x6830,0xA820,0x6B20,0xAA18,0x6A18,0xAD18,0x8E18,0x8B08,0x8700,0x4900,0x4800,0x4600,0x4500,0x2608,0xA608,0x8C08,0xF010,0x3411,0x3309,0xF108,0x2B00,0x4300,0x4608,0xCD10,0x0F11,0xAC08,0x9108,0x6D00,0x4C00,0x4900,0x6400,0x4908,0x8D10,0x8D08,0x6A10,0x6908,0x8808,0x8700,0x4800,0x6600,0x4900,0x4900,0x2600,0x2600,0x2600,0x0300,0x2400,0x0400,0x0400,0x2400,0x4400,0x4800,0x4D00,0x4D00,0x4B00,0x4A00,0x2A00,0x4500,0x0808,0x2500,0x2600,0x2500,0x4400,0x2500,0x2400,0x2300,0x4200,0x2200,0x2100,0x0100,0x2000,0x0008,0x2000,0x0000,0x2000,0x2000,0x0100,0x0100,0x2200,0x2300,0x2200,0x2208,0x4208,0x2300,0x4300,0x0600,0x2400,0x4300,0x2300,0x2500,0x2400,0x4500,0x2500,0x4600,0x6700,0x4708,0x8608,0xA708,0xA900,0xE908,0x0819,0xA821,0xE839,0x4A42,0xEA52,0xEB5A,0x2C6B,0x2C6B,0x8B73,0x8B73,0x8B6B,0x6C73,0x6B6B,0x8B6B,0x8A6B,0x4B63,0x4B63,0x2A6B,0x4B73,0xE7D4,0x44DD,0xE1D4,0x81D4,0x05B4,0xE972,0x0A6B,0x0A63,0x295B,0xEA62,0x0A63,0xEA5A,0xEA5A,0xE95A,0xE95A,0xE95A,0xE95A,0xE952,0xE952,0xCA52,0xC952,0xA952,0xC952,0xC95A,0xA952,0x8952,0xA952,0xA852,0xA852,0xA852,0xA952,0xA852,0x6952,0x884A,0x884A,0xA952,0x874A,0x8852,0x6852,}, +{0xAAFB,0x69FB,0x49FB,0x69FB,0x4AFB,0x6AFB,0x89FB,0xAAFB,0xABFB,0xAAFB,0xACFB,0xACFB,0x4BFB,0xEBFA,0x49FA,0x48FA,0x67FA,0x87FA,0x87FA,0x66FA,0x65FA,0x86FA,0xA8FA,0xE9FA,0xC9FA,0xA8FA,0xA7FA,0x87FA,0x87FA,0x67FA,0x47FA,0x66FA,0x46FA,0x66FA,0xE7FA,0x08FB,0xC8FA,0x47FA,0x46FA,0xE6F1,0xA5D9,0xA5D1,0x86C1,0x26A9,0x0799,0xA788,0x8570,0x6468,0xC378,0xC578,0x2240,0x0238,0x0120,0x0210,0x0118,0x0118,0x2010,0x0010,0x0018,0x0028,0x0050,0x0068,0x0060,0x0068,0x0060,0x0050,0x0050,0x0048,0x0040,0x0040,0x0048,0x0040,0x0030,0x0028,0x0030,0x0038,0x0040,0x0038,0x0038,0x0040,0x0040,0x2038,0x0040,0x0130,0x6930,0x6B28,0x8A20,0xAB20,0x6C18,0x4B10,0x6A08,0x6900,0x6600,0x6600,0x2700,0x2500,0x4400,0xCB18,0x0D21,0x0E11,0xF008,0xD010,0x0600,0x0300,0x2300,0xD010,0x0F11,0x1011,0xD008,0x8E00,0x4B00,0x4400,0x6300,0x4700,0x4800,0x6808,0x6808,0x6600,0x6700,0x6600,0x4700,0x4500,0x2800,0x4700,0x2700,0x2600,0x0600,0x0500,0x4400,0x2400,0x0300,0x0400,0x2500,0x6600,0x8808,0x6800,0x6900,0x4800,0x2600,0x2600,0x0600,0x2600,0x2500,0x2500,0x4500,0x0600,0x0400,0x2200,0x2200,0x0100,0x0100,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2100,0x2100,0x2100,0x2200,0x4200,0x2100,0x4208,0x4208,0x4300,0x2400,0x4300,0x4300,0x2400,0x0500,0x4500,0x2500,0x2600,0x4600,0x6700,0x6700,0xA600,0xA800,0xCA00,0x2901,0x6819,0xE731,0x6742,0xC952,0x0A5B,0x0A63,0x2C6B,0x4C6B,0x8C6B,0x8C73,0xAB73,0x8B6B,0x6C6B,0x8B73,0x6B6B,0x6C6B,0x6B63,0x2B6B,0x4B6B,0xC8C4,0x27DD,0xC4CC,0x07AC,0x096B,0xEA5A,0xEA62,0x0A5B,0x0953,0x0A63,0x0963,0xEA62,0xEA62,0xE95A,0xE95A,0xCA5A,0xC952,0xC952,0xC95A,0xC952,0xC952,0xC852,0xA95A,0xA852,0x8952,0xA952,0xC952,0xA952,0xA852,0x8852,0x884A,0xA852,0xA952,0x8852,0xA94A,0x8952,0x8852,0x894A,0x894A,}, +{0xABFB,0x69FB,0x49FB,0x28FB,0x28FB,0x49FB,0x8AFB,0x8BFB,0x8BFB,0x8AFB,0x8BFB,0x8CFB,0x6BFB,0x0BFB,0xA9FA,0x29FA,0x07FA,0x68FA,0x66FA,0x66FA,0x86FA,0x87FA,0xC9FA,0xC9FA,0xC8FA,0xC8FA,0xC9FA,0xC9FA,0xA8FA,0xA7FA,0x88FA,0xA7FA,0xA7FA,0xC8FA,0x6AFB,0x29FB,0x09FB,0xCAFA,0xC9FA,0xA8FA,0x48F2,0xE7E9,0xC6C9,0x87C1,0x67B9,0x0699,0x26A1,0x25B1,0x49B1,0x8670,0x2260,0x0340,0x0230,0x0228,0x0128,0x0128,0x0120,0x0120,0x0020,0x0038,0x0058,0x0068,0x0080,0x0080,0x0070,0x0070,0x0068,0x0058,0x0048,0x0048,0x0058,0x0048,0x0030,0x0028,0x0048,0x0040,0x0050,0x0048,0x0050,0x0050,0x0050,0x0048,0x0040,0x0040,0x2450,0xA738,0x8A30,0x6B28,0x6A30,0x6718,0x4A08,0x4908,0x6708,0x6700,0x2508,0x4400,0x2400,0x6400,0x8608,0xCA10,0xEC10,0x6800,0x2300,0x2400,0x6700,0xD108,0xCC08,0xD110,0xAE00,0x8C00,0x2808,0x4300,0x6500,0x4400,0x2300,0x4300,0x6400,0x8500,0x4700,0x6600,0x4600,0x4700,0x2600,0x6600,0x2600,0x2600,0x2500,0x0600,0x2500,0x2400,0x0400,0x0400,0x2400,0x2400,0x4308,0x4400,0x4500,0x4500,0x2400,0x0300,0x2400,0x2600,0x2400,0x2400,0x2500,0x0608,0x0300,0x2200,0x2100,0x0100,0x0000,0x2000,0x2000,0x2000,0x0000,0x0000,0x0000,0x2000,0x0000,0x2000,0x4000,0x2100,0x4100,0x4000,0x4108,0x4108,0x6200,0x6300,0x4400,0x4400,0x2500,0x2500,0x2500,0x4600,0x4500,0x6600,0x6700,0x8600,0xA608,0xC700,0xCA00,0x2909,0xA821,0x4632,0xC74A,0x495B,0x8A63,0x8B6B,0x6C6B,0x8C73,0xAC73,0x8D73,0x8C6B,0x6C73,0x6C73,0x6C73,0x6B6B,0x6B63,0x4B6B,0x4B63,0x6A63,0xCA83,0x49AC,0xC99B,0x0A63,0x0A5B,0xEB62,0x0A5B,0x0A63,0xEA5A,0x0A5B,0xE95A,0xCA62,0x095B,0x095B,0xCA5A,0xC962,0xC952,0xE95A,0xE95A,0xC952,0xA952,0xC85A,0xC85A,0xA952,0x8952,0x8952,0xC952,0x8952,0xA852,0x8952,0x8852,0xA852,0x8852,0xA94A,0xA84A,0xA95A,0x894A,0x894A,0x884A,}, +{0x8AFB,0x48FB,0x07FB,0x07FB,0x07FB,0x48FB,0x89FB,0x8AFB,0x8BFB,0x8AFB,0x8AFB,0x8BFB,0x6BFB,0x2CFB,0xEBFA,0x49FA,0x47E1,0x64E1,0x66FA,0xA7FA,0xA7FA,0xA8FA,0xA8FA,0xC9FA,0xE9FA,0xC8FA,0xE9FA,0xEAFA,0xE9FA,0xC8FA,0xC8FA,0xA8FA,0xC8FA,0x49FB,0x49FB,0x0AFB,0x09FB,0x2BFB,0x2BFB,0x2BFB,0xCAFA,0x6AF2,0x07EA,0xE7D9,0x67C1,0x66C9,0x86D9,0xEAD9,0x0899,0xC698,0x4778,0x0368,0x0050,0x0148,0x0240,0x0238,0x2128,0x0030,0x0028,0x0130,0x0050,0x0068,0x2090,0x0080,0x0078,0x0080,0x0078,0x0068,0x0050,0x0058,0x0060,0x0058,0x0048,0x0040,0x0050,0x0068,0x0068,0x0060,0x0060,0x0060,0x0070,0x0068,0x0058,0x0050,0x0050,0x4350,0x4648,0x8740,0x6538,0x8830,0x6810,0x8408,0x4708,0x6800,0x6600,0x4500,0x2400,0x2308,0x2200,0x6308,0x6408,0x2200,0x2300,0x2400,0xAC08,0xF210,0x0E01,0xF008,0xB008,0x8800,0x2300,0x2400,0x4300,0x4100,0x2100,0x2300,0x4400,0x4600,0x4600,0x2500,0x4500,0x2500,0x2600,0x4600,0x4600,0x4400,0x2600,0x2600,0x2500,0x2300,0x0400,0x0300,0x2300,0x0200,0x2100,0x4300,0x2400,0x2600,0x2500,0x2300,0x2300,0x2400,0x4400,0x0600,0x2600,0x0500,0x0200,0x0200,0x0000,0x2000,0x0000,0x2000,0x2000,0x2000,0x2000,0x0100,0x0000,0x2000,0x2000,0x2000,0x4000,0x4008,0x2000,0x2000,0x4100,0x6100,0x4208,0x4300,0x2400,0x4400,0x2500,0x4400,0x4500,0x4600,0x6500,0x6600,0x4708,0xA608,0xA508,0xE508,0x0809,0x8809,0x071A,0x853A,0x264B,0x875B,0xC863,0xCB6B,0xAC73,0xAC73,0x8C73,0x6C73,0x8C6B,0x6B73,0x6C6B,0x6B73,0x4B6B,0x6B6B,0x4B6B,0x2B6B,0x4B63,0x2B63,0x2A6B,0x0A6B,0x0A63,0xEA62,0x0A63,0x0A63,0x0A5B,0xEA5A,0xEA5A,0xEA5A,0x095B,0xEA5A,0xE95A,0xCA5A,0xE952,0xE952,0xA952,0xC952,0xC952,0xC952,0xA952,0xCA52,0xC952,0xA952,0xA852,0xC84A,0xA94A,0x8952,0x8952,0xA852,0x8852,0x8952,0x894A,0xA952,0x8952,0x874A,0xA74A,0x694A,}, +{0x69FB,0x48FB,0x07FB,0x08FB,0xE7FA,0x48FB,0x69FB,0x6BFB,0x6AFB,0x8AFB,0x8AFB,0x6BFB,0x69FB,0x4BFB,0x2CFB,0x4AF2,0x86D9,0x88F2,0x67FA,0x68FA,0x88FA,0xA8FA,0xC8FA,0xC9FA,0xE8FA,0xE9FA,0x09FB,0x0AFB,0x09FB,0xE9FA,0xE8FA,0xC8FA,0xE9FA,0x29FB,0x4AFB,0x0AFB,0x2AFB,0x4AFB,0x6CFB,0x4BFB,0x0CFB,0xCBFA,0x8AF2,0x07EA,0x07EA,0x08EA,0xE8E9,0x89C9,0x87C9,0xE9A8,0x8890,0x2590,0x2378,0x0360,0x0158,0x0350,0x0238,0x0338,0x0140,0x0238,0x0050,0x2060,0x0068,0x0060,0x0060,0x0080,0x2080,0x0078,0x0068,0x0068,0x0070,0x0060,0x0048,0x0060,0x0060,0x0078,0x0078,0x0078,0x0078,0x0078,0x0080,0x0080,0x0078,0x0078,0x0068,0x0068,0x0060,0x2158,0x6458,0x2350,0x4330,0x8318,0x8618,0x8508,0x6408,0x2308,0x2308,0x0300,0x0100,0x0100,0x2000,0x2108,0x2308,0x6500,0xCD18,0xCC08,0xF018,0xCE18,0xAC08,0x4400,0x2300,0x2400,0x2400,0x0400,0x0300,0x4400,0x8500,0x4508,0x4700,0x6600,0x4600,0x6500,0x4600,0x4600,0x4500,0x6500,0x4500,0x0600,0x0400,0x4500,0x2300,0x0200,0x2100,0x0000,0x2000,0x2200,0x4200,0x2500,0x2500,0x4400,0x2300,0x2400,0x2500,0x0600,0x2600,0x0400,0x2100,0x0100,0x2000,0x2000,0x0000,0x0000,0x2000,0x2000,0x2000,0x2100,0x2000,0x2000,0x2000,0x2000,0x2008,0x2000,0x2000,0x2000,0x2000,0x4108,0x2200,0x4300,0x4400,0x4400,0x4600,0x2600,0x4600,0x4600,0x6500,0x8500,0x6608,0xC508,0xC508,0xE508,0x4701,0xC809,0x2622,0xE53A,0x8553,0xE55B,0xE763,0xEA73,0x0B74,0xEC73,0xCC6B,0xAC73,0x8B6B,0x6B73,0x6C6B,0x6B6B,0x4B6B,0x4B6B,0x4B6B,0x2B6B,0x4B6B,0x2B63,0x2963,0x2A63,0x2A63,0x0A63,0x0A5B,0xEA62,0xEB62,0xEA5A,0xEA62,0xEA5A,0xC962,0xE95A,0xE95A,0xCA5A,0xC952,0xC952,0x895A,0xAA5A,0xA952,0xA952,0xA952,0xA952,0x8A5A,0xA852,0xA952,0xA94A,0xA952,0x8952,0x8952,0x894A,0xA852,0x8852,0xA952,0x884A,0x8952,0x684A,0x6852,0x894A,}, +{0x69FB,0x69FB,0x68FB,0x07FB,0x07FB,0x27FB,0x28FB,0x49FB,0x69FB,0x6AFB,0x6AFB,0x6AFB,0x8AFB,0x6BFB,0x2CFB,0x6BFA,0x0AFB,0xCAFA,0x48FA,0xE7F9,0x07FA,0x68FA,0xE8FA,0xC8FA,0xE8FA,0xC8FA,0x29FB,0x2AFB,0x09FB,0x09FB,0x09FB,0x29FB,0x4AFB,0x2AFB,0x4AFB,0x4AFB,0x8CFB,0xCCFB,0x8CFB,0x8CFB,0x6DFB,0x4DFB,0x2BFB,0xA9FA,0x89FA,0xACF2,0x49F2,0xC8E1,0x87D1,0xE8C0,0xC7B0,0x85B0,0x86A0,0x4488,0x0580,0x2360,0x0458,0x0260,0x0158,0x0250,0x0060,0x0050,0x0060,0x0050,0x2058,0x0060,0x0070,0x2078,0x0080,0x0078,0x4078,0x2060,0x2058,0x2070,0x0070,0x0080,0x2090,0x2090,0x2088,0x2090,0x2090,0x20A0,0x2090,0x0090,0x0088,0x0078,0x0078,0x0070,0x0070,0x0060,0x0058,0x2038,0x6228,0x6210,0x4210,0x2308,0x2208,0x2208,0x0200,0x2100,0x0100,0x2100,0x6208,0x6508,0x8608,0xA808,0xA910,0x8A10,0x6400,0x2500,0x2400,0x4500,0x2500,0x2400,0x4400,0x6400,0x8500,0x4508,0x6500,0x6800,0x4800,0x2700,0x2800,0x4800,0x4600,0x6500,0x4600,0x2500,0x2300,0x0500,0x2300,0x2200,0x0100,0x0000,0x2000,0x4000,0x4100,0x4408,0x4400,0x2400,0x2500,0x2500,0x0500,0x2500,0x0500,0x0300,0x2100,0x0100,0x2000,0x0000,0x0000,0x2000,0x2000,0x4000,0x2000,0x2000,0x2000,0x4000,0x2008,0x2008,0x2000,0x2100,0x4100,0x2100,0x2000,0x4100,0x4200,0x4300,0x4300,0x4508,0x6500,0x4500,0x4500,0x4508,0x6608,0x8600,0x8608,0xC608,0xE608,0x2509,0x8509,0xE711,0x861A,0x4443,0xE44B,0x445C,0x465C,0x286C,0x496C,0x2A74,0x0B74,0xCC73,0x8C6B,0x6C6B,0x6C6B,0x8B6B,0x4B6B,0x4A6B,0x4B6B,0x4B6B,0x2A63,0x2A63,0x2A63,0x0A63,0x0A6B,0x2A63,0x0A63,0xE95A,0x0A63,0xEA5A,0x0963,0x0A5B,0xC962,0x095B,0xC95A,0xC95A,0xC95A,0xEA5A,0xC85A,0xC952,0xC952,0xC952,0xA952,0xA952,0xA95A,0xA852,0xA95A,0xA952,0xA95A,0x8852,0x894A,0x894A,0xA852,0x884A,0xA84A,0x8852,0x684A,0x884A,0x684A,0x684A,}, +{0x8BFB,0xABFB,0x89FB,0x49FB,0x27FB,0x07FB,0xE7FA,0x27FB,0x49FB,0x49FB,0x6AFB,0x6AFB,0x8AFB,0x4AFB,0x2AFB,0x6CFB,0x6DFB,0xEBFA,0x6AFA,0x09FA,0xC8F9,0xE7F9,0x89FA,0xE9FA,0xE9FA,0x09FB,0x2AFB,0x09FB,0x09FB,0x29FB,0x29FB,0x6AFB,0x4AFB,0x6AFB,0x6BFB,0xACFB,0xEDFB,0x0FFC,0x8BFB,0x6BFB,0x6DFB,0x8DFB,0x8DFB,0xEAFA,0xA9FA,0xEDFA,0x49FA,0x08F2,0x87E1,0x48D9,0x26D1,0xC6C8,0xC6C8,0x67B0,0x25A8,0x4590,0x2588,0x2478,0x2288,0x2180,0x0168,0x0160,0x0070,0x0060,0x0068,0x0068,0x0070,0x0068,0x0068,0x2178,0x6080,0x6078,0x4098,0x4088,0x2098,0x4090,0x40A8,0x20A8,0x20A0,0x60A8,0x40B8,0x60B8,0x60A8,0x20B0,0x40A8,0x2098,0x0090,0x0090,0x0088,0x0080,0x0070,0x0058,0x0048,0x2028,0x4110,0x2110,0x2210,0x0310,0x0208,0x0200,0x0200,0x2100,0x4100,0x2318,0x2200,0x4600,0x4400,0x4600,0x4508,0x2608,0x4700,0x2700,0x2708,0x2608,0x6600,0x6400,0x4500,0x2500,0x6400,0x6700,0x4900,0x4900,0x4800,0x6A00,0x6800,0x4800,0x6600,0x6400,0x2300,0x0500,0x2300,0x2100,0x2100,0x0000,0x0000,0x0000,0x2000,0x2210,0x4208,0x4400,0x2600,0x4500,0x2500,0x2300,0x2308,0x2200,0x2200,0x0000,0x2000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,0x2100,0x2000,0x4100,0x2208,0x4008,0x4108,0x2208,0x4100,0x4100,0x6100,0x4200,0x4200,0x6208,0x6208,0x4408,0x6300,0x6508,0x6400,0x8508,0x6608,0x8608,0xA608,0xE608,0x2601,0x4509,0x8511,0x260A,0xA41A,0x433B,0x024C,0x8364,0xA364,0x655C,0x666C,0x496C,0x0A6C,0x2A74,0xAC73,0x8B6B,0x8B6B,0x8B6B,0x6B6B,0x6A63,0x4A6B,0x4B6B,0x2A63,0x2A6B,0x0A5B,0x2A5B,0x0A63,0x2A63,0x0A5B,0x0A5B,0x095B,0x095B,0xE962,0xE95A,0xCA5A,0xE95A,0xEA5A,0xC95A,0xE85A,0xEA52,0xA952,0xC952,0xC952,0xC852,0xA952,0xA852,0xA952,0xA752,0xA95A,0xA84A,0x8952,0xA752,0x894A,0x884A,0xA852,0x894A,0x884A,0x884A,0x884A,0x6852,0x684A,0x684A,}, +{0x8CFB,0xABFB,0x89FB,0x68FB,0x27FB,0xE8FA,0xE7FA,0x07FB,0x49FB,0x6AFB,0x6BFB,0x6AFB,0x8AFB,0x4AFB,0x6AFB,0xACFB,0x6CFB,0xECFA,0xABFA,0x48FA,0x4AFA,0xE9F9,0xE8F1,0x68FA,0x69FA,0xC9FA,0x29FB,0x09FB,0x09FB,0x29FB,0x2BFB,0x6AFB,0x6BFB,0x8BFB,0x8CFB,0xEEFB,0x50FC,0xEEFB,0xABFB,0x6BFB,0x4CFB,0xADFB,0xADFB,0x2BFB,0x0AFB,0x0BFB,0xEBFA,0x48FA,0x27F2,0xA7E9,0x87E9,0x25E1,0x06E1,0xC6D0,0x86B8,0x65B0,0x64A0,0x6590,0x43B8,0x85A8,0x4388,0x4288,0x2288,0x0178,0x0178,0x0078,0x0080,0x0180,0x4178,0x8390,0xC198,0x80A8,0x60C0,0x60B0,0x60C0,0x40B0,0x60B0,0x40A8,0x40C0,0x40C8,0x40C8,0x60D0,0x60C8,0x40D0,0x80C0,0x60B0,0x20B0,0x20A8,0x00A8,0x0098,0x2088,0x0080,0x0068,0x0050,0x2030,0x2128,0x2220,0x2118,0x0310,0x2308,0x0308,0x2208,0x2108,0x2108,0x2210,0x2308,0x4508,0x2300,0x2808,0x2400,0x4800,0x6808,0x4808,0x4800,0x4900,0x4600,0x2700,0x2500,0x6500,0x6800,0x4800,0x6908,0x8900,0x6B00,0x8800,0x2800,0x4800,0x4400,0x6400,0x4600,0x2300,0x2100,0x0008,0x0000,0x2000,0x0000,0x0000,0x2000,0x2108,0x4200,0x6300,0x4400,0x2400,0x2300,0x2400,0x2200,0x0200,0x0000,0x2000,0x0000,0x0000,0x2000,0x0000,0x2000,0x2008,0x2100,0x2100,0x4100,0x2208,0x4108,0x4208,0x4208,0x6108,0x4108,0x4200,0x4200,0x4100,0x6200,0x6208,0x6408,0x6310,0x6408,0x8408,0x6508,0xA500,0xA608,0xC800,0x0611,0x4509,0x6501,0xC509,0x260A,0xA422,0x6233,0x214C,0x825C,0xE264,0xC35C,0xC464,0x8764,0x696C,0x4974,0xEB6B,0xAB6B,0x8B6B,0x6A6B,0x4B6B,0x4B6B,0x4B6B,0x2B63,0x4B63,0x2B63,0x0B63,0x0B63,0x2A5B,0x0A63,0x2A63,0x0A5B,0xEA5A,0x095B,0x0953,0xE962,0xCA62,0xEA5A,0xE95A,0xE85A,0xA95A,0xC95A,0xA95A,0xCA52,0xA952,0xA852,0x894A,0xA952,0xA852,0xA852,0xA952,0x894A,0x8852,0xA84A,0x8952,0x884A,0x8852,0x884A,0x8852,0x884A,0x694A,0x684A,0x484A,0x484A,}, +{0x6CFB,0x6BFB,0x6AFB,0x48FB,0x27FB,0x08FB,0x07FB,0x27FB,0x49FB,0x29FB,0x29FB,0x4AFB,0x69FB,0x6AFB,0x8BFB,0x6BFB,0x6CFB,0x2BFB,0xEDFA,0x0CFB,0xADFA,0x4BFA,0x08FA,0xE8F1,0xE9F1,0x28FA,0xE9FA,0xE9FA,0x0AFB,0x29FB,0x09FB,0x8BFB,0xACFB,0xCEFB,0x8DFB,0xADFB,0xEEFB,0x8DFB,0x6BFB,0x6BFB,0x6CFB,0x8EFB,0x6DFB,0x2BFB,0x0AFB,0x2BFB,0x0BFB,0xEAFA,0x68FA,0x49FA,0xC6F9,0x84F9,0x44F1,0xE4E8,0xC5E0,0xC4D8,0x84C8,0x63C0,0xA5D0,0xE7C8,0x83C0,0x83A0,0xA3B8,0x62A0,0x4390,0x4198,0x6090,0x4198,0xA298,0xE4B8,0x00B9,0xE1C8,0x80C8,0x80C0,0xA1D8,0x80D0,0x80C8,0xA0B8,0x80D0,0x80D8,0x80D8,0xC0D8,0xA1D8,0x80E8,0x80E0,0x60D8,0x60D0,0x60C8,0x20C0,0x60B8,0x60B0,0x4098,0x20A0,0x0080,0x2040,0x4148,0x0240,0x2328,0x2418,0x2310,0x2308,0x2208,0x2018,0x2210,0x2210,0x2110,0x4210,0x4108,0x4608,0x2708,0x2808,0x4800,0x6600,0x6900,0x2900,0x2700,0x2600,0x2500,0x6500,0x6500,0x6508,0x6708,0x8908,0x8A08,0x8800,0x8800,0x6800,0x4200,0x2500,0x2400,0x4200,0x2100,0x2008,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2208,0x4200,0x2200,0x4300,0x4300,0x4200,0x2108,0x2000,0x0000,0x0000,0x0000,0x2000,0x2000,0x2000,0x2108,0x4108,0x2208,0x4208,0x4208,0x4200,0x4308,0x4210,0x4308,0x4208,0x4208,0x4200,0x4200,0x6100,0x6208,0x6308,0x8308,0x8310,0xA308,0x8508,0xA508,0xC508,0xE708,0x0609,0x4411,0xA409,0xE509,0x460A,0xC322,0x812B,0x2044,0x8054,0xE154,0x0265,0x0365,0xA464,0x8764,0x686C,0x2B74,0x0B6C,0xAC6B,0x4B73,0x4B6B,0x4B63,0x4B6B,0x2A6B,0x4A6B,0x2B63,0x2A6B,0x0A63,0x2A5B,0x0A63,0x0A63,0x0A5B,0xE95A,0x095B,0x0963,0xE962,0xE962,0xC95A,0xE952,0xE95A,0xCA52,0xC952,0xA952,0xA952,0xA952,0xA85A,0xA852,0xA852,0xA952,0x8952,0x8852,0xA952,0x8952,0x884A,0x8952,0x884A,0x884A,0x6952,0x684A,0x6952,0x684A,0x4852,0x684A,0x684A,}, +{0x4CFB,0x2BFB,0x0AFB,0x48FB,0xAAFB,0x29FB,0x68FB,0x48FB,0x07FB,0x07FB,0x28FB,0x08FB,0x28FB,0x8AFB,0x6CFB,0x6BFB,0x6BFB,0x4BFB,0x4DFB,0x0DFB,0xEDFA,0xEDFA,0x4AFA,0xC9F1,0x89E9,0xC9E1,0xE8F9,0x89FA,0x89FA,0xE9FA,0xC8FA,0x6BFB,0xACFB,0xADFB,0x8DFB,0xADFB,0x8CFB,0x4BFB,0x6BFB,0x8BFB,0x6CFB,0x6DFB,0x8DFB,0x2BFB,0xEBFA,0x4CFB,0x4CFB,0x0AFB,0xAAFA,0xCAFA,0x67FA,0xE7F9,0x85F9,0x84F9,0x22F9,0x02F1,0xE2E8,0xE3E0,0x02E1,0x44E9,0x65E1,0xE3C8,0xE3C8,0xC3B8,0xA2B8,0x81B0,0x80B0,0x80B8,0xA0C0,0x44D1,0x81D1,0x43E1,0xE0D8,0xE0D0,0x21E9,0x00E1,0x00E1,0xE0D0,0xC0E0,0xA1E8,0xC0E0,0xC0E0,0xC1E8,0xC2F8,0xE1F0,0xC0F0,0xC1F0,0xA0E0,0x60D8,0xA0D8,0x80D0,0xA0C0,0x40C0,0x20A0,0x2050,0x4178,0x2160,0x2340,0x4420,0x2620,0x4418,0x2220,0x2020,0x2220,0x0418,0x2318,0x0318,0x4318,0x2410,0x6610,0x4810,0x4608,0x8508,0x8708,0x4500,0x6608,0x6508,0x6608,0x6500,0x4408,0x4408,0x6300,0x6610,0x6608,0x6708,0x8710,0x6408,0x4300,0x4400,0x2300,0x2200,0x2200,0x2108,0x0100,0x2100,0x2000,0x0000,0x2000,0x0000,0x0000,0x0008,0x2000,0x4100,0x4108,0x4208,0x2108,0x2000,0x2000,0x2000,0x0000,0x0100,0x2000,0x2000,0x2108,0x4108,0x4108,0x4208,0x4108,0x4208,0x4300,0x4310,0x4408,0x6308,0x6308,0x4308,0x6300,0x4300,0x4308,0x6208,0x6208,0x6310,0x8310,0x8408,0xA508,0xA510,0xC508,0xE608,0x0511,0x4509,0xA411,0xE309,0x4312,0xC21A,0x402B,0xE03B,0x404C,0xC054,0x015D,0x2265,0xE364,0xE66C,0xC76C,0x6974,0x2A74,0xEB6B,0x8A63,0x4B6B,0x2B6B,0x2B6B,0x2B6B,0x0B63,0x2B63,0x0A6B,0x2A63,0x0A63,0x295B,0x0A5B,0xEA5A,0x095B,0xE962,0xE95A,0xE95A,0x095B,0xC952,0xE852,0xE852,0xC952,0xC95A,0xA952,0xA952,0xA952,0xA852,0xC852,0xA952,0xA952,0x8952,0x884A,0x8852,0x8852,0x884A,0x884A,0x884A,0x8852,0x894A,0x684A,0x674A,0x4852,0x674A,0x684A,0x484A,}, +{0x2BFB,0x0CFB,0x0BFB,0x0BFB,0xE9FA,0x08FB,0x8AFB,0x69FB,0x28FB,0xE7FA,0xC7FA,0xE7FA,0x6AFB,0x6BFB,0x4AFB,0x6BFB,0x4AFB,0x4BFB,0x6DFB,0x4CFB,0x0DFB,0x2DFB,0xEDFA,0x4CFA,0xCAE9,0x69E9,0xC7E9,0xE8F1,0x09F2,0x28FA,0xC7FA,0x8BFB,0xADFB,0xAEFB,0x6DFB,0xADFB,0x2BFB,0x2AFB,0x4BFB,0x8CFB,0x6BFB,0x2CFB,0x6CFB,0x2BFB,0x0AFB,0x0BFB,0x4BFB,0xEAFA,0x89FA,0x8AFA,0x26FA,0x06FA,0xA4F9,0xE5F9,0xA4F9,0x83F9,0x63F9,0x23F1,0x82F9,0xE5F9,0xA5F1,0x23E9,0x22E1,0x22E1,0x02E1,0xC2D8,0xE0D0,0xA1D0,0xE1D8,0x22E1,0xE3F1,0xC5F1,0x21E1,0x22E1,0xC6F1,0x84E9,0x83F1,0x02E1,0x42F1,0x22F1,0x21F1,0x01E9,0x41E9,0x02F1,0x42F9,0x02F1,0x22F9,0x01F1,0xE2F0,0xE1E8,0xC3E8,0xE2E0,0xE1E0,0xA1C0,0x0058,0x2088,0x2280,0x6358,0x6430,0x4528,0x4630,0x2120,0x2328,0x0330,0x2420,0x0128,0x0320,0x2320,0x2318,0x4218,0x0218,0x2210,0x6310,0x6310,0x4108,0x6310,0x6310,0x6310,0x6210,0x2408,0x2400,0x2300,0x2508,0x6408,0x4610,0x6508,0x4300,0x4408,0x6300,0x2300,0x2200,0x2200,0x0208,0x2100,0x2000,0x2000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2108,0x2110,0x4008,0x2000,0x2000,0x2000,0x2000,0x2108,0x2008,0x4100,0x2100,0x4100,0x4200,0x4200,0x4208,0x4100,0x6208,0x6308,0x4408,0x6408,0x6400,0x6408,0x6400,0x4500,0x4408,0x6200,0x6208,0x8210,0x8210,0xA310,0xA308,0xC310,0xE410,0x0509,0x2411,0x6409,0xA311,0x0212,0x411A,0xA122,0x2023,0xE033,0x4044,0xC04C,0xE05C,0x0165,0x2365,0x036D,0x056D,0xC674,0x897C,0x2A74,0xCB6B,0x6B63,0x4B6B,0x6A6B,0x4B6B,0x2B63,0x2B63,0x0B63,0x2A63,0x0B63,0x0A63,0x0A63,0xEA5A,0xEA62,0xEA5A,0xE95A,0xC962,0xC952,0xAA5A,0xE952,0xC952,0xC952,0xC95A,0xAA52,0xC95A,0xA952,0xA95A,0xA852,0x8952,0xA852,0x884A,0x684A,0x6852,0x8952,0x8852,0x8852,0x684A,0x684A,0x884A,0x6852,0x684A,0x484A,0x674A,0x4842,0x484A,}, +{0x09FB,0x0AFB,0xEBFA,0xEBFA,0xAAFA,0xEBFA,0x0BFB,0x29FB,0x09FB,0xC7FA,0xA7FA,0xE7FA,0x2AFB,0x29FB,0x29FB,0x4AFB,0x2AFB,0x2AFB,0x0AFB,0x4DFB,0x6DFB,0x4FFB,0x2FFB,0x10FB,0x6DF2,0x09F2,0xC9E9,0xC8F1,0x2CEA,0x68FA,0xC9FA,0x2DEB,0xD0FB,0x8CFB,0x2BFB,0x2BFB,0x0AFB,0x0AFB,0x4BFB,0x6CFB,0x4BFB,0xEAFA,0x0BFB,0x0AFB,0xE9FA,0xEBFA,0x0AFB,0xC9FA,0x48FA,0x07FA,0x26FA,0x26FA,0x46FA,0x46FA,0x25FA,0x25FA,0x05FA,0xE5F9,0x26FA,0x67FA,0x06FA,0x84F9,0x63F9,0x42F1,0x23F9,0x02F1,0x01F1,0x23E9,0x23F1,0x42F9,0x43FA,0xC3F9,0x61F1,0x42F1,0xE6F1,0xA6E9,0xA4E9,0x44E1,0xA5F9,0x65E9,0xA4F1,0x82F1,0xA4F1,0x84F1,0x84F9,0x62F1,0xA4F9,0x22F9,0x42F1,0x42F9,0x63F1,0x63F1,0x63F1,0x01D9,0x0068,0x0078,0x8290,0x8278,0xA540,0x8428,0x2640,0x2038,0x4628,0x0438,0x2230,0x0038,0x0438,0x0328,0x2320,0x0220,0x0120,0x2110,0x2108,0x2218,0x0010,0x2118,0x4218,0x4310,0x2310,0x2418,0x2308,0x2500,0x2600,0x4500,0x4500,0x4400,0x4400,0x2400,0x4500,0x2200,0x2300,0x4200,0x4108,0x4100,0x4000,0x2008,0x0008,0x2000,0x0000,0x0000,0x0000,0x0008,0x0000,0x0000,0x2008,0x2000,0x0008,0x2000,0x4000,0x2000,0x2008,0x4000,0x4100,0x2108,0x4100,0x4200,0x4200,0x4208,0x6200,0x6208,0x6408,0x6508,0x4608,0x6500,0x8400,0x6600,0x4600,0x6408,0x6208,0x6308,0x8208,0xA208,0xA208,0xC308,0xE308,0xE310,0x2309,0x4309,0x6209,0xC211,0x200A,0x601A,0xC01A,0x201B,0xA02B,0xE03B,0x8044,0xC054,0x205D,0x415D,0x426D,0x247D,0x0675,0xC76C,0x8974,0x2A74,0xCB6B,0x4B6B,0x4A63,0x2B6B,0x2B63,0x2A63,0x2A63,0x2A63,0x0A63,0x0A63,0x0A63,0x0A5B,0xCA5A,0xE95A,0xEA5A,0xE95A,0xE95A,0xC95A,0xE95A,0xEA5A,0xA95A,0xC85A,0xC952,0xA952,0xA952,0xA952,0xA952,0x8952,0x8952,0xA852,0x8852,0x8852,0x8852,0x884A,0x894A,0x6852,0x684A,0x684A,0x684A,0x6852,0x684A,0x484A,0x674A,0x484A,}, +{0xE7FA,0xEAFA,0xCAFA,0xABFA,0x8AFA,0xCAFA,0xABFA,0xAAFA,0xC8FA,0xC8FA,0xA6FA,0xE8FA,0xE7FA,0x29FB,0x09FB,0xE8FA,0xE9FA,0x09FB,0x2AFB,0x2BFB,0x6DFB,0x4DFB,0x0FFB,0x0EFB,0x0EFB,0x0FFB,0x6BFA,0xEBF1,0xAAFA,0xE9FA,0x0DFB,0x76AB,0x12D3,0x89FA,0x0DFB,0x47FA,0xC8FA,0x09FB,0x09FB,0xEAFA,0x0AFB,0xC9FA,0xAAFA,0xE9FA,0xC9FA,0xA9FA,0xC9FA,0x88FA,0x27FA,0x67FA,0x66FA,0x67FA,0x48FA,0x67FA,0x26FA,0x67FA,0x88FA,0xA8FA,0x87FA,0xA8FA,0x47FA,0x07FA,0x05FA,0xE5F9,0xC5F9,0x84F9,0x84F9,0xA3F9,0xA4F9,0xC4F9,0xC6FA,0x26FA,0xA3F9,0xA4F9,0x07FA,0xC6F1,0xA6F1,0x87E9,0xC8E9,0xA7E1,0xA6F1,0x85F9,0xC7F1,0x07FA,0xE6F9,0x44F1,0xA5F1,0x43E9,0xA3F9,0x83F1,0xE5F9,0xA5F1,0x65D9,0x04C9,0x0078,0x0070,0xC290,0x0569,0x0639,0x8420,0x0030,0x4448,0x6620,0x4630,0x2230,0x4430,0x4630,0x2630,0x2428,0x2320,0x0220,0x4208,0x2210,0x0120,0x0018,0x0010,0x0120,0x0110,0x2418,0x2410,0x2610,0x4508,0x2608,0x2508,0x2600,0x4408,0x4500,0x4508,0x6600,0x4300,0x4400,0x4308,0x4108,0x2100,0x4000,0x2008,0x0108,0x2000,0x2000,0x2000,0x0000,0x0000,0x0008,0x0000,0x0000,0x0008,0x0008,0x0008,0x2000,0x2000,0x2000,0x4000,0x4100,0x4100,0x4100,0x4200,0x4300,0x6400,0x4400,0x4308,0x6400,0x6500,0x8600,0x4608,0x8608,0x8600,0x8600,0x8408,0x8208,0x8208,0x8208,0x8208,0xA208,0xC308,0xC308,0xE308,0x0301,0x4301,0x6309,0xC111,0x200A,0x201A,0x801A,0xC022,0x4023,0xA033,0x003C,0x4054,0xE04C,0x404D,0x4165,0x436D,0x446D,0x056D,0xC76C,0x896C,0x0A64,0x8B63,0x4B63,0x2B63,0x2B63,0x4A6B,0x2A63,0x0A5B,0x0A63,0x0963,0xEA5A,0x095B,0xE95A,0xE95A,0xEA52,0xCA52,0xC95A,0xE95A,0xC95A,0xCA52,0xC95A,0xC952,0xC952,0xA952,0xA84A,0xA852,0xA952,0x8952,0x8A52,0x8952,0x8952,0x8952,0x8952,0x884A,0x694A,0x8852,0x894A,0x684A,0x6752,0x674A,0x684A,0x4842,0x6742,0x284A,}, +{0x08FB,0xC9FA,0xCAFA,0xAAFA,0x6AFA,0x89FA,0x69FA,0x68FA,0x68FA,0x65FA,0x27FB,0xC7FA,0xE7FA,0x28FB,0xE7FA,0xE8FA,0xE8FA,0xE9FA,0x09FB,0x2AFB,0x0AFB,0x4CFB,0x2EFB,0x0CFB,0x2FFB,0x6FFB,0x0EFB,0xCDFA,0x2CFB,0x4BFB,0x0EF3,0x7BA3,0xF2D9,0xC8F1,0xEAF1,0xE5F9,0x47FA,0x0BFB,0x0AFB,0x89FA,0xCAFA,0xC9FA,0x68FA,0x68FA,0xA8FA,0x88FA,0xA9FA,0xA8FA,0x25FA,0x88FA,0x88FA,0x67FA,0x47FA,0x88FA,0xA9FA,0xC9FA,0xC9FA,0xA9FA,0x87FA,0xC8FA,0xA8FA,0x66FA,0x46FA,0x47FA,0x67FA,0x26FA,0xE6F9,0x26FA,0x25FA,0x27FA,0xA7FA,0x47FA,0xE4F9,0x26FA,0x47FA,0x05FA,0xE5F9,0xC5F1,0x09F2,0xEAE9,0xE6E9,0x86E9,0x69E1,0x68D9,0x68E1,0x05D1,0x46D1,0x46E1,0x87E1,0x65D9,0xA6E9,0xC7D1,0x6899,0x0879,0x2278,0x0078,0x8288,0x6A59,0x6A29,0xAA18,0x0138,0x4640,0xA830,0x4828,0x2428,0x6A18,0x6920,0x4820,0x4728,0x2510,0x0420,0x2310,0x2310,0x0028,0x0020,0x0018,0x0018,0x2110,0x2318,0x2520,0x2520,0x4518,0x2710,0x4708,0x4700,0x6408,0x4508,0x6508,0x4608,0x6300,0x4308,0x4300,0x4208,0x4208,0x4100,0x4108,0x2100,0x0100,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x0008,0x0008,0x2008,0x4000,0x2008,0x2008,0x4008,0x2000,0x4000,0x4108,0x4308,0x4300,0x4400,0x4508,0x8400,0x6400,0x6508,0x6600,0x6708,0x8708,0xA600,0x6808,0x8608,0x8308,0x8210,0x8208,0x8208,0xA408,0xE400,0xE308,0xE200,0x2201,0x4201,0x6209,0xC009,0x000A,0x2012,0x601A,0xC01A,0x002B,0x6033,0xA043,0x0044,0x804C,0xE054,0x4055,0x6165,0x436D,0x256D,0xE76C,0xC874,0x686C,0xCB6B,0x6A6B,0x2B63,0x4B63,0x2A63,0x0B63,0xEB62,0x0A6B,0x095B,0xEA5A,0x095B,0xE95A,0x095B,0xEA5A,0xCA5A,0xCA5A,0xE95A,0xCA52,0xC952,0xC852,0xA95A,0xA95A,0xA952,0xA94A,0x8852,0xA852,0x884A,0x694A,0x894A,0xA852,0x6852,0x8952,0x684A,0x8852,0x884A,0x884A,0x884A,0x484A,0x684A,0x674A,0x4742,0x4742,0x274A,}, +{0x08FB,0xA8FA,0xA8FA,0x8AFA,0x8AFA,0x6AFA,0xA9FA,0x6AFA,0x47FA,0x67FA,0xA7FA,0x08FB,0x48FB,0x08FB,0xE6FA,0xE7FA,0xE8FA,0xC8FA,0xE8FA,0x2AFB,0x2AFB,0x0AFB,0xECFA,0x6CFB,0x0DFB,0x6DFB,0x90FB,0xEBFA,0x2CFB,0x6CFB,0x53EB,0xF8C2,0x48F1,0xCCF9,0x08FA,0xE8F9,0xC8F9,0x4BFA,0xE9F9,0xE8F9,0x28FA,0x29FA,0xE6F1,0xA6F9,0xE6F9,0x67F2,0x47FA,0x67FA,0x26FA,0xC9FA,0xE9FA,0x88FA,0x47FA,0x88FA,0xCAFA,0xEBFA,0xCAFA,0xEAFA,0xC9FA,0xC9FA,0xE9FA,0xC8FA,0xA8FA,0xA9FA,0xA8FA,0x67FA,0x87FA,0x68FA,0x87FA,0x88FA,0xC8FA,0xA8FA,0x46FA,0x67FA,0x67FA,0x66FA,0x06FA,0x05FA,0x68FA,0x27FA,0xA6F1,0xC9E9,0xA9E9,0xABE1,0x89D1,0x26D1,0x69C1,0x2BD9,0x4BC1,0x28B1,0x48B9,0x4991,0x4A81,0x2A81,0x6688,0x2088,0x6098,0x6A89,0xF239,0x7111,0x4548,0x0450,0x8948,0x8928,0x2430,0x8818,0x6918,0x4918,0x6910,0x6710,0x4520,0x0228,0x2520,0x0038,0x0020,0x0020,0x0020,0x0020,0x4118,0x2428,0x2328,0x4620,0x4520,0x4810,0x6608,0x8508,0x6408,0x6510,0x4508,0x8208,0x6310,0x6308,0x6308,0x4308,0x4208,0x4200,0x4108,0x2108,0x2100,0x2000,0x0008,0x0008,0x0000,0x0008,0x0000,0x0008,0x0008,0x2008,0x2008,0x2000,0x2008,0x2010,0x2008,0x4000,0x4108,0x2308,0x4208,0x4408,0x6400,0x6600,0x6508,0x4610,0x6608,0x4808,0x6808,0x8608,0x6808,0xA500,0x8310,0x8210,0xA210,0xA210,0xA408,0xE400,0xE408,0x2301,0x2209,0x4201,0x8109,0xE009,0x0012,0x201A,0x601A,0xA01A,0xE022,0x2023,0xA033,0xE033,0x403C,0x804C,0x0055,0x4155,0x2365,0x246D,0x066D,0xC86C,0x876C,0x0A74,0xCA6B,0x2A63,0x4A63,0x2A63,0x2A63,0x0A63,0x0A5B,0x0A63,0x0A5B,0x0A5B,0xEA62,0xEA5A,0xCA5A,0xAA5A,0xAA5A,0xC952,0xA95A,0xA852,0xA952,0xC85A,0x8952,0xA952,0xA852,0xA85A,0xA85A,0x8852,0x8952,0x894A,0x884A,0x8852,0x684A,0x694A,0x685A,0x684A,0x8842,0x684A,0x484A,0x684A,0x484A,0x484A,0x484A,0x274A,}, +{0xE8FA,0xA7FA,0x66FA,0x67FA,0x69FA,0x88FA,0xCBFA,0x89FA,0x49FA,0x29FA,0x68FA,0xA8FA,0x48FB,0xE6FA,0xE7FA,0x07FB,0x87FA,0x87FA,0xE8FA,0xC8FA,0x0AFB,0x08FB,0xC9FA,0x4DFB,0x0BFB,0x4EFB,0x4DFB,0x0AFB,0xEAFA,0x0BFB,0x36EB,0xEFE9,0xC8F9,0xCDF9,0x48FA,0xEAF1,0xE8F9,0x0AFA,0xABF1,0xA8F1,0xA6F9,0xE9F9,0xC8F1,0x27FA,0xE8F1,0x07DA,0x85E9,0xA6F1,0x06F2,0x88F2,0xEAFA,0xA9FA,0x68FA,0x68EA,0xCBF2,0xCAFA,0xCAFA,0x2BFB,0x4BFB,0x2BFB,0x0AFB,0xE9FA,0x09FB,0x0AFB,0xE9FA,0xC8FA,0xC8FA,0xA9FA,0xA9FA,0xCAFA,0xC8FA,0xE9FA,0xA9FA,0xA8FA,0xC8FA,0xA8FA,0x87FA,0x87FA,0x67FA,0x67FA,0x26FA,0xA6F1,0x09F2,0xEAF9,0x88E9,0x69E1,0xACD9,0x2CD9,0x0BC1,0x09A9,0x6CA9,0x8C99,0x6D89,0x2B91,0x8998,0x2098,0x4090,0xC598,0x7682,0x1732,0x8850,0x0070,0x4470,0x8A40,0x8640,0x8638,0x8728,0x6820,0x8818,0xA718,0x4528,0x0138,0x0438,0x0040,0x0038,0x0028,0x0020,0x0020,0x2028,0x2220,0x2328,0x2530,0x2428,0x6710,0x6618,0x6610,0x6410,0x6510,0x8410,0x8408,0xA408,0x8408,0x6408,0x4508,0x4408,0x4308,0x2308,0x2208,0x4100,0x2000,0x0008,0x2000,0x0008,0x2000,0x0000,0x0008,0x2000,0x2008,0x0008,0x2000,0x0008,0x2008,0x2008,0x4008,0x4108,0x2108,0x4108,0x4208,0x6308,0x4510,0x6508,0x6608,0x6608,0x6708,0x6808,0x8608,0xA708,0xC408,0xA410,0xA310,0x8310,0xA308,0xC408,0xE400,0x0401,0x2301,0x2209,0x6101,0xA001,0xC011,0x0012,0x2012,0x8012,0xA022,0xA02A,0x401B,0xA02B,0xA033,0x003C,0x603C,0xC04C,0x0055,0x215D,0x226D,0xE46C,0xC56C,0x876C,0x2874,0xE96B,0x6A63,0x4A63,0x2A63,0x2A63,0x2A63,0x0A5B,0xEA5A,0x0963,0xEA5A,0xEA5A,0xE95A,0xC952,0xE952,0xC95A,0xC95A,0xA95A,0xC95A,0xC852,0xA952,0xA952,0xA84A,0xA85A,0x8952,0xA94A,0x8952,0xA952,0x894A,0x694A,0x8852,0x894A,0x8852,0x6952,0x684A,0x6842,0x6842,0x684A,0x684A,0x484A,0x4742,0x4742,0x4742,}, +{0xC7FA,0x87FA,0x46FA,0x45FA,0x88FA,0xABFA,0xAAFA,0xA9FA,0x8BFA,0x48FA,0x6AFA,0xAAFA,0xA8FA,0x48FB,0xA7FA,0xA7FA,0xA6FA,0x87FA,0xC7FA,0xE7FA,0xC8FA,0xC8FA,0xE7FA,0xC8FA,0xEAFA,0xEBFA,0xA9FA,0xEAFA,0xC9FA,0xAAFA,0xF5FA,0x29FA,0x2CFA,0x0AFA,0x08FA,0xEAF9,0x2DFA,0x6CFA,0xEBF9,0x2BFA,0x47FA,0x49FA,0x09F2,0xA9FA,0xE8F1,0xE9E1,0x84E9,0xC6E1,0x49EA,0xA8EA,0x0CF3,0xEAF2,0xA9F2,0xEBF2,0x4DEB,0x4CFB,0x4CFB,0x4BFB,0x2BFB,0x0AFB,0x2AFB,0x2AFB,0x2AFB,0x4BFB,0x0AFB,0x09FB,0x09FB,0xEAFA,0xE9FA,0xEAFA,0x2AFB,0x28FB,0xE9FA,0xEAFA,0x09FB,0x09FB,0x08FB,0xA8FA,0x88FA,0x87FA,0x46FA,0x06FA,0x48FA,0x28FA,0xA5F1,0x67F1,0xEDF1,0xABE9,0x4BD9,0xE8B8,0x6FB9,0x6D99,0x6F89,0x2D89,0xEDA0,0x00A8,0x20A8,0x40A8,0x6DA1,0x7D62,0x3149,0x2088,0x0088,0x8960,0xCC60,0x6360,0x2250,0x6640,0xA828,0x8A30,0x8538,0x0058,0x0158,0x0050,0x0048,0x0040,0x0030,0x0028,0x0028,0x0030,0x2340,0x0440,0x2628,0x4818,0x6818,0x8818,0x6918,0x6710,0x8610,0x8710,0xA708,0x8608,0x6608,0x4608,0x6508,0x4408,0x4308,0x2408,0x2208,0x4100,0x2008,0x0008,0x0008,0x2008,0x0000,0x0010,0x0000,0x0008,0x2008,0x2000,0x2008,0x2008,0x2008,0x2008,0x4000,0x2108,0x2110,0x4108,0x4210,0x6310,0x6410,0x8508,0x4708,0x4608,0x4708,0x8708,0xA510,0xA510,0xC410,0xA308,0xA308,0xC308,0xC308,0xE400,0x0301,0x2301,0x2201,0x6201,0x8009,0xC011,0x0012,0x2012,0x601A,0x8022,0xC022,0x202B,0x402B,0x6033,0xE033,0x2034,0x4044,0xA04C,0x0055,0x015D,0xE264,0xC56C,0x8564,0x276C,0xC86B,0x8963,0x4A63,0x2A63,0x0A6B,0x0A63,0x0A5B,0x095B,0xEA62,0xEA5A,0xEA5A,0xE95A,0xE95A,0xCA5A,0xAA5A,0xA952,0xA95A,0x895A,0xC852,0xC952,0xA952,0xA852,0xA952,0x8952,0xA852,0x884A,0x8852,0x894A,0x8952,0x8852,0x694A,0x894A,0x884A,0x684A,0x4852,0x484A,0x684A,0x4742,0x484A,0x484A,0x474A,0x274A,}, +{0xA6FA,0xA6FA,0x46FA,0x65FA,0x67FA,0x68FA,0x67FA,0xABFA,0x69FA,0x89FA,0x6BFA,0x8BFA,0xA9FA,0xC8FA,0x68FA,0x86FA,0xA6FA,0xE7FA,0x86FA,0xE8FA,0xA7FA,0x66FA,0xC7FA,0xE8FA,0xC8FA,0xC8FA,0xA7FA,0xA7FA,0xC8FA,0x0BFB,0xB0FA,0x69FA,0x4CFA,0x48FA,0x49FA,0x2BFA,0x8EFA,0x8DFA,0xC9F9,0xACFA,0xACFA,0x8BFA,0x6CFA,0x4AFA,0xE8F1,0x2AFA,0x07EA,0x08EA,0x8CDA,0x69EA,0x2DEB,0x2BF3,0x4DFB,0x4DF3,0x8DFB,0x6DFB,0x0BFB,0x0BFB,0x0AFB,0x0AFB,0x4AFB,0x4AFB,0x4AFB,0x4BFB,0x2BFB,0x2AFB,0x2AFB,0x0AFB,0x2AFB,0x2AFB,0x6AFB,0x27FB,0x4BFB,0x0AFB,0x09FB,0x29FB,0x09FB,0xC9FA,0xA9FA,0x87FA,0x25FA,0x26FA,0x46FA,0x88FA,0x27FA,0x65F9,0x29FA,0xAAF1,0x89E9,0x28C9,0x6DC9,0x6FA1,0x8F99,0x4EA9,0x70C1,0x41B8,0x20C0,0x40C0,0x41C0,0x5792,0x3B6A,0x64A8,0x20A8,0x6490,0x1279,0x6178,0x0070,0x0260,0x6750,0xCB48,0x8940,0x0070,0x0090,0x0068,0x0060,0x0058,0x0048,0x0038,0x0028,0x0030,0x0040,0x0148,0x2438,0x4628,0x6918,0x8A18,0x6B20,0x6828,0xA720,0x8920,0xAA18,0x8810,0x8810,0x8710,0x6610,0x2710,0x4508,0x4408,0x4208,0x4100,0x0010,0x0008,0x0008,0x2000,0x0000,0x0008,0x0010,0x2008,0x2000,0x2008,0x2008,0x2010,0x4000,0x2108,0x4108,0x2108,0x2108,0x2210,0x4208,0x6108,0x6410,0x6410,0x6410,0x6508,0x6508,0xA510,0xA410,0xA510,0xC308,0xA308,0xC308,0xC408,0xC408,0x0301,0x2301,0x0309,0x2209,0x6001,0x8001,0xC011,0x000A,0x201A,0x6022,0xA01A,0xE022,0x0023,0x402B,0x6033,0x8033,0xC033,0x003C,0x4044,0xC044,0xC054,0xC15C,0xA454,0x645C,0x255C,0xE75B,0xA85B,0x6963,0x2A5B,0x0A5B,0x0A5B,0x095B,0xEA5A,0xEA62,0xC962,0xEA5A,0xCA5A,0xC95A,0xC952,0xAA5A,0xA95A,0xAA5A,0x8952,0xA95A,0xA952,0x8952,0xA952,0xA952,0x884A,0x8852,0x8842,0x8852,0x894A,0x6852,0x8952,0x6952,0x894A,0x8842,0x684A,0x484A,0x4852,0x484A,0x4742,0x474A,0x4742,0x4742,0x2842,}, +{0xC6FA,0x86FA,0x86FA,0x66FA,0x47FA,0x67FA,0x87FA,0x68FA,0x66FA,0xAAFA,0x8BFA,0x68FA,0x6AFA,0x48FA,0x29FA,0xA9FA,0x88FA,0xC8FA,0xE7FA,0xA7FA,0xA7FA,0x86FA,0xA7FA,0xE8FA,0xA6FA,0xC7FA,0xA7FA,0xA7FA,0x88FA,0x0AFB,0x89FA,0x47FA,0x28FA,0x67FA,0xABFA,0x6BFA,0xCDFA,0x8CFA,0x69FA,0xCBFA,0xACFA,0xCAFA,0xAAFA,0x87F1,0x08FA,0xCAFA,0xCAEA,0x68FA,0xE9E1,0x07EA,0xCCEA,0xEAFA,0x8CF2,0x0CF3,0x0CF3,0xCAF2,0xE9FA,0x0AFB,0xA9FA,0x88FA,0xE9FA,0xC9FA,0x4BFB,0x8CFB,0x2AFB,0x2AFB,0x49FB,0x09FB,0x0AFB,0x0AFB,0xC8FA,0x67FA,0xC9FA,0xE8FA,0x09FB,0x08FB,0x29FB,0x29FB,0xEAFA,0x87FA,0x88FA,0x67FA,0x48FA,0x47FA,0xC7F9,0xA5F9,0xE8F9,0x88F1,0xC9E9,0x89D1,0xA9E1,0xCDB9,0xCFA9,0x8CC1,0x6DD1,0x82D0,0x40D8,0x80D8,0x80D0,0x6AC9,0x1D93,0xECC0,0x60C0,0x20C0,0x1199,0xAA98,0x0098,0x0080,0x2368,0xAA60,0x8860,0x0070,0x20A0,0x0088,0x0078,0x0078,0x0068,0x0050,0x0038,0x0030,0x0038,0x0050,0x2030,0x2130,0x2538,0x6930,0x8C20,0x6730,0x8928,0xAC28,0xAC20,0x8C18,0x6B18,0x8A18,0x6720,0x4518,0x4418,0x6208,0x4208,0x2010,0x0018,0x0010,0x0010,0x0010,0x0000,0x0008,0x0010,0x2008,0x2008,0x2008,0x0110,0x2008,0x2000,0x4100,0x2108,0x2108,0x2110,0x4110,0x4108,0x6108,0x6208,0x6310,0x8310,0x6410,0x8310,0xA310,0xA408,0xA308,0xA208,0x8310,0xA308,0xE408,0xC508,0x0201,0x2101,0x2109,0x4101,0x8001,0x8009,0xA009,0xE011,0x2012,0x601A,0xA022,0xE022,0x2023,0x402B,0x2033,0x6033,0xA03B,0xA03B,0x003C,0x603C,0x604C,0x814C,0x6254,0x4354,0x245C,0xE55B,0xA753,0x885B,0x295B,0x2A63,0x0B63,0x095B,0xEA5A,0xEA62,0xEA5A,0xCA5A,0xEA5A,0xCA5A,0xE952,0xA95A,0xA952,0xC95A,0xA952,0xA952,0xA95A,0x895A,0x8952,0xA84A,0xA94A,0xA852,0x884A,0x884A,0x6852,0x8852,0x894A,0x6952,0x684A,0x6842,0x684A,0x484A,0x484A,0x4842,0x474A,0x474A,0x2742,0x284A,0x2742,}, +{0xA6FA,0xA7FA,0xA7FA,0x87FA,0x66FA,0x67FA,0x47FA,0x25FA,0xA8FA,0xEAFA,0x89FA,0xAAFA,0x8AFA,0x49FA,0x68FA,0x69FA,0xA9FA,0x67FA,0xC9FA,0xC7FA,0x67FA,0xE8FA,0xC8FA,0xA7FA,0xA7FA,0xA6FA,0xA7FA,0xA8FA,0x87FA,0xA8FA,0x87FA,0x88FA,0x67FA,0x67FA,0xA9FA,0xAAFA,0xABFA,0x69FA,0xA9FA,0xEBFA,0xC9FA,0x0AFB,0x89FA,0x45F9,0x06FA,0xEAFA,0x6CFB,0xE7F9,0x86F1,0xC7F1,0xAAEA,0x48FA,0xC8E9,0xC8E1,0xEAD9,0x2BCA,0x6ACA,0x4ADA,0x08C2,0x08C2,0x48E2,0x69E2,0x0BF3,0x4BF3,0x2AF3,0x0AFB,0x4AFB,0xA8F2,0x67F2,0xE9FA,0x86FA,0xE5E9,0x25EA,0xA7FA,0x2AFB,0x09FB,0xE8FA,0xE9FA,0x29F2,0xC9E9,0x89D9,0xA8E1,0xCBE9,0x29FA,0xA7F1,0xA7F1,0x07F2,0x67E9,0xA8F1,0x87F1,0xA5F1,0xCAF1,0xCBD9,0xAAD9,0xEDF1,0x05F1,0xC0E8,0x80F0,0xA0E8,0xA2E8,0x55BA,0x70D1,0xC0E0,0x80E0,0xA6C0,0xCDB0,0x61C0,0x20A8,0x2088,0x6668,0x8588,0x4190,0x8488,0x0080,0x2098,0x2098,0x2088,0x0070,0x0050,0x0038,0x0040,0x0058,0x0030,0x0030,0x2140,0x6740,0x8940,0x6440,0x8938,0xEC38,0xCC30,0xCC20,0x8C20,0x8A20,0x6728,0x6520,0x4420,0x2218,0x2018,0x0018,0x0018,0x0010,0x0010,0x2010,0x2010,0x0010,0x0010,0x0010,0x2008,0x2008,0x2008,0x2008,0x2108,0x2208,0x2108,0x4108,0x4108,0x4008,0x4108,0x4110,0x6208,0x4208,0x8208,0x8208,0x8208,0xA310,0x8408,0x8310,0xC208,0xA308,0xC408,0xE308,0xE308,0x2309,0x4101,0x4009,0x4109,0x8009,0x8011,0xC011,0xE011,0x2012,0x8012,0xA022,0xE01A,0x0023,0x202B,0x002B,0x402B,0x6033,0x803B,0xA03B,0x003C,0x403C,0x2044,0x414C,0x224C,0x2354,0xE553,0xC553,0x865B,0x685B,0x495B,0x0A5B,0xE95A,0xEA5A,0xEA5A,0xEA5A,0xCA5A,0xC962,0xE95A,0xC95A,0xA95A,0xA95A,0xC952,0xA852,0xA84A,0xA852,0x8952,0x8952,0xA95A,0xA852,0x8952,0x8852,0x8852,0x6952,0x884A,0x884A,0x6852,0x684A,0x884A,0x684A,0x684A,0x494A,0x474A,0x2742,0x4742,0x2742,0x284A,0x2642,}, +{0xC7FA,0xA7FA,0xA7FA,0x67FA,0x25FA,0x25FA,0x05FA,0x45FA,0x88FA,0x88FA,0x66FA,0xA9FA,0x88FA,0x69FA,0xAAFA,0x89FA,0x49FA,0x88FA,0x69FA,0x69FA,0x88FA,0xE8FA,0xE9FA,0x87FA,0xC8FA,0x08FB,0xE9FA,0xA9FA,0xA7FA,0xA7FA,0xA9FA,0xA8FA,0xA9FA,0x88FA,0xC9FA,0xCAFA,0xEAFA,0x68FA,0xC9FA,0x0BFB,0x09FB,0x2BFB,0x28FA,0xC5F9,0xC8FA,0x4BFB,0xACFB,0x47FA,0xC4F9,0x06FA,0xEBFA,0xC5F1,0x25E9,0x25E9,0xAAD1,0xAAB9,0x0BC2,0xEDB9,0x89A1,0xA899,0xA999,0xE9A1,0x4CBA,0x6CCA,0x29C2,0xABCA,0x2CF3,0x6AE2,0xE6D9,0xA9EA,0x27EA,0x87C1,0x42D9,0xE9E1,0x4BE2,0x09DA,0xC9D1,0xC8C9,0xA9D9,0xCDD9,0xCBE9,0xAAE1,0xEEE1,0xADFA,0xAAFA,0x8BFA,0xA8FA,0xE9F9,0xA7F9,0xA6F9,0x26FA,0xC6F9,0xC7F9,0x87F1,0x29FA,0xE7F9,0x00F9,0x02F9,0xE1F8,0xC0F8,0x89E9,0xD0E1,0x01F1,0xC1F0,0xC0E0,0xE7D0,0xA2D8,0xC1E0,0xA0B8,0x6088,0xC368,0xC5A0,0xC980,0x6188,0x20A0,0x00B0,0x40A8,0x0088,0x0060,0x0050,0x0050,0x0050,0x0040,0x0038,0x0038,0x4550,0x6758,0x4150,0x6848,0xCB38,0xCB38,0xCC28,0x8B28,0x6930,0x6638,0x6430,0x2230,0x2128,0x0020,0x0020,0x0020,0x0018,0x0010,0x0010,0x0010,0x0018,0x0018,0x0010,0x0010,0x2010,0x2108,0x2010,0x2108,0x2208,0x4208,0x2110,0x4108,0x6008,0x4110,0x6208,0x6108,0x6208,0x6308,0x8300,0xA308,0x8310,0xA410,0xC308,0xC408,0xC408,0xE408,0x0301,0x0309,0x2209,0x4001,0x6101,0x6009,0x8009,0x8009,0xA011,0xE001,0x200A,0x8012,0xA01A,0xC022,0x0023,0x2023,0x0023,0x0033,0x402B,0x4033,0x602B,0xA033,0xE033,0xE043,0x2044,0x2144,0x224C,0x234C,0x0554,0xC55B,0xA75B,0x875B,0x4A63,0x0A63,0x095B,0xCA5A,0xEA5A,0xEA5A,0xE95A,0xCA62,0xE85A,0xE95A,0xC952,0xA952,0xC952,0xA952,0xA85A,0xA952,0xA94A,0xA84A,0x884A,0x884A,0x8852,0x684A,0x694A,0x8952,0x8952,0x684A,0x6852,0x484A,0x694A,0x474A,0x4742,0x4842,0x4742,0x4742,0x4742,0x2742,0x0742,}, +{0xC7FA,0xC7FA,0x87FA,0x46FA,0x24FA,0x04FA,0x04FA,0x66FA,0x46FA,0x46FA,0x66FA,0x87FA,0x67FA,0x88FA,0x68FA,0x88FA,0x67FA,0x6AFA,0x89FA,0x47FA,0xA9FA,0xCAFA,0x88FA,0xC9FA,0xC8FA,0x0AFB,0x0AFB,0xE9FA,0xC8FA,0xE9FA,0x0AFB,0xC8FA,0xEAFA,0xE9FA,0x2AFB,0x2BFB,0x0BFB,0xABFA,0x0AFB,0x4BFB,0x6CFB,0x6CFB,0x69FA,0xC9FA,0x6BFB,0xCEFB,0x8CFB,0xEBFA,0xA7FA,0x0AFB,0x0BFB,0x84F9,0x04F9,0x45F1,0x67E1,0x8AC9,0xEAB9,0xABB9,0xA9B1,0x68A9,0x69A9,0xECA9,0x4EBA,0x4FC2,0x09BA,0x8DBA,0xADCA,0x6AD2,0x28E2,0x2DCA,0xE8C1,0x4991,0xC2D0,0x6CB1,0xCBA9,0xEDC1,0xCCB9,0xABC9,0xEED9,0x30E2,0x2CFA,0x2EF2,0x6FFA,0xEDFA,0x2BFB,0x8EFB,0x0AFB,0xC9FA,0x69FA,0x69FA,0xCAFA,0x26FA,0x47FA,0x27FA,0x06FA,0x8AFA,0xC4F9,0x06FA,0xC5F9,0x84F9,0x65F9,0xC9F1,0x42F9,0x84F9,0x02F9,0xC2F0,0x03F1,0x23F9,0x44F1,0xA0D0,0xC588,0x0871,0x2D91,0x84B0,0x20B8,0x20C0,0x41B0,0x4478,0x2368,0x0068,0x0068,0x0058,0x0070,0x0050,0x0040,0x2258,0x6368,0x4260,0x8960,0xAA50,0xAA48,0xCB40,0x6A38,0x6748,0x4350,0x4140,0x0050,0x0040,0x0028,0x0028,0x0030,0x0020,0x0010,0x0018,0x0018,0x0020,0x0018,0x0010,0x0018,0x2010,0x4108,0x2008,0x4108,0x2108,0x2110,0x4018,0x4110,0x4110,0x6208,0x8208,0x8210,0x4410,0x6408,0x6508,0x8408,0xE300,0xC308,0xE308,0xE508,0xE408,0x0409,0x2411,0x2311,0x4101,0x4001,0x8009,0x8009,0x8011,0xA009,0xA011,0xE009,0x200A,0x600A,0xA01A,0xE022,0xC022,0xE022,0x0023,0x002B,0x0023,0x402B,0x402B,0x6033,0x8033,0xA033,0x003C,0x0144,0x4244,0x6254,0x434C,0x2354,0xE65B,0xA76B,0x885B,0x6A63,0x095B,0xEA62,0xCA5A,0xE95A,0xE95A,0xCA5A,0xC95A,0xC952,0xAA52,0x895A,0xA952,0xA852,0x8852,0x8952,0xA94A,0x8952,0x8952,0x8852,0x884A,0x8852,0x684A,0x6952,0x694A,0x4852,0x684A,0x6852,0x484A,0x484A,0x474A,0x4842,0x4742,0x2742,0x273A,0x2742,0x0742,}, +{0xC7FA,0xC8FA,0xA7FA,0x66FA,0x25FA,0x04FA,0x45FA,0x25FA,0x04FA,0x46FA,0x46FA,0x66FA,0x66FA,0x67FA,0x67FA,0x66FA,0x88FA,0x87FA,0x89FA,0xA8FA,0xAAFA,0xAAFA,0xC9FA,0xCBFA,0xCAFA,0xCAFA,0xEAFA,0x4BFB,0x0AFB,0x2AFB,0x2AFB,0xE8FA,0xC8FA,0x6BFB,0x4CFB,0x2CFB,0x4CFB,0x0AFB,0x6CFB,0xCDFB,0xEEFB,0x6CFB,0xEBFA,0x8DFB,0x0FFC,0x30FC,0x6CFB,0xEDFB,0x8CFB,0x6DFB,0xC9FA,0xC5F9,0xC3F9,0x84F9,0x24E9,0x67D9,0xC9D1,0xCCC9,0xCAC1,0xA9C1,0x88B9,0xEBB9,0x2DCA,0x8ECA,0xE9C1,0x0BCA,0x6EDA,0x6CDA,0xA5C9,0x2FC2,0x4BDA,0x4DC2,0xC6F1,0xCDC9,0xAAB1,0xCFB9,0x8EB9,0x88E1,0x30EA,0x6DFA,0xCEFA,0xEFFA,0x12FB,0x2EFB,0x8CFB,0xCEFB,0x4CFB,0xEAFA,0xCAFA,0xE9FA,0x4BFB,0xA8FA,0x67FA,0x68FA,0x47FA,0x0AFB,0xC9FA,0x67FA,0x67FA,0x27FA,0xE6F9,0xE6F9,0xC7F9,0xE6F9,0xA3F9,0x23F9,0x64F9,0x63F9,0x84F9,0xC2F0,0xC7C8,0xE778,0x0999,0xA4C8,0x40D8,0x40C8,0x41B8,0x8A68,0xAB40,0x2380,0x0080,0x0170,0x0180,0x0080,0x2068,0x2060,0x4070,0x6370,0x8670,0xA868,0xA968,0xC950,0x8658,0x6458,0x4068,0x2060,0x2060,0x0058,0x0048,0x0038,0x0040,0x0030,0x0020,0x0018,0x0020,0x0020,0x0020,0x0020,0x0018,0x0018,0x2110,0x6008,0x2110,0x4108,0x4118,0x4210,0x4210,0x6210,0x6210,0x6210,0x6308,0x6410,0x8308,0x8510,0xA410,0xE408,0xC510,0xC408,0x0309,0x0501,0x0409,0x2409,0x4211,0x6001,0x8009,0x8009,0xA009,0xA011,0xA009,0xA011,0xC009,0x000A,0x2012,0x601A,0xC01A,0xC022,0xC022,0x002B,0x0033,0x001B,0xE022,0x2023,0x402B,0x6033,0xA033,0xE03B,0x404C,0x6144,0x824C,0xA34C,0x8454,0x4664,0x0664,0xC75B,0xA85B,0x495B,0x095B,0xEA5A,0xC95A,0xC95A,0xA95A,0xA95A,0xC952,0xA952,0xA952,0xA952,0xC852,0x874A,0xA852,0x894A,0x8952,0x6852,0x6852,0xA84A,0x894A,0x6952,0x6952,0x684A,0x684A,0x684A,0x484A,0x684A,0x4842,0x2742,0x4842,0x2742,0x2742,0x0742,0x073A,0x0742,}, +{0x87FA,0xA8FA,0xA8FA,0x25FA,0x24FA,0x66FA,0x45FA,0x05FA,0x24FA,0x05FA,0x25FA,0x66FA,0x67FA,0x87FA,0x87FA,0x87FA,0x86FA,0x87FA,0xA8FA,0xE9FA,0xEAFA,0xCAFA,0xE9FA,0xEBFA,0x0CFB,0xCAFA,0x09FB,0x4CFB,0x6CFB,0xACFB,0x4BFB,0x4BFB,0x08FB,0x8CFB,0x4CFB,0x6BFB,0x2CFB,0x6BFB,0xADFB,0x0FFC,0x50FC,0x6CFB,0x4CFB,0x50FC,0x71FC,0xEFFB,0x8DFB,0x6FFC,0x4FFC,0x6CFB,0xC8FA,0x27FA,0x46FA,0x64F9,0x01F1,0x84F1,0xE6E9,0x2BEA,0xC6E1,0xEAE1,0xE9D1,0xECD1,0x0EE3,0xD0DA,0xE9C9,0xCBD9,0x0DDA,0x4DE2,0x06EA,0x0FCA,0x0ADA,0x4DC2,0x0BFB,0xAEEA,0x0CDA,0xEFB9,0xADD9,0xCBE9,0xEEF1,0x4CFA,0x8DFA,0xEDFA,0x50FB,0x4DFB,0xACFB,0xEEFB,0x6CFB,0x2CFB,0x0BFB,0x2AFB,0xABFB,0x0AFB,0xA8FA,0x88FA,0x89FA,0x08FB,0x6CFB,0xA7FA,0xA8FA,0x87FA,0x67FA,0x47FA,0xABFA,0x68FA,0x47FA,0xC5F9,0xC6F9,0xC5F9,0xC5F9,0x43F9,0x05E1,0xA3C0,0xE6A8,0xE4D8,0x61E8,0x60E0,0x60D0,0x46A0,0x7148,0x4B78,0x2098,0x2178,0x2098,0x20A0,0x2098,0x4090,0x2080,0x4180,0x8170,0xA378,0x8570,0x8370,0x4178,0x4070,0x4070,0x2078,0x0070,0x2070,0x2060,0x0050,0x0048,0x0040,0x0030,0x0028,0x0020,0x0028,0x0028,0x0028,0x0020,0x0020,0x0018,0x4010,0x4118,0x2218,0x4110,0x4210,0x6210,0x4118,0x6210,0x6210,0x6318,0x6518,0xA310,0xA310,0xA410,0xC408,0xE508,0xC610,0x0301,0x0209,0x0309,0x2209,0x4009,0x8001,0x8009,0xA011,0xA009,0xC001,0xC009,0xA011,0xC009,0x0002,0x2012,0x4012,0x601A,0xA022,0xA022,0xC02A,0xC022,0xC022,0xE022,0x002B,0x202B,0x4033,0x603B,0xC03B,0x0044,0x814C,0xA254,0xC254,0xC34C,0xC35C,0x645C,0x265C,0xE75B,0x8963,0x2A5B,0xE952,0xE852,0xC95A,0xC95A,0xA952,0xAA52,0xA952,0xA952,0x8852,0xA952,0x894A,0xA952,0x894A,0x884A,0x8952,0x694A,0x684A,0x684A,0x884A,0x684A,0x684A,0x6842,0x4842,0x4842,0x4752,0x4842,0x2742,0x2742,0x4842,0x2742,0x0742,0x2742,0x073A,}, +{0x25FA,0x86FA,0x27FA,0x05FA,0x87FA,0x45FA,0x04FA,0x04FA,0x23FA,0x25FA,0x45FA,0x45FA,0xA7FA,0x87FA,0x87FA,0x86FA,0x86FA,0xC7FA,0xC7FA,0x2BFB,0xE9FA,0xE8FA,0xE8FA,0x0AFB,0x0BFB,0xEAFA,0x4BFB,0x4BFB,0xAEFB,0x8DFB,0x8DFB,0x6CFB,0x8BFB,0xCCFB,0x6BFB,0xCDFB,0xACFB,0x0EFC,0xEFFB,0x6FFC,0x51FC,0xADFB,0xCEFB,0x92FC,0x30FC,0xEEFB,0xAEFB,0x2FFC,0x8FFC,0x2BFB,0xC8FA,0xC8FA,0xA9FA,0x85F9,0x62F9,0x46FA,0x68FA,0x48FA,0xE6F9,0x2AF2,0x09EA,0x09E2,0xCEF3,0xCEEA,0x08D2,0x0BEA,0x2DF2,0x6FEA,0x2CFB,0x0FDA,0x4AF2,0x2DDA,0xC9FA,0xCBEA,0x10F3,0x4EDA,0x2DF2,0x4DFA,0x2AFA,0x6BFA,0x69FA,0x0AFB,0x2BFB,0x6BFB,0x8BFB,0xADFB,0x8DFB,0x6CFB,0x6CFB,0x4BFB,0xACFB,0x8DFB,0xE9FA,0xA9FA,0xC9FA,0x08FB,0xABFB,0x2AFB,0xE9FA,0x09FB,0xC8FA,0x68FA,0xA9FA,0xCAFA,0xA8FA,0x48FA,0x06FA,0x05FA,0x26FA,0xE5F9,0x43F9,0xC1F0,0xE3B0,0x04D1,0xC2F0,0x80F0,0x60F0,0x20E0,0x49A8,0x8F70,0x46B8,0x6390,0x01B0,0x60B8,0x60C0,0x80B8,0x40B0,0x6098,0x6088,0x8088,0x4098,0x4090,0x4090,0x6088,0x2088,0x6080,0x4080,0x2080,0x2070,0x2068,0x0060,0x0048,0x0040,0x0040,0x0030,0x0030,0x0030,0x0030,0x2020,0x2020,0x0028,0x2020,0x2020,0x4018,0x4120,0x2020,0x4118,0x4120,0x4118,0x6118,0x6220,0x8318,0xA318,0xA310,0xA318,0xC510,0x0409,0x0511,0x0309,0x2109,0x2109,0x2009,0x4009,0x6001,0x6011,0x8011,0xA011,0xC009,0xC009,0xC011,0xC009,0xE009,0x0012,0x200A,0x2012,0x401A,0x6022,0x8022,0x8022,0xA01A,0xC022,0xC022,0xE02A,0x402B,0x803B,0xA043,0x0044,0x4144,0x804C,0xE154,0x0255,0x035D,0x035D,0xA55C,0x4664,0xE75B,0xA963,0x295B,0xE95A,0xEA5A,0xC95A,0xA952,0x8A52,0xA952,0xA952,0x8952,0x895A,0xA84A,0xA952,0x8852,0x8852,0x884A,0x8952,0x6852,0x6852,0x684A,0x4952,0x684A,0x4852,0x2852,0x4742,0x2742,0x2742,0x2842,0x2842,0x2842,0x273A,0x0742,0x2642,0x0742,}, +{0xC3F9,0x04FA,0xE4F9,0x46FA,0x46FA,0x86FA,0x45FA,0x04FA,0x05FA,0x25FA,0x45FA,0x65FA,0x86FA,0x66FA,0x66FA,0x66FA,0xC7FA,0xA7FA,0x6AFB,0xAAFA,0xE9FA,0x08FB,0xE9FA,0x4AFB,0x29FB,0x2AFB,0x2AFB,0x4CFB,0x6CFB,0x4BFB,0x6DFB,0x6DFB,0xCCFB,0x0DFC,0xECFB,0xEFFB,0x0FFC,0x4FFC,0xEEFB,0x90FC,0x71FC,0xEEFB,0x30FC,0xB3FC,0x0FFC,0xEEFB,0xCEFB,0x0EFC,0x4FFC,0x6CFB,0xCAFA,0x2AFB,0xC9FA,0x26FA,0x04FA,0xE8FA,0x4BFB,0xEBFA,0xA9FA,0x89FA,0x27F2,0x47F2,0x0FFC,0xEBF2,0x08EA,0x4AF2,0x4BFA,0x4DF2,0x8DFB,0xCEE9,0x68F2,0x09DA,0x2BFB,0xC9E2,0x2FEB,0x6BF2,0x0EFB,0x2DFB,0xEBFA,0xECFA,0xA9FA,0xEAFA,0x4BFB,0x4BFB,0x4CFB,0x8DFB,0x8CFB,0xACFB,0x6BFB,0x4CFB,0x6CFB,0x8BFB,0x2AFB,0x0AFB,0x0AFB,0x2AFB,0x89FB,0xABFB,0x0AFB,0x4BFB,0x2BFB,0xC8FA,0xC8FA,0x2DFB,0x2BFB,0xCAFA,0xA8FA,0x68FA,0x47FA,0x26FA,0xE6F9,0x83F9,0x24E1,0xE7B8,0x25F1,0xE1F8,0xE0F0,0x80F8,0x82E8,0x68B0,0xA8A0,0xA2B0,0x40C0,0xA0C0,0x60D8,0xA0D8,0x80C8,0x80C0,0x60B8,0x60A8,0x60A8,0x60B0,0x40A0,0x40A0,0x2098,0x6098,0x4098,0x40A0,0x4088,0x2080,0x0070,0x0068,0x0058,0x0048,0x0040,0x0040,0x0048,0x0048,0x0038,0x0030,0x0030,0x2028,0x4020,0x4020,0x2120,0x0030,0x2120,0x4118,0x4028,0x4020,0x4128,0x6128,0x6228,0x6228,0xA218,0xA418,0xC418,0x0209,0x0209,0x0001,0x2001,0x2009,0x4009,0x4009,0x6011,0xA009,0xA011,0xA009,0xC011,0xC011,0xC011,0xC009,0xC009,0xE009,0xE011,0x0012,0x201A,0x2022,0x601A,0x801A,0xA01A,0xA02A,0xE022,0x002B,0x602B,0x8033,0xC03B,0x203C,0x6044,0xC044,0xE254,0x215D,0x0365,0x0465,0xA55C,0x665C,0xE85B,0xA863,0x495B,0xE952,0xC952,0xA952,0xA952,0xA952,0xA952,0xA95A,0x895A,0x8952,0x8852,0x894A,0x8852,0x8952,0x874A,0x684A,0x884A,0x884A,0x494A,0x6852,0x284A,0x484A,0x484A,0x4852,0x284A,0x4742,0x2842,0x273A,0x273A,0x0642,0x0642,0x063A,}, +{0xE3F9,0x04FA,0x24FA,0x05FA,0xE5F9,0x27FA,0x46FA,0x66FA,0x24FA,0x45FA,0x46FA,0x46FA,0x26FA,0x45FA,0x65FA,0x87FA,0x66FA,0xE8FA,0xC9FA,0x26FA,0x2BFB,0x2AFB,0x09FB,0x2AFB,0x2AFB,0x2AFB,0x4AFB,0x6CFB,0xACFB,0x6BFB,0x4BFB,0xADFB,0x6BFB,0xCDFB,0xCDFB,0xCEFB,0x10FC,0x0EFC,0xCEFB,0x91FC,0x71FC,0x0FFC,0x10FC,0xD1FC,0xEEFB,0x0FFC,0xEEFB,0x4EFC,0x4FFC,0x8CFB,0x2AFB,0xACFB,0xEAFA,0xA9FA,0x87FA,0x49FB,0x8CFB,0x8DFB,0x6CFB,0x2CFB,0xEAFA,0x2BFB,0x91FC,0xEAFA,0x06FA,0x06FA,0x27FA,0x28FA,0x8CFB,0x4BEA,0x45FA,0x46F2,0x4AFB,0x4BF3,0x6EFB,0xEAFA,0xEBFA,0x4DFB,0x0AFB,0x0AFB,0xA8FA,0xE9FA,0x4BFB,0x2BFB,0x0AFB,0x4BFB,0x8CFB,0xADFB,0x8CFB,0x6BFB,0x6AFB,0x6BFB,0x2BFB,0x2AFB,0x4AFB,0x6BFB,0x2AFB,0x6AFB,0x09FB,0x0BFB,0x4DFB,0xE9FA,0x4BFB,0x0CFB,0x8CFA,0xAEFA,0xEAFA,0xAAFA,0xA9FA,0x68FA,0x68FA,0x46FA,0x06FA,0xE6E0,0x28E1,0x44F9,0x24F9,0x03F9,0xE2F8,0xE3F0,0xC4C0,0xC2D0,0xA0D8,0xA0D0,0xC0E8,0xE1E8,0xE0E0,0xC0D8,0x80D8,0x80C8,0xA0C0,0x60C0,0x80B8,0x20C0,0x80B0,0x60B0,0x60B0,0x60A8,0x20A0,0x20A0,0x4090,0x4070,0x0068,0x0058,0x0050,0x0050,0x0050,0x0050,0x0050,0x0048,0x2040,0x0038,0x2030,0x2030,0x2030,0x4028,0x4028,0x4120,0x4028,0x4028,0x4130,0x4130,0x4138,0x6128,0x6028,0xA220,0xC220,0x0009,0x0011,0x0001,0x0001,0x0009,0x2009,0x2009,0x6009,0x8011,0xA011,0xA011,0xC009,0xC009,0xC009,0xA011,0xC009,0xC009,0xC001,0xC009,0xC011,0x0012,0x4012,0x4022,0x601A,0xA022,0xC022,0xE02A,0x202B,0x602B,0x8033,0xC02B,0x4034,0xA13C,0xE154,0x215D,0x6265,0x4365,0x0455,0xC55C,0x4664,0xC763,0x885B,0x2853,0xCA52,0xA95A,0xA952,0x8952,0x8952,0x8852,0xA84A,0x6952,0x8852,0x8852,0x6852,0x6952,0x884A,0x684A,0x6852,0x684A,0x484A,0x494A,0x2842,0x4842,0x284A,0x4842,0x2842,0x284A,0x2742,0x2742,0x273A,0xE741,0x0742,0xE741,}, +{0x24FA,0x44FA,0x05FA,0xE4F9,0x06FA,0xC7F9,0x27FA,0x06FA,0x45FA,0x67FA,0x66FA,0x66FA,0x25FA,0x46FA,0x65FA,0x05FA,0x46FA,0x46FA,0x42F9,0xA8FA,0x2BFB,0x4BFB,0x09FB,0x0AFB,0x4CFB,0x4BFB,0x8BFB,0x8CFB,0xEDFB,0x8CFB,0x6CFB,0x8EFB,0xADFB,0xEDFB,0xCDFB,0xCDFB,0xEFFB,0x2EFC,0xEEFB,0x92FC,0x71FC,0x0EFC,0x0FFC,0xB1FC,0x0EFC,0xEEFB,0xCFFB,0x70FC,0x50FC,0x6CFB,0x4AFB,0xCDFB,0x0BFB,0x0AFB,0x09FB,0xACFB,0xEEFB,0xF0FB,0xEFFB,0xAEFB,0x8DFB,0xCDFB,0x51FC,0x0AFB,0x68FA,0x27FA,0xE4F9,0xA8FA,0x2BFB,0xEAFA,0x85FA,0x29FB,0xC7FA,0x6CFB,0xCEFB,0x6BFB,0x09FB,0x6DFB,0x0AFB,0x2BFB,0x88FA,0xE9FA,0x6CFB,0x0BFB,0x09FB,0x0AFB,0xADFB,0xAEFB,0xADFB,0x6CFB,0x6BFB,0xADFB,0x6CFB,0x2BFB,0x4BFB,0xADFB,0x6BFB,0x4BFB,0x0BFB,0xCAFA,0x0BFB,0x0AFB,0x6DFB,0x6DFB,0xCBFA,0xAFFA,0x4DFB,0x4CFB,0x0CFB,0xC9FA,0xCAFA,0x88FA,0x47FA,0xC6F9,0x26E9,0x45F9,0xC6F9,0xA6F9,0xA5F9,0xA5F9,0x65F1,0x24F1,0x22F1,0xA2E8,0xC1F0,0x63F9,0x22F9,0xE0F0,0xC0E8,0xC0E0,0xC0D8,0x80D0,0x80D0,0x80D0,0xA0C0,0x60C0,0x40C0,0x60B8,0x20B8,0x40B0,0x80A0,0x6088,0x2080,0x2070,0x2060,0x0058,0x0058,0x0058,0x2060,0x2058,0x2050,0x2040,0x2048,0x0040,0x2040,0x4040,0x0038,0x4030,0x4030,0x2038,0x2038,0x2040,0x2040,0x4038,0x6038,0xA030,0xC020,0xE018,0xE018,0xE008,0xE008,0xE008,0xE008,0x0009,0x4001,0x6009,0x8009,0x8009,0x8009,0x8011,0xA009,0x8011,0xA009,0xA009,0xA011,0xA011,0xA011,0xC011,0x0012,0x201A,0x401A,0x8022,0xA02A,0xC022,0x0023,0x0023,0x202B,0x8023,0xC02B,0x4034,0xA044,0x2055,0x625D,0x6365,0x625D,0xE45C,0x8564,0x6554,0xC75B,0x885B,0x295B,0xE85A,0x895A,0xA952,0x885A,0xA852,0x8952,0x885A,0x6952,0x6952,0x6952,0x6852,0x694A,0x694A,0x6852,0x484A,0x484A,0x484A,0x484A,0x4842,0x4742,0x2742,0x284A,0x0742,0x2742,0x0642,0x0742,0x073A,0x073A,0xE639,}, +{0x65FA,0x45FA,0x04FA,0x25FA,0x05FA,0xC7F9,0xC6F9,0xE8F9,0xC6F9,0x68FA,0xC8FA,0x65FA,0x87FA,0x86FA,0x26FA,0x04FA,0x27FA,0x02F9,0x21F1,0xA8FA,0x2AFB,0x09FB,0x08FB,0x2BFB,0x6CFB,0x4BFB,0xACFB,0xACFB,0xCDFB,0xEDFB,0xADFB,0x8DFB,0xCEFB,0x0EFC,0xEEFB,0xEDFB,0xEFFB,0x50FC,0x0EFC,0x71FC,0x71FC,0x0EFC,0xEFFB,0x50FC,0xEEFB,0xEDFB,0xEEFB,0x4FFC,0x0EFC,0x6CFB,0x6BFB,0x6BFB,0x2BFB,0x6BFB,0x4BFB,0x0DFC,0x70FC,0x71FC,0x50FC,0x31FC,0x0EFC,0x0FFC,0x0FFC,0x6CFB,0xEAFA,0xA8FA,0x06FA,0x0AFB,0x2AFB,0x4CFB,0x08FB,0xEDFB,0x44FA,0x8BFB,0x0DFC,0xACFB,0x09FB,0x8EFB,0x2AFB,0x2BFB,0x67FA,0xEAFA,0x6DFB,0x4CFB,0x4BFB,0xE9FA,0x8DFB,0xAEFB,0x8CFB,0x6CFB,0x6BFB,0xCEFB,0x8CFB,0x4CFB,0x2AFB,0xAEFB,0x8CFB,0x4BFB,0x0AFB,0x0AFB,0xE9FA,0x0AFB,0x4CFB,0xAFFB,0x6EFB,0x4DFB,0x8DFB,0x6DFB,0x0BFB,0xEAFA,0xEBFA,0x88FA,0x68FA,0x69FA,0xE6F9,0x85F9,0x28FA,0x27FA,0x68FA,0x8AFA,0x47FA,0xE6F9,0xC5F9,0x64F9,0x02F9,0xA4F9,0xA5F9,0x01F9,0xE1F0,0xE1F0,0xE1F0,0xC1E0,0xA0E0,0xA0D8,0xA0D8,0x80D0,0x60D0,0x60C0,0x40C0,0x40C0,0x80B0,0x60B0,0x6090,0x4080,0x4078,0x2070,0x2068,0x2068,0x2068,0x4068,0x2068,0x2058,0x0058,0x2058,0x2050,0x2048,0x2048,0x2040,0x2048,0x4048,0x2050,0x0050,0x0050,0x2048,0x6040,0x8038,0xA030,0xA020,0xC020,0xC018,0xC008,0xE008,0xE008,0x0009,0x2009,0x4001,0x6009,0x4011,0x4009,0x6011,0x6009,0x8011,0x8011,0x8011,0x8011,0xA011,0xC009,0xC011,0xE011,0x0012,0x4012,0x4012,0x8022,0xC022,0xC02A,0xC022,0xE02A,0x202B,0x6023,0xE02B,0x803C,0xC054,0x4155,0x8255,0x8365,0x6365,0x035D,0xA45C,0x4554,0xC763,0x485B,0x0853,0xC952,0xA952,0x895A,0xA952,0xA952,0x8852,0x894A,0x8852,0x8852,0x684A,0x684A,0x684A,0x684A,0x684A,0x4852,0x484A,0x484A,0x4742,0x4742,0x2742,0x2742,0x0742,0x2742,0x0742,0x0642,0x063A,0x073A,0xE739,}, +{0x85FA,0x24FA,0x44FA,0xE4F9,0xE5F9,0xC5F9,0xE7F9,0xA7F9,0xC8F9,0x49FA,0x47FA,0xE8FA,0x87FA,0x87FA,0xC3F9,0x45FA,0x43F9,0x80F8,0xA4F9,0xC8FA,0x09FB,0x87FA,0xC9FA,0xE9FA,0x09FB,0x4BFB,0x8DFB,0x8BFB,0x8CFB,0xADFB,0xEDFB,0xADFB,0xADFB,0xADFB,0x0FFC,0xEDFB,0xAEFB,0x30FC,0x0DFC,0x0EFC,0x30FC,0x2EFC,0xCDFB,0xEFFB,0xEEFB,0x0DFC,0xEDFB,0x4FFC,0xCDFB,0x6BFB,0x6BFB,0x8BFB,0xACFB,0xEDFB,0xCCFB,0x6FFC,0xD3FC,0xF3FC,0xB2FC,0x92FC,0x71FC,0x91FC,0x2FFC,0xEEFB,0xACFB,0x2BFB,0xC9FA,0x8BFB,0x0BFB,0x09FB,0xABFB,0x30FC,0x65FA,0xACFB,0x4FFC,0xEDFB,0x29FB,0x4BFB,0xE9FA,0x2BFB,0xA8FA,0x0AFB,0x6DFB,0x4DFB,0x6CFB,0xE8FA,0x6DFB,0xCFFB,0x8DFB,0x4CFB,0x4CFB,0xAEFB,0x6CFB,0x4CFB,0x2BFB,0xAEFB,0xADFB,0x6CFB,0x4CFB,0x0BFB,0xEAFA,0x6BFB,0x8CFB,0xCFFB,0xD0FB,0x4CFB,0x6CFB,0x4DFB,0xE9FA,0xEAFA,0x0BFB,0xC9FA,0x88FA,0x68FA,0x48FA,0x28FA,0x69FA,0x89FA,0x88FA,0x89FA,0x88FA,0x67FA,0x68FA,0xE5F9,0x43F9,0xE5F9,0x07FA,0x83F9,0x23F9,0xE1F8,0xE1F8,0xE2F0,0xE1E8,0xC0E8,0xC1E8,0xC0E0,0xA0D0,0x80C8,0x60D0,0x60C8,0x80C0,0xA0C0,0xA0B0,0x60A0,0x4090,0x4080,0x6078,0x2078,0x2078,0x4070,0x4068,0x4068,0x4060,0x2068,0x4058,0x4058,0x4058,0x2058,0x4050,0x0060,0x2058,0x2058,0x0060,0x4058,0xA048,0xA030,0xA028,0xA028,0xC010,0xC008,0xC008,0xE008,0xE008,0x0009,0x0009,0x4009,0x4009,0x4011,0x4009,0x4009,0x6009,0x6011,0x8011,0x8011,0x8011,0x8011,0xC011,0xE011,0xE019,0x001A,0x201A,0x401A,0x601A,0xA01A,0xC022,0xE01A,0xC022,0x001B,0x401B,0xA023,0x2034,0xA044,0x204D,0x6245,0x8255,0x815D,0x2265,0xE35C,0x6354,0x0454,0x6753,0x2853,0xE95A,0xC952,0xC852,0xA852,0x8952,0x894A,0x884A,0x8952,0x694A,0x684A,0x684A,0x484A,0x684A,0x684A,0x684A,0x484A,0x284A,0x4842,0x2742,0x2742,0x2742,0x0742,0x2742,0x0642,0x073A,0x073A,0xE639,0xE739,}, +{0x85FA,0x66FA,0x45FA,0x25FA,0xE4F9,0x04FA,0x27FA,0x28FA,0x4BFA,0x2AFA,0x07FA,0x47FA,0x69FA,0xE6F9,0x86FA,0x83F9,0xC0F8,0x80F0,0x67FA,0x2AFB,0x47FA,0x04FA,0x46FA,0xA7FA,0x88FA,0xE8FA,0x2AFB,0x4BFB,0x4AFB,0x4BFB,0x8CFB,0xACFB,0x6BFB,0x6CFB,0xEEFB,0xADFB,0x8BFB,0xCEFB,0x2EFC,0xCDFB,0xEFFB,0x2EFC,0xADFB,0xCDFB,0xCCFB,0xCBFB,0xACFB,0x0DFC,0xACFB,0x4AFB,0x6BFB,0xCCFB,0x0EFC,0x2FFC,0x2EFC,0x91FC,0x14FD,0x34FD,0x13FD,0xF3FC,0xD3FC,0xF2FC,0x91FC,0x50FC,0x0EFC,0xADFB,0x2AFB,0xCDFB,0xEAFA,0xC8FA,0x4FFC,0x71FC,0xC7FA,0xECFB,0x2FFC,0xEEFB,0x4AFB,0xC9FA,0xEAFA,0x4AFB,0x0AFB,0xA9FA,0x8DFB,0x6CFB,0x4DFB,0xC9FA,0xADFB,0x32FC,0xAFFB,0x4BFB,0x6BFB,0xAEFB,0x6DFB,0x6CFB,0x4BFB,0x8CFB,0xAEFB,0x8EFB,0x8EFB,0xCBFA,0xEAFA,0xABFB,0xCDFB,0xACFB,0xB0FB,0x4DFB,0x0AFB,0x4DFB,0x2AFB,0xE8FA,0xEAFA,0xECFA,0xEAFA,0xAAFA,0xAAFA,0x68FA,0x89FA,0xC9FA,0x88FA,0xA8FA,0xC9FA,0xA9FA,0x8AFA,0x46FA,0xC5F9,0xC5F9,0x48FA,0x06FA,0x84F9,0x42F9,0x42F9,0x02F9,0x02F9,0xE1F0,0xE1E8,0xC1E8,0xA0E0,0x80D8,0x40D8,0x60D8,0xA0D0,0xC0C8,0xC0C8,0x80C0,0x80A0,0x4098,0x4090,0x2088,0x4078,0x2078,0x4070,0x6068,0x6070,0x6070,0x6060,0x4068,0x2070,0x4068,0x6068,0x4060,0x6058,0x4060,0x6060,0x8058,0xA038,0xC028,0xC018,0xC018,0xC008,0xE000,0xE008,0x0001,0x0001,0xE008,0x2009,0x4009,0x6009,0x4009,0x2009,0x2009,0x2009,0x4009,0x6009,0x8009,0x8011,0xA019,0xE009,0xC011,0xE011,0x001A,0x001A,0x401A,0x801A,0x801A,0xC022,0xC022,0xE022,0xC01A,0x0013,0x401B,0xC023,0x403C,0x0145,0x414D,0x8155,0xA155,0x615D,0x0255,0xA254,0x434C,0xC443,0x464B,0xE852,0xC852,0x895A,0xA84A,0xA952,0x8852,0xA952,0x6952,0x4852,0x6852,0x684A,0x6842,0x6742,0x674A,0x484A,0x484A,0x084A,0x484A,0x4742,0x2742,0x263A,0x273A,0x073A,0x2642,0x073A,0xE639,0xE739,0xC639,}, +{0xE7FA,0xA7FA,0xA6FA,0x86FA,0x25FA,0x24FA,0x46FA,0x68FA,0x2AFA,0x0AFA,0x88F9,0x88F1,0x65F9,0x88FA,0x47FA,0x42F9,0xC0F8,0xE0F0,0x09FB,0x0BFB,0x84F9,0x06FA,0x25FA,0x25FA,0x87FA,0xA7FA,0xC8FA,0xEAFA,0xE9FA,0x08FB,0x2AFB,0x6AFB,0x6BFB,0x6BFB,0xADFB,0xCDFB,0xCDFB,0xCEFB,0xEDFB,0xCCFB,0xADFB,0xEDFB,0x8BFB,0x8CFB,0xABFB,0xAAFB,0x6AFB,0xABFB,0xACFB,0x8BFB,0x8BFB,0x0EFC,0x50FC,0x6FFC,0x4EFC,0xB1FC,0x14FD,0x55FD,0x34FD,0x55FD,0x14FD,0x13FD,0xD2FC,0x91FC,0x4FFC,0x0EFC,0x8CFB,0x0EFC,0x2BFB,0xA8FA,0x90FC,0x10FC,0x08FB,0xEEFB,0xCDFB,0xACFB,0x6BFB,0x67FA,0xEAFA,0x6BFB,0x6CFB,0xC9FA,0x2BFB,0x6BFB,0x6CFB,0x4AFB,0x8CFB,0x31FC,0x6DFB,0x6CFB,0x4BFB,0xAEFB,0xCFFB,0xEFFB,0xAEFB,0x8CFB,0xCEFB,0xAFFB,0xB0FB,0xEBFA,0x2AFB,0xCCFB,0xECFB,0xACFB,0x8EFB,0xB0FB,0x2BFB,0x6DFB,0x2BFB,0x29FB,0x0AFB,0x2DFB,0x2BFB,0xEAFA,0x2BFB,0xA9FA,0xEAFA,0xEAFA,0xC8FA,0xC9FA,0xEBFA,0xC8FA,0x68FA,0x67FA,0x26FA,0xE4F9,0x27FA,0x28FA,0xC5F9,0x85F9,0x44F9,0x42F9,0x23F9,0x42F9,0xE1F0,0xC2F0,0xC1F0,0xC0E0,0x80E0,0xA0E0,0xC0D8,0xC0D8,0xC0D0,0xE0C8,0xA0B8,0x80B0,0x40B0,0x20A0,0x6088,0x6080,0x4078,0x4070,0x4070,0x6068,0x6068,0x6068,0x4078,0x4078,0x6078,0x6070,0x6070,0x4068,0x6058,0x8048,0xC020,0xE010,0xE000,0xC008,0xC008,0xE000,0xE008,0xE000,0xE008,0x0011,0x4219,0x4319,0x2319,0x4011,0x2009,0x2009,0x2009,0x4009,0x6009,0x6011,0x8011,0xA011,0xC011,0xE011,0x000A,0x0012,0x2012,0x4012,0x601A,0x801A,0xA022,0xC022,0xC01A,0xC01A,0xE01A,0x0023,0x802B,0x2034,0xA034,0x213D,0x414D,0x424D,0x6255,0x015D,0xC254,0x624C,0x0344,0x8443,0x0753,0xE74A,0xC952,0xA952,0x884A,0x874A,0x684A,0x694A,0x684A,0x6752,0x684A,0x4842,0x494A,0x4842,0x484A,0x4742,0x284A,0x4842,0x2742,0x084A,0x0742,0x273A,0x0742,0xE741,0xE639,0xE639,0xE739,0xC639,}, +{0x07FB,0xE8FA,0xE8FA,0xC8FA,0x67FA,0x88FA,0x88FA,0x68FA,0x88FA,0x4AFA,0x4AFA,0x0AFA,0xA6F9,0xC9F9,0xA5F9,0x22F9,0xC0F8,0xA2F9,0x4BFB,0x48FA,0xA2F9,0x25FA,0x26FA,0x04FA,0x67FA,0x88FA,0x86FA,0x88FA,0xA8FA,0xA8FA,0xC8FA,0xE9FA,0x2AFB,0x2AFB,0x4BFB,0x6CFB,0x8DFB,0x8CFB,0x4BFB,0xACFB,0x4BFB,0x6CFB,0x4AFB,0x2AFB,0x49FB,0x4AFB,0x6BFB,0x6BFB,0xAEFB,0xADFB,0x8BFB,0x4FFC,0x71FC,0x90FC,0x70FC,0xD2FC,0x13FD,0x55FD,0x75FD,0x75FD,0x34FD,0x13FD,0xF2FC,0xB2FC,0x70FC,0x4FFC,0x0EFC,0xEDFB,0x2BFB,0xE9FA,0x0EFC,0x4CFB,0x4AFB,0xACFB,0x6BFB,0x8BFB,0x6BFB,0x67FA,0xA8FA,0x4BFB,0xACFB,0x09FB,0xA8FA,0x4BFB,0x6CFB,0x4BFB,0x4BFB,0x52FC,0x2BFB,0x8DFB,0x8CFB,0xEEFB,0x11FC,0x0FFC,0xCEFB,0xCCFB,0xADFB,0xF0FB,0xD1FB,0xEAFA,0x6AFB,0xCBFB,0xECFB,0xCCFB,0x8BFB,0x8EFB,0x4CFB,0xAEFB,0x8EFB,0x69FB,0x48FB,0x6EFB,0x4CFB,0x2AFB,0x0AFB,0xE9FA,0xEAFA,0xEAFA,0xC8FA,0xA9FA,0xCAFA,0xC9FA,0x88FA,0x67FA,0x46FA,0x05FA,0x26FA,0x27FA,0x07FA,0xE5F9,0x85F9,0xC4F9,0x84F9,0x43F9,0x22F9,0x02F9,0x01F9,0xE2F0,0xE1E8,0x00E1,0xE0E0,0xE1E0,0xE0E0,0x00D1,0xE0D0,0xA0C8,0x80B8,0x80B0,0x60A0,0xA088,0x4080,0x6068,0x8058,0xA050,0xA050,0x8050,0xA060,0x8070,0x6078,0x8078,0x6078,0x6068,0xA048,0xC030,0xE018,0xE008,0xE000,0xC000,0xC008,0xC008,0xE000,0xE008,0x0009,0x4109,0x6321,0x4429,0x4321,0x4011,0x2009,0x2001,0x0001,0x2009,0x4009,0x6011,0x8011,0xA011,0xC019,0xE011,0x2012,0x2012,0x2012,0x401A,0x4022,0xA01A,0xA022,0xC022,0xC02A,0xA022,0xE01A,0x001B,0x6023,0xE033,0x6034,0xE034,0x003D,0x0255,0x004D,0xE14C,0xA154,0x814C,0x4344,0xC443,0x4553,0x064B,0xE852,0xC852,0x894A,0xA852,0xA852,0x494A,0x6952,0x674A,0x684A,0x484A,0x484A,0x484A,0x284A,0x474A,0x284A,0x2742,0x2742,0x074A,0x0742,0x2742,0x0642,0xE741,0x063A,0xE641,0xE739,0xC639,}, +{0x08FB,0xE9FA,0x08FB,0xC8FA,0x87FA,0xC7FA,0xA8FA,0x67FA,0x67FA,0xA9FA,0x49FA,0x08FA,0xA8F9,0x84F9,0x84F9,0x22F9,0xE0F8,0xE6F9,0x89FA,0x43F9,0x05FA,0x46FA,0xE5F9,0x45FA,0x86FA,0x46FA,0x87FA,0x87FA,0x67FA,0x88FA,0x89FA,0xA7FA,0xA7FA,0xC9FA,0x0AFB,0x2BFB,0x2BFB,0x4AFB,0xC9FA,0x0AFB,0xC8FA,0xC9FA,0xC8FA,0xC7FA,0x08FB,0x29FB,0x8CFB,0x6BFB,0xAEFB,0xAEFB,0xACFB,0x70FC,0x70FC,0x90FC,0x6FFC,0xD1FC,0x33FD,0x75FD,0x74FD,0x74FD,0x74FD,0x33FD,0x33FD,0x13FD,0xB0FC,0x70FC,0x2EFC,0x8BFB,0x4AFB,0x0AFB,0xECFB,0x6BFB,0xABFB,0xACFB,0x6BFB,0xABFB,0x6BFB,0xC8FA,0x86FA,0x09FB,0xCCFB,0x29FB,0x87FA,0x8BFB,0x8CFB,0x0AFB,0x4AFB,0x51FC,0x8BFB,0xADFB,0x8BFB,0xCDFB,0x31FC,0x0FFC,0xCDFB,0xABFB,0x8BFB,0x11FC,0xF2FB,0x09FB,0xAAFB,0x0BFC,0xEBFB,0xEBFB,0xEBFB,0x8BFB,0x8EFB,0xCDFB,0xF1FB,0xAAFB,0x88FB,0x8CFB,0x8DFB,0x49FB,0x2AFB,0x0CFB,0xC9FA,0xCAFA,0xA8FA,0xA8FA,0xCAFA,0xEAFA,0xC8FA,0x88FA,0x46FA,0xE5F9,0x06FA,0x27FA,0x48FA,0xE5F9,0xC6F9,0xC5F9,0xA4F9,0x84F9,0x63F9,0x42F9,0x41F9,0xE3F8,0x01F9,0xE2F0,0x01F1,0x00E9,0x00E9,0x00E1,0x40D9,0x03D9,0x01C9,0xC0B8,0x80B8,0x80A0,0x8088,0x6068,0xA048,0xE030,0xE028,0xE030,0xC040,0xC050,0xA060,0x8078,0x8078,0x8060,0xC038,0xC018,0xE008,0xE000,0xE000,0xC000,0xC008,0xE000,0x0001,0x2009,0x2009,0x6211,0x8421,0xA429,0x8421,0x8111,0x4009,0x2009,0x2009,0x2009,0x4009,0x6009,0xA009,0xA011,0xC011,0x001A,0x201A,0x201A,0x2022,0x401A,0x801A,0xA01A,0xC022,0xE02A,0x0023,0xE022,0x201B,0x2023,0x802B,0xC033,0x2034,0xA034,0xC034,0xC144,0xC03C,0xC044,0xA044,0x8044,0x614C,0x023C,0x834B,0x444B,0x074B,0x0753,0xC952,0x8952,0x894A,0x694A,0x884A,0x484A,0x6852,0x684A,0x284A,0x484A,0x284A,0x4842,0x274A,0x2742,0x2742,0x0742,0x2642,0x063A,0x0642,0xE741,0xE741,0xE639,0xE639,0xC639,}, +{0xE8FA,0x09FB,0x0AFB,0xA8FA,0xA7FA,0xA7FA,0xA9FA,0xA8FA,0x68FA,0x69FA,0x88FA,0x08FA,0x0AFA,0xE5F9,0xA4F9,0xA4F9,0x43F9,0x69E9,0x65F9,0x23F9,0x47FA,0x47FA,0xC4F9,0x67FA,0x88FA,0x05FA,0x26FA,0x47FA,0x26FA,0x26FA,0x46FA,0x66FA,0x45FA,0x66FA,0xA8FA,0x4BFB,0xCAFA,0xEAFA,0xC8FA,0x88FA,0x87FA,0x66FA,0x87FA,0xE8FA,0x09FB,0x0AFB,0x4AFB,0x8CFB,0xAEFB,0x4CFB,0xEEFB,0x4FFC,0x2FFC,0x8FFC,0x6FFC,0xB0FC,0xF3FC,0x53FD,0x54FD,0x74FD,0x53FD,0x33FD,0x12FD,0x12FD,0xD0FC,0x6EFC,0xECFB,0x49FB,0x4BFB,0x09FB,0xECFB,0x6AFB,0xCCFB,0xCCFB,0x8BFB,0xEDFB,0x8BFB,0x2AFB,0xE9FA,0x2AFB,0xACFB,0x09FB,0x66FA,0x6AFB,0x8CFB,0xEAFA,0x0AFB,0xEFFB,0x8CFB,0xACFB,0x8CFB,0xCCFB,0x51FC,0xEEFB,0xACFB,0xACFB,0xACFB,0xF1FB,0xF4FB,0x29FB,0xEBFB,0x0AFC,0x2BFC,0x4BFC,0x2CFC,0xECFB,0xADFB,0xEEFB,0xB0FB,0xCBFB,0xA8FB,0x6AFB,0x8DFB,0x49FB,0x4BFB,0x0BFB,0xE9FA,0xE9FA,0xE9FA,0xC8FA,0xCAFA,0xC9FA,0xC9FA,0x88FA,0x46FA,0xE6F9,0x06FA,0x48FA,0x27FA,0x06FA,0xE5F9,0xC5F9,0xA4F9,0xA4F9,0x83F9,0x63F9,0x42F9,0x02F9,0x21F9,0x03F9,0x01F1,0xE1F0,0x00E9,0x00E9,0x40E1,0x42E1,0x22D1,0xA1C8,0xA0C0,0xA0B0,0x8098,0x8060,0xC030,0x0021,0xE010,0xE010,0xC020,0xC030,0xC040,0xC048,0xA058,0xA040,0xC020,0xE010,0xE008,0xE008,0xE008,0xE000,0xE000,0x0001,0x0009,0x2109,0x4109,0x8311,0xC529,0xE529,0xE521,0xA319,0x8109,0x6011,0x6009,0x2009,0x4101,0x6009,0x8009,0xA011,0xE011,0x001A,0x4022,0x4022,0x601A,0x6022,0xC01A,0xA022,0xE022,0xE02A,0x0023,0x2023,0x4023,0x402B,0xC02B,0x002C,0x402C,0x402C,0x8034,0x8034,0xA034,0x803C,0x603C,0x404C,0x4044,0x223C,0xE343,0x8453,0x2553,0x064B,0x0853,0xE852,0x884A,0x884A,0x684A,0x484A,0x484A,0x484A,0x4742,0x284A,0x2842,0x2842,0x274A,0x273A,0x273A,0x263A,0x073A,0x0642,0x0742,0xE739,0xE639,0xC639,0xC639,0xC641,}, +{0xE8FA,0xE9FA,0xC8FA,0x87FA,0x88FA,0xA8FA,0x87FA,0x89FA,0xC8FA,0x49FA,0x68FA,0x89FA,0x27FA,0x26FA,0x25FA,0xC4F9,0x25F9,0x4BE9,0xA5F9,0x04F9,0x86F9,0xA5F9,0x27FA,0x47FA,0x07FA,0x25FA,0x46FA,0xA4F9,0x26FA,0x47FA,0xE5F9,0x46FA,0x46FA,0x45FA,0x26FA,0xEAFA,0xA8FA,0xA9FA,0x0BFB,0x27FA,0x66FA,0x66FA,0x87FA,0x2AFB,0x4AFB,0x0BFB,0x29FB,0x8DFB,0x6CFB,0x6BFB,0x2EFC,0x4FFC,0x2EFC,0x2FFC,0x6FFC,0x90FC,0xD2FC,0x12FD,0x13FD,0x12FD,0x11FD,0xF2FC,0x11FD,0x12FD,0xAFFC,0x6EFC,0xECFB,0x2AFB,0x2AFB,0x49FB,0xADFB,0x2AFB,0xCDFB,0xECFB,0xADFB,0xECFB,0xABFB,0xABFB,0x6BFB,0x4AFB,0xCCFB,0x4AFB,0xA8FA,0x09FB,0x4AFB,0xE9FA,0x0AFB,0x8DFB,0x4CFB,0x8DFB,0x8CFB,0x6AFB,0x32FC,0xCFFB,0xABFB,0xCCFB,0x8BFB,0x6FFB,0x54DB,0x8CFB,0xEBFB,0x0BFC,0x2BFC,0x4BFC,0x4BFC,0x4BFC,0xABFB,0xB1FB,0x8DFB,0xEDF3,0xE8FB,0x69FB,0x4CFB,0x69FB,0x28FB,0x09FB,0xE8FA,0xE9FA,0xE9FA,0xC9FA,0xA9FA,0xA9FA,0xC9FA,0x88FA,0x26FA,0xE6F9,0x07FA,0x48FA,0x27FA,0x47FA,0x06FA,0x05FA,0xC6F9,0xC5F9,0x63F9,0x63F9,0x42F9,0x02F9,0x21F9,0x21F9,0x01F9,0x00F1,0xE0E8,0xC0F0,0x20E1,0x60E1,0x22D9,0x02D9,0xC0C8,0xE0B8,0x8098,0x8158,0xE128,0x0011,0x0109,0x0011,0x0011,0xE010,0x0019,0x0021,0xC030,0xE020,0xE010,0xE008,0xE000,0xE000,0xE000,0xE000,0x0009,0x2101,0x4009,0x4211,0x6221,0xC421,0xE629,0x0632,0x2632,0x0422,0xC319,0xC111,0xA109,0x6111,0x6009,0x6109,0x8009,0xA011,0xE111,0x4022,0x6022,0x8022,0xA01A,0xC02A,0xC022,0xE122,0x0123,0x202B,0x202B,0x401B,0x602B,0xA02B,0xE02B,0x2034,0x603C,0x8034,0x6034,0x803C,0x6034,0x403C,0x203C,0x403C,0x2044,0x213C,0xE243,0xC34B,0x844B,0x464B,0x0753,0x074B,0xC752,0x684A,0x684A,0x684A,0x484A,0x284A,0x4842,0x484A,0x0842,0x274A,0x2742,0x0742,0xE741,0x0742,0x0742,0x063A,0xE741,0x063A,0xC641,0xE739,0xC639,0xA639,}, +{0xE9FA,0xA8FA,0x86FA,0xC7FA,0x87FA,0xA8FA,0x87FA,0x67FA,0xA9FA,0x87FA,0x47FA,0x89FA,0x46FA,0x06FA,0x26FA,0xA4F9,0xCAF9,0x0AFA,0x64F9,0x67F9,0x05F9,0x84F9,0x08FA,0x68FA,0x42F9,0x46FA,0x27FA,0xC5F9,0x27FA,0x47FA,0x26FA,0x87FA,0x47FA,0x45FA,0x04FA,0x87FA,0x67FA,0xC8FA,0xCBFA,0x05FA,0x25FA,0x86FA,0xC8FA,0x0AFB,0x8BFB,0x4BFB,0x2AFB,0x6CFB,0x09FB,0xCDFB,0x0DFC,0x4FFC,0xEEFB,0x2EFC,0x6FFC,0x6FFC,0x90FC,0xB1FC,0xD2FC,0xD1FC,0xB0FC,0xB0FC,0xD0FC,0xD1FC,0x6FFC,0x4EFC,0xCDFB,0x4BFB,0x2AFB,0xAAFB,0xACFB,0x09FB,0x0EFC,0x0DFC,0xCCFB,0xCDFB,0xEDFB,0xCDFB,0xACFB,0x6AFB,0x0EFC,0x6BFB,0x4BFB,0x6BFB,0x6BFB,0x29FB,0xEAFA,0x09FB,0xC9FA,0x4BFB,0x4BFB,0x29FB,0xF0FB,0x10FC,0x8CFB,0xCCFB,0xACFB,0x8DFB,0x12EB,0xABFB,0xEBFB,0xECFB,0x0BFC,0x2BFC,0x2BFC,0x4AFC,0xEAFB,0xD0FB,0xADFB,0xCEFB,0xE9FB,0xA8FB,0x89FB,0x68FB,0x48FB,0x28FB,0x09FB,0x09FB,0xE9FA,0xC9FA,0xA9FA,0xA9FA,0xA8FA,0x67FA,0x27FA,0x06FA,0x07FA,0x48FA,0x48FA,0x47FA,0x27FA,0x05FA,0xC5F9,0xA5F9,0x83F9,0x43F9,0x42F9,0x22F9,0x21F9,0x02F9,0xE2F8,0xC1F8,0xA0F0,0xC0F0,0x00E9,0x20E1,0x00D9,0xC2E0,0xC0D0,0xC0B8,0xA180,0xC150,0xC228,0x0119,0x0009,0xE008,0x0009,0x0009,0x0009,0x0011,0x0011,0x0011,0x0009,0xE008,0xE000,0xE008,0x0001,0x2009,0x2111,0x4211,0x8109,0x8319,0xA529,0x062A,0x272A,0x283A,0x483A,0x4732,0x2522,0x0322,0xE219,0xC211,0xA219,0xA119,0xC111,0xA221,0x0222,0x212A,0x6122,0x8022,0x801A,0xA02A,0xE122,0x021B,0x022B,0x612B,0x8133,0x812B,0xC133,0xE033,0x2034,0x403C,0x8044,0x803C,0xA04C,0x603C,0x403C,0x403C,0x203C,0x403C,0x4034,0x203C,0x014C,0x023C,0xA443,0x844B,0x254B,0x2743,0x074B,0xC84A,0x684A,0x684A,0x284A,0x484A,0x474A,0x274A,0x2742,0x2742,0x2742,0x0742,0x2742,0x073A,0x063A,0xE641,0xE741,0xE641,0xC639,0xE639,0xC639,0xA639,}, +{0x88FA,0x88FA,0x88FA,0xA8FA,0xA8FA,0x67FA,0x88FA,0x87FA,0x68FA,0x88FA,0x47FA,0x48FA,0x46FA,0x06FA,0xE6F9,0x06FA,0xE7F9,0xC5F9,0xA4F9,0xA8F9,0x24F9,0x84F9,0x26F9,0x05F9,0xC1F8,0x07FA,0xA7F9,0xE5F9,0x25FA,0x26FA,0x67FA,0xA7FA,0x26FA,0x06FA,0x25FA,0x26FA,0xA7FA,0xC8FA,0x48FA,0x25FA,0x87FA,0xC9FA,0x0AFB,0xEAFA,0x2BFB,0x4BFB,0x2AFB,0x2AFB,0x4AFB,0xEEFB,0xEDFB,0x2EFC,0xEDFB,0x2EFC,0x30FC,0x4EFC,0x4FFC,0x8FFC,0xB0FC,0x90FC,0x6FFC,0x6FFC,0x70FC,0x90FC,0x4EFC,0x0EFC,0xEDFB,0x4AFB,0x4BFB,0xCBFB,0x6AFB,0x4BFB,0x0EFC,0x50FC,0x0EFC,0xCDFB,0xEDFB,0xEEFB,0xEDFB,0xABFB,0xCEFB,0x4AFB,0xACFB,0x8CFB,0xAEFB,0x6BFB,0x0AFB,0x4BFB,0xA8FA,0xCAFA,0xC9FA,0x2AFB,0x8CFB,0xAEFB,0x8CFB,0xCDFB,0xCDFB,0xADFB,0x51FB,0x8BFB,0xCCFB,0xECFB,0x0BFC,0x0BFC,0x0BFC,0x0AFC,0x0AFC,0x2CFC,0xCDFB,0x8BFB,0xC8FB,0xC8FB,0x88FB,0x67FB,0x49FB,0x4AFB,0x2AFB,0x09FB,0xE9FA,0xCAFA,0xA9FA,0x89FA,0x68FA,0x47FA,0x26FA,0x26FA,0x47FA,0x68FA,0xA9FA,0x25FA,0x06FA,0x25FA,0xE5F9,0xC5F9,0xA4F9,0x42F9,0x43F9,0x02F9,0x02F9,0xE1F8,0xE1F8,0xC1F8,0xC0F0,0xC0F0,0xC0F0,0xE0E8,0xE0D8,0xE0D8,0xC0D0,0xC0B0,0xA270,0xC248,0xE230,0x0119,0xE008,0xE008,0xE008,0xE000,0x0101,0x2009,0x2009,0x4009,0x0009,0x0009,0xE008,0x2001,0x2109,0x4211,0x6319,0x8419,0xC411,0xE529,0x282A,0x4932,0x693A,0x894A,0x6A42,0x8A3A,0x883A,0x6732,0x252A,0x051A,0xE421,0xE321,0xE219,0xE229,0x0222,0x212A,0x6122,0x801A,0xA01A,0xA22A,0x0223,0x232B,0x4533,0xA42B,0xC433,0xE43B,0x2234,0x2134,0x403C,0x804C,0xA044,0xC044,0xC04C,0xA044,0x603C,0x603C,0x403C,0x4034,0x402C,0x603C,0x404C,0x2044,0xE13B,0xA34B,0x6443,0x4543,0x274B,0xC74A,0xA84A,0x684A,0x4842,0x284A,0x2742,0x2842,0x2842,0x2742,0x0742,0x0742,0x263A,0x073A,0xE739,0xE739,0xE739,0xE639,0xC741,0xC639,0xC639,0xC639,}, +{0x25FA,0x45FA,0x66FA,0x66FA,0x67FA,0x66FA,0x65FA,0xA8FA,0x27FA,0x27FA,0x67FA,0x06FA,0x06FA,0x06FA,0xE5F9,0x06FA,0xE5F9,0x82F9,0xE5F9,0xA5F9,0xA4F9,0x23F9,0xE4F8,0x42F8,0xE4F8,0x87F9,0x65F9,0xA5F9,0xE5F9,0x07FA,0x46FA,0x66FA,0x46FA,0xE5F9,0x26FA,0x46FA,0x67FA,0xC9FA,0x47FA,0x66FA,0xC9FA,0xE9FA,0xE9FA,0x09FB,0x09FB,0x2AFB,0x29FB,0x09FB,0x8CFB,0xCDFB,0x0DFC,0x0EFC,0xEDFB,0x0EFC,0x0FFC,0x0DFC,0x2FFC,0x6FFC,0x4EFC,0x4EFC,0x4EFC,0x4EFC,0x2EFC,0x2EFC,0xCDFB,0xADFB,0xEDFB,0x8BFB,0x4BFB,0xCBFB,0x4BFB,0x6BFB,0xEDFB,0x50FC,0x2EFC,0xEDFB,0x0DFC,0x2FFC,0x0DFC,0xCCFB,0xACFB,0x4AFB,0x4AFB,0x8BFB,0xCEFB,0x8CFB,0x6BFB,0x4CFB,0xC9FA,0xA7FA,0xC9FA,0x2AFB,0x8EFB,0xAFFB,0x8CFB,0xEEFB,0xADFB,0xADFB,0x6EFB,0x4BFB,0xADFB,0xEDFB,0x0CFC,0xEBFB,0xEBFB,0xCAFB,0xEBFB,0xC9FB,0x8BFB,0x69FB,0xA8FB,0xC9FB,0x88FB,0x68FB,0x48FB,0x09FB,0x0AFB,0xE9FA,0xE8FA,0xC9FA,0xA8FA,0x88FA,0x67FA,0x49FA,0x26FA,0x46FA,0x48FA,0x87FA,0xC9FA,0x66FA,0x46FA,0x48FA,0x26FA,0x06FA,0xE4F9,0xA3F9,0x43F9,0x43F9,0x02F9,0xE1F8,0xC1F8,0xC1F8,0xC0F8,0xA1F8,0xE0F0,0xE0E8,0x00E1,0xE0D8,0x00C9,0xE0A0,0xA370,0xC458,0xE340,0x0119,0x0009,0xE008,0xE008,0x0109,0x2209,0x4211,0x8211,0x6319,0x6111,0x2109,0x2001,0x4109,0x6321,0xC521,0xE629,0x272A,0x283A,0x6942,0x8942,0xAA4A,0xAA4A,0xAA52,0xAB4A,0xEB4A,0xCA4A,0xAA42,0x6832,0x472A,0x062A,0x0632,0x242A,0x2322,0x2222,0x012A,0x2122,0x611A,0xA21A,0x042B,0x452B,0xA83B,0xCA43,0xE94B,0x2844,0x0744,0x243C,0x4234,0x403C,0x8044,0xC03C,0xE04C,0xC04C,0xA04C,0xA04C,0x8044,0x803C,0x6044,0x603C,0x6044,0x6044,0x6044,0x2144,0xE343,0xE343,0x8343,0x454B,0x2753,0xE852,0x874A,0x6842,0x4842,0x2842,0x2742,0x284A,0x074A,0x0742,0x2742,0x073A,0x0642,0x0642,0xE739,0xC631,0xE639,0xC639,0xC639,0xC631,0xC539,}, +{0xE4F9,0xE4F9,0x05FA,0x46FA,0x25FA,0x27FA,0x66FA,0x47FA,0x47FA,0x26FA,0x47FA,0x06FA,0x06FA,0x25FA,0x45FA,0x05FA,0xC4F9,0xA4F9,0xE5F9,0x05FA,0x06FA,0x43F9,0xA1F8,0xA1F8,0x43F9,0x44F9,0x44F9,0x04F9,0x65F9,0xA5F9,0x07FA,0x06FA,0x26FA,0xE4F9,0x26FA,0x87FA,0x88FA,0x67FA,0x47FA,0xA8FA,0x0AFB,0xE8FA,0xA8FA,0x2AFB,0x29FB,0x4AFB,0x69FB,0x29FB,0xABFB,0xCEFB,0xEDFB,0xCDFB,0xCCFB,0xCDFB,0xEDFB,0xEDFB,0x2EFC,0x0EFC,0x0DFC,0x2DFC,0x0DFC,0xEDFB,0xCCFB,0xECFB,0x6CFB,0x6BFB,0xACFB,0x8CFB,0x8BFB,0xADFB,0x2AFB,0xACFB,0xCCFB,0x4FFC,0x0EFC,0xECFB,0x0DFC,0x0DFC,0x2EFC,0xEDFB,0x0EFC,0x8CFB,0x29FB,0x6AFB,0xCEFB,0x0FFC,0x0FFC,0x0BFB,0x4BFB,0xE8FA,0xCAFA,0x6CFB,0xF0FB,0x8EFB,0x4DFB,0x8CFB,0xCFFB,0xEFFB,0x2BFB,0x4CFB,0x6DFB,0xEFFB,0xEDFB,0xCCFB,0xCBFB,0xABFB,0xAAFB,0xAAFB,0xCBFB,0x69FB,0x88FB,0x8AFB,0x89FB,0x89FB,0x49FB,0x09FB,0x09FB,0xA8FA,0xA8FA,0xA8FA,0x67FA,0x68FA,0x67FA,0x28FA,0x47FA,0x68FA,0x89FA,0xC9FA,0x09FB,0xA8FA,0x66FA,0x68FA,0x25FA,0xE4F9,0xC3F9,0xC4F9,0xA4F9,0xA6F9,0x23F9,0x22F9,0x21F9,0x02F9,0xE1F8,0xE1F8,0xE1F8,0xE1F0,0xE0E8,0x00E1,0xE0B8,0x0181,0xE470,0x0579,0x2351,0x2131,0x2011,0x0009,0x0111,0x4219,0x8419,0xA531,0xC531,0x8529,0x8429,0x8219,0x6211,0x8531,0xC739,0x2942,0x8A52,0xAB5A,0xEC5A,0xCD62,0xEC5A,0xCC5A,0xCB52,0xEB52,0xEB4A,0x0C5B,0x0C5B,0xEC52,0xEB4A,0xC93A,0x883A,0x8632,0x6632,0x442A,0x2322,0x221A,0x421A,0x6422,0xC62A,0x4833,0xAB4B,0x6C5C,0x6E64,0x6F6C,0x4D5C,0x4954,0x453C,0x4334,0x613C,0x813C,0xA13C,0xA04C,0xC04C,0xE054,0xA05C,0xC04C,0xC044,0xA044,0x8044,0xA044,0xC044,0xA044,0x8144,0x4144,0x0244,0x024C,0x834B,0x4553,0x2653,0xE752,0x8842,0x484A,0x4742,0x274A,0x2742,0x0742,0x2642,0x0742,0x063A,0xE639,0xE639,0xC741,0xE739,0xE631,0xC631,0xC639,0xC639,0xC631,}, +{0x83F9,0x83F9,0xE4F9,0xE5F9,0x05FA,0x05FA,0x26FA,0x25FA,0x26FA,0x46FA,0x05FA,0x05FA,0x25FA,0x25FA,0xE4F9,0xE6F9,0xC5F9,0xA5F9,0xC4F9,0x27FA,0x08FA,0x02F9,0xC1F8,0x02F9,0x22F9,0x22F9,0x43F9,0xA0F8,0x63F9,0x85F9,0xA5F9,0x84F9,0x84F9,0x04FA,0x47FA,0x67FA,0x67FA,0x46FA,0x66FA,0xC8FA,0x2AFB,0x09FB,0x05FA,0x8BFB,0x69FB,0xE8FA,0x8AFB,0x29FB,0x6AFB,0xACFB,0x8BFB,0x6BFB,0x8CFB,0x8BFB,0xACFB,0xCCFB,0x0DFC,0xEDFB,0xCDFB,0xCCFB,0xCCFB,0x8BFB,0x8BFB,0x8BFB,0x4BFB,0x2AFB,0x6AFB,0x6AFB,0x6BFB,0xCDFB,0x6BFB,0xACFB,0xCDFB,0x2EFC,0xEDFB,0xECFB,0x0EFC,0x2EFC,0x2EFC,0x0DFC,0x2EFC,0xACFB,0x4AFB,0x09FB,0x4BFB,0x0FFC,0xCFFB,0xC8FA,0x6BFB,0x0AFB,0x0BFB,0xAEFB,0x33FC,0x0CFB,0x4DFB,0x8CFB,0x12FC,0xAFFB,0x88FA,0xADFB,0x6CFB,0xEFFB,0xACFB,0xCDFB,0x8AFB,0x8AFB,0x8AFB,0x69FB,0xCBFB,0x69FB,0x69FB,0x69FB,0x48FB,0x48FB,0x08FB,0x09FB,0xE9FA,0x88FA,0x68FA,0x67FA,0x67FA,0x46FA,0x26FA,0x48FA,0x68FA,0x89FA,0xCAFA,0x0AFB,0x2AFB,0x09FB,0x86FA,0x26FA,0x05FA,0x04FA,0x03FA,0xC4F9,0xC3F9,0xC4F9,0x84F9,0x64F9,0x63F9,0x43F9,0x23F9,0x22F9,0x23F9,0x22F9,0x01E9,0x21D1,0xE1B8,0xE388,0x2489,0x4591,0x6489,0x2371,0x6031,0x2121,0x4321,0xA531,0xC639,0xE739,0xE739,0xC739,0xE631,0xC529,0xA629,0xE739,0x294A,0xAB52,0xEC62,0x0E6B,0x0D73,0x0D7B,0x2C63,0x0B5B,0x0C5B,0x0C5B,0x0D63,0x2D63,0x4E6B,0x6E63,0x6E63,0x4F53,0x4C43,0x0A43,0xC94A,0xA832,0x8522,0x8522,0x6422,0xC82A,0x4B43,0x0F5C,0x9174,0xD27C,0xF384,0x127D,0xEF64,0xAC4C,0x8844,0x463C,0x433C,0x413C,0x603C,0x8044,0xC044,0xA04C,0xA04C,0xC04C,0xC044,0xC044,0xA04C,0xC044,0xE04C,0xC044,0xE044,0xA14C,0x414C,0x024C,0x0254,0xA453,0x644B,0x0753,0xC842,0x6742,0x4742,0x2742,0x2742,0x0742,0xE741,0xE739,0xE639,0xE739,0xE639,0xE639,0xC639,0xE631,0xE531,0xA639,0xC531,0xA639,}, +{0x01F9,0xA3F9,0x83F9,0xC4F9,0xE4F9,0xE5F9,0xC5F9,0x04FA,0x25FA,0x06FA,0x05FA,0x25FA,0x25FA,0x24FA,0xE4F9,0xE5F9,0xC5F9,0x84F9,0xA3F9,0x43F9,0x44F9,0x01F9,0xE1F8,0x22F9,0x62F9,0x21F9,0xC1F8,0x01F9,0x62F9,0x02F9,0x83F9,0x43F9,0x41F9,0xE4F9,0x46FA,0x05FA,0xE5F9,0x26FA,0x87FA,0xC8FA,0x0AFB,0xC9FA,0xE4F9,0x4AFB,0x29FB,0x4AFB,0xCCFB,0x8BFB,0x6AFB,0x6BFB,0x8CFB,0x4BFB,0x2AFB,0x09FB,0xE8FA,0x6BFB,0xCCFB,0xABFB,0xABFB,0x6BFB,0x6AFB,0x29FB,0x2AFB,0x09FB,0x29FB,0x09FB,0x2AFB,0x6AFB,0x4AFB,0xCCFB,0x8BFB,0xCCFB,0xACFB,0xECFB,0x0DFC,0x0DFC,0xEDFB,0x4EFC,0x2DFC,0x0CFC,0x0DFC,0xEDFB,0x8BFB,0x09FB,0x08FB,0x50FC,0x8DFB,0xA7FA,0x4BFB,0x2AFB,0xEAFA,0x10FC,0x11FC,0xC8FA,0x8EFB,0x8BFB,0xF1FB,0x0BFB,0x46FA,0xAFFB,0x6CFB,0xCFFB,0x6BFB,0xCEFB,0x6BFB,0x29FB,0x4AFB,0x29FB,0x4AFB,0x08FB,0x08FB,0x29FB,0x08FB,0xE8FA,0xC8FA,0xA7FA,0xA8FA,0x67FA,0x46FA,0x26FA,0x27FA,0x26FA,0x27FA,0x48FA,0x88FA,0xA8FA,0x0AFB,0x4AFB,0x6AFB,0x4AFB,0xC7FA,0x66FA,0x65FA,0x64FA,0x64FA,0x24FA,0x04FA,0xE5F9,0xE5F9,0xA4F9,0xA3F9,0x85F9,0xA4F9,0x84F9,0x64F1,0x43E9,0x43C9,0x23A1,0x23B1,0x43B1,0x25A1,0x45A9,0xA4B1,0xA5A9,0x8471,0xC549,0xA649,0xE649,0xE749,0x2742,0x2742,0x073A,0x073A,0x073A,0x0842,0x494A,0xAA4A,0xAB5A,0xEB5A,0x0C5B,0x0C63,0xCB62,0xEB5A,0xEA62,0xEC5A,0x2D6B,0x4F6B,0x6F73,0x9073,0xD063,0xD17B,0xD273,0xD073,0xAE6B,0xCD53,0x8C53,0x6B43,0x0B3B,0x2B33,0xAE43,0x306C,0xD384,0x1595,0x5695,0x569D,0x548D,0x3275,0xF064,0xCD54,0x894C,0x6544,0x2244,0x413C,0x4044,0x8044,0x804C,0xC044,0xC044,0xC044,0xC03C,0xC04C,0xE04C,0x004D,0xE04C,0x0055,0xE04C,0xC044,0x614C,0x224C,0xC34B,0x8453,0x654B,0x064B,0xA84A,0x474A,0x2742,0x2742,0x0742,0x073A,0x073A,0xE739,0xE639,0xC639,0xE639,0xE639,0xC639,0xC631,0xC531,0xC531,0x8531,}, +{0x63F9,0x42F9,0x62F9,0x84F9,0xC4F9,0x83F9,0xC3F9,0xC4F9,0xE4F9,0x05FA,0xE4F9,0xE5F9,0xE5F9,0xE4F9,0xE4F9,0xA4F9,0xA4F9,0x63F9,0x42F9,0x01F9,0xE1F8,0xC0F8,0xE2F8,0xC1F8,0x02F9,0x43F9,0x80F8,0x62F9,0x63F9,0x21F9,0x63F9,0x43F9,0x63F9,0xA3F9,0xC4F9,0x05FA,0xE4F9,0xE4F9,0x66FA,0xA8FA,0x88FA,0xE6F9,0x62F9,0xC8FA,0x08FB,0xCDFB,0xCDFB,0xACFB,0x4BFB,0x4AFB,0xC7FA,0xE9FA,0x29FB,0x0AFB,0xA8FA,0x29FB,0x8BFB,0x6BFB,0x4AFB,0x0AFB,0x2AFB,0x09FB,0x29FB,0x09FB,0x09FB,0x09FB,0x0AFB,0xABFB,0x4AFB,0xCCFB,0x8AFB,0xABFB,0xACFB,0xCCFB,0xECFB,0x0EFC,0x0CFC,0x0CFC,0x4DFC,0x4DFC,0x0DFC,0xECFB,0xCCFB,0x69FB,0x49FB,0xF3FC,0xCDFB,0xE7FA,0x6CFB,0x8BFB,0x0AFB,0xAEFB,0x8DFB,0x09FB,0x6CFB,0x4BFB,0xB0FB,0xA8FA,0x67FA,0x8EFB,0xAEFB,0x4CFB,0x2AFB,0x8EFB,0x2AFB,0xE8FA,0x08FB,0xE8FA,0xC9FA,0xC7FA,0xE8FA,0xE8FA,0xC7FA,0xA8FA,0xA8FA,0xA7FA,0x87FA,0x46FA,0x26FA,0x25FA,0x26FA,0x46FA,0x66FA,0x67FA,0x67FA,0xC9FA,0x29FB,0x49FB,0x6AFB,0x6AFB,0x27FB,0xE7FA,0xE6FA,0xE5FA,0xE4FA,0xE4FA,0x84FA,0x44FA,0x23FA,0x04FA,0xE4F9,0xC5F9,0xE5F9,0xC5F1,0x63D9,0x24D1,0x45A9,0x4599,0x64B1,0x64C9,0x65C9,0x84C1,0xA5C1,0xE5C1,0x26AA,0x2682,0x2762,0x2752,0x084A,0x0752,0x274A,0x484A,0x4842,0x2842,0x484A,0x494A,0x894A,0x8952,0xA952,0x8952,0x8952,0x694A,0x894A,0xA952,0xCB5A,0xEB62,0x0D63,0x2D6B,0x6F73,0xB173,0xF383,0x148C,0x337C,0x727C,0x937C,0x927C,0x7274,0x316C,0x316C,0x936C,0xD584,0x379D,0x589D,0x9795,0x9895,0x9795,0x768D,0x748D,0x327D,0xEF64,0xCB4C,0x474C,0x4334,0x2134,0x4034,0x603C,0x603C,0x8044,0x804C,0xC044,0xE04C,0xC054,0x004D,0x004D,0x0055,0x204D,0xE044,0xA054,0x614C,0x024C,0xC34B,0x844B,0x254B,0x074B,0x874A,0x2742,0x0742,0x073A,0x063A,0x0642,0xE639,0xE641,0xE639,0xE639,0xC639,0xA639,0xA639,0xC531,0xA539,0xA531,}, +{0x42F9,0x41F9,0x62F9,0x82F9,0x42F9,0x41F9,0x61F9,0x82F9,0xA4F9,0xC4F9,0xA3F9,0xC3F9,0xC3F9,0xA3F9,0xA3F9,0x83F9,0x63F9,0x42F9,0x22F9,0xE0F8,0xC0F8,0xC0F8,0x81F8,0x62F8,0xC1F8,0xE1F8,0x41F9,0xC5F9,0x22F9,0x62F9,0xA3F9,0x42F9,0x64F9,0xE4F9,0x83F9,0xA4F9,0xE5F9,0x03FA,0x05FA,0x66FA,0x46FA,0x44F9,0x21F9,0x67FA,0x09FB,0x6CFB,0x4AFB,0x09FB,0x09FB,0x09FB,0x87FA,0x45FA,0xE7FA,0xE8FA,0xA8FA,0x08FB,0x2AFB,0x2AFB,0xC8FA,0xE9FA,0xE8FA,0x09FB,0x29FB,0x09FB,0xE9FA,0x4AFB,0x08FB,0xCDFB,0x2AFB,0x8BFB,0x6AFB,0x8AFB,0xABFB,0xCBFB,0xCBFB,0xECFB,0xECFB,0x0CFC,0x2CFC,0x2DFC,0x0DFC,0xECFB,0xACFB,0x8BFB,0x8AFB,0x8FFC,0xAAFB,0x49FB,0x0EFC,0xACFB,0x29FB,0x6CFB,0x2BFB,0x2CFB,0x4BFB,0xAEFB,0xAEFB,0xA8FA,0xC9FA,0x4CFB,0xAEFB,0x2AFB,0x09FB,0x4BFB,0x09FB,0xC8FA,0xC7FA,0xA7FA,0x88FA,0x66FA,0xA8FA,0xC8FA,0xA8FA,0xA7FA,0x87FA,0x67FA,0x67FA,0x26FA,0x46FA,0x46FA,0x67FA,0x86FA,0x87FA,0x88FA,0xA7FA,0x09FB,0xA9FB,0xE9FB,0xA9FB,0x89FB,0x69FB,0xA8FB,0x87FB,0x87FB,0x87FB,0x65FB,0x26FB,0x05FB,0xC5FA,0x23FA,0xE4F1,0xC5E9,0xE5F1,0xA5E1,0x25D1,0x05C1,0x26B9,0x46A1,0x65B9,0xA6D9,0x85E1,0xA3D9,0xA4E1,0x05E2,0x67D2,0x88AA,0x687A,0x6752,0x4742,0x0752,0x484A,0x2842,0x0842,0x273A,0x273A,0x4842,0x694A,0x684A,0x674A,0x2852,0x4842,0x4742,0x474A,0x6842,0x884A,0xA952,0xCA52,0xEB5A,0x2C5B,0x6E73,0xB073,0xD17B,0x3174,0x9484,0xD79C,0x38A5,0x579D,0x5795,0x378D,0x589D,0x999D,0xB9A5,0xB89D,0xB89D,0xD89D,0xD8A5,0xF8AD,0xF8AD,0xD7A5,0xB485,0x506D,0xCB5C,0x8634,0x433C,0x2134,0x4034,0x2034,0x4034,0x603C,0x8044,0x8044,0xA04C,0xE04C,0xE054,0xE04C,0x0045,0xE04C,0xC044,0x804C,0x414C,0xE24B,0xA243,0x6453,0x254B,0xC74A,0x6742,0x2742,0x073A,0x0642,0x0742,0xE739,0xE639,0xC639,0xE639,0xC639,0xA631,0xA639,0xA531,0xA531,0x8529,}, +{0x21F9,0x62F9,0x21F9,0x43F9,0x01F9,0x42F9,0x61F9,0x63F9,0xA3F9,0x83F9,0xA2F9,0xA3F9,0x63F9,0x83F9,0x63F9,0x62F9,0x23F9,0x23F9,0x02F9,0xA0F8,0xE1F8,0xC0F8,0x80F0,0x81F8,0x62F8,0xC1F8,0x82F9,0xC4F9,0x63F9,0xC3F9,0xC4F9,0xC3F9,0xC3F9,0xA4F9,0xE5F9,0xC4F9,0xC3F9,0x04FA,0x24FA,0x26FA,0x05FA,0x22F9,0x21F9,0x45FA,0xA7FA,0x2BFB,0xEAFA,0xC9FA,0xA8FA,0x87FA,0x47FA,0x86FA,0x87FA,0xA7FA,0xA8FA,0x08FB,0xE8FA,0xE9FA,0xA7FA,0xE9FA,0xE8FA,0x2AFB,0x29FB,0x4BFB,0x2AFB,0xADFB,0x6AFB,0xCDFB,0x4AFB,0x29FB,0x69FB,0x69FB,0x69FB,0x8AFB,0xAAFB,0xCBFB,0xCBFB,0xEDFB,0x2CFC,0x0CFC,0x0CFC,0x0CFC,0xCCFB,0xABFB,0xABFB,0xEEFC,0xCAFB,0x8AFB,0x0DFC,0xEBFB,0x68FB,0xEEFB,0x6BFB,0xAEFB,0x8DFB,0xEFFB,0x8DFB,0x09FB,0x2AFB,0x4BFB,0xAEFB,0x29FB,0x08FB,0xC8FA,0xC8FA,0xC8FA,0xC7FA,0xA8FA,0x87FA,0x86FA,0x88FA,0xA7FA,0x87FA,0x87FA,0x67FA,0x67FA,0x68FA,0x67FA,0x47FA,0x66FA,0x88FA,0xE8FA,0x09FB,0xC8FA,0x26FB,0x89FB,0x6AFC,0x67FC,0x07FC,0xA8FB,0xEAFB,0x49FC,0x28FC,0x28FC,0x08FC,0xE7FB,0xA7FB,0x66FB,0xE6FA,0x43FA,0xC3E9,0xA3D9,0xA6E1,0x64D9,0x05C9,0x25D1,0x26D1,0x45C1,0x63C1,0xA5D9,0xC5F1,0xC3E9,0xA4F1,0xE5F1,0x26EA,0x88C2,0x888A,0x685A,0x4842,0x283A,0x084A,0x2842,0x274A,0x2742,0x063A,0x263A,0x073A,0x264A,0x4742,0x274A,0x2742,0x274A,0x4742,0x484A,0x684A,0x894A,0xAA52,0xAA5A,0xCA52,0xEB5A,0x2C5B,0x2D63,0x8E6B,0x3384,0xB79C,0x59A5,0xBAB5,0xDBAD,0xFCAD,0xFCB5,0x1BAE,0xFAA5,0xF99D,0x19A6,0x1AA6,0x3AB6,0x3BBE,0x5BBE,0x3ABE,0x18A6,0xB595,0x517D,0xCD64,0x8854,0x2434,0x212C,0x0034,0x0034,0xE03B,0x0044,0x603C,0xA044,0xE044,0xE04C,0xE04C,0x004D,0xE044,0xC044,0xA04C,0x404C,0x004C,0xC143,0x634B,0x444B,0xE652,0xA74A,0x6642,0x0742,0x073A,0xE639,0xC739,0xC639,0xC639,0xC631,0xC631,0xC631,0xC631,0xA531,0xA531,0x8629,}, +{0x62F9,0xE1F0,0x42F9,0xE1F8,0x42F9,0x40F9,0xA2F9,0x83F9,0x82F9,0x83F9,0x83F9,0x63F9,0x82F9,0x43F9,0x42F9,0x42F9,0x02F9,0x22F9,0xE1F8,0xE1F8,0x22F9,0xE0F8,0xC0F8,0xA0F8,0xC1F8,0x02F9,0x23F9,0x23F9,0xC5F9,0xE5F9,0x83F9,0xE3F9,0x04FA,0xC3F9,0xE4F9,0x45FA,0xC3F9,0xC3F9,0x25FA,0x25FA,0xA3F9,0x42F9,0x42F9,0x46FA,0xA6FA,0x09FB,0xCAFA,0xC9FA,0xA8FA,0x66FA,0x25FA,0x66FA,0x87FA,0x66FA,0x87FA,0xA7FA,0xE8FA,0xE9FA,0xA6FA,0x08FB,0x08FB,0x09FB,0x29FB,0x6CFB,0x29FB,0x4AFB,0xCCFB,0xABFB,0x4AFB,0x09FB,0x69FB,0x49FB,0x48FB,0x28FB,0x6AFB,0x8AFB,0xABFB,0xABFB,0x0CFC,0x0CFC,0xEBFB,0xECFB,0xECFB,0xEAFB,0xCCFB,0x2BFC,0xAAFB,0xAAFB,0x4CFC,0x2BFC,0xA9FB,0x4EFC,0xCCFB,0xB1FC,0x2FFC,0x10FC,0xADFB,0x49FB,0x8BFB,0x8BFB,0x8DFB,0x49FB,0x48FB,0xE7FA,0xE9FA,0xC8FA,0xA7FA,0x87FA,0x66FA,0x87FA,0x87FA,0xA7FA,0x86FA,0xA7FA,0xA7FA,0xA7FA,0x87FA,0x67FA,0x67FA,0x87FA,0xC7FA,0x29FB,0x6AFB,0x6AFB,0x07FC,0x49FC,0xE9FC,0xE6FC,0x86FC,0x68FC,0xA9FC,0xC9FC,0xC8FC,0xA8FC,0x87FC,0x26FC,0xE6FB,0x87FB,0xC6FA,0x43FA,0xA2F9,0x83E1,0x64E1,0x42E9,0xE2D8,0xE2E0,0xE3E0,0x23D9,0x61D1,0x83E1,0xA4F1,0xE4F9,0xC5F9,0xC4F9,0xE5F1,0x07DA,0x27AA,0x286A,0xE849,0x0842,0xE749,0x0742,0x0742,0xE739,0xE631,0x0532,0x063A,0x454A,0x2642,0x2642,0x263A,0x463A,0x663A,0x664A,0x884A,0x894A,0x8952,0x895A,0xA94A,0x894A,0x694A,0xAA4A,0x0C5B,0x8F6B,0x327C,0xF794,0x5AAD,0xBCB5,0xFDBD,0x3DBE,0x5CB6,0x5BAE,0x3AAE,0x5AA6,0x5CAE,0x7CBE,0x7CC6,0x9CBE,0x5BBE,0x3AAE,0xD7A5,0x958D,0x317D,0x8C64,0x254C,0xE233,0xC02B,0xA02B,0xA033,0xA03B,0x003C,0x003C,0x603C,0xA044,0xA044,0xA04C,0xA04C,0xA044,0x6044,0x6044,0x204C,0xE14B,0x824B,0x634B,0x044B,0xA54A,0x8742,0x2742,0xE741,0xE641,0xC639,0xE639,0xC639,0xC531,0xC631,0xA631,0xA631,0x8531,0x8531,0x8531,}, +{0xE1F8,0x42F9,0xE0F8,0x63F9,0x21F9,0x83F9,0x83F9,0x83F9,0x82F9,0x83F9,0x83F9,0x62F9,0x62F9,0x42F9,0x42F9,0x22F9,0x22F9,0x22F9,0xC0F8,0x22F9,0x83F9,0xE1F8,0x00F9,0xE1F8,0x21F9,0x42F9,0x24F9,0x23F9,0x84F9,0xC4F9,0x04FA,0xE3F9,0xE5F9,0x45FA,0x24FA,0x05FA,0x24FA,0xE2F9,0x45FA,0x25FA,0x83F9,0x42F9,0x63F9,0xA7FA,0x08FB,0x2BFB,0x68FA,0xC9FA,0x66FA,0x65FA,0x04FA,0x27FA,0x66FA,0x87FA,0xA7FA,0xA7FA,0xE8FA,0x08FB,0x29FB,0x28FB,0x09FB,0x09FB,0x8BFB,0x6CFB,0x6AFB,0x8BFB,0x0DFC,0x6BFB,0x29FB,0x49FB,0x29FB,0x49FB,0x49FB,0x29FB,0x29FB,0x49FB,0x89FB,0x8AFB,0xCAFB,0xEBFB,0xCBFB,0xCBFB,0xCCFB,0xECFB,0xABFB,0xAAFB,0xABFB,0xAAFB,0xEBFB,0x0AFC,0xEAFB,0x4CFC,0xC9FB,0x6EFC,0xECFB,0x52FC,0xEBFB,0x8AFB,0xCBFB,0x8AFB,0x6BFB,0x2AFB,0x69FB,0xE7FA,0x2AFB,0x08FB,0xA7FA,0xA7FA,0x47FA,0x88FA,0xA6FA,0x86FA,0xA7FA,0x88FA,0xA7FA,0xA7FA,0x87FA,0x87FA,0x66FA,0xE7FA,0x28FB,0xAAFB,0xEBFB,0x0AFC,0x68FC,0xC8FC,0x47FD,0x46FD,0x46FD,0x28FD,0x29FD,0x29FD,0x28FD,0xE8FC,0x86FC,0x27FC,0xA6FB,0x05FB,0xA5FA,0x45FA,0x26FA,0x84F9,0x21F1,0x01F9,0xE1E8,0xE1F0,0x02F1,0x20E9,0x60E9,0x83F1,0xA4F9,0xC4F9,0xA4F9,0xA5F9,0xC5F9,0xC5E1,0xE6C1,0xE779,0xE749,0xC741,0xE739,0xC739,0xE739,0x063A,0x2532,0x053A,0x053A,0x253A,0x053A,0x253A,0x2632,0x4532,0x4532,0x8642,0x874A,0x8642,0x673A,0x6642,0x4632,0x263A,0x0742,0x273A,0x684A,0xCA4A,0x4C5B,0x106C,0x9584,0x389D,0xBBB5,0xFCB5,0x5CBE,0x7DB6,0x7CBE,0x9DB6,0x9DB6,0x7DBE,0x7CBE,0x7BBE,0x3AB6,0x19A6,0xD69D,0x9595,0x327D,0xCD64,0x2744,0xC233,0x802B,0x802B,0x8033,0xA02B,0xA033,0xE03B,0x403C,0x803C,0x803C,0xA044,0x8044,0xA03C,0x603C,0x203C,0x0044,0xC04B,0x804B,0x424B,0x0343,0xA54A,0x8642,0x4742,0x0742,0xC639,0xE739,0xC639,0xC539,0xC631,0xC631,0xC631,0x8631,0xA531,0x8531,0x8531,}, +{0x41F9,0x01F9,0x84F9,0x02F9,0x82F9,0xC3F9,0xA3F9,0x42F9,0xA3F9,0xA3F9,0x41F9,0x62F9,0x42F9,0x42F9,0x43F9,0x42F9,0x43F9,0xE2F8,0x21F9,0x62F9,0xA4F9,0x22F9,0x21F9,0x61F9,0x62F9,0x82F9,0x83F9,0x63F9,0xC5F9,0xA4F9,0xA5F9,0xE5F9,0xC4F9,0x47FA,0xA6FA,0x24FA,0x45FA,0x85FA,0x86FA,0x05FA,0x63F9,0x63F9,0x83F9,0xE7FA,0xABFB,0x4BFB,0x45FA,0x86FA,0x26FA,0x45FA,0x25FA,0x47FA,0x87FA,0xC7FA,0xE8FA,0xC8FA,0x07FB,0x29FB,0x6BFB,0x49FB,0x29FB,0x29FB,0x8AFB,0x4AFB,0xABFB,0x4AFB,0x8AFB,0x29FB,0x49FB,0x6AFB,0x49FB,0x28FB,0x28FB,0x49FB,0x29FB,0xE8FA,0x49FB,0x49FB,0x6AFB,0xAAFB,0xAAFB,0xAAFB,0xAAFB,0xCBFB,0xABFB,0x8AFB,0x8AFB,0xAAFB,0x89FB,0xA9FB,0x89FB,0x0BFC,0xCAFB,0xEBFB,0xABFB,0xEFFB,0xCBFB,0xAAFB,0xC9FB,0x6AFB,0x4CFB,0x2BFB,0x2DFB,0xE9FA,0x0BFB,0x09FB,0xC8FA,0x88FA,0x45FA,0xA9FA,0xA7FA,0x87FA,0x68FA,0x68FA,0xA7FA,0xC8FA,0x87FA,0x88FA,0x86FA,0xC8FA,0x29FB,0xEAFB,0x4CFC,0x69FC,0x87FC,0x06FD,0x87FD,0xA7FD,0xA7FD,0xA8FD,0x49FD,0x28FD,0x27FD,0xE7FC,0x45FC,0xE5FB,0x45FB,0xC5FA,0x86FA,0x25FA,0x25FA,0x84F9,0x20F9,0x01F9,0x23F9,0x22F9,0x22F9,0x63F9,0xA2F9,0xA2F9,0xA3F9,0xC4F9,0x84F9,0xA5F9,0xC6F9,0xC5F1,0xA5D9,0x85A1,0xA669,0xA639,0xC639,0xC731,0x0732,0x063A,0x073A,0x2742,0x2642,0x263A,0x2642,0x2642,0x463A,0x453A,0x4532,0x8532,0x663A,0x8432,0x853A,0x4432,0x4422,0x2422,0xE529,0x052A,0x0532,0x463A,0x8842,0x0B53,0xAE5B,0x7274,0xF58C,0x79A5,0xFBBD,0x5EBE,0x7EBE,0x9EC6,0xBDBE,0x9DBE,0x7CB6,0x1BB6,0xF89D,0xB795,0xB695,0x5495,0x327D,0xCD5C,0x273C,0xC223,0x602B,0x6023,0x602B,0xA02B,0xA02B,0xC02B,0x0034,0x603C,0x6044,0x803C,0x6044,0x603C,0x2034,0x203C,0xE03B,0xC043,0x8043,0x4143,0x2143,0xC342,0x854A,0x4642,0x2642,0xE639,0xC631,0xA631,0xA539,0xC631,0xC631,0x8531,0x8531,0xA531,0x8529,0x6531,}, +{0x21F9,0x82F9,0x43F9,0x21F9,0xC4F9,0xE3F9,0x41F9,0x82F9,0x63F9,0x82F9,0x63F9,0x63F9,0x41F9,0x63F9,0x42F9,0x83F9,0x42F9,0xE1F8,0x83F9,0x62F9,0xC5F9,0x63F9,0x82F9,0xA2F9,0xA2F9,0xC3F9,0xC3F9,0xE3F9,0x25FA,0xE5F9,0xE4F9,0xC4F9,0xA5F9,0xE6F9,0x47FA,0x66FA,0x05FA,0xC7FA,0xC7FA,0x05FA,0xA4F9,0x83F9,0xA3F9,0xC7FA,0xECFB,0x0AFB,0x26FA,0x87FA,0x07FA,0x66FA,0x64FA,0x86FA,0xA7FA,0x29FB,0x29FB,0x29FB,0x29FB,0x49FB,0x8AFB,0x4AFB,0x4AFB,0xAAFB,0xCBFB,0xABFB,0xABFB,0x29FB,0x69FB,0x8AFB,0x4AFB,0x4AFB,0x69FB,0x28FB,0x07FB,0x28FB,0x08FB,0x08FB,0xE8FA,0x08FB,0x48FB,0x49FB,0x69FB,0x69FB,0x69FB,0x6AFB,0x8AFB,0x69FB,0x69FB,0xAAFB,0x69FB,0x89FB,0x69FB,0xA9FB,0x89FB,0xA9FB,0x49FB,0xEEFB,0xABFB,0xAAFB,0x89FB,0x8BFB,0x4BFB,0x2DFB,0x0DFB,0xC8FA,0xAAFA,0xAAFA,0x89FA,0x49FA,0x25FA,0x6BFA,0x67FA,0x4AFA,0x85F9,0xC8F9,0xC6F9,0x48FA,0x48FA,0x69FA,0xC7FA,0xC8FA,0x08FB,0xA9FB,0x6BFC,0x89FC,0x87FC,0x26FD,0x87FD,0xA6FD,0xA6FD,0xA7FD,0x27FD,0xC7FC,0xE7FC,0xC6FC,0x05FC,0x64FB,0xE4FA,0x65FA,0x25FA,0xE4F9,0xA3F9,0x62F9,0x20F9,0x01F9,0x44F9,0x41F9,0x42F9,0x81F9,0xC2F9,0xC3F9,0xA3F9,0xA3F9,0xA4F9,0x84F9,0xA5F9,0xC6F9,0x64E9,0x43C9,0x4489,0x4469,0xA549,0xA641,0xE739,0x0842,0x2632,0x273A,0x273A,0x473A,0x473A,0x2742,0x473A,0x453A,0x6432,0x8432,0x8532,0x6432,0x6432,0x432A,0x442A,0x242A,0x0322,0x2222,0x022A,0x242A,0x642A,0x6632,0xE842,0x8C4B,0x306C,0xB484,0x3895,0x9BAD,0x1DBE,0x7EC6,0x7DC6,0x7CBE,0x5BAE,0xF99D,0xD795,0x968D,0x7695,0x3595,0x1385,0xAE64,0x4844,0xC32B,0x802B,0x601B,0x6023,0x8023,0x8033,0xA02B,0xE033,0x2034,0x203C,0x403C,0x403C,0x203C,0x003C,0xA03B,0xE033,0xA033,0x8033,0x203B,0x004B,0xC242,0x8442,0x6542,0x4642,0x063A,0xC639,0xC639,0xC639,0xA631,0xA631,0xA531,0xA529,0x8531,0x8429,0x6529,}, +{0x00F1,0xA3F9,0xC0F8,0x82F9,0xC4F9,0x83F9,0xC3F9,0xC4F9,0x63F9,0x62F9,0x43F9,0x63F9,0x62F9,0x02F9,0x83F9,0x83F9,0x01F9,0x43F9,0x43F9,0x62F9,0xE5F9,0x84F9,0x83F9,0xE4F9,0xC4F9,0xE4F9,0x05FA,0x44FA,0xA6FA,0x45FA,0x04FA,0xE4F9,0xE5F9,0x05FA,0x05FA,0x28FA,0x05FA,0x47FA,0x68FA,0xC4F9,0xA4F9,0xA4F9,0xC4F9,0x08FB,0xEDFB,0x87FA,0x67FA,0x88FA,0xE5F9,0x86FA,0xA6FA,0xA6FA,0xA7FA,0x08FB,0x49FB,0x49FB,0x4AFB,0x8AFB,0xCBFB,0x8AFB,0xABFB,0x2CFC,0x0CFC,0xEBFB,0xEBFB,0xAAFB,0x8AFB,0x8AFB,0xAAFB,0x29FB,0x29FB,0x49FB,0x28FB,0x08FB,0x08FB,0x28FB,0x08FB,0x28FB,0x68FB,0x48FB,0x28FB,0x29FB,0x28FB,0x08FB,0x29FB,0x48FB,0x49FB,0x49FB,0x69FB,0x68FB,0x48FB,0x68FB,0x89FB,0x67FB,0x27FB,0x0DFC,0x8BFB,0x6AFB,0x49FB,0x6AFB,0x29FB,0x2DFB,0x2EFB,0xA9FA,0xAAFA,0x8BFA,0x6AFA,0x49FA,0xE5F9,0x4AFA,0x47FA,0x4AFA,0xE8F9,0xC9F9,0xA7F9,0xE8F9,0xC9F9,0x48FA,0xC9FA,0xA7FA,0xA7FA,0x26FB,0xC7FB,0x48FC,0x88FC,0x06FD,0x46FD,0x66FD,0x46FD,0x46FD,0xC7FC,0x67FC,0x47FC,0x26FC,0x85FB,0xC5FA,0x65FA,0x24FA,0x04FA,0xA4F9,0x63F9,0x42F9,0x41F9,0x61F9,0x63F9,0x63F9,0x42F9,0x61E9,0xA2F1,0xA3F9,0xA4F9,0x62F9,0x62F9,0x62F9,0x84F9,0xA5F9,0x84F9,0x23D9,0x22B9,0x2389,0x4571,0x6661,0xE649,0xC741,0x073A,0x483A,0x683A,0x6842,0x473A,0x473A,0x463A,0x663A,0x8532,0x8432,0x6432,0x6432,0x8432,0x632A,0x632A,0x432A,0x4322,0x4222,0x4222,0x231A,0x431A,0x6422,0xA432,0xE63A,0x294B,0x8E53,0x326C,0xD584,0x589D,0x9BA5,0xBBB5,0xDBB5,0xFAA5,0xD99D,0x9795,0x7695,0x5795,0x3595,0x1385,0xB074,0x4C54,0x063C,0xC22B,0xA023,0xC023,0xA02B,0xA033,0xC033,0xE033,0xE03B,0x0044,0x2044,0x003C,0x003C,0xC033,0x803B,0x8033,0x6033,0x6033,0x2033,0xE03A,0xA13A,0x833A,0x643A,0x453A,0x253A,0xC539,0xC631,0xA531,0xA631,0xA631,0xA531,0x8529,0x8429,0x6531,0x6531,}, +{0xA0F8,0xE0F8,0xC0F8,0x41F9,0x82F9,0xA3F9,0xC3F9,0xA4F9,0x62F9,0xA3F9,0x83F9,0x63F9,0x42F9,0x42F9,0x83F9,0x01F9,0x22F9,0x63F9,0x02F9,0x62F9,0xE5F9,0xA3F9,0xA4F9,0xE4F9,0xE4F9,0x04FA,0x45FA,0x44FA,0xC7FA,0x86FA,0x24FA,0x05FA,0x05FA,0xE5F9,0x46FA,0x28FA,0x06FA,0xA6F9,0xA7F9,0xC4F9,0xC4F9,0x05FA,0xE5F9,0x87FA,0x6DFB,0x05FA,0x88FA,0x68FA,0x26FA,0x87FA,0x08FB,0xC7FA,0xE7FA,0x29FB,0x6AFB,0x2AFB,0x8BFB,0xCCFB,0xEBFB,0xECFB,0xCCFB,0xEDFB,0xEBFB,0x0BFC,0x0CFC,0xECFB,0xCBFB,0xAAFB,0xEBFB,0x8AFB,0x49FB,0x48FB,0x69FB,0x48FB,0x07FB,0x29FB,0x27FB,0xE7FA,0x68FB,0x88FB,0x08FB,0x07FB,0x08FB,0xE7FA,0x08FB,0x07FB,0xE8FA,0x28FB,0x48FB,0x26FB,0x06FB,0x67FB,0x68FB,0x27FB,0x07FB,0x0CFC,0x4AFB,0x29FB,0x28FB,0x08FB,0xE8FA,0xC8FA,0xA9FA,0x46FA,0x69FA,0x48FA,0x48FA,0x07FA,0xE5F9,0x49FA,0x48FA,0x6AFA,0x28FA,0x4AFA,0x08FA,0x08FA,0x09FA,0x27FA,0x68FA,0x67FA,0x66FA,0xA5FA,0x46FB,0xA7FB,0xE6FB,0x27FC,0x66FC,0xA5FC,0x85FC,0x65FC,0x25FC,0xC7FB,0x87FB,0x87FB,0x26FB,0x84FA,0x24FA,0x04FA,0xE5F9,0xA3F9,0x63F9,0x83F9,0x82F9,0x82F9,0x23F9,0x42F9,0x41F1,0x81E9,0x82F1,0x83F9,0x63F9,0x42F9,0x21F9,0x82F9,0xA4F9,0xC5F9,0x64F9,0x24F1,0x22D1,0x21A9,0x0291,0x2489,0x6669,0xA659,0x0742,0x4842,0x6842,0x8842,0x684A,0x473A,0x6642,0x6442,0x843A,0x8532,0x843A,0xA432,0xA332,0x822A,0x6222,0x622A,0x6222,0x8212,0x6322,0x4322,0x6222,0x432A,0x632A,0xA42A,0xC532,0xC83A,0x2B3B,0xAD53,0x3164,0x9374,0xD584,0xF794,0x18A5,0x379D,0x579D,0x589D,0x789D,0x579D,0x548D,0xF27C,0xAF64,0x4A4C,0x053C,0xC23B,0xC23B,0x013C,0xE033,0xC03B,0xE03B,0xC043,0xC03B,0xE03B,0xE033,0xC033,0x8033,0x603B,0x402B,0x2033,0x002B,0x0033,0xE032,0xA13A,0x823A,0x833A,0x6442,0x253A,0x063A,0xC631,0xA531,0xA531,0x8631,0x8531,0x8529,0x6531,0x6531,0x6529,}, +{0xC0F8,0xC0F8,0xE0F8,0x21F9,0xE0F8,0xE1F8,0x62F9,0x21F9,0x22F9,0x63F9,0x62F9,0x63F9,0x22F9,0x83F9,0x42F9,0xE2F8,0x83F9,0x23F9,0xE1F8,0xC4F9,0x07FA,0xA4F9,0xE4F9,0x03FA,0xE3F9,0x04FA,0x04FA,0x24FA,0x87FA,0x46FA,0x05FA,0x05FA,0x05FA,0x05FA,0x05FA,0xE5F9,0x06FA,0xE7F9,0xE6F9,0xE5F9,0xE5F9,0x27FA,0x06FA,0x27FA,0xE9F1,0xC5F9,0x48FA,0x07FA,0x89FA,0x06FA,0xC8FA,0x68FA,0x86FA,0x6AFB,0x6AFB,0x8BFB,0xABFB,0xECFB,0xCCFB,0xEBFB,0xECFB,0xCBFB,0x0CFC,0x2DFC,0x0CFC,0x0CFC,0xEBFB,0xEBFB,0xCBFB,0xC9FB,0x88FB,0x88FB,0x89FB,0x68FB,0x46FB,0x47FB,0x47FB,0x07FB,0x69FB,0x8AFB,0x28FB,0x06FB,0x07FB,0x26FB,0xE7FA,0x07FB,0xC7FA,0x27FB,0x47FB,0x06FB,0x26FB,0x27FB,0x27FB,0x27FB,0x28FB,0xCDFB,0xE8FA,0x29FB,0xE7FA,0xC7FA,0x87FA,0xA7FA,0x66FA,0x67FA,0xCAFA,0x25FA,0xE5F9,0xE5F9,0x07FA,0x48FA,0x47FA,0x89FA,0x26FA,0x47FA,0x27FA,0x06FA,0xE5F9,0xC5F9,0x25FA,0x67FA,0x87FA,0x84FA,0xC6FA,0x06FB,0x47FB,0x68FB,0x66FB,0xA5FB,0xC6FB,0x84FB,0x45FB,0x06FB,0x26FB,0x06FB,0xE7FA,0x64FA,0x03FA,0xE4F9,0xE3F9,0xC4F9,0xA4F9,0xE4F9,0x63F9,0x42F9,0x22F9,0x22F1,0x41E1,0x41F1,0x62F9,0x41F9,0x41F9,0x22F9,0x22F9,0x62F9,0x83F9,0xA4F9,0x65F9,0x43F9,0x22E9,0x00C9,0x01B1,0x22A1,0x4499,0x6589,0xC751,0x4742,0x6842,0x6742,0x673A,0x473A,0x6632,0x6532,0xA53A,0x8542,0x853A,0xA332,0xA332,0x832A,0x632A,0x6232,0x6222,0x641A,0x442A,0x4532,0x4432,0x652A,0x8522,0x8532,0x663A,0x6732,0x8842,0xA942,0x2A3B,0x8C43,0xAE5B,0x105C,0x737C,0x948C,0xD694,0xF79C,0x389D,0x379D,0x378D,0x148D,0xD284,0x8F6C,0x2B54,0xE74B,0xE64B,0xE753,0x0444,0xE13B,0xA03B,0xC033,0xC03B,0xA033,0xA033,0x803B,0x803B,0x4033,0x002B,0xE032,0xE032,0xE02A,0xE02A,0xC03A,0xA13A,0x823A,0x633A,0x643A,0x2532,0xE631,0xA531,0xA531,0x8529,0x8531,0x6531,0x8431,0x6529,0x4529,}, +{0xA0F8,0xA0F8,0xC0F8,0xE2F8,0xA0F8,0xC0F8,0xE1F8,0xE0F8,0x80F8,0x22F9,0x21F9,0xE1F8,0x22F9,0xE2F8,0x02F9,0x03F9,0x63F9,0x02F9,0x22F9,0xE4F9,0x27FA,0xE4F9,0xE5F9,0x04FA,0xE4F9,0xE4F9,0xE4F9,0x25FA,0x47FA,0x06FA,0x24FA,0x25FA,0xE5F9,0x05FA,0x05FA,0x05FA,0x24FA,0xE5F9,0x26FA,0x06FA,0x05FA,0x67FA,0x48FA,0x07FA,0xE6F9,0x05FA,0x08FA,0xE7F9,0x08FA,0x88FA,0xA8FA,0x88FA,0x86FA,0x09FB,0x29FB,0x6BFB,0xABFB,0xABFB,0xCBFB,0xECFB,0x0CFC,0x0CFC,0xECFB,0x2CFC,0x2BFC,0x0BFC,0x0BFC,0x2CFC,0xE9FB,0xA9FB,0x88FB,0xA8FB,0xC8FB,0xA9FB,0xA8FB,0x87FB,0x88FB,0x68FB,0xA9FB,0xA9FB,0x07FB,0x26FB,0x27FB,0x46FB,0x26FB,0x47FB,0x06FB,0xE7FA,0x06FB,0x06FB,0x06FB,0x06FB,0xE7FA,0x07FB,0x06FB,0x48FB,0xC5FA,0xE7FA,0xA6FA,0x86FA,0x46FA,0x87FA,0x46FA,0x67FA,0x87FA,0x26FA,0xE4F9,0xE5F9,0x26FA,0x05FA,0x67FA,0x88FA,0x46FA,0x45FA,0x26FA,0x06FA,0x06FA,0xE5F9,0x46FA,0xA8FA,0xC8FA,0x85FA,0x86FA,0xA6FA,0xC6FA,0x08FB,0xE6FA,0x26FB,0x06FB,0xE5FA,0xC5FA,0xC5FA,0xE7FA,0xA7FA,0x86FA,0x45FA,0x03FA,0xC3F9,0xC3F9,0xC4F9,0xE4F9,0xC5F9,0x63F9,0x42F1,0x43F1,0x42F9,0x22F1,0x22F9,0x22F9,0x61F9,0x41F9,0x22F9,0x42F9,0x61F9,0xA3F9,0x84F9,0x64F9,0x43F9,0x22F9,0x20D9,0x20B9,0x22A1,0x02A1,0x4489,0xC549,0xE639,0x2732,0x463A,0x673A,0x6732,0x863A,0x863A,0xA63A,0x853A,0x8432,0x8432,0x8432,0x6332,0x2432,0x6432,0x6432,0x452A,0x4532,0x663A,0x453A,0x8732,0x883A,0x6842,0x8842,0x673A,0x473A,0x2742,0x683A,0xA93A,0xC94A,0x2B4B,0x6C43,0xAE5B,0x106C,0x737C,0x9584,0xD69C,0xD694,0xF58C,0xB384,0x5174,0x2E64,0x0C54,0xEB6B,0xEB6B,0x074C,0x013C,0xA03B,0xC033,0xA03B,0xA033,0x8033,0x4033,0x6033,0x203B,0x0033,0xC032,0xC032,0xA032,0xA02A,0xA032,0x813A,0x823A,0x633A,0x633A,0x443A,0x2532,0xC531,0x8531,0x8529,0x8529,0x6531,0x8429,0x6429,0x6429,}, +{0xA0F8,0xA1F8,0xE1F8,0x03F9,0xC0F8,0xC0F8,0xC1F8,0xE0F8,0xA0F8,0x42F9,0x01F9,0xA1F8,0xC2F8,0xC2F8,0x43F9,0x23F9,0x44F9,0x01F9,0x83F9,0xC4F9,0x26FA,0x04FA,0xE5F9,0xE4F9,0xE5F9,0xE5F9,0x24FA,0x46FA,0x46FA,0x06FA,0x25FA,0x05FA,0x04FA,0x25FA,0x25FA,0x45FA,0x26FA,0xE6F9,0x25FA,0x26FA,0x26FA,0x87FA,0x68FA,0x47FA,0x68FA,0x05FA,0x47FA,0xC5F9,0xE6F9,0x67FA,0x87FA,0x66FA,0x66FA,0xE7FA,0x09FB,0x4AFB,0x8AFB,0xAAFB,0xEBFB,0xECFB,0xEBFB,0x0DFC,0x0BFC,0x4CFC,0x0BFC,0x2BFC,0x2AFC,0x4AFC,0x2AFC,0x2AFC,0x09FC,0x08FC,0x08FC,0x6AFC,0x28FC,0x07FC,0xE8FB,0xC9FB,0x29FC,0xE8FB,0x67FB,0x67FB,0x85FB,0xA6FB,0xA6FB,0xA6FB,0x66FB,0x06FB,0x25FB,0x26FB,0x05FB,0xE5FA,0xE6FA,0x06FB,0x27FB,0x27FB,0xA4FA,0xE6FA,0x85FA,0x65FA,0x65FA,0x86FA,0x67FA,0x45FA,0x65FA,0x68FA,0x25FA,0x85FA,0x67FA,0x44FA,0x66FA,0x87FA,0x65FA,0x65FA,0x45FA,0x26FA,0x46FA,0x25FA,0x66FA,0x67FA,0x66FA,0x66FA,0x66FA,0xA7FA,0xA7FA,0xC7FA,0xA6FA,0xE7FA,0xC6FA,0xA6FA,0x85FA,0xA6FA,0xC8FA,0xA7FA,0x85FA,0x65FA,0x44FA,0xE3F9,0xE4F9,0xC3F9,0x83F9,0xA4F9,0x23F1,0x23F1,0x23F9,0x42F9,0x42F9,0x42F9,0x62F9,0x61F9,0x41F9,0x43F9,0x42F9,0x63F9,0x63F9,0x84F9,0x63F9,0x42F9,0x21F9,0x21E9,0x21C9,0x0289,0x2481,0x4569,0x8549,0xA631,0x0632,0x2632,0x473A,0x6842,0x673A,0x863A,0x6632,0xA532,0x852A,0x653A,0x6532,0x643A,0x453A,0x443A,0x052A,0x052A,0x252A,0x463A,0x674A,0x894A,0xAA4A,0x894A,0x884A,0x673A,0x4632,0x4642,0x463A,0x473A,0x463A,0x8632,0xA73A,0xE83A,0x4B4B,0xAD53,0x1054,0x516C,0x737C,0x937C,0x7274,0x106C,0xED63,0xCC5B,0xEC73,0xEB6B,0x0644,0xE13B,0xA03B,0xC03B,0xC03B,0xA03B,0x8033,0x6033,0x4033,0x4033,0x2033,0xC032,0x802A,0xA02A,0x802A,0x8032,0x803A,0x823A,0x823A,0x833A,0x643A,0x6432,0x053A,0xC531,0x8529,0x8531,0x6529,0x6429,0x6429,0x4429,}, +{0xA0F8,0xC0F8,0x22F9,0xC2F8,0xA0F8,0xC0F8,0xE0F8,0xC2F8,0xC0F8,0x83F9,0x03F9,0xE1F8,0x22F9,0x02F9,0x64F9,0x42F9,0x43F9,0x62F9,0xE3F9,0xE4F9,0x46FA,0x04FA,0xE5F9,0x04FA,0x25FA,0x05FA,0x25FA,0x66FA,0x66FA,0x45FA,0x26FA,0x25FA,0x25FA,0x27FA,0x47FA,0x67FA,0x47FA,0x67FA,0x66FA,0x67FA,0x47FA,0x88FA,0xC8FA,0xA7FA,0x47FA,0xA4F9,0x46FA,0x07FA,0x25FA,0xA7FA,0x08FB,0xA7FA,0x85FA,0xC5FA,0xE8FA,0x28FB,0x48FB,0x89FB,0xAAFB,0xCAFB,0xCAFB,0xEBFB,0x2CFC,0x0BFC,0xEAFB,0x0AFC,0x0AFC,0x6BFC,0x4AFC,0x29FC,0x4AFC,0x8AFC,0x89FC,0xE9FC,0xC8FC,0xA9FC,0x27FC,0x69FC,0xE9FC,0x69FC,0xE8FB,0xE8FB,0x46FC,0x47FC,0x26FC,0xC6FB,0xA7FB,0x45FB,0x25FB,0x46FB,0x25FB,0xE5FA,0xC7FA,0xC5FA,0x27FB,0x27FB,0xA4FA,0xC6FA,0xA5FA,0x65FA,0x44FA,0xA6FA,0x66FA,0x44FA,0x43FA,0x85FA,0x85FA,0xC5FA,0xA7FA,0xE6FA,0xA4FA,0xC5FA,0xA4FA,0x84FA,0xA6FA,0x86FA,0x87FA,0x26FA,0x47FA,0x26FA,0x25FA,0x66FA,0xA7FA,0x87FA,0x86FA,0xA8FA,0xA7FA,0xA6FA,0xA6FA,0x85FA,0xA6FA,0xA6FA,0xC7FA,0xE8FA,0xA6FA,0x85FA,0x64FA,0x23FA,0xE4F9,0x83F9,0x03F1,0x04F9,0x23F1,0x42F1,0x23F9,0x83F9,0xC4F9,0xA4F9,0x63F9,0x41F9,0x42F9,0x43F9,0x61F9,0x42F9,0x62F9,0x42F9,0x42F9,0x21F9,0x21F9,0x60F9,0x61E9,0x40C1,0x2299,0x4479,0x8561,0xC551,0x053A,0x0632,0x4632,0x473A,0x673A,0x663A,0x463A,0x8632,0x673A,0x463A,0x653A,0x443A,0x252A,0x042A,0x042A,0x252A,0x263A,0x6742,0x6942,0x6952,0xA942,0x8942,0x6742,0x673A,0x473A,0x463A,0x452A,0x2532,0x2532,0x4332,0x4432,0x6532,0xA73A,0x0933,0x2A43,0xAD53,0xCF63,0xF16B,0xF06B,0xCE63,0x8C63,0xAB53,0xCB5B,0xE953,0xE53B,0xE333,0xE13B,0xE03B,0xE03B,0xE03B,0xC03B,0xC03B,0x8043,0x8033,0x6033,0x2033,0xC02A,0xA022,0xA02A,0x802A,0xA032,0xA13A,0xA13A,0xA23A,0x833A,0x643A,0x443A,0x4432,0xC529,0x8529,0x6429,0x6529,0x4429,0x4429,}, +{0xC0F0,0xC0F8,0x43F9,0xC1F8,0xA0F8,0xE1F8,0x00F9,0xC1F8,0xA0F8,0x84F9,0xA2F0,0x21F9,0x63F9,0x42F9,0x64F9,0x84F9,0x62F9,0x03FA,0x23FA,0x44FA,0x67FA,0x24FA,0x25FA,0x45FA,0x65FA,0x45FA,0x46FA,0xC6FA,0x87FA,0x86FA,0x87FA,0x67FA,0x86FA,0x66FA,0xA8FA,0xA8FA,0xC8FA,0xC9FA,0x88FA,0x67FA,0x67FA,0x48FA,0xC9FA,0xC8FA,0x68FA,0x66FA,0x86FA,0x47FA,0x45FA,0xE8FA,0x08FB,0xA7FA,0xC6FA,0xC6FA,0xC6FA,0x07FB,0x27FB,0x69FB,0x68FB,0x8AFB,0xAAFB,0x89FB,0xEBFB,0x0AFC,0xE9FB,0xC9FB,0xE9FB,0x2AFC,0x4AFC,0x8AFC,0x69FC,0x0BFD,0x09FD,0x29FD,0x69FD,0x4BFD,0xA8FC,0xA7FC,0x6BFD,0xCBFC,0x48FC,0x68FC,0x46FC,0x46FC,0x86FC,0x47FC,0xE7FB,0x87FB,0x66FB,0x46FB,0x46FB,0xE5FA,0xC6FA,0xC5FA,0x06FB,0x07FB,0x84FA,0x85FA,0x86FA,0x64FA,0x44FA,0xA6FA,0x85FA,0x65FA,0x65FA,0x85FA,0x87FA,0xA6FA,0x07FB,0x47FB,0x45FB,0x06FB,0x06FB,0x85FA,0x86FA,0xA6FA,0x04FA,0x25FA,0x47FA,0x46FA,0x04FA,0x67FA,0xA7FA,0xC8FA,0xA6FA,0xA6FA,0xA7FA,0xC7FA,0xA6FA,0x86FA,0xA5FA,0xC5FA,0xA5FA,0xE8FA,0xC6FA,0x87FA,0x25FA,0x04FA,0x23F9,0x45F9,0xE3F0,0xE3F0,0x84F9,0x42F9,0x83F9,0xC4F9,0xC4F9,0xC4F9,0xA3F9,0x82F9,0x82F9,0x62F9,0x62F9,0x42F9,0x63F9,0x22F9,0x21F9,0x00F9,0x20F9,0x40F9,0xC0F9,0x81E1,0x01C1,0x01A9,0x2389,0xA271,0xE449,0x063A,0x6632,0x673A,0x6842,0x6742,0x673A,0x4632,0x262A,0x2532,0x452A,0x2532,0x2632,0x252A,0x2732,0x273A,0x273A,0x483A,0x4842,0x494A,0x8842,0x684A,0x4842,0x483A,0x2632,0x4532,0x2532,0x0432,0x042A,0x042A,0xE431,0x2432,0x6432,0x862A,0xA83A,0x0C53,0x4E5B,0x6F63,0xAF63,0x8E63,0x8D5B,0x8C53,0xAC63,0xCB5B,0xE853,0xC743,0xA54B,0xE243,0xE143,0xC24B,0xC253,0xC34B,0xC24B,0x8143,0x8043,0x2033,0xC02A,0x8022,0x6022,0x8022,0xA02A,0xC032,0xC132,0xE132,0x823A,0x833A,0x643A,0x443A,0x053A,0xC429,0x6529,0x6429,0x4429,0x4429,}, +{0x60F0,0xC0F8,0xE2F8,0xA0F8,0xC0F8,0x02F9,0x43F9,0xC0F8,0xE0F0,0x85F9,0xA0E8,0x21F9,0x43F9,0x63F9,0x22F9,0x63F9,0xA4F9,0x65FA,0x64FA,0xA5FA,0xC7FA,0xA4FA,0x85FA,0xA6FA,0xA6FA,0x66FA,0x67FA,0xE7FA,0xA7FA,0xA8FA,0xA8FA,0xA7FA,0xA9FA,0xC8FA,0x2AFB,0xEAFA,0xE9FA,0xEAFA,0x89FA,0x68FA,0x47FA,0x67FA,0xA8FA,0xA7FA,0xE8FA,0xE9FA,0xA7FA,0xA8FA,0x87FA,0xA6FA,0x28FB,0x86FA,0xE6FA,0xC6FA,0xC7FA,0xE6FA,0xE5FA,0x07FB,0x27FB,0x48FB,0x68FB,0x67FB,0x88FB,0xE8FB,0xC8FB,0xA8FB,0xE9FB,0xEAFB,0x09FC,0x8AFC,0x68FC,0x0AFD,0x09FD,0x28FD,0x48FD,0x6CFD,0x09FD,0xE9FC,0x6BFD,0xCAFC,0x88FC,0x68FC,0xC8FC,0x68FC,0x88FC,0x27FC,0x28FC,0x07FC,0xC7FB,0x46FB,0xA7FB,0x05FB,0x07FB,0xE5FA,0x05FB,0x07FB,0xA4FA,0x84FA,0xC5FA,0x63FA,0x84FA,0xC6FA,0xC6FA,0xA5FA,0xC6FA,0x06FB,0xC6FA,0x07FB,0x27FB,0x07FB,0xC5FA,0xE6FA,0xC6FA,0x65FA,0x84FA,0x85FA,0x04FA,0x44FA,0x66FA,0x85FA,0x86FA,0x87FA,0x08FB,0x08FB,0x07FB,0xC5FA,0xE7FA,0xE7FA,0xE7FA,0xC6FA,0xC6FA,0xC6FA,0xA5FA,0xA7FA,0xE7FA,0x86FA,0xC5F9,0xC4F9,0x23F9,0x44F9,0x23F9,0x03F9,0x83F9,0xC3F9,0xC3F9,0xE4F9,0xE5F9,0xE5F9,0x05FA,0xA3F9,0x61F9,0x62F9,0x42F9,0x41F9,0x62F9,0x22F9,0x00F9,0xE0F8,0xE0F8,0x60F9,0xE1F9,0xC1E9,0x20D1,0x00C1,0x01A1,0x6189,0xE551,0x063A,0x6732,0x6832,0x8842,0x683A,0x262A,0x462A,0x2532,0x452A,0x6732,0x663A,0x273A,0x473A,0x673A,0x4742,0x473A,0x483A,0x2842,0x2842,0x4942,0x484A,0x4842,0x473A,0x473A,0x463A,0x2532,0x0432,0x0422,0x0422,0xE429,0xE429,0x0432,0x4432,0x663A,0xC942,0xEB52,0x2E5B,0x4E63,0x4E63,0x4E5B,0x6E63,0xAE6B,0xCE6B,0xEC63,0xCA5B,0xA853,0xA54B,0xA453,0xC353,0xC453,0xA353,0xC24B,0xA143,0x8043,0x2033,0xE02A,0x802A,0x6022,0x6022,0xA02A,0xE02A,0x0033,0x0133,0xE23A,0xC23A,0x823A,0x633A,0x243A,0xE531,0xA429,0x8429,0x4421,0x4429,}, +{0x01F0,0x81F0,0x43E8,0x60F0,0xC1F0,0x03F9,0x23F9,0xE0F8,0x62F9,0x64F9,0xA0F0,0x01F9,0x21F9,0x82F9,0x41F9,0x41E9,0xE5F9,0x08FB,0x24FA,0x84FA,0x26F2,0xC5FA,0xA6FA,0x66FA,0x66FA,0x67FA,0xA8FA,0xE8FA,0x88FA,0x6AFA,0x89FA,0xA9FA,0xCAFA,0xCAFA,0x2BFB,0x0BFB,0xEBFA,0xECFA,0x89FA,0x68FA,0x45FA,0x86FA,0xA7FA,0x07FB,0x69FB,0x08FB,0xC5FA,0xE7FA,0xC8FA,0xA7FA,0x28FB,0xA7FA,0xE6FA,0xC5FA,0xE7FA,0xC5FA,0xC5FA,0xE6FA,0xE5FA,0x06FB,0x26FB,0x45FB,0x46FB,0xA8FB,0x88FB,0x67FB,0xA8FB,0x88FB,0x87FB,0x09FC,0x07FC,0x48FC,0x88FC,0xA7FC,0x85FC,0x87FC,0xE8FC,0xC7FC,0x4CFD,0xAAFC,0xC9FC,0x08FC,0x89FC,0x48FC,0x08FC,0xE6FB,0xEAFB,0xC8FB,0x87FB,0x45FB,0x88FB,0x47FB,0x27FB,0x25FB,0xE5FA,0xE6FA,0xA4FA,0xA3FA,0x27FB,0xA4FA,0x06FB,0x25FB,0x05FB,0xE6FA,0xE6FA,0x26FB,0xC6FA,0x09FB,0x28FB,0xC7FA,0x65FA,0x64FA,0x25FA,0x04FA,0x23FA,0x65FA,0x45FA,0x44FA,0x85FA,0xA6FA,0xA7FA,0xA5FA,0x27FB,0x68FB,0x67FB,0x25FB,0x48FB,0x27FB,0x27FB,0xC4FA,0xC5FA,0x86FA,0xA5FA,0x87FA,0xC7FA,0x85FA,0xC4F9,0x83F9,0x41F9,0x62F9,0x84F9,0x23F9,0x83F9,0x03FA,0x03FA,0x04FA,0x24FA,0x46FA,0x46FA,0xC5F9,0x40F9,0x21F9,0x61F9,0x41F9,0x40F9,0x20F9,0xE0F8,0xC0F8,0x00F9,0x80F9,0xE1F9,0xA0E9,0xE0D8,0xE0C8,0xE0B8,0x4391,0xC659,0x0742,0x483A,0x883A,0xA942,0xA94A,0xA842,0x893A,0x673A,0xA842,0xA952,0xA74A,0x874A,0x8742,0x663A,0x4742,0x663A,0x673A,0x663A,0x2742,0x483A,0x483A,0x2842,0x483A,0x4832,0x6732,0x4532,0x2532,0x0432,0xE529,0xE429,0xE429,0xE329,0x242A,0x2532,0x6732,0x8842,0xCA3A,0xCB42,0xCC52,0xCC52,0xED5A,0x2D63,0x2D63,0x8C5B,0x4A5B,0x484B,0x4643,0x4443,0x6343,0x8243,0xA243,0x813B,0x803B,0x4033,0x0033,0xA02A,0x802A,0x6022,0xA022,0xC02A,0x002B,0x203B,0x213B,0x413B,0x2233,0xE23A,0xA33A,0x433A,0x2432,0xE429,0xA429,0x6429,0x4421,}, +{0x42F8,0x82F0,0x22F0,0x40F0,0x40E0,0xC1F8,0xA0F8,0xE0F8,0x63F9,0x03F9,0x01F9,0x21F9,0x41F9,0x21F1,0x62F9,0xA3F1,0x46FA,0x28FB,0xE4F1,0x04FA,0xC4F1,0x65FA,0x85FA,0xC6F9,0x66FA,0xA9FA,0x2AFB,0xA9FA,0x89FA,0xCAFA,0xECFA,0xCCFA,0x0CFB,0x2DFB,0x2CFB,0xEBFA,0x0BFB,0xAAFA,0x68FA,0x87FA,0xA6FA,0xC8FA,0x29FB,0xCAFB,0xCAFB,0x28FB,0xE5FA,0x05FB,0x09FB,0xA7FA,0x06FB,0x07FB,0x28FB,0xC5FA,0x07FB,0xC5FA,0xA5FA,0xC6FA,0xA5FA,0xC5FA,0x06FB,0x05FB,0x26FB,0x48FB,0x27FB,0x06FB,0x66FB,0x87FB,0x46FB,0xE7FB,0xE7FB,0xE7FB,0x27FC,0x27FC,0xE6FB,0x46FC,0x66FC,0x46FC,0x89FC,0x25FC,0x68FC,0xA5FB,0x49FC,0xC7FB,0x87FB,0xC7FB,0x89FB,0x69FB,0x27FB,0x05FB,0x08FB,0x29FB,0x06FB,0x04FB,0xE5FA,0x07FB,0x04FB,0x03FB,0x48FB,0x04FB,0xC7FA,0xA3FA,0xC5FA,0xC6FA,0xC6FA,0xC4FA,0x85FA,0xE7FA,0x86FA,0x65FA,0x63FA,0x43FA,0x04FA,0x23FA,0x24FA,0x44FA,0x45FA,0x24FA,0x44FA,0x85FA,0xE6FA,0xC4FA,0x25FB,0x87FB,0xA7FB,0xA5FB,0xC7FB,0xA6FB,0x88FB,0x25FB,0xE5FA,0xC6FA,0x05FB,0xE5FA,0xC5FA,0x84FA,0x02FA,0xA2F9,0xC2F9,0xC3F9,0xC3F9,0xA4F9,0xC4F9,0x24FA,0x64FA,0x44FA,0x45FA,0x66FA,0x85FA,0x45FA,0x40F1,0x00F1,0x40F9,0x41F9,0x40F9,0x20F9,0xE1F8,0xC0F8,0x00F9,0x60F9,0xE0F9,0x80E9,0x00E1,0xA0D0,0xC0C0,0x42A9,0xA571,0x274A,0x483A,0x894A,0xCA5A,0x0B5B,0x0953,0xC942,0xC84A,0xC842,0xC74A,0xA74A,0xA642,0xA64A,0x853A,0x663A,0xA442,0x653A,0x453A,0x4532,0x4732,0x4742,0x6742,0x6842,0x483A,0x273A,0x4632,0x0532,0x0432,0xE429,0xE429,0xE329,0x021A,0x0322,0xE321,0x0422,0x052A,0x482A,0x2832,0x2832,0x283A,0x2942,0x8A42,0xAA4A,0xC942,0x8742,0xC53A,0xC432,0xC432,0x032B,0x2233,0x603B,0x403B,0x2033,0xE032,0xC02A,0x802A,0x8022,0x8022,0xA022,0xC02A,0x0033,0x203B,0x6033,0x613B,0x4243,0x2243,0xE232,0xA33A,0x4332,0x032A,0xC331,0x8429,0x4421,}, +{0xC2F8,0x81F0,0x40F8,0x20E8,0x41E0,0x81F8,0x80F8,0xE0F8,0x21F1,0xA1F0,0x42F9,0x62F9,0x61F9,0x61F9,0xA3F9,0xE3F9,0x65FA,0x66FA,0x42F1,0x65F9,0xA4F9,0xE5F9,0x48FA,0x28FA,0x87FA,0xCBFA,0x4AFB,0xAAFA,0xCBFA,0xCBFA,0x0CFB,0x0DFB,0x0CFB,0xEBFA,0xC9FA,0xCAFA,0x87FA,0x47FA,0xA8FA,0xA8FA,0xC7FA,0x49FB,0x89FB,0x0AFC,0x09FC,0x68FB,0x25FB,0x47FB,0x89FB,0x27FB,0x06FB,0x48FB,0x28FB,0x07FB,0x48FB,0x06FB,0x84FA,0xA5FA,0xA4FA,0x85FA,0xE6FA,0xC6FA,0x06FB,0x48FB,0x07FB,0xC5FA,0x26FB,0x47FB,0x26FB,0x66FB,0xA6FB,0xA7FB,0xA6FB,0xC6FB,0xC5FB,0xC6FB,0x05FC,0x05FC,0x47FC,0x23FC,0x05FC,0x63FB,0x25FC,0xA5FB,0x65FB,0x87FB,0x26FB,0x07FB,0x07FB,0x26FB,0x07FB,0x28FB,0xE6FA,0x44FB,0x06FB,0x08FB,0x44FB,0x43FB,0x68FB,0x05FB,0xA6FA,0xA3FA,0xA4FA,0xA5FA,0xC5FA,0xC5FA,0x24FA,0x44FA,0x43FA,0x43FA,0x62FA,0x63FA,0x43FA,0x63FA,0x23FA,0x03FA,0x23FA,0x43FA,0x42FA,0xA3FA,0x44FB,0x43FB,0x64FB,0x84FB,0xC4FB,0x03FC,0x25FC,0xE4FB,0xA6FB,0x64FB,0x43FB,0x03FB,0xE3FA,0xE5FA,0xA3FA,0x63FA,0x03FA,0x03FA,0x22FA,0x04FA,0xE4F9,0xE4F9,0xE3F9,0x44FA,0xC4FA,0xA4FA,0xA5FA,0x85FA,0xA4FA,0x85FA,0xC1F1,0x20E9,0x20F1,0x40F9,0x40F9,0x00F9,0xE0F8,0xC0F8,0x00F9,0xA0F9,0xC0F1,0x80E9,0x00E1,0xA0C8,0xA0C0,0x41B1,0xE4A1,0x4682,0x6852,0xA94A,0xCA52,0x2B5B,0x2A53,0xE94A,0x0843,0x073B,0xC642,0xA542,0x853A,0x843A,0x843A,0x8432,0x8532,0x8432,0x642A,0x4532,0x4632,0x463A,0x673A,0x483A,0x4842,0x473A,0x2732,0x053A,0x0432,0x042A,0x0422,0xE229,0xE221,0xC321,0xE221,0xC221,0xE321,0xE521,0xE729,0xE719,0xE621,0xE521,0xC629,0xE631,0x052A,0x252A,0x242A,0x4432,0x842A,0xC22A,0x022B,0x2033,0x2033,0x0033,0xC02A,0x8022,0x602A,0x8022,0x802A,0xA022,0xE022,0x202B,0x203B,0x603B,0x813B,0x6143,0x6243,0x423B,0xE23A,0xA332,0x4332,0xE331,0xA321,0x6429,}, +{0x22F9,0xA1F8,0x81F8,0x20E0,0xA0F0,0xA0F8,0xA0F8,0xE1F8,0xC0F8,0xA0F8,0x22F9,0x42F9,0xA2F9,0xE3F9,0x03FA,0x24FA,0x44FA,0x62F1,0x00F1,0x62F9,0x06FA,0xE5F9,0x88FA,0x89FA,0xA8FA,0xCAFA,0x08FB,0xCBFA,0xCBFA,0xCAFA,0xCAFA,0xEBFA,0xC9FA,0x89FA,0x87FA,0x88FA,0x87FA,0x86FA,0xC7FA,0xC9FA,0x09FB,0x6AFB,0xCAFB,0x2AFC,0x0AFC,0xE9FB,0x48FC,0x47FB,0x68FB,0x89FB,0x88FB,0x48FB,0x28FB,0x47FB,0x47FB,0x26FB,0xE5FA,0xA4FA,0xE5FA,0xA6FA,0xA4FA,0xE6FA,0x27FB,0x49FB,0xE6FA,0xA5FA,0x27FB,0x27FB,0x06FB,0x46FB,0x87FB,0x45FB,0x45FB,0x66FB,0xA5FB,0x84FB,0xC5FB,0x25FC,0x26FC,0x03FC,0xC6FB,0x05FC,0x23FC,0xE6FB,0x65FB,0x44FB,0xE5FA,0xE5FA,0x26FB,0x66FB,0x05FB,0x25FB,0x45FB,0x44FB,0x45FB,0x45FB,0x84FB,0xA3FB,0xA5FB,0x03FB,0xC5FA,0x04FB,0x84FA,0x83FA,0xC5FA,0x05FB,0x63FA,0x42FA,0x83FA,0xA2FA,0xC2FA,0xE3FA,0xC3FA,0xA4FA,0x22FA,0x43FA,0x62FA,0xC3FA,0xE3FA,0x43FB,0xE2FB,0x23FC,0x24FC,0x23FC,0x63FC,0xC4FC,0x84FC,0x63FC,0x44FC,0xC3FB,0x82FB,0x63FB,0x03FB,0xC3FA,0x82FA,0x42FA,0x43FA,0x65FA,0x65FA,0x43FA,0x44FA,0x04FA,0x24FA,0xC4FA,0x04FB,0xE5FA,0xC5FA,0xC5FA,0xE3FA,0xE3FA,0x23FA,0x40E9,0x20E1,0x40F9,0x20F9,0xC0F8,0xE0F0,0xC0F8,0x00F1,0xA0E1,0xE0D9,0x80E9,0x20E1,0x80D8,0x80D0,0x02C1,0xC5A1,0x887A,0xC852,0xAA4A,0xEA4A,0x2B53,0x0A4B,0x094B,0xE94A,0xE73A,0xA63A,0xA53A,0x843A,0xA43A,0x643A,0x6332,0x832A,0x6232,0x632A,0x632A,0x442A,0x852A,0x8432,0x463A,0x463A,0x473A,0x473A,0x263A,0x2532,0x052A,0x042A,0xE421,0xE321,0xC319,0xC319,0xC221,0xC219,0xA419,0xA521,0x8521,0xA419,0x6419,0x6419,0x8321,0x6321,0xA321,0xC321,0x032A,0x232A,0x833A,0xE22A,0x0133,0x2033,0x0133,0xC02A,0xA022,0x6022,0x8022,0xA022,0xC022,0xE022,0x2033,0x6033,0x803B,0x813B,0x814B,0x8143,0x6243,0x423B,0xE23A,0xA23A,0x4332,0xE329,0xA329,}, +{0x22F9,0xE1F8,0xE2F8,0x20D8,0xC1F8,0x01F9,0xE1F8,0x02F9,0x00F9,0x00F9,0x21F9,0x82F9,0xC2F9,0x04FA,0x03FA,0x43FA,0x05FA,0x01F9,0x42F9,0xC2F9,0x45FA,0x25FA,0x87FA,0x47FA,0xA7FA,0xC7FA,0xE7FA,0xC9FA,0xA8FA,0xC9FA,0x88FA,0xA8FA,0x66FA,0x67FA,0x67FA,0x87FA,0x86FA,0xA7FA,0xE8FA,0x09FB,0x68FB,0xC9FB,0x09FC,0x49FC,0x6AFC,0xAAFC,0x89FC,0xA7FB,0x88FB,0x0AFC,0x0AFC,0x89FB,0x67FB,0x88FB,0x66FB,0x66FB,0x25FB,0xC3FA,0xE5FA,0xE6FA,0x65FA,0x85FA,0x08FB,0x29FB,0x85FA,0x28FB,0x27FB,0x07FB,0x06FB,0x05FB,0x89FB,0x26FB,0x25FB,0x87FB,0x86FB,0x64FB,0x86FB,0x04FC,0x05FC,0xC4FB,0x05FC,0x86FC,0x24FC,0x66FC,0xA4FB,0xA4FB,0x26FB,0x65FB,0x85FB,0xC5FB,0xE3FB,0xE4FB,0xC4FB,0xC3FB,0x84FB,0xE4FB,0xC3FB,0x23FC,0x83FB,0x03FB,0xE4FA,0xE4FA,0xC5FA,0x62FA,0x83FA,0x82FA,0xA2FA,0x82FA,0xC3FA,0xE2FA,0x02FB,0x62FB,0x22FB,0xE2FA,0x62FA,0xC2F1,0xA4FA,0x83FB,0xC3FB,0x04FC,0x84FC,0xC4FC,0xE3FC,0x04FD,0x04FD,0x25FD,0x06FD,0xA3FC,0x64FC,0xA3FB,0x62FB,0x23FB,0xA2FA,0x62FA,0x41FA,0x42FA,0x62FA,0x82FA,0x83FA,0xA2FA,0x83FA,0x64FA,0xA4FA,0x45FB,0x65FB,0x25FB,0xE4FA,0xC4FA,0xE3FA,0xE2FA,0x84FA,0xC2F1,0x20E1,0x00F1,0x00F9,0xC0F8,0xA0F0,0xE0E8,0x40E1,0xC0C1,0xC0C9,0x40F1,0xE0F0,0x80E0,0xA0D0,0xE0C8,0xA491,0x8862,0xE94A,0xCA4A,0x0B4B,0x2A53,0x4A53,0x2A4B,0x084B,0xE73A,0xA53A,0xA532,0xA432,0x8332,0x8332,0x8332,0x6232,0x612A,0x6122,0x422A,0x821A,0x6322,0x832A,0xC32A,0x842A,0x6532,0x463A,0x263A,0x452A,0x242A,0x0422,0xE421,0xE311,0xE319,0xC319,0xA221,0xC219,0xA221,0x8321,0x8421,0x8319,0x4321,0x4319,0x6319,0x6311,0x6319,0x8321,0xC321,0x022A,0x2332,0xA22A,0xE132,0x0133,0x023B,0xE032,0xA02A,0x8122,0x801A,0xC01A,0xC022,0x002B,0x202B,0x612B,0x613B,0x813B,0x8143,0xA143,0x8143,0x6143,0x223B,0xE23A,0x8232,0x422A,0xE329,}, +{0x64F9,0x22F9,0xC3F8,0x80E0,0x21F9,0x83F9,0x23F9,0x22F9,0x42F9,0x21F9,0x41F9,0x82F9,0xC2F9,0xC3F9,0xC3F9,0xE3F9,0x84F9,0x42F9,0xC3F9,0x24FA,0x45FA,0x25FA,0x87FA,0x66FA,0x85FA,0x86FA,0x85FA,0xA6FA,0x87FA,0x87FA,0x87FA,0xA7FA,0x86FA,0xA7FA,0xA7FA,0xA8FA,0xA7FA,0xC7FA,0xE8FA,0x49FB,0xC9FB,0x2AFC,0x49FC,0xA9FC,0x29FD,0x09FD,0xC8FC,0x68FC,0xE8FB,0x6AFC,0x2AFC,0xA9FB,0x85FB,0xE9FB,0x07FC,0x87FB,0x86FB,0x44FB,0x26FB,0x26FB,0xC5FA,0xC5FA,0x8AFB,0x29FB,0x42FA,0x47FB,0x27FB,0xA5FA,0x27FB,0xE5FA,0x87FB,0x67FB,0x46FB,0x48FB,0x66FB,0x63FB,0x66FB,0x64FB,0x08FC,0xA5FB,0x25FC,0x68FC,0xA5FC,0xE5FC,0x05FC,0x05FC,0x86FB,0xC4FB,0xA4FB,0x04FC,0xA4FC,0x44FC,0x04FC,0x04FC,0xE4FB,0xE4FB,0xE4FB,0x23FC,0x44FB,0x04FB,0xE5FA,0xC4FA,0x05FB,0x83FA,0x82FA,0xA3FA,0xE2FA,0xC2FA,0x23FB,0x42FB,0x63FB,0xC2FB,0xA2FB,0xE3FB,0x03FB,0xC1F1,0x06FB,0x04FC,0xA4FC,0xA3FC,0xA3FC,0xA3FC,0x03FD,0x45FD,0x44FD,0x25FD,0xE6FC,0x64FC,0x03FC,0x63FB,0xE2FA,0xA2FA,0x62FA,0x42FA,0x21FA,0x41FA,0x82FA,0xA2FA,0xC3FA,0xE1FA,0x22FB,0x44FB,0x84FB,0xA5FB,0xA5FB,0x43FB,0x03FB,0xE3FA,0x23FB,0x22FB,0xE3FA,0x63FA,0x40E9,0xE0E8,0xA0F8,0xA0F8,0xC0F0,0x40E1,0xA0B9,0xC0B9,0x40D1,0x40E9,0xE0F8,0xA0E0,0xA0C8,0x00C1,0x61B9,0x6592,0x085B,0x0B4B,0x0B4B,0x2A53,0x4A4B,0x2A4B,0x284B,0xE63A,0xA53A,0xC42A,0xA43A,0x8332,0x832A,0x632A,0x612A,0x8022,0x812A,0x6222,0x811A,0x6222,0xA222,0xA322,0xA42A,0xA52A,0x863A,0x6632,0x4632,0x4422,0x2422,0xE421,0x021A,0xC321,0xC221,0xA221,0xA221,0xA219,0x8221,0x8221,0x6319,0x8321,0x8319,0x6219,0x8319,0x8219,0x8321,0xA219,0xE221,0x222A,0x822A,0xA232,0x0133,0x023B,0xE13A,0xC032,0xC122,0xA12A,0xA122,0xC12A,0x012B,0x2133,0x4133,0x613B,0x813B,0xA143,0xA14B,0x814B,0x6143,0x4143,0xE242,0xA13A,0x6232,0x222A,}, +{0x63F9,0x23F9,0x41E8,0xE1E8,0x83F9,0xE5F9,0xC5F9,0x84F9,0x62F9,0x82F9,0x82F9,0xA3F9,0xC3F9,0xA2F9,0xA2F9,0xC2F9,0x42F9,0x83F9,0x04FA,0x24FA,0x65FA,0x64FA,0x87FA,0x46FA,0x85FA,0x85FA,0xA5FA,0x86FA,0x85FA,0x85FA,0xC5FA,0xE8FA,0xE7FA,0xC7FA,0xA7FA,0xA7FA,0xC7FA,0x08FB,0x49FB,0xAAFB,0xEAFB,0x4AFC,0xAAFC,0x48FD,0x88FD,0x48FD,0x49FD,0xE8FC,0x27FC,0x8BFC,0x89FC,0x28FC,0x26FC,0x49FC,0x07FC,0xC6FB,0xE6FB,0x65FB,0x25FB,0x06FB,0x26FB,0xC4FA,0x89FB,0x07FB,0x62FA,0x47FB,0x27FB,0xA4FA,0x47FB,0x06FB,0x26FB,0x46FB,0x26FB,0xA5FA,0xA7FB,0x04FB,0x45FB,0x04FB,0xC8FB,0x65FB,0x84FB,0x29FC,0x06FD,0xC5FC,0x46FC,0x05FC,0x65FB,0xE4FB,0xE6FB,0xE4FB,0x26FD,0xA5FC,0x83FC,0x85FC,0x05FC,0xE5FB,0xA4FB,0x45FB,0x05FB,0xE5FA,0xA4FA,0x83FA,0xC3FA,0x63FA,0x83FA,0xA2FA,0x22FB,0x23FB,0x83FB,0xA2FB,0xC3FB,0x42FC,0x02FC,0x63FC,0xC4FB,0x41FA,0x66FB,0x85FC,0x26FD,0x26FD,0xC3FB,0x41FB,0x83FC,0x44FD,0x24FD,0xC5FC,0x85FC,0x04FC,0x62FB,0xE3FA,0x82FA,0x62FA,0x21FA,0x21FA,0x41FA,0x61FA,0x81FA,0xC1FA,0x01FB,0x62FB,0x02FC,0x44FC,0x45FC,0xE4FB,0xE3FB,0xC3FB,0x62FB,0x42FB,0xA4FB,0x82FB,0x23FB,0xA3FA,0xA2F9,0xC0E8,0xA0E8,0xC0F0,0x00E9,0x60B9,0xC091,0xA0A9,0x20D1,0x00F1,0xE0F0,0xC0E8,0xA0D0,0x00C1,0x80C1,0x43A2,0x0673,0x2A53,0x2A4B,0x2A4B,0x2A4B,0x2A43,0xE94A,0xE63A,0xA63A,0x8432,0x832A,0x6332,0x632A,0x822A,0x6122,0x8022,0x611A,0x402A,0x412A,0x6122,0x8122,0x8222,0xA322,0xC42A,0xA632,0x8532,0x6632,0x6422,0x2422,0x0522,0x0222,0xE321,0xE119,0xC219,0x8121,0xA219,0x6219,0x8219,0x8211,0x8319,0x8319,0xA321,0x8319,0x8219,0xA119,0xA119,0xE219,0x012A,0x612A,0xA12A,0xE232,0x0233,0x013B,0x0133,0xC22A,0xC22A,0xC22A,0xA12A,0xE12A,0x2133,0x4133,0x4233,0x6133,0x813B,0x6243,0x8143,0x6143,0x4143,0x0143,0xC242,0x8232,0x2232,}, +{0xE2E0,0xA2F0,0x80E8,0x01F1,0x63F9,0xC5F9,0xE6F9,0xA5F9,0x83F9,0x82F9,0x81F9,0xA2F9,0xA2F9,0xA2F9,0x82F9,0xC2F9,0x20F9,0xC3F9,0x44FA,0x24FA,0x46FA,0x66FA,0x46FA,0x65FA,0xA6FA,0xC4FA,0xC5FA,0xA5FA,0xA5FA,0xC6FA,0x06FB,0x28FB,0x07FB,0x07FB,0xE7FA,0xC6FA,0x08FB,0x6AFB,0xAAFB,0xE9FB,0x29FC,0x6AFC,0xCAFC,0x68FD,0x48FD,0x89FD,0x6AFD,0x48FD,0x08FD,0x2BFD,0x2AFD,0xE8FC,0x66FC,0xAAFC,0x48FC,0x68FC,0x07FC,0x86FB,0x46FB,0x87FB,0x87FB,0x45FB,0xAAFB,0x06FB,0xC4FA,0x47FB,0x46FB,0xA3FA,0x69FB,0x06FB,0xA5FA,0x47FB,0x27FB,0xC5FA,0x68FB,0x64FA,0x88FB,0x83FA,0x47FB,0xE5FA,0x04FB,0x0AFC,0xC6FC,0x04FC,0xA7FC,0x45FC,0x65FB,0x85FB,0x07FC,0x05FC,0xC5FC,0x84FC,0xA6FC,0x24FC,0xA4FB,0xA6FB,0xE4FA,0xE6FA,0x63FA,0x62FA,0xA4FA,0x83FA,0x62FA,0x63FA,0xA3FA,0x62FA,0x02FB,0x23FB,0x41FB,0xA2FB,0x04FC,0x83FC,0xC1FB,0x03FC,0x22FC,0x82FA,0xE3FA,0xE7FC,0xA7FD,0x85FD,0x03FC,0x80FA,0x62FB,0xC4FC,0xC3FC,0x44FC,0xA4FB,0x44FB,0xE2FA,0xA2FA,0x61FA,0x41FA,0x02FA,0x22FA,0x62FA,0xC1FA,0x01FB,0x41FB,0x81FB,0x02FC,0x82FC,0xC3FC,0x85FC,0x84FC,0x64FC,0x44FC,0xC2FB,0x82FB,0xC2FB,0xA2FB,0x23FB,0x83FA,0xC2F9,0xE1F8,0xC0E0,0xE0E8,0x40D1,0xA0A9,0xA0A1,0x80A9,0x00E1,0xC0F0,0xC0F8,0x80F0,0xC0D0,0x20C1,0x60B9,0x0192,0xE56A,0x2853,0x2A53,0x0A4B,0x0A4B,0xE94A,0xE842,0xE63A,0xC53A,0xA432,0x642A,0x6332,0x8332,0x822A,0x612A,0x802A,0x4022,0x402A,0x402A,0x4022,0x6122,0x811A,0x8222,0xA42A,0xA42A,0xA32A,0xA32A,0x8332,0x4232,0x232A,0x2322,0x011A,0xE211,0xA119,0xA111,0xA111,0x6219,0x6219,0x6219,0x6219,0xA319,0xA321,0xC219,0xC119,0xC219,0xA121,0xC119,0x0022,0x4122,0xA132,0xE232,0x0233,0x213B,0x023B,0x023B,0xE232,0xC232,0xC22A,0xC12A,0xE22A,0x0133,0x2233,0x2133,0x413B,0x413B,0x423B,0x2243,0x214B,0x0243,0xE23A,0x823A,0x4232,}, +{0x81D8,0x80E8,0x80E0,0x22E9,0x45E9,0x83F1,0xA5F9,0xA5F9,0x62F1,0x21F9,0xA1F9,0x81F9,0xC2F9,0xA2F9,0xE2F9,0xA2F9,0x81F9,0x44FA,0x85FA,0x66FA,0x66FA,0x45FA,0x25FA,0x84FA,0x84FA,0xA5FA,0xA5FA,0xC6FA,0xC6FA,0x28FB,0x48FB,0x48FB,0x28FB,0x28FB,0x28FB,0x26FB,0xA9FB,0x0BFC,0x2AFC,0x49FC,0x69FC,0x88FC,0xE9FC,0x48FD,0x27FD,0x28FD,0x68FD,0x87FD,0x88FD,0x6BFD,0x6AFD,0xA9FD,0xC8FC,0xE9FC,0x66FC,0x08FD,0x26FC,0xE7FB,0x06FC,0x08FC,0x27FC,0xA5FB,0xCAFB,0x25FB,0xA5FB,0x65FB,0x66FB,0x64FB,0x66FB,0x67FB,0x85FA,0x27FB,0x47FB,0xC4FA,0x28FB,0x43FA,0x47FB,0x63FA,0x47FB,0x83FA,0xA5FA,0x88FB,0xA6FB,0x64FB,0x05FC,0x26FC,0x25FB,0x25FB,0xE6FB,0x06FC,0xE4FB,0x03FC,0x26FC,0xC5FB,0x64FB,0x25FB,0x64FA,0x45FA,0xE2F9,0xE1F9,0x44FA,0xC2F9,0x43FA,0x42FA,0x83FA,0xC3FA,0x42FB,0xC2FB,0xC2FB,0x63FC,0xC4FC,0xE3FC,0x23FC,0x82FB,0x63FC,0x61FA,0x20FA,0xA6FC,0x85FD,0x86FD,0xA5FC,0x40FA,0x40FA,0xA4FB,0x24FC,0xC4FB,0x23FB,0xC3FA,0xA4FA,0x82FA,0x61FA,0x21FA,0xE1F9,0x42FA,0xA2FA,0x01FB,0x42FB,0xC1FB,0x01FC,0x82FC,0xE3FC,0x04FD,0x64FC,0xC5FC,0xC5FC,0xC4FC,0x42FC,0xC1FB,0xA2FB,0xA1FB,0x23FB,0x02FA,0x82F9,0x02F9,0xE0E8,0x20D9,0x60B1,0xA0A1,0x80A9,0x40B9,0xE0E0,0xE0F8,0xA0F8,0xA0E8,0xC0D0,0x40B9,0xA0A9,0xE099,0x846A,0xC752,0xE94A,0x0B43,0x094B,0x094B,0x2743,0xE63A,0xE632,0xA432,0x8432,0x6332,0xA232,0xA22A,0x612A,0x8022,0x6022,0x412A,0x412A,0x6022,0x4122,0x601A,0x6122,0x8112,0x8112,0xA12A,0xC122,0xC12A,0x812A,0x622A,0x4222,0x2222,0xE219,0xA119,0xA119,0xA109,0x6111,0x6211,0x6219,0x6319,0x8319,0xC219,0xC219,0xC219,0xA221,0xC119,0xE119,0x011A,0x611A,0xA12A,0xE232,0x2233,0x4233,0x4243,0x223B,0x033B,0xE332,0xA32A,0x812A,0x822A,0xA132,0xC12A,0xE132,0xE132,0x0133,0x0133,0x013B,0xE13A,0xC242,0xC23A,0x823A,0x4232,}, +{0x83F0,0xA0F0,0xA0E8,0x04F1,0x47F1,0x85F9,0x45F1,0x44F9,0xC5F1,0x03FA,0x03FA,0x03FA,0x23FA,0xE2F9,0x23FA,0xC2F9,0x24FA,0xA6FA,0x86FA,0xA7FA,0x86FA,0xA6FA,0x45FA,0x85FA,0x66FA,0xC6FA,0xE6FA,0xE8FA,0xE7FA,0x28FB,0x68FB,0xA7FB,0x47FB,0x69FB,0x68FB,0xA8FB,0x0AFC,0x4AFC,0x4AFC,0x88FC,0xA8FC,0xC7FC,0xE9FC,0x68FD,0x27FD,0x48FD,0x87FD,0xC7FD,0xE8FD,0xABFD,0x0BFE,0x09FE,0x07FD,0x48FD,0xE7FC,0xE6FC,0x85FC,0x66FC,0x67FC,0x86FC,0xC7FC,0x05FC,0x09FC,0x05FC,0xC6FB,0x25FB,0x67FB,0x85FB,0x25FB,0x89FB,0xE3F9,0x84FA,0x28FB,0x85FA,0xC8FA,0x44FA,0xA6FA,0xA4FA,0x27FB,0x64FA,0x86FA,0xC5FA,0xE6FA,0xA4FA,0xA3FA,0x87FB,0xE7FA,0xC5FA,0x25FB,0x87FB,0x66FB,0x24FB,0x25FB,0x45FB,0xA4FA,0x23FA,0x23FA,0x03FA,0x81F9,0xA2F9,0xA2F9,0xC3F9,0xE3F9,0x02FA,0x22FA,0xA2FA,0x21FB,0xC3FB,0xE2FB,0x63FC,0xA4FC,0xC3FC,0x02FC,0xA3FB,0xA3FC,0xA1FA,0xC0F9,0x83FB,0x06FD,0x07FD,0x65FC,0x61FA,0xA0F9,0x83FA,0xE3FA,0x03FB,0xE3FA,0x82FA,0xA5FA,0xE3FA,0xA2FA,0x62FA,0x02FA,0x82FA,0xE2FA,0x01FB,0x21FB,0xC0FB,0x42FC,0xA2FC,0xE3FC,0x04FD,0x42FC,0x42FC,0xA4FC,0xE4FC,0xA3FC,0xC1FB,0xA0FB,0x61FB,0x81FA,0x81F9,0x21F9,0x00F9,0x00F9,0x20D9,0x60B1,0xA0A1,0x80B9,0x20C9,0x00E9,0xE0F0,0xE0F0,0xC0E8,0x00D1,0x80A9,0xC081,0xE169,0x444A,0x8742,0xEA4A,0x0B4B,0x2A43,0x2A4B,0x294B,0x0743,0xE73A,0xC53A,0xC432,0x8432,0xA332,0xA432,0xA332,0xA22A,0x6122,0x612A,0x6022,0x6122,0x4222,0x6122,0x601A,0x4012,0x601A,0x8012,0xA022,0x8022,0x601A,0x601A,0x611A,0x2222,0xE221,0xC219,0xA119,0xA119,0x6111,0x6111,0x4219,0x4311,0x6319,0x8219,0x8219,0xA219,0x8129,0xC119,0xE119,0x001A,0x401A,0x812A,0x0133,0x423B,0x4233,0x4143,0x423B,0x033B,0xE232,0xA22A,0x812A,0x612A,0x6122,0x8122,0x802A,0x812A,0xA022,0xA12A,0xC132,0xA032,0xA132,0x8132,0x6132,0x4232,}, +{0xC4F8,0x81F8,0x00F9,0x24F9,0x46F9,0x86F1,0x24F9,0x63F9,0xC7E9,0x65FA,0x86FA,0x85FA,0xA5FA,0x64FA,0x84FA,0x23FA,0x06FB,0x68FB,0x08FB,0x28FB,0x07FB,0xC6FA,0x86FA,0xA7FA,0x86FA,0xE6FA,0xE7FA,0x07FB,0x08FB,0x28FB,0x68FB,0xC9FB,0x89FB,0x89FB,0xCAFB,0xEAFB,0x4BFC,0x49FC,0x4AFC,0x89FC,0x88FC,0xE8FC,0x08FD,0x47FD,0x47FD,0x86FD,0xC7FD,0x27FE,0x48FE,0x0AFE,0x4AFE,0x89FE,0xE8FD,0xA8FD,0x88FD,0x67FD,0x47FD,0x07FD,0xA8FC,0xA6FC,0x87FC,0x25FC,0x48FC,0xC7FC,0x08FC,0xE7FB,0xC9FB,0x87FB,0x06FB,0x69FB,0x45FA,0xE4F9,0x08FB,0x87FA,0x66FA,0x24FA,0x05FA,0xA6FA,0xE7FA,0x64FA,0xA5FA,0x84FA,0xE6FA,0x64FA,0x23FA,0x27FB,0x06FB,0x84FA,0xA4FA,0xA5FA,0x68FB,0xA4FA,0x43FA,0xE5FA,0x44FA,0xA2F9,0x03FA,0xA2F9,0x83F9,0xE2F9,0x80F9,0xC3F9,0xC2F9,0x43FA,0x22FA,0x22FA,0x01FA,0xC3FA,0xE2FA,0x83FB,0x23FC,0xA3FC,0xC2FB,0x83FB,0x06FD,0xE1FA,0xE0F9,0x60FA,0x25FC,0x46FC,0xC5FB,0x82FA,0xC0F9,0xA1F9,0x64FA,0x83FA,0x23FA,0xE3F9,0x44FA,0x83FA,0xA2FA,0x61FA,0xE2F9,0xC2FA,0x21FB,0x62FB,0xC2FB,0x02FC,0x42FC,0xA2FC,0xE2FC,0x23FD,0x21FC,0x60FB,0x41FC,0xA2FC,0xA2FC,0x41FC,0x40FB,0xE0FA,0x20FA,0x40F9,0x20F9,0x40E9,0x20F1,0x40E9,0xA0D1,0xC0B9,0x80B9,0x20D9,0x40E9,0x00F9,0x00F1,0x00E1,0x40D1,0xA0A1,0xA071,0xC351,0x473A,0xA83A,0x0B4B,0x2A43,0x4A53,0x294B,0x2943,0x4843,0x273B,0x063B,0xC432,0xA442,0xA332,0xA53A,0xA43A,0xA22A,0x802A,0x602A,0x402A,0x4022,0x6222,0x8022,0x6022,0x601A,0x401A,0x6112,0x401A,0x4022,0x4022,0x4022,0x4122,0x212A,0x2222,0x0222,0xE119,0xC111,0x8011,0x8011,0x4111,0x6111,0x6111,0x6111,0x8111,0x8209,0x8119,0xC111,0xC119,0x001A,0x211A,0x6222,0xE12A,0x0133,0x6133,0x413B,0x4233,0x023B,0xC132,0x822A,0x4122,0x4222,0x211A,0x2022,0x2122,0x411A,0x401A,0x4022,0x6022,0x602A,0x602A,0x412A,0x212A,0x012A,}, +}; diff --git a/Inc/FreeRTOSConfig.h b/Inc/FreeRTOSConfig.h new file mode 100644 index 0000000..35de7fd --- /dev/null +++ b/Inc/FreeRTOSConfig.h @@ -0,0 +1,130 @@ +/* USER CODE BEGIN Header */ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + /* USER CODE END Header */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * These parameters and more are described within the 'configuration' section of the + * FreeRTOS API documentation available on the FreeRTOS.org web site. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ +/* Section where include file can be added */ +/* USER CODE END Includes */ + +/* Ensure definitions are only used by the compiler, and not by the assembler. */ +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + #include + extern uint32_t SystemCoreClock; + void xPortSysTickHandler(void); +#endif +#define configUSE_PREEMPTION 1 +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES ( 7 ) +#define configMINIMAL_STACK_SIZE ((uint16_t)128) +#define configTOTAL_HEAP_SIZE ((size_t)3072) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_16_BIT_TICKS 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 4 +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +/* USER CODE BEGIN 1 */ +#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} +/* USER CODE END 1 */ + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler + +/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick, + to prevent overwriting SysTick_Handler defined within STM32Cube HAL */ +/* #define xPortSysTickHandler SysTick_Handler */ + +/* USER CODE BEGIN Defines */ +/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ +/* USER CODE END Defines */ + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Inc/main.h b/Inc/main.h new file mode 100644 index 0000000..7a5ce0b --- /dev/null +++ b/Inc/main.h @@ -0,0 +1,71 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Inc/stm32f1xx_hal_conf.h b/Inc/stm32f1xx_hal_conf.h new file mode 100644 index 0000000..8e0025d --- /dev/null +++ b/Inc/stm32f1xx_hal_conf.h @@ -0,0 +1,392 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_CONF_H +#define __STM32F1xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_CAN_MODULE_ENABLED */ +/*#define HAL_CAN_LEGACY_MODULE_ENABLED */ +/*#define HAL_CEC_MODULE_ENABLED */ +/*#define HAL_CORTEX_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_DMA_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_FLASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_PCCARD_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_PWR_MODULE_ENABLED */ +/*#define HAL_RCC_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_SDRAM_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/*#define HAL_SRAM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ + +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)15) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32f1xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32f1xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32f1xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32f1xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32f1xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED +#include "stm32f1xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32f1xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32f1xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32f1xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32f1xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32f1xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32f1xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32f1xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32f1xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32f1xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32f1xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32f1xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32f1xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32f1xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32f1xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED +#include "stm32f1xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32f1xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32f1xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32f1xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32f1xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32f1xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32f1xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32f1xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32f1xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32f1xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32f1xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32f1xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32f1xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t* file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Inc/stm32f1xx_it.h b/Inc/stm32f1xx_it.h new file mode 100644 index 0000000..6623672 --- /dev/null +++ b/Inc/stm32f1xx_it.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f1xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_IT_H +#define __STM32F1xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +void SysTick_Handler(void); +void USB_LP_CAN1_RX0_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Inc/usb_device.h b/Inc/usb_device.h new file mode 100644 index 0000000..dba0ee6 --- /dev/null +++ b/Inc/usb_device.h @@ -0,0 +1,105 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usb_device.h + * @version : v2.0_Cube + * @brief : Header for usb_device.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_DEVICE__H__ +#define __USB_DEVICE__H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" +#include "stm32f1xx_hal.h" +#include "usbd_def.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBD_OTG_DRIVER + * @{ + */ + +/** @defgroup USBD_DEVICE USBD_DEVICE + * @brief Device file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables + * @brief Public variables. + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN VARIABLES */ + +/* USER CODE END VARIABLES */ +/** + * @} + */ + +/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/** USB Device initialization function. */ +void MX_USB_DEVICE_Init(void); + +/* + * -- Insert functions declaration here -- + */ +/* USER CODE BEGIN FD */ + +/* USER CODE END FD */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEVICE__H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Inc/usbd_cdc_if.h b/Inc/usbd_cdc_if.h new file mode 100644 index 0000000..5299c47 --- /dev/null +++ b/Inc/usbd_cdc_if.h @@ -0,0 +1,130 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_cdc_if.h + * @version : v2.0_Cube + * @brief : Header for usbd_cdc_if.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CDC_IF_H__ +#define __USBD_CDC_IF_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @brief For Usb device. + * @{ + */ + +/** @defgroup USBD_CDC_IF USBD_CDC_IF + * @brief Usb VCP device module + * @{ + */ + +/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines + * @brief Defines. + * @{ + */ +/* USER CODE BEGIN EXPORTED_DEFINES */ + +/* USER CODE END EXPORTED_DEFINES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types + * @brief Types. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_TYPES */ + +/* USER CODE END EXPORTED_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_MACRO */ + +/* USER CODE END EXPORTED_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** CDC Interface callback. */ +extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; + +/* USER CODE BEGIN EXPORTED_VARIABLES */ + +/* USER CODE END EXPORTED_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype + * @brief Public functions declaration. + * @{ + */ + +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); + +/* USER CODE BEGIN EXPORTED_FUNCTIONS */ + +/* USER CODE END EXPORTED_FUNCTIONS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CDC_IF_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Inc/usbd_conf.h b/Inc/usbd_conf.h new file mode 100644 index 0000000..60f4fec --- /dev/null +++ b/Inc/usbd_conf.h @@ -0,0 +1,177 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_conf.h + * @version : v2.0_Cube + * @brief : Header for usbd_conf.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CONF__H__ +#define __USBD_CONF__H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include "main.h" +#include "stm32f1xx.h" +#include "stm32f1xx_hal.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBD_OTG_DRIVER + * @{ + */ + +/** @defgroup USBD_CONF USBD_CONF + * @brief Configuration file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines + * @brief Defines for configuration of the Usb device. + * @{ + */ + +/*---------- -----------*/ +#define USBD_MAX_NUM_INTERFACES 1 +/*---------- -----------*/ +#define USBD_MAX_NUM_CONFIGURATION 1 +/*---------- -----------*/ +#define USBD_MAX_STR_DESC_SIZ 512 +/*---------- -----------*/ +#define USBD_DEBUG_LEVEL 0 +/*---------- -----------*/ +#define USBD_SELF_POWERED 1 +/*---------- -----------*/ +#define MAX_STATIC_ALLOC_SIZE 512 + +/****************************************/ +/* #define for FS and HS identification */ +#define DEVICE_FS 0 + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* Memory management macros */ + +/** Alias for memory allocation. */ +#define USBD_malloc (uint32_t *)USBD_static_malloc + +/** Alias for memory release. */ +#define USBD_free USBD_static_free + +/** Alias for memory set. */ +#define USBD_memset /* Not used */ + +/** Alias for memory copy. */ +#define USBD_memcpy /* Not used */ + +/** Alias for delay. */ +#define USBD_Delay HAL_Delay + +/* For footprint reasons and since only one allocation is handled in the HID class + driver, the malloc/free is changed into a static allocation method */ +void *USBD_static_malloc(uint32_t size); +void USBD_static_free(void *p); + +/* DEBUG macros */ + +#if (USBD_DEBUG_LEVEL > 0) +#define USBD_UsrLog(...) printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_UsrLog(...) +#endif + +#if (USBD_DEBUG_LEVEL > 1) + +#define USBD_ErrLog(...) printf("ERROR: ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_ErrLog(...) +#endif + +#if (USBD_DEBUG_LEVEL > 2) +#define USBD_DbgLog(...) printf("DEBUG : ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_DbgLog(...) +#endif + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types + * @brief Types. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/* Exported functions -------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CONF__H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Inc/usbd_desc.h b/Inc/usbd_desc.h new file mode 100644 index 0000000..1af85d4 --- /dev/null +++ b/Inc/usbd_desc.h @@ -0,0 +1,145 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_desc.c + * @version : v2.0_Cube + * @brief : Header for usbd_conf.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DESC__C__ +#define __USBD_DESC__C__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_DESC USBD_DESC + * @brief Usb device descriptors module. + * @{ + */ + +/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants + * @brief Constants. + * @{ + */ +#define DEVICE_ID1 (UID_BASE) +#define DEVICE_ID2 (UID_BASE + 0x4) +#define DEVICE_ID3 (UID_BASE + 0x8) + +#define USB_SIZ_STRING_SERIAL 0x1A + +/* USER CODE BEGIN EXPORTED_CONSTANTS */ + +/* USER CODE END EXPORTED_CONSTANTS */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines + * @brief Defines. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_DEFINES */ + +/* USER CODE END EXPORTED_DEFINES */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions + * @brief Types. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_TYPES */ + +/* USER CODE END EXPORTED_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_MACRO */ + +/* USER CODE END EXPORTED_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** Descriptor for the Usb device. */ +extern USBD_DescriptorsTypeDef FS_Desc; + +/* USER CODE BEGIN EXPORTED_VARIABLES */ + +/* USER CODE END EXPORTED_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype + * @brief Public functions declaration. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_FUNCTIONS */ + +/* USER CODE END EXPORTED_FUNCTIONS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_DESC__C__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h new file mode 100644 index 0000000..6702b54 --- /dev/null +++ b/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -0,0 +1,179 @@ +/** + ****************************************************************************** + * @file usbd_cdc.h + * @author MCD Application Team + * @brief header file for the usbd_cdc.c file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CDC_H +#define __USB_CDC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_cdc + * @brief This file is the Header file for usbd_cdc.c + * @{ + */ + + +/** @defgroup usbd_cdc_Exported_Defines + * @{ + */ +#define CDC_IN_EP 0x81U /* EP1 for data IN */ +#define CDC_OUT_EP 0x01U /* EP1 for data OUT */ +#define CDC_CMD_EP 0x82U /* EP2 for CDC commands */ + +#ifndef CDC_HS_BINTERVAL +#define CDC_HS_BINTERVAL 0x10U +#endif /* CDC_HS_BINTERVAL */ + +#ifndef CDC_FS_BINTERVAL +#define CDC_FS_BINTERVAL 0x10U +#endif /* CDC_FS_BINTERVAL */ + +/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 512U /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_FS_MAX_PACKET_SIZE 64U /* Endpoint IN & OUT Packet size */ +#define CDC_CMD_PACKET_SIZE 8U /* Control Endpoint Packet size */ + +#define USB_CDC_CONFIG_DESC_SIZ 67U +#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE +#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE + +#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE +#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE + +/*---------------------------------------------------------------------*/ +/* CDC definitions */ +/*---------------------------------------------------------------------*/ +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00U +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01U +#define CDC_SET_COMM_FEATURE 0x02U +#define CDC_GET_COMM_FEATURE 0x03U +#define CDC_CLEAR_COMM_FEATURE 0x04U +#define CDC_SET_LINE_CODING 0x20U +#define CDC_GET_LINE_CODING 0x21U +#define CDC_SET_CONTROL_LINE_STATE 0x22U +#define CDC_SEND_BREAK 0x23U + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ +typedef struct +{ + uint32_t bitrate; + uint8_t format; + uint8_t paritytype; + uint8_t datatype; +} USBD_CDC_LineCodingTypeDef; + +typedef struct _USBD_CDC_Itf +{ + int8_t (* Init)(void); + int8_t (* DeInit)(void); + int8_t (* Control)(uint8_t cmd, uint8_t *pbuf, uint16_t length); + int8_t (* Receive)(uint8_t *Buf, uint32_t *Len); + +} USBD_CDC_ItfTypeDef; + + +typedef struct +{ + uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE / 4U]; /* Force 32bits alignment */ + uint8_t CmdOpCode; + uint8_t CmdLength; + uint8_t *RxBuffer; + uint8_t *TxBuffer; + uint32_t RxLength; + uint32_t TxLength; + + __IO uint32_t TxState; + __IO uint32_t RxState; +} +USBD_CDC_HandleTypeDef; + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_ClassTypeDef USBD_CDC; +#define USBD_CDC_CLASS &USBD_CDC +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops); + +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length); + +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff); + +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev); + +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_CDC_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c new file mode 100644 index 0000000..b27fb55 --- /dev/null +++ b/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -0,0 +1,945 @@ +/** + ****************************************************************************** + * @file usbd_cdc.c + * @author MCD Application Team + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB CDC Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as CDC Device (and enumeration for each implemented memory interface) + * - OUT/IN data transfer + * - Command IN transfer (class requests management) + * - Error management + * + * @verbatim + * + * =================================================================== + * CDC Class Driver Description + * =================================================================== + * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices + * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus + * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) + * - Requests management (as described in section 6.2 in specification) + * - Abstract Control Model compliant + * - Union Functional collection (using 1 IN endpoint for control) + * - Data interface class + * + * These aspects may be enriched or modified for a specific user application. + * + * This driver doesn't implement the following aspects of the specification + * (but it is possible to manage these features with some modifications on this driver): + * - Any class-specific aspect relative to communication classes should be managed by user application. + * - All communication classes other than PSTN are not managed + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* BSPDependencies +- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c" +- "stm32xxxxx_{eval}{discovery}_io.c" +EndBSPDependencies */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" +#include "usbd_ctlreq.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CDC + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CDC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_FunctionPrototypes + * @{ + */ + + +static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, + uint8_t cfgidx); + +static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, + uint8_t epnum); + +static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, + uint8_t epnum); + +static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev); + +static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length); + +static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length); + +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); + +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); + +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length); + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Variables + * @{ + */ + + +/* CDC interface class callbacks structure */ +USBD_ClassTypeDef USBD_CDC = +{ + USBD_CDC_Init, + USBD_CDC_DeInit, + USBD_CDC_Setup, + NULL, /* EP0_TxSent, */ + USBD_CDC_EP0_RxReady, + USBD_CDC_DataIn, + USBD_CDC_DataOut, + NULL, + NULL, + NULL, + USBD_CDC_GetHSCfgDesc, + USBD_CDC_GetFSCfgDesc, + USBD_CDC_GetOtherSpeedCfgDesc, + USBD_CDC_GetDeviceQualifierDescriptor, +}; + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + CDC_HS_BINTERVAL, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; + + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + CDC_FS_BINTERVAL, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00 /* bInterval: ignore for Bulk transfer */ +} ; + +__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + CDC_FS_BINTERVAL, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00 /* bInterval */ +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Functions + * @{ + */ + +/** + * @brief USBD_CDC_Init + * Initialize the CDC interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + uint8_t ret = 0U; + USBD_CDC_HandleTypeDef *hcdc; + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, + CDC_DATA_HS_IN_PACKET_SIZE); + + pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, + CDC_DATA_HS_OUT_PACKET_SIZE); + + pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; + + } + else + { + /* Open EP IN */ + USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, + CDC_DATA_FS_IN_PACKET_SIZE); + + pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; + + /* Open EP OUT */ + USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, + CDC_DATA_FS_OUT_PACKET_SIZE); + + pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; + } + /* Open Command IN EP */ + USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); + pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U; + + pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); + + if (pdev->pClassData == NULL) + { + ret = 1U; + } + else + { + hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + + /* Init physical Interface components */ + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); + + /* Init Xfer states */ + hcdc->TxState = 0U; + hcdc->RxState = 0U; + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + } + return ret; +} + +/** + * @brief USBD_CDC_Init + * DeInitialize the CDC layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + uint8_t ret = 0U; + + /* Close EP IN */ + USBD_LL_CloseEP(pdev, CDC_IN_EP); + pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U; + + /* Close EP OUT */ + USBD_LL_CloseEP(pdev, CDC_OUT_EP); + pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U; + + /* Close Command IN EP */ + USBD_LL_CloseEP(pdev, CDC_CMD_EP); + pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U; + + /* DeInit physical Interface components */ + if (pdev->pClassData != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); + USBD_free(pdev->pClassData); + pdev->pClassData = NULL; + } + + return ret; +} + +/** + * @brief USBD_CDC_Setup + * Handle the CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + uint8_t ifalt = 0U; + uint16_t status_info = 0U; + uint8_t ret = USBD_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + if (req->wLength) + { + if (req->bmRequest & 0x80U) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)(void *)hcdc->data, + req->wLength); + + USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); + } + else + { + hcdc->CmdOpCode = req->bRequest; + hcdc->CmdLength = (uint8_t)req->wLength; + + USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); + } + } + else + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)(void *)req, 0U); + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + USBD_CtlSendData(pdev, &ifalt, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state != USBD_STATE_CONFIGURED) + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + + return ret; +} + +/** + * @brief USBD_CDC_DataIn + * Data sent on non-control IN endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + PCD_HandleTypeDef *hpcd = pdev->pData; + + if (pdev->pClassData != NULL) + { + if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) + { + /* Update the packet total length */ + pdev->ep_in[epnum].total_length = 0U; + + /* Send ZLP */ + USBD_LL_Transmit(pdev, epnum, NULL, 0U); + } + else + { + hcdc->TxState = 0U; + } + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + + /* Get the received data length */ + hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); + + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application Xfer */ + if (pdev->pClassData != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} + +/** + * @brief USBD_CDC_EP0_RxReady + * Handle EP0 Rx Ready event + * @param pdev: device instance + * @retval status + */ +static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + + if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, + (uint8_t *)(void *)hcdc->data, + (uint16_t)hcdc->CmdLength); + hcdc->CmdOpCode = 0xFFU; + + } + return USBD_OK; +} + +/** + * @brief USBD_CDC_GetFSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) +{ + *length = sizeof(USBD_CDC_CfgFSDesc); + return USBD_CDC_CfgFSDesc; +} + +/** + * @brief USBD_CDC_GetHSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) +{ + *length = sizeof(USBD_CDC_CfgHSDesc); + return USBD_CDC_CfgHSDesc; +} + +/** + * @brief USBD_CDC_GetCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) +{ + *length = sizeof(USBD_CDC_OtherSpeedCfgDesc); + return USBD_CDC_OtherSpeedCfgDesc; +} + +/** +* @brief DeviceQualifierDescriptor +* return Device Qualifier descriptor +* @param length : pointer data length +* @retval pointer to descriptor buffer +*/ +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) +{ + *length = sizeof(USBD_CDC_DeviceQualifierDesc); + return USBD_CDC_DeviceQualifierDesc; +} + +/** +* @brief USBD_CDC_RegisterInterface + * @param pdev: device instance + * @param fops: CD Interface callback + * @retval status + */ +uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops) +{ + uint8_t ret = USBD_FAIL; + + if (fops != NULL) + { + pdev->pUserData = fops; + ret = USBD_OK; + } + + return ret; +} + +/** + * @brief USBD_CDC_SetTxBuffer + * @param pdev: device instance + * @param pbuff: Tx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff, + uint16_t length) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + + hcdc->TxBuffer = pbuff; + hcdc->TxLength = length; + + return USBD_OK; +} + + +/** + * @brief USBD_CDC_SetRxBuffer + * @param pdev: device instance + * @param pbuff: Rx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + + hcdc->RxBuffer = pbuff; + + return USBD_OK; +} + +/** + * @brief USBD_CDC_TransmitPacket + * Transmit packet on IN endpoint + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + + if (pdev->pClassData != NULL) + { + if (hcdc->TxState == 0U) + { + /* Tx Transfer in progress */ + hcdc->TxState = 1U; + + /* Update the packet total length */ + pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength; + + /* Transmit next packet */ + USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, + (uint16_t)hcdc->TxLength); + + return USBD_OK; + } + else + { + return USBD_BUSY; + } + } + else + { + return USBD_FAIL; + } +} + + +/** + * @brief USBD_CDC_ReceivePacket + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + + /* Suspend or Resume USB Out process */ + if (pdev->pClassData != NULL) + { + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + USBD_LL_PrepareReceive(pdev, + CDC_OUT_EP, + hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + return USBD_OK; + } + else + { + return USBD_FAIL; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h new file mode 100644 index 0000000..030927b --- /dev/null +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h @@ -0,0 +1,161 @@ +/** + ****************************************************************************** + * @file usbd_core.h + * @author MCD Application Team + * @brief Header file for usbd_core.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" +#include "usbd_def.h" +#include "usbd_ioreq.h" +#include "usbd_ctlreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_CORE + * @brief This file is the Header file for usbd_core.c file + * @{ + */ + + +/** @defgroup USBD_CORE_Exported_Defines + * @{ + */ +#ifndef USBD_DEBUG_LEVEL +#define USBD_DEBUG_LEVEL 0U +#endif /* USBD_DEBUG_LEVEL */ +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ +#define USBD_SOF USBD_LL_SOF +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_FunctionsPrototype + * @{ + */ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id); +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); + +USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); + +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata); +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata); + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); + +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); + +/* USBD Low Level Driver */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps); + +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr); +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size); + +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, + uint8_t ep_addr, + uint8_t *pbuf, + uint16_t size); + +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +void USBD_LL_Delay(uint32_t Delay); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CORE_H */ + +/** + * @} + */ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h new file mode 100644 index 0000000..25a4758 --- /dev/null +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file usbd_req.h + * @author MCD Application Team + * @brief Header file for the usbd_req.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_REQUEST_H +#define __USB_REQUEST_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_REQ + * @brief header file for the usbd_req.c file + * @{ + */ + +/** @defgroup USBD_REQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_REQ_Exported_Types + * @{ + */ +/** + * @} + */ + + + +/** @defgroup USBD_REQ_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_REQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + + +void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + +void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata); + +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_REQUEST_H */ + +/** + * @} + */ + +/** +* @} +*/ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h new file mode 100644 index 0000000..8d7502f --- /dev/null +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -0,0 +1,348 @@ +/** + ****************************************************************************** + * @file usbd_def.h + * @author MCD Application Team + * @brief General defines for the usb device library + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_DEF_H +#define __USBD_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USB_DEF + * @brief general defines for the usb device library file + * @{ + */ + +/** @defgroup USB_DEF_Exported_Defines + * @{ + */ + +#ifndef NULL +#define NULL 0U +#endif /* NULL */ + +#ifndef USBD_MAX_NUM_INTERFACES +#define USBD_MAX_NUM_INTERFACES 1U +#endif /* USBD_MAX_NUM_CONFIGURATION */ + +#ifndef USBD_MAX_NUM_CONFIGURATION +#define USBD_MAX_NUM_CONFIGURATION 1U +#endif /* USBD_MAX_NUM_CONFIGURATION */ + +#ifndef USBD_LPM_ENABLED +#define USBD_LPM_ENABLED 0U +#endif /* USBD_LPM_ENABLED */ + +#ifndef USBD_SELF_POWERED +#define USBD_SELF_POWERED 1U +#endif /*USBD_SELF_POWERED */ + +#ifndef USBD_SUPPORT_USER_STRING_DESC +#define USBD_SUPPORT_USER_STRING_DESC 0U +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +#define USB_LEN_DEV_QUALIFIER_DESC 0x0AU +#define USB_LEN_DEV_DESC 0x12U +#define USB_LEN_CFG_DESC 0x09U +#define USB_LEN_IF_DESC 0x09U +#define USB_LEN_EP_DESC 0x07U +#define USB_LEN_OTG_DESC 0x03U +#define USB_LEN_LANGID_STR_DESC 0x04U +#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09U + +#define USBD_IDX_LANGID_STR 0x00U +#define USBD_IDX_MFC_STR 0x01U +#define USBD_IDX_PRODUCT_STR 0x02U +#define USBD_IDX_SERIAL_STR 0x03U +#define USBD_IDX_CONFIG_STR 0x04U +#define USBD_IDX_INTERFACE_STR 0x05U + +#define USB_REQ_TYPE_STANDARD 0x00U +#define USB_REQ_TYPE_CLASS 0x20U +#define USB_REQ_TYPE_VENDOR 0x40U +#define USB_REQ_TYPE_MASK 0x60U + +#define USB_REQ_RECIPIENT_DEVICE 0x00U +#define USB_REQ_RECIPIENT_INTERFACE 0x01U +#define USB_REQ_RECIPIENT_ENDPOINT 0x02U +#define USB_REQ_RECIPIENT_MASK 0x03U + +#define USB_REQ_GET_STATUS 0x00U +#define USB_REQ_CLEAR_FEATURE 0x01U +#define USB_REQ_SET_FEATURE 0x03U +#define USB_REQ_SET_ADDRESS 0x05U +#define USB_REQ_GET_DESCRIPTOR 0x06U +#define USB_REQ_SET_DESCRIPTOR 0x07U +#define USB_REQ_GET_CONFIGURATION 0x08U +#define USB_REQ_SET_CONFIGURATION 0x09U +#define USB_REQ_GET_INTERFACE 0x0AU +#define USB_REQ_SET_INTERFACE 0x0BU +#define USB_REQ_SYNCH_FRAME 0x0CU + +#define USB_DESC_TYPE_DEVICE 0x01U +#define USB_DESC_TYPE_CONFIGURATION 0x02U +#define USB_DESC_TYPE_STRING 0x03U +#define USB_DESC_TYPE_INTERFACE 0x04U +#define USB_DESC_TYPE_ENDPOINT 0x05U +#define USB_DESC_TYPE_DEVICE_QUALIFIER 0x06U +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 0x07U +#define USB_DESC_TYPE_BOS 0x0FU + +#define USB_CONFIG_REMOTE_WAKEUP 0x02U +#define USB_CONFIG_SELF_POWERED 0x01U + +#define USB_FEATURE_EP_HALT 0x00U +#define USB_FEATURE_REMOTE_WAKEUP 0x01U +#define USB_FEATURE_TEST_MODE 0x02U + +#define USB_DEVICE_CAPABITY_TYPE 0x10U + +#define USB_HS_MAX_PACKET_SIZE 512U +#define USB_FS_MAX_PACKET_SIZE 64U +#define USB_MAX_EP0_SIZE 64U + +/* Device Status */ +#define USBD_STATE_DEFAULT 0x01U +#define USBD_STATE_ADDRESSED 0x02U +#define USBD_STATE_CONFIGURED 0x03U +#define USBD_STATE_SUSPENDED 0x04U + + +/* EP0 State */ +#define USBD_EP0_IDLE 0x00U +#define USBD_EP0_SETUP 0x01U +#define USBD_EP0_DATA_IN 0x02U +#define USBD_EP0_DATA_OUT 0x03U +#define USBD_EP0_STATUS_IN 0x04U +#define USBD_EP0_STATUS_OUT 0x05U +#define USBD_EP0_STALL 0x06U + +#define USBD_EP_TYPE_CTRL 0x00U +#define USBD_EP_TYPE_ISOC 0x01U +#define USBD_EP_TYPE_BULK 0x02U +#define USBD_EP_TYPE_INTR 0x03U + + +/** + * @} + */ + + +/** @defgroup USBD_DEF_Exported_TypesDefinitions + * @{ + */ + +typedef struct usb_setup_req +{ + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USBD_SetupReqTypedef; + +struct _USBD_HandleTypeDef; + +typedef struct _Device_cb +{ + uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx); + uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx); + /* Control Endpoints*/ + uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev); + uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev); + /* Class Specific Endpoints*/ + uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev); + uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + + uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); + uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); + uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) + uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length); +#endif + +} USBD_ClassTypeDef; + +/* Following USB Device Speed */ +typedef enum +{ + USBD_SPEED_HIGH = 0U, + USBD_SPEED_FULL = 1U, + USBD_SPEED_LOW = 2U, +} USBD_SpeedTypeDef; + +/* Following USB Device status */ +typedef enum +{ + USBD_OK = 0U, + USBD_BUSY, + USBD_FAIL, +} USBD_StatusTypeDef; + +/* USB Device descriptors structure */ +typedef struct +{ + uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); +#if (USBD_LPM_ENABLED == 1U) + uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); +#endif +} USBD_DescriptorsTypeDef; + +/* USB Device handle structure */ +typedef struct +{ + uint32_t status; + uint32_t is_used; + uint32_t total_length; + uint32_t rem_length; + uint32_t maxpacket; +} USBD_EndpointTypeDef; + +/* USB Device handle structure */ +typedef struct _USBD_HandleTypeDef +{ + uint8_t id; + uint32_t dev_config; + uint32_t dev_default_config; + uint32_t dev_config_status; + USBD_SpeedTypeDef dev_speed; + USBD_EndpointTypeDef ep_in[16]; + USBD_EndpointTypeDef ep_out[16]; + uint32_t ep0_state; + uint32_t ep0_data_len; + uint8_t dev_state; + uint8_t dev_old_state; + uint8_t dev_address; + uint8_t dev_connection_status; + uint8_t dev_test_mode; + uint32_t dev_remote_wakeup; + + USBD_SetupReqTypedef request; + USBD_DescriptorsTypeDef *pDesc; + USBD_ClassTypeDef *pClass; + void *pClassData; + void *pUserData; + void *pData; +} USBD_HandleTypeDef; + +/** + * @} + */ + + + +/** @defgroup USBD_DEF_Exported_Macros + * @{ + */ +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define LOBYTE(x) ((uint8_t)((x) & 0x00FFU)) +#define HIBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4U))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler */ +#define __ALIGN_BEGIN __align(4U) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_DEF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_DEF_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h new file mode 100644 index 0000000..8a6dd5f --- /dev/null +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.h + * @author MCD Application Team + * @brief Header file for the usbd_ioreq.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_IOREQ_H +#define __USBD_IOREQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_IOREQ + * @brief header file for the usbd_ioreq.c file + * @{ + */ + +/** @defgroup USBD_IOREQ_Exported_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Exported_Types + * @{ + */ + + +/** + * @} + */ + + + +/** @defgroup USBD_IOREQ_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype + * @{ + */ + +USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, + uint16_t len); + +USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev); + +USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev); + +uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_IOREQ_H */ + +/** + * @} + */ + +/** +* @} +*/ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c new file mode 100644 index 0000000..b1a60ae --- /dev/null +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c @@ -0,0 +1,611 @@ +/** + ****************************************************************************** + * @file usbd_core.c + * @author MCD Application Team + * @brief This file provides all the USBD core functions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_core.h" + +/** @addtogroup STM32_USBD_DEVICE_LIBRARY +* @{ +*/ + + +/** @defgroup USBD_CORE +* @brief usbd core module +* @{ +*/ + +/** @defgroup USBD_CORE_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Defines +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Macros +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup USBD_CORE_Private_Variables +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup USBD_CORE_Private_Functions +* @{ +*/ + +/** +* @brief USBD_Init +* Initializes the device stack and load the class driver +* @param pdev: device instance +* @param pdesc: Descriptor structure address +* @param id: Low level core index +* @retval None +*/ +USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, + USBD_DescriptorsTypeDef *pdesc, uint8_t id) +{ + /* Check whether the USB Host handle is valid */ + if (pdev == NULL) + { +#if (USBD_DEBUG_LEVEL > 1U) + USBD_ErrLog("Invalid Device handle"); +#endif + return USBD_FAIL; + } + + /* Unlink previous class*/ + if (pdev->pClass != NULL) + { + pdev->pClass = NULL; + } + + /* Assign USBD Descriptors */ + if (pdesc != NULL) + { + pdev->pDesc = pdesc; + } + + /* Set Device initial State */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->id = id; + /* Initialize low level driver */ + USBD_LL_Init(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_DeInit +* Re-Initialize th device library +* @param pdev: device instance +* @retval status: status +*/ +USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) +{ + /* Set Default State */ + pdev->dev_state = USBD_STATE_DEFAULT; + + /* Free Class Resources */ + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + + /* Stop the low level driver */ + USBD_LL_Stop(pdev); + + /* Initialize low level driver */ + USBD_LL_DeInit(pdev); + + return USBD_OK; +} + +/** + * @brief USBD_RegisterClass + * Link class driver to Device Core. + * @param pDevice : Device Handle + * @param pclass: Class handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) +{ + USBD_StatusTypeDef status = USBD_OK; + if (pclass != NULL) + { + /* link the class to the USB Device handle */ + pdev->pClass = pclass; + status = USBD_OK; + } + else + { +#if (USBD_DEBUG_LEVEL > 1U) + USBD_ErrLog("Invalid Class handle"); +#endif + status = USBD_FAIL; + } + + return status; +} + +/** + * @brief USBD_Start + * Start the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) +{ + /* Start the low level driver */ + USBD_LL_Start(pdev); + + return USBD_OK; +} + +/** + * @brief USBD_Stop + * Stop the USB Device Core. + * @param pdev: Device Handle + * @retval USBD Status + */ +USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev) +{ + /* Free Class Resources */ + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + + /* Stop the low level driver */ + USBD_LL_Stop(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_RunTestMode +* Launch test mode process +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) +{ + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_SetClassConfig +* Configure device and start the interface +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status +*/ + +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + USBD_StatusTypeDef ret = USBD_FAIL; + + if (pdev->pClass != NULL) + { + /* Set configuration and Start the Class*/ + if (pdev->pClass->Init(pdev, cfgidx) == 0U) + { + ret = USBD_OK; + } + } + + return ret; +} + +/** +* @brief USBD_ClrClassConfig +* Clear current configuration +* @param pdev: device instance +* @param cfgidx: configuration index +* @retval status: USBD_StatusTypeDef +*/ +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + /* Clear configuration and De-initialize the Class process*/ + pdev->pClass->DeInit(pdev, cfgidx); + + return USBD_OK; +} + + +/** +* @brief USBD_SetupStage +* Handle the setup stage +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) +{ + USBD_ParseSetupRequest(&pdev->request, psetup); + + pdev->ep0_state = USBD_EP0_SETUP; + + pdev->ep0_data_len = pdev->request.wLength; + + switch (pdev->request.bmRequest & 0x1FU) + { + case USB_REQ_RECIPIENT_DEVICE: + USBD_StdDevReq(pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + USBD_StdItfReq(pdev, &pdev->request); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + USBD_StdEPReq(pdev, &pdev->request); + break; + + default: + USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); + break; + } + + return USBD_OK; +} + +/** +* @brief USBD_DataOutStage +* Handle data OUT stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, + uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + + if (epnum == 0U) + { + pep = &pdev->ep_out[0]; + + if (pdev->ep0_state == USBD_EP0_DATA_OUT) + { + if (pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + + USBD_CtlContinueRx(pdev, pdata, + (uint16_t)MIN(pep->rem_length, pep->maxpacket)); + } + else + { + if ((pdev->pClass->EP0_RxReady != NULL) && + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->EP0_RxReady(pdev); + } + USBD_CtlSendStatus(pdev); + } + } + else + { + if (pdev->ep0_state == USBD_EP0_STATUS_OUT) + { + /* + * STATUS PHASE completed, update ep0_state to idle + */ + pdev->ep0_state = USBD_EP0_IDLE; + USBD_LL_StallEP(pdev, 0U); + } + } + } + else if ((pdev->pClass->DataOut != NULL) && + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataOut(pdev, epnum); + } + else + { + /* should never be in this condition */ + return USBD_FAIL; + } + + return USBD_OK; +} + +/** +* @brief USBD_DataInStage +* Handle data in stage +* @param pdev: device instance +* @param epnum: endpoint index +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, + uint8_t epnum, uint8_t *pdata) +{ + USBD_EndpointTypeDef *pep; + + if (epnum == 0U) + { + pep = &pdev->ep_in[0]; + + if (pdev->ep0_state == USBD_EP0_DATA_IN) + { + if (pep->rem_length > pep->maxpacket) + { + pep->rem_length -= pep->maxpacket; + + USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length); + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + } + else + { + /* last packet is MPS multiple, so send ZLP packet */ + if ((pep->total_length % pep->maxpacket == 0U) && + (pep->total_length >= pep->maxpacket) && + (pep->total_length < pdev->ep0_data_len)) + { + USBD_CtlContinueSendData(pdev, NULL, 0U); + pdev->ep0_data_len = 0U; + + /* Prepare endpoint for premature end of transfer */ + USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + } + else + { + if ((pdev->pClass->EP0_TxSent != NULL) && + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->EP0_TxSent(pdev); + } + USBD_LL_StallEP(pdev, 0x80U); + USBD_CtlReceiveStatus(pdev); + } + } + } + else + { + if ((pdev->ep0_state == USBD_EP0_STATUS_IN) || + (pdev->ep0_state == USBD_EP0_IDLE)) + { + USBD_LL_StallEP(pdev, 0x80U); + } + } + + if (pdev->dev_test_mode == 1U) + { + USBD_RunTestMode(pdev); + pdev->dev_test_mode = 0U; + } + } + else if ((pdev->pClass->DataIn != NULL) && + (pdev->dev_state == USBD_STATE_CONFIGURED)) + { + pdev->pClass->DataIn(pdev, epnum); + } + else + { + /* should never be in this condition */ + return USBD_FAIL; + } + + return USBD_OK; +} + +/** +* @brief USBD_LL_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) +{ + /* Open EP0 OUT */ + USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + pdev->ep_out[0x00U & 0xFU].is_used = 1U; + + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + + /* Open EP0 IN */ + USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + pdev->ep_in[0x80U & 0xFU].is_used = 1U; + + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + + /* Upon Reset call user call back */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->ep0_state = USBD_EP0_IDLE; + pdev->dev_config = 0U; + pdev->dev_remote_wakeup = 0U; + + if (pdev->pClassData) + { + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + } + + return USBD_OK; +} + +/** +* @brief USBD_LL_Reset +* Handle Reset event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, + USBD_SpeedTypeDef speed) +{ + pdev->dev_speed = speed; + + return USBD_OK; +} + +/** +* @brief USBD_Suspend +* Handle Suspend event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) +{ + pdev->dev_old_state = pdev->dev_state; + pdev->dev_state = USBD_STATE_SUSPENDED; + + return USBD_OK; +} + +/** +* @brief USBD_Resume +* Handle Resume event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) +{ + if (pdev->dev_state == USBD_STATE_SUSPENDED) + { + pdev->dev_state = pdev->dev_old_state; + } + + return USBD_OK; +} + +/** +* @brief USBD_SOF +* Handle SOF event +* @param pdev: device instance +* @retval status +*/ + +USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) +{ + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + if (pdev->pClass->SOF != NULL) + { + pdev->pClass->SOF(pdev); + } + } + + return USBD_OK; +} + +/** +* @brief USBD_IsoINIncomplete +* Handle iso in incomplete event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, + uint8_t epnum) +{ + /* Prevent unused arguments compilation warning */ + UNUSED(pdev); + UNUSED(epnum); + + return USBD_OK; +} + +/** +* @brief USBD_IsoOUTIncomplete +* Handle iso out incomplete event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, + uint8_t epnum) +{ + /* Prevent unused arguments compilation warning */ + UNUSED(pdev); + UNUSED(epnum); + + return USBD_OK; +} + +/** +* @brief USBD_DevConnected +* Handle device connection event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) +{ + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + + return USBD_OK; +} + +/** +* @brief USBD_DevDisconnected +* Handle device disconnection event +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) +{ + /* Free Class Resources */ + pdev->dev_state = USBD_STATE_DEFAULT; + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + + return USBD_OK; +} +/** +* @} +*/ + + +/** +* @} +*/ + + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c new file mode 100644 index 0000000..e57c1bc --- /dev/null +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c @@ -0,0 +1,918 @@ +/** + ****************************************************************************** + * @file usbd_req.c + * @author MCD Application Team + * @brief This file provides the standard USB requests following chapter 9. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ctlreq.h" +#include "usbd_ioreq.h" + + +/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_REQ + * @brief USB standard requests module + * @{ + */ + +/** @defgroup USBD_REQ_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_FunctionPrototypes + * @{ + */ +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static void USBD_SetConfig(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static void USBD_GetConfig(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static void USBD_GetStatus(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static uint8_t USBD_GetLen(uint8_t *buf); + +/** + * @} + */ + + +/** @defgroup USBD_REQ_Private_Functions + * @{ + */ + + +/** +* @brief USBD_StdDevReq +* Handle standard usb device requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_StatusTypeDef ret = USBD_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + pdev->pClass->Setup(pdev, req); + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + USBD_GetDescriptor(pdev, req); + break; + + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + break; + + case USB_REQ_SET_CONFIGURATION: + USBD_SetConfig(pdev, req); + break; + + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig(pdev, req); + break; + + case USB_REQ_GET_STATUS: + USBD_GetStatus(pdev, req); + break; + + case USB_REQ_SET_FEATURE: + USBD_SetFeature(pdev, req); + break; + + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature(pdev, req); + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + + return ret; +} + +/** +* @brief USBD_StdItfReq +* Handle standard usb interface requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_StatusTypeDef ret = USBD_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + case USB_REQ_TYPE_STANDARD: + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + + if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) + { + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + + if ((req->wLength == 0U) && (ret == USBD_OK)) + { + USBD_CtlSendStatus(pdev); + } + } + else + { + USBD_CtlError(pdev, req); + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + + return USBD_OK; +} + +/** +* @brief USBD_StdEPReq +* Handle standard usb endpoint requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_EndpointTypeDef *pep; + uint8_t ep_addr; + USBD_StatusTypeDef ret = USBD_OK; + ep_addr = LOBYTE(req->wIndex); + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + pdev->pClass->Setup(pdev, req); + break; + + case USB_REQ_TYPE_STANDARD: + /* Check if it is a class request */ + if ((req->bmRequest & 0x60U) == 0x20U) + { + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + + return ret; + } + + switch (req->bRequest) + { + case USB_REQ_SET_FEATURE: + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + USBD_LL_StallEP(pdev, ep_addr); + USBD_LL_StallEP(pdev, 0x80U); + } + else + { + USBD_CtlError(pdev, req); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00U) && + (ep_addr != 0x80U) && (req->wLength == 0x00U)) + { + USBD_LL_StallEP(pdev, ep_addr); + } + } + USBD_CtlSendStatus(pdev); + + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + case USB_REQ_CLEAR_FEATURE: + + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + USBD_LL_StallEP(pdev, ep_addr); + USBD_LL_StallEP(pdev, 0x80U); + } + else + { + USBD_CtlError(pdev, req); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr & 0x7FU) != 0x00U) + { + USBD_LL_ClearStallEP(pdev, ep_addr); + } + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + case USB_REQ_GET_STATUS: + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + USBD_CtlError(pdev, req); + break; + } + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + &pdev->ep_out[ep_addr & 0x7FU]; + + pep->status = 0x0000U; + + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); + break; + + case USBD_STATE_CONFIGURED: + if ((ep_addr & 0x80U) == 0x80U) + { + if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) + { + USBD_CtlError(pdev, req); + break; + } + } + else + { + if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) + { + USBD_CtlError(pdev, req); + break; + } + } + + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + &pdev->ep_out[ep_addr & 0x7FU]; + + if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) + { + pep->status = 0x0000U; + } + else if (USBD_LL_IsStallEP(pdev, ep_addr)) + { + pep->status = 0x0001U; + } + else + { + pep->status = 0x0000U; + } + + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + + return ret; +} + + +/** +* @brief USBD_GetDescriptor +* Handle Get Descriptor requests +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t err = 0U; + + switch (req->wValue >> 8) + { +#if (USBD_LPM_ENABLED == 1U) + case USB_DESC_TYPE_BOS: + if (pdev->pDesc->GetBOSDescriptor != NULL) + { + pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; +#endif + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + break; + + case USB_DESC_TYPE_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pbuf = pdev->pClass->GetHSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + else + { + pbuf = pdev->pClass->GetFSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + if (pdev->pDesc->GetLangIDStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_MFC_STR: + if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_PRODUCT_STR: + if (pdev->pDesc->GetProductStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_SERIAL_STR: + if (pdev->pDesc->GetSerialStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_CONFIG_STR: + if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_INTERFACE_STR: + if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + default: +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) + if (pdev->pClass->GetUsrStrDescriptor != NULL) + { + pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; +#else + USBD_CtlError(pdev, req); + err++; +#endif + } + break; + + case USB_DESC_TYPE_DEVICE_QUALIFIER: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + default: + USBD_CtlError(pdev, req); + err++; + break; + } + + if (err != 0U) + { + return; + } + else + { + if ((len != 0U) && (req->wLength != 0U)) + { + len = MIN(len, req->wLength); + (void)USBD_CtlSendData(pdev, pbuf, len); + } + + if (req->wLength == 0U) + { + (void)USBD_CtlSendStatus(pdev); + } + } +} + +/** +* @brief USBD_SetAddress +* Set device address +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + uint8_t dev_addr; + + if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) + { + dev_addr = (uint8_t)(req->wValue) & 0x7FU; + + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + USBD_CtlError(pdev, req); + } + else + { + pdev->dev_address = dev_addr; + USBD_LL_SetUSBAddress(pdev, dev_addr); + USBD_CtlSendStatus(pdev); + + if (dev_addr != 0U) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + } + else + { + pdev->dev_state = USBD_STATE_DEFAULT; + } + } + } + else + { + USBD_CtlError(pdev, req); + } +} + +/** +* @brief USBD_SetConfig +* Handle Set device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_MAX_NUM_CONFIGURATION) + { + USBD_CtlError(pdev, req); + } + else + { + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if (cfgidx) + { + pdev->dev_config = cfgidx; + pdev->dev_state = USBD_STATE_CONFIGURED; + if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) + { + USBD_CtlError(pdev, req); + return; + } + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + case USBD_STATE_CONFIGURED: + if (cfgidx == 0U) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + pdev->dev_config = cfgidx; + USBD_ClrClassConfig(pdev, cfgidx); + USBD_CtlSendStatus(pdev); + } + else if (cfgidx != pdev->dev_config) + { + /* Clear old configuration */ + USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + + /* set new configuration */ + pdev->dev_config = cfgidx; + if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) + { + USBD_CtlError(pdev, req); + return; + } + USBD_CtlSendStatus(pdev); + } + else + { + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev, req); + USBD_ClrClassConfig(pdev, cfgidx); + break; + } + } +} + +/** +* @brief USBD_GetConfig +* Handle Get device configuration request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + if (req->wLength != 1U) + { + USBD_CtlError(pdev, req); + } + else + { + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + pdev->dev_default_config = 0U; + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U); + break; + + case USBD_STATE_CONFIGURED: + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U); + break; + + default: + USBD_CtlError(pdev, req); + break; + } + } +} + +/** +* @brief USBD_GetStatus +* Handle Get Status request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wLength != 0x2U) + { + USBD_CtlError(pdev, req); + break; + } + +#if (USBD_SELF_POWERED == 1U) + pdev->dev_config_status = USB_CONFIG_SELF_POWERED; +#else + pdev->dev_config_status = 0U; +#endif + + if (pdev->dev_remote_wakeup) + { + pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + } + + USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U); + break; + + default: + USBD_CtlError(pdev, req); + break; + } +} + + +/** +* @brief USBD_SetFeature +* Handle Set device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev_remote_wakeup = 1U; + USBD_CtlSendStatus(pdev); + } +} + + +/** +* @brief USBD_ClrFeature +* Handle clear device feature request +* @param pdev: device instance +* @param req: usb request +* @retval status +*/ +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + pdev->dev_remote_wakeup = 0U; + USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } +} + +/** +* @brief USBD_ParseSetupRequest +* Copy buffer into setup structure +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) +{ + req->bmRequest = *(uint8_t *)(pdata); + req->bRequest = *(uint8_t *)(pdata + 1U); + req->wValue = SWAPBYTE(pdata + 2U); + req->wIndex = SWAPBYTE(pdata + 4U); + req->wLength = SWAPBYTE(pdata + 6U); + +} + +/** +* @brief USBD_CtlError +* Handle USB low level Error +* @param pdev: device instance +* @param req: usb request +* @retval None +*/ + +void USBD_CtlError(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_LL_StallEP(pdev, 0x80U); + USBD_LL_StallEP(pdev, 0U); +} + + +/** + * @brief USBD_GetString + * Convert Ascii string into unicode one + * @param desc : descriptor buffer + * @param unicode : Formatted string buffer (unicode) + * @param len : descriptor length + * @retval None + */ +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + uint8_t idx = 0U; + + if (desc != NULL) + { + *len = (uint16_t)USBD_GetLen(desc) * 2U + 2U; + unicode[idx++] = *(uint8_t *)(void *)len; + unicode[idx++] = USB_DESC_TYPE_STRING; + + while (*desc != '\0') + { + unicode[idx++] = *desc++; + unicode[idx++] = 0U; + } + } +} + +/** + * @brief USBD_GetLen + * return the string length + * @param buf : pointer to the ascii string buffer + * @retval string length + */ +static uint8_t USBD_GetLen(uint8_t *buf) +{ + uint8_t len = 0U; + + while (*buf != '\0') + { + len++; + buf++; + } + + return len; +} +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c new file mode 100644 index 0000000..3351972 --- /dev/null +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c @@ -0,0 +1,216 @@ +/** + ****************************************************************************** + * @file usbd_ioreq.c + * @author MCD Application Team + * @brief This file provides the IO requests APIs for control endpoints. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_IOREQ + * @brief control I/O requests module + * @{ + */ + +/** @defgroup USBD_IOREQ_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_IOREQ_Private_Functions + * @{ + */ + +/** +* @brief USBD_CtlSendData +* send data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint16_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_IN; + pdev->ep_in[0].total_length = len; + pdev->ep_in[0].rem_length = len; + + /* Start the transfer */ + USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlContinueSendData +* continue sending data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be sent +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint16_t len) +{ + /* Start the next transfer */ + USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlPrepareRx +* receive data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint16_t len) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_OUT; + pdev->ep_out[0].total_length = len; + pdev->ep_out[0].rem_length = len; + + /* Start the transfer */ + USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlContinueRx +* continue receive data on the ctl pipe +* @param pdev: device instance +* @param buff: pointer to data buffer +* @param len: length of data to be received +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint16_t len) +{ + USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + + return USBD_OK; +} + +/** +* @brief USBD_CtlSendStatus +* send zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_IN; + + /* Start the transfer */ + USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); + + return USBD_OK; +} + +/** +* @brief USBD_CtlReceiveStatus +* receive zero lzngth packet on the ctl pipe +* @param pdev: device instance +* @retval status +*/ +USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) +{ + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_STATUS_OUT; + + /* Start the transfer */ + USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + + return USBD_OK; +} + +/** +* @brief USBD_GetRxCount +* returns the received data length +* @param pdev: device instance +* @param ep_addr: endpoint address +* @retval Rx Data blength +*/ +uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + return USBD_LL_GetRxDataSize(pdev, ep_addr); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c new file mode 100644 index 0000000..c6f6a6f --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -0,0 +1,1727 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.c + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * + * + *---------------------------------------------------------------------------- + * + * Portions Copyright © 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright (c) 2013 ARM LIMITED + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include +#include "cmsis_os.h" + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + + #define __ASM __asm + #define __INLINE __inline + #define __STATIC_INLINE static __inline + + #include "cmsis_armcc.h" + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include +#endif + +extern void xPortSysTickHandler(void); + +/* Convert from CMSIS type osPriority to FreeRTOS priority number */ +static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority) +{ + unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY; + + if (priority != osPriorityError) { + fpriority += (priority - osPriorityIdle); + } + + return fpriority; +} + +#if (INCLUDE_uxTaskPriorityGet == 1) +/* Convert from FreeRTOS priority number to CMSIS type osPriority */ +static osPriority makeCmsisPriority (unsigned portBASE_TYPE fpriority) +{ + osPriority priority = osPriorityError; + + if ((fpriority - tskIDLE_PRIORITY) <= (osPriorityRealtime - osPriorityIdle)) { + priority = (osPriority)((int)osPriorityIdle + (int)(fpriority - tskIDLE_PRIORITY)); + } + + return priority; +} +#endif + + +/* Determine whether we are in thread mode or handler mode. */ +static int inHandlerMode (void) +{ + return __get_IPSR() != 0; +} + +/*********************** Kernel Control Functions *****************************/ +/** +* @brief Initialize the RTOS Kernel for creating objects. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +*/ +osStatus osKernelInitialize (void); + +/** +* @brief Start the RTOS Kernel with executing the specified thread. +* @param thread_def thread definition referenced with \ref osThread. +* @param argument pointer that is passed to the thread function as start argument. +* @retval status code that indicates the execution status of the function +* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +*/ +osStatus osKernelStart (void) +{ + vTaskStartScheduler(); + + return osOK; +} + +/** +* @brief Check if the RTOS kernel is already started +* @param None +* @retval (0) RTOS is not started +* (1) RTOS is started +* (-1) if this feature is disabled in FreeRTOSConfig.h +* @note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +*/ +int32_t osKernelRunning(void) +{ +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) + return 0; + else + return 1; +#else + return (-1); +#endif +} + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available +/** +* @brief Get the value of the Kernel SysTick timer +* @param None +* @retval None +* @note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +*/ +uint32_t osKernelSysTick(void) +{ + if (inHandlerMode()) { + return xTaskGetTickCountFromISR(); + } + else { + return xTaskGetTickCount(); + } +} +#endif // System Timer available +/*********************** Thread Management *****************************/ +/** +* @brief Create a thread and add it to Active Threads and set it to state READY. +* @param thread_def thread definition referenced with \ref osThread. +* @param argument pointer that is passed to the thread function as start argument. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) +{ + TaskHandle_t handle; + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) { + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); + } + else { + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + &handle) != pdPASS) { + return NULL; + } + } +#elif( configSUPPORT_STATIC_ALLOCATION == 1 ) + + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); +#else + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + &handle) != pdPASS) { + return NULL; + } +#endif + + return handle; +} + +/** +* @brief Return the thread ID of the current running thread. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadGetId (void) +{ +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + return xTaskGetCurrentTaskHandle(); +#else + return NULL; +#endif +} + +/** +* @brief Terminate execution of a thread and remove it from Active Threads. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +*/ +osStatus osThreadTerminate (osThreadId thread_id) +{ +#if (INCLUDE_vTaskDelete == 1) + vTaskDelete(thread_id); + return osOK; +#else + return osErrorOS; +#endif +} + +/** +* @brief Pass control to next thread that is in state \b READY. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +*/ +osStatus osThreadYield (void) +{ + taskYIELD(); + + return osOK; +} + +/** +* @brief Change priority of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @param priority new priority value for the thread function. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +*/ +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) +{ +#if (INCLUDE_vTaskPrioritySet == 1) + vTaskPrioritySet(thread_id, makeFreeRtosPriority(priority)); + return osOK; +#else + return osErrorOS; +#endif +} + +/** +* @brief Get current priority of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval current priority value of the thread function. +* @note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +*/ +osPriority osThreadGetPriority (osThreadId thread_id) +{ +#if (INCLUDE_uxTaskPriorityGet == 1) + if (inHandlerMode()) + { + return makeCmsisPriority(uxTaskPriorityGetFromISR(thread_id)); + } + else + { + return makeCmsisPriority(uxTaskPriorityGet(thread_id)); + } +#else + return osPriorityError; +#endif +} + +/*********************** Generic Wait Functions *******************************/ +/** +* @brief Wait for Timeout (Time Delay) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelay (uint32_t millisec) +{ +#if INCLUDE_vTaskDelay + TickType_t ticks = millisec / portTICK_PERIOD_MS; + + vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */ + + return osOK; +#else + (void) millisec; + + return osErrorResource; +#endif +} + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) /* Generic Wait available */ +/** +* @brief Wait for Signal, Message, Mail, or Timeout +* @param millisec timeout value or 0 in case of no time-out +* @retval event that contains signal, message, or mail information or error code. +* @note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +*/ +osEvent osWait (uint32_t millisec); + +#endif /* Generic Wait available */ + +/*********************** Timer Management Functions ***************************/ +/** +* @brief Create a timer. +* @param timer_def timer object referenced with \ref osTimer. +* @param type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +* @param argument argument to the timer call back function. +* @retval timer ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +*/ +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) +{ +#if (configUSE_TIMERS == 1) + +#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + if(timer_def->controlblock != NULL) { + return xTimerCreateStatic((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TaskFunction_t)timer_def->ptimer, + (StaticTimer_t *)timer_def->controlblock); + } + else { + return xTimerCreate((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TaskFunction_t)timer_def->ptimer); + } +#elif( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xTimerCreateStatic((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TaskFunction_t)timer_def->ptimer, + (StaticTimer_t *)timer_def->controlblock); +#else + return xTimerCreate((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TaskFunction_t)timer_def->ptimer); +#endif + +#else + return NULL; +#endif +} + +/** +* @brief Start or restart a timer. +* @param timer_id timer ID obtained by \ref osTimerCreate. +* @param millisec time delay value of the timer. +* @retval status code that indicates the execution status of the function +* @note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +*/ +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec) +{ + osStatus result = osOK; +#if (configUSE_TIMERS == 1) + portBASE_TYPE taskWoken = pdFALSE; + TickType_t ticks = millisec / portTICK_PERIOD_MS; + + if (ticks == 0) + ticks = 1; + + if (inHandlerMode()) + { + if (xTimerChangePeriodFromISR(timer_id, ticks, &taskWoken) != pdPASS) + { + result = osErrorOS; + } + else + { + portEND_SWITCHING_ISR(taskWoken); + } + } + else + { + if (xTimerChangePeriod(timer_id, ticks, 0) != pdPASS) + result = osErrorOS; + } + +#else + result = osErrorOS; +#endif + return result; +} + +/** +* @brief Stop a timer. +* @param timer_id timer ID obtained by \ref osTimerCreate +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +*/ +osStatus osTimerStop (osTimerId timer_id) +{ + osStatus result = osOK; +#if (configUSE_TIMERS == 1) + portBASE_TYPE taskWoken = pdFALSE; + + if (inHandlerMode()) { + if (xTimerStopFromISR(timer_id, &taskWoken) != pdPASS) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xTimerStop(timer_id, 0) != pdPASS) { + result = osErrorOS; + } + } +#else + result = osErrorOS; +#endif + return result; +} + +/** +* @brief Delete a timer. +* @param timer_id timer ID obtained by \ref osTimerCreate +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +*/ +osStatus osTimerDelete (osTimerId timer_id) +{ +osStatus result = osOK; + +#if (configUSE_TIMERS == 1) + + if (inHandlerMode()) { + return osErrorISR; + } + else { + if ((xTimerDelete(timer_id, osWaitForever )) != pdPASS) { + result = osErrorOS; + } + } + +#else + result = osErrorOS; +#endif + + return result; +} + +/*************************** Signal Management ********************************/ +/** +* @brief Set the specified Signal Flags of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @param signals specifies the signal flags of the thread that should be set. +* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSignalSet (osThreadId thread_id, int32_t signal) +{ +#if( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint32_t ulPreviousNotificationValue = 0; + + if (inHandlerMode()) + { + if(xTaskGenericNotifyFromISR( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue, &xHigherPriorityTaskWoken ) != pdPASS ) + return 0x80000000; + + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + else if(xTaskGenericNotify( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue) != pdPASS ) + return 0x80000000; + + return ulPreviousNotificationValue; +#else + (void) thread_id; + (void) signal; + + return 0x80000000; /* Task Notification not supported */ +#endif +} + +/** +* @brief Clear the specified Signal Flags of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @param signals specifies the signal flags of the thread that shall be cleared. +* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSignalClear (osThreadId thread_id, int32_t signal); + +/** +* @brief Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +* @param signals wait until all specified signal flags set or 0 for any single signal flag. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event flag information or error code. +* @note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +*/ +osEvent osSignalWait (int32_t signals, uint32_t millisec) +{ + osEvent ret; + +#if( configUSE_TASK_NOTIFICATIONS == 1 ) + + TickType_t ticks; + + ret.value.signals = 0; + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) + { + ret.status = osErrorISR; /*Not allowed in ISR*/ + } + else + { + if(xTaskNotifyWait( 0,(uint32_t) signals, (uint32_t *)&ret.value.signals, ticks) != pdTRUE) + { + if(ticks == 0) ret.status = osOK; + else ret.status = osEventTimeout; + } + else if(ret.value.signals < 0) + { + ret.status = osErrorValue; + } + else ret.status = osEventSignal; + } +#else + (void) signals; + (void) millisec; + + ret.status = osErrorOS; /* Task Notification not supported */ +#endif + + return ret; +} + +/**************************** Mutex Management ********************************/ +/** +* @brief Create and Initialize a Mutex object +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +*/ +osMutexId osMutexCreate (const osMutexDef_t *mutex_def) +{ +#if ( configUSE_MUTEXES == 1) + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if (mutex_def->controlblock != NULL) { + return xSemaphoreCreateMutexStatic( mutex_def->controlblock ); + } + else { + return xSemaphoreCreateMutex(); + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xSemaphoreCreateMutexStatic( mutex_def->controlblock ); +#else + return xSemaphoreCreateMutex(); +#endif +#else + return NULL; +#endif +} + +/** +* @brief Wait until a Mutex becomes available +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) +{ + TickType_t ticks; + portBASE_TYPE taskWoken = pdFALSE; + + + if (mutex_id == NULL) { + return osErrorParameter; + } + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) { + return osErrorOS; + } + + return osOK; +} + +/** +* @brief Release a Mutex that was obtained by \ref osMutexWait +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexRelease (osMutexId mutex_id) +{ + osStatus result = osOK; + portBASE_TYPE taskWoken = pdFALSE; + + if (inHandlerMode()) { + if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else if (xSemaphoreGive(mutex_id) != pdTRUE) + { + result = osErrorOS; + } + return result; +} + +/** +* @brief Delete a Mutex +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexDelete (osMutexId mutex_id) +{ + if (inHandlerMode()) { + return osErrorISR; + } + + vQueueDelete(mutex_id); + + return osOK; +} + +/******************** Semaphore Management Functions **************************/ + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) + +/** +* @brief Create and Initialize a Semaphore object used for managing resources +* @param semaphore_def semaphore definition referenced with \ref osSemaphore. +* @param count number of available resources. +* @retval semaphore ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +*/ +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) +{ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + osSemaphoreId sema; + + if (semaphore_def->controlblock != NULL){ + if (count == 1) { + return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock ); + } + else { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock ); +#else + return NULL; +#endif + } + } + else { + if (count == 1) { + vSemaphoreCreateBinary(sema); + return sema; + } + else { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCounting(count, count); +#else + return NULL; +#endif + } + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) // configSUPPORT_DYNAMIC_ALLOCATION == 0 + if(count == 1) { + return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock ); + } + else + { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock ); +#else + return NULL; +#endif + } +#else // configSUPPORT_STATIC_ALLOCATION == 0 && configSUPPORT_DYNAMIC_ALLOCATION == 1 + osSemaphoreId sema; + + if (count == 1) { + vSemaphoreCreateBinary(sema); + return sema; + } + else { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCounting(count, count); +#else + return NULL; +#endif + } +#endif +} + +/** +* @brief Wait until a Semaphore token becomes available +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @param millisec timeout value or 0 in case of no time-out. +* @retval number of available tokens, or -1 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) +{ + TickType_t ticks; + portBASE_TYPE taskWoken = pdFALSE; + + + if (semaphore_id == NULL) { + return osErrorParameter; + } + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) { + return osErrorOS; + } + + return osOK; +} + +/** +* @brief Release a Semaphore token +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +*/ +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) +{ + osStatus result = osOK; + portBASE_TYPE taskWoken = pdFALSE; + + + if (inHandlerMode()) { + if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xSemaphoreGive(semaphore_id) != pdTRUE) { + result = osErrorOS; + } + } + + return result; +} + +/** +* @brief Delete a Semaphore +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +*/ +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) +{ + if (inHandlerMode()) { + return osErrorISR; + } + + vSemaphoreDelete(semaphore_id); + + return osOK; +} + +#endif /* Use Semaphores */ + +/******************* Memory Pool Management Functions ***********************/ + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) + +//TODO +//This is a primitive and inefficient wrapper around the existing FreeRTOS memory management. +//A better implementation will have to modify heap_x.c! + + +typedef struct os_pool_cb { + void *pool; + uint8_t *markers; + uint32_t pool_sz; + uint32_t item_sz; + uint32_t currentIndex; +} os_pool_cb_t; + + +/** +* @brief Create and Initialize a memory pool +* @param pool_def memory pool definition referenced with \ref osPool. +* @retval memory pool ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +*/ +osPoolId osPoolCreate (const osPoolDef_t *pool_def) +{ +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + osPoolId thePool; + int itemSize = 4 * ((pool_def->item_sz + 3) / 4); + uint32_t i; + + /* First have to allocate memory for the pool control block. */ + thePool = pvPortMalloc(sizeof(os_pool_cb_t)); + + + if (thePool) { + thePool->pool_sz = pool_def->pool_sz; + thePool->item_sz = itemSize; + thePool->currentIndex = 0; + + /* Memory for markers */ + thePool->markers = pvPortMalloc(pool_def->pool_sz); + + if (thePool->markers) { + /* Now allocate the pool itself. */ + thePool->pool = pvPortMalloc(pool_def->pool_sz * itemSize); + + if (thePool->pool) { + for (i = 0; i < pool_def->pool_sz; i++) { + thePool->markers[i] = 0; + } + } + else { + vPortFree(thePool->markers); + vPortFree(thePool); + thePool = NULL; + } + } + else { + vPortFree(thePool); + thePool = NULL; + } + } + + return thePool; + +#else + return NULL; +#endif +} + +/** +* @brief Allocate a memory block from a memory pool +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @retval address of the allocated memory block or NULL in case of no memory available. +* @note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osPoolAlloc (osPoolId pool_id) +{ + int dummy = 0; + void *p = NULL; + uint32_t i; + uint32_t index; + + if (inHandlerMode()) { + dummy = portSET_INTERRUPT_MASK_FROM_ISR(); + } + else { + vPortEnterCritical(); + } + + for (i = 0; i < pool_id->pool_sz; i++) { + index = (pool_id->currentIndex + i) % pool_id->pool_sz; + + if (pool_id->markers[index] == 0) { + pool_id->markers[index] = 1; + p = (void *)((uint32_t)(pool_id->pool) + (index * pool_id->item_sz)); + pool_id->currentIndex = index; + break; + } + } + + if (inHandlerMode()) { + portCLEAR_INTERRUPT_MASK_FROM_ISR(dummy); + } + else { + vPortExitCritical(); + } + + return p; +} + +/** +* @brief Allocate a memory block from a memory pool and set memory block to zero +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @retval address of the allocated memory block or NULL in case of no memory available. +* @note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osPoolCAlloc (osPoolId pool_id) +{ + void *p = osPoolAlloc(pool_id); + + if (p != NULL) + { + memset(p, 0, sizeof(pool_id->pool_sz)); + } + + return p; +} + +/** +* @brief Return an allocated memory block back to a specific memory pool +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @param block address of the allocated memory block that is returned to the memory pool. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +*/ +osStatus osPoolFree (osPoolId pool_id, void *block) +{ + uint32_t index; + + if (pool_id == NULL) { + return osErrorParameter; + } + + if (block == NULL) { + return osErrorParameter; + } + + if (block < pool_id->pool) { + return osErrorParameter; + } + + index = (uint32_t)block - (uint32_t)(pool_id->pool); + if (index % pool_id->item_sz) { + return osErrorParameter; + } + index = index / pool_id->item_sz; + if (index >= pool_id->pool_sz) { + return osErrorParameter; + } + + pool_id->markers[index] = 0; + + return osOK; +} + + +#endif /* Use Memory Pool Management */ + +/******************* Message Queue Management Functions *********************/ + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) /* Use Message Queues */ + +/** +* @brief Create and Initialize a Message Queue +* @param queue_def queue definition referenced with \ref osMessageQ. +* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +* @retval message queue ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +*/ +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) +{ + (void) thread_id; + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) { + return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); + } + else { + return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); +#else + return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); +#endif +} + +/** +* @brief Put a Message to a Queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param info message information. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) +{ + portBASE_TYPE taskWoken = pdFALSE; + TickType_t ticks; + + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + + if (inHandlerMode()) { + if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueSend(queue_id, &info, ticks) != pdTRUE) { + return osErrorOS; + } + } + + return osOK; +} + +/** +* @brief Get a Message or Wait for a Message from a Queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +* @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +*/ +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) +{ + portBASE_TYPE taskWoken; + TickType_t ticks; + osEvent event; + + event.def.message_id = queue_id; + event.value.v = 0; + + if (queue_id == NULL) { + event.status = osErrorParameter; + return event; + } + + taskWoken = pdFALSE; + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) { + /* We have mail */ + event.status = osEventMessage; + } + else { + event.status = osOK; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) { + /* We have mail */ + event.status = osEventMessage; + } + else { + event.status = (ticks == 0) ? osOK : osEventTimeout; + } + } + + return event; +} + +#endif /* Use Message Queues */ + +/******************** Mail Queue Management Functions ***********************/ +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) /* Use Mail Queues */ + + +typedef struct os_mailQ_cb { + const osMailQDef_t *queue_def; + QueueHandle_t handle; + osPoolId pool; +} os_mailQ_cb_t; + +/** +* @brief Create and Initialize mail queue +* @param queue_def reference to the mail queue definition obtain with \ref osMailQ +* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +* @retval mail queue ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +*/ +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) +{ +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + (void) thread_id; + + osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL}; + + /* Create a mail queue control block */ + + *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb)); + + if (*(queue_def->cb) == NULL) { + return NULL; + } + (*(queue_def->cb))->queue_def = queue_def; + + /* Create a queue in FreeRTOS */ + (*(queue_def->cb))->handle = xQueueCreate(queue_def->queue_sz, sizeof(void *)); + + + if ((*(queue_def->cb))->handle == NULL) { + vPortFree(*(queue_def->cb)); + return NULL; + } + + /* Create a mail pool */ + (*(queue_def->cb))->pool = osPoolCreate(&pool_def); + if ((*(queue_def->cb))->pool == NULL) { + //TODO: Delete queue. How to do it in FreeRTOS? + vPortFree(*(queue_def->cb)); + return NULL; + } + + return *(queue_def->cb); +#else + return NULL; +#endif +} + +/** +* @brief Allocate a memory block from a mail +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval pointer to memory block that can be filled with mail or NULL in case error. +* @note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osMailAlloc (osMailQId queue_id, uint32_t millisec) +{ + (void) millisec; + void *p; + + + if (queue_id == NULL) { + return NULL; + } + + p = osPoolAlloc(queue_id->pool); + + return p; +} + +/** +* @brief Allocate a memory block from a mail and set memory block to zero +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval pointer to memory block that can be filled with mail or NULL in case error. +* @note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) +{ + uint32_t i; + void *p = osMailAlloc(queue_id, millisec); + + if (p) { + for (i = 0; i < queue_id->queue_def->item_sz; i++) { + ((uint8_t *)p)[i] = 0; + } + } + + return p; +} + +/** +* @brief Put a mail to a queue +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMailPut (osMailQId queue_id, void *mail) +{ + portBASE_TYPE taskWoken; + + + if (queue_id == NULL) { + return osErrorParameter; + } + + taskWoken = pdFALSE; + + if (inHandlerMode()) { + if (xQueueSendFromISR(queue_id->handle, &mail, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueSend(queue_id->handle, &mail, 0) != pdTRUE) { + return osErrorOS; + } + } + + return osOK; +} + +/** +* @brief Get a mail from a queue +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param millisec timeout value or 0 in case of no time-out +* @retval event that contains mail information or error code. +* @note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +*/ +osEvent osMailGet (osMailQId queue_id, uint32_t millisec) +{ + portBASE_TYPE taskWoken; + TickType_t ticks; + osEvent event; + + event.def.mail_id = queue_id; + + if (queue_id == NULL) { + event.status = osErrorParameter; + return event; + } + + taskWoken = pdFALSE; + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xQueueReceiveFromISR(queue_id->handle, &event.value.p, &taskWoken) == pdTRUE) { + /* We have mail */ + event.status = osEventMail; + } + else { + event.status = osOK; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueReceive(queue_id->handle, &event.value.p, ticks) == pdTRUE) { + /* We have mail */ + event.status = osEventMail; + } + else { + event.status = (ticks == 0) ? osOK : osEventTimeout; + } + } + + return event; +} + +/** +* @brief Free a memory block from a mail +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param mail pointer to the memory block that was obtained with \ref osMailGet. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMailFree (osMailQId queue_id, void *mail) +{ + if (queue_id == NULL) { + return osErrorParameter; + } + + return osPoolFree(queue_id->pool, mail); +} +#endif /* Use Mail Queues */ + +/*************************** Additional specific APIs to Free RTOS ************/ +/** +* @brief Handles the tick increment +* @param none. +* @retval none. +*/ +void osSystickHandler(void) +{ + +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + { +#endif /* INCLUDE_xTaskGetSchedulerState */ + xPortSysTickHandler(); +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + } +#endif /* INCLUDE_xTaskGetSchedulerState */ +} + +#if ( INCLUDE_eTaskGetState == 1 ) +/** +* @brief Obtain the state of any thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval the stae of the thread, states are encoded by the osThreadState enumerated type. +*/ +osThreadState osThreadGetState(osThreadId thread_id) +{ + eTaskState ThreadState; + osThreadState result; + + ThreadState = eTaskGetState(thread_id); + + switch (ThreadState) + { + case eRunning : + result = osThreadRunning; + break; + case eReady : + result = osThreadReady; + break; + case eBlocked : + result = osThreadBlocked; + break; + case eSuspended : + result = osThreadSuspended; + break; + case eDeleted : + result = osThreadDeleted; + break; + default: + result = osThreadError; + } + + return result; +} +#endif /* INCLUDE_eTaskGetState */ + +#if (INCLUDE_eTaskGetState == 1) +/** +* @brief Check if a thread is already suspended or not. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadIsSuspended(osThreadId thread_id) +{ + if (eTaskGetState(thread_id) == eSuspended) + return osOK; + else + return osErrorOS; +} +#endif /* INCLUDE_eTaskGetState */ +/** +* @brief Suspend execution of a thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspend (osThreadId thread_id) +{ +#if (INCLUDE_vTaskSuspend == 1) + vTaskSuspend(thread_id); + + return osOK; +#else + return osErrorResource; +#endif +} + +/** +* @brief Resume execution of a suspended thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResume (osThreadId thread_id) +{ +#if (INCLUDE_vTaskSuspend == 1) + if(inHandlerMode()) + { + if (xTaskResumeFromISR(thread_id) == pdTRUE) + { + portYIELD_FROM_ISR(pdTRUE); + } + } + else + { + vTaskResume(thread_id); + } + return osOK; +#else + return osErrorResource; +#endif +} + +/** +* @brief Suspend execution of a all active threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspendAll (void) +{ + vTaskSuspendAll(); + + return osOK; +} + +/** +* @brief Resume execution of a all suspended threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResumeAll (void) +{ + if (xTaskResumeAll() == pdTRUE) + return osOK; + else + return osErrorOS; + +} + +/** +* @brief Delay a task until a specified time +* @param PreviousWakeTime Pointer to a variable that holds the time at which the +* task was last unblocked. PreviousWakeTime must be initialised with the current time +* prior to its first use (PreviousWakeTime = osKernelSysTick() ) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec) +{ +#if INCLUDE_vTaskDelayUntil + TickType_t ticks = (millisec / portTICK_PERIOD_MS); + vTaskDelayUntil((TickType_t *) PreviousWakeTime, ticks ? ticks : 1); + + return osOK; +#else + (void) millisec; + (void) PreviousWakeTime; + + return osErrorResource; +#endif +} + +/** +* @brief Abort the delay for a specific thread +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId +* @retval status code that indicates the execution status of the function. +*/ +osStatus osAbortDelay(osThreadId thread_id) +{ +#if INCLUDE_xTaskAbortDelay + + xTaskAbortDelay(thread_id); + + return osOK; +#else + (void) thread_id; + + return osErrorResource; +#endif +} + +/** +* @brief Lists all the current threads, along with their current state +* and stack usage high water mark. +* @param buffer A buffer into which the above mentioned details +* will be written +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadList (uint8_t *buffer) +{ +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) ) + vTaskList((char *)buffer); +#endif + return osOK; +} + +/** +* @brief Receive an item from a queue without removing the item from the queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +*/ +osEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec) +{ + TickType_t ticks; + osEvent event; + + event.def.message_id = queue_id; + + if (queue_id == NULL) { + event.status = osErrorParameter; + return event; + } + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (xQueuePeek(queue_id, &event.value.v, ticks) == pdTRUE) + { + /* We have mail */ + event.status = osEventMessage; + } + else + { + event.status = (ticks == 0) ? osOK : osEventTimeout; + } + + return event; +} + +/** +* @brief Get the number of messaged stored in a queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval number of messages stored in a queue. +*/ +uint32_t osMessageWaiting(osMessageQId queue_id) +{ + if (inHandlerMode()) { + return uxQueueMessagesWaitingFromISR(queue_id); + } + else + { + return uxQueueMessagesWaiting(queue_id); + } +} + +/** +* @brief Get the available space in a message queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval available space in a message queue. +*/ +uint32_t osMessageAvailableSpace(osMessageQId queue_id) +{ + return uxQueueSpacesAvailable(queue_id); +} + +/** +* @brief Delete a Message Queue +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osMessageDelete (osMessageQId queue_id) +{ + if (inHandlerMode()) { + return osErrorISR; + } + + vQueueDelete(queue_id); + + return osOK; +} + +/** +* @brief Create and Initialize a Recursive Mutex +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error.. +*/ +osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def) +{ +#if (configUSE_RECURSIVE_MUTEXES == 1) +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if (mutex_def->controlblock != NULL){ + return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock ); + } + else { + return xSemaphoreCreateRecursiveMutex(); + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock ); +#else + return xSemaphoreCreateRecursiveMutex(); +#endif +#else + return NULL; +#endif +} + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexRelease (osMutexId mutex_id) +{ +#if (configUSE_RECURSIVE_MUTEXES == 1) + osStatus result = osOK; + + if (xSemaphoreGiveRecursive(mutex_id) != pdTRUE) + { + result = osErrorOS; + } + return result; +#else + return osErrorResource; +#endif +} + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec) +{ +#if (configUSE_RECURSIVE_MUTEXES == 1) + TickType_t ticks; + + if (mutex_id == NULL) + { + return osErrorParameter; + } + + ticks = 0; + if (millisec == osWaitForever) + { + ticks = portMAX_DELAY; + } + else if (millisec != 0) + { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) + { + ticks = 1; + } + } + + if (xSemaphoreTakeRecursive(mutex_id, ticks) != pdTRUE) + { + return osErrorOS; + } + return osOK; +#else + return osErrorResource; +#endif +} + +/** +* @brief Returns the current count value of a counting semaphore +* @param semaphore_id semaphore_id ID obtained by \ref osSemaphoreCreate. +* @retval count value +*/ +uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id) +{ + return uxSemaphoreGetCount(semaphore_id); +} diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h new file mode 100644 index 0000000..1fb4186 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -0,0 +1,1026 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * + * + *---------------------------------------------------------------------------- + * + * Portions Copyright © 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright (c) 2013 ARM LIMITED + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "queue.h" +#include "semphr.h" +#include "event_groups.h" + +/** +\page cmsis_os_h Header File Template: cmsis_os.h + +The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). +Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents +its implementation. + +The file cmsis_os.h contains: + - CMSIS-RTOS API function definitions + - struct definitions for parameters and return types + - status and priority values used by CMSIS-RTOS API functions + - macros for defining threads and other kernel objects + + +Name conventions and header file modifications + +All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions. +Definitions that are prefixed \b os_ are not used in the application code but local to this header file. +All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread. + +Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. +These definitions can be specific to the underlying RTOS kernel. + +Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer +compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation. + + +Function calls from interrupt service routines + +The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR): + - \ref osSignalSet + - \ref osSemaphoreRelease + - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree + - \ref osMessagePut, \ref osMessageGet + - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree + +Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called +from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector. + +Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. +If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive. + + +Define and reference object definitions + +With \#define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file +that is used throughout a project as shown below: + +Header File +\code +#include // CMSIS RTOS header file + +// Thread definition +extern void thread_sample (void const *argument); // function prototype +osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100); + +// Pool definition +osPoolDef(MyPool, 10, long); +\endcode + + +This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is +present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be +used throughout the whole project. + +Example +\code +#include "osObjects.h" // Definition of the CMSIS-RTOS objects +\endcode + +\code +#define osObjectExternal // Objects will be defined as external symbols +#include "osObjects.h" // Reference to the CMSIS-RTOS objects +\endcode + +*/ + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 1 ///< osFeature_Semaphore function: 1=available, 0=not available +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + +#if ( INCLUDE_eTaskGetState == 1 ) +/* Thread state returned by osThreadGetState */ +typedef enum { + osThreadRunning = 0x0, /* A thread is querying the state of itself, so must be running. */ + osThreadReady = 0x1 , /* The thread being queried is in a read or pending ready list. */ + osThreadBlocked = 0x2, /* The thread being queried is in the Blocked state. */ + osThreadSuspended = 0x3, /* The thread being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ + osThreadDeleted = 0x4, /* The thread being queried has been deleted, but its TCB has not yet been freed. */ + osThreadError = 0x7FFFFFFF +} osThreadState; +#endif /* INCLUDE_eTaskGetState */ + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef TaskHandle_t osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef TimerHandle_t osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef SemaphoreHandle_t osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef SemaphoreHandle_t osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef QueueHandle_t osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + +typedef StaticTask_t osStaticThreadDef_t; +typedef StaticTimer_t osStaticTimerDef_t; +typedef StaticSemaphore_t osStaticMutexDef_t; +typedef StaticSemaphore_t osStaticSemaphoreDef_t; +typedef StaticQueue_t osStaticMessageQDef_t; + +#endif + + + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + char *name; ///< Thread name + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + uint32_t *buffer; ///< stack buffer for static allocation; NULL for dynamic allocation + osStaticThreadDef_t *controlblock; ///< control block to hold thread's data for static allocation; NULL for dynamic allocation +#endif +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + osStaticTimerDef_t *controlblock; ///< control block to hold timer's data for static allocation; NULL for dynamic allocation +#endif +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value. +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + osStaticMutexDef_t *controlblock; ///< control block for static allocation; NULL for dynamic allocation +#endif +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + osStaticSemaphoreDef_t *controlblock; ///< control block for static allocation; NULL for dynamic allocation +#endif +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + uint8_t *buffer; ///< buffer for static allocation; NULL for dynamic allocation + osStaticMessageQDef_t *controlblock; ///< control block to hold queue's data for static allocation; NULL for dynamic allocation +#endif + //void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + struct os_mailQ_cb **cb; +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency (configTICK_RATE_HZ) + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) + +#endif // System Timer available + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, thread, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osThreadDef(name, thread, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ #name, (thread), (priority), (instances), (stacksz), NULL, NULL } + +#define osThreadStaticDef(name, thread, priority, instances, stacksz, buffer, control) \ +const osThreadDef_t os_thread_def_##name = \ +{ #name, (thread), (priority), (instances), (stacksz), (buffer), (control) } +#else //configSUPPORT_STATIC_ALLOCATION == 0 + +#define osThreadDef(name, thread, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ #name, (thread), (priority), (instances), (stacksz)} +#endif +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec time delay value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), NULL } + +#define osTimerStaticDef(name, function, control) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), (control) } +#else //configSUPPORT_STATIC_ALLOCATION == 0 +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec time delay value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return osOK if successful, osErrorOS if failed. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0, NULL } + +#define osMutexStaticDef(name, control) \ +const osMutexDef_t os_mutex_def_##name = { 0, (control) } +#else //configSUPPORT_STATIC_ALLOCATION == 0 +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } + +#endif + +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0, NULL } + +#define osSemaphoreStaticDef(name, control) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0, (control) } + +#else //configSUPPORT_STATIC_ALLOCATION == 0 +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type), NULL, NULL } + +#define osMessageQStaticDef(name, queue_sz, type, buffer, control) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) , (buffer), (control)} +#else //configSUPPORT_STATIC_ALLOCATION == 1 +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } + +#endif +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern struct os_mailQ_cb *os_mailQ_cb_##name \ +extern osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +struct os_mailQ_cb *os_mailQ_cb_##name; \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type), (&os_mailQ_cb_##name) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + +/*************************** Additional specific APIs to Free RTOS ************/ +/** +* @brief Handles the tick increment +* @param none. +* @retval none. +*/ +void osSystickHandler(void); + +#if ( INCLUDE_eTaskGetState == 1 ) +/** +* @brief Obtain the state of any thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval the stae of the thread, states are encoded by the osThreadState enumerated type. +*/ +osThreadState osThreadGetState(osThreadId thread_id); +#endif /* INCLUDE_eTaskGetState */ + +#if ( INCLUDE_eTaskGetState == 1 ) +/** +* @brief Check if a thread is already suspended or not. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ + +osStatus osThreadIsSuspended(osThreadId thread_id); + +#endif /* INCLUDE_eTaskGetState */ + +/** +* @brief Suspend execution of a thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspend (osThreadId thread_id); + +/** +* @brief Resume execution of a suspended thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResume (osThreadId thread_id); + +/** +* @brief Suspend execution of a all active threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspendAll (void); + +/** +* @brief Resume execution of a all suspended threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResumeAll (void); + +/** +* @brief Delay a task until a specified time +* @param PreviousWakeTime Pointer to a variable that holds the time at which the +* task was last unblocked. PreviousWakeTime must be initialised with the current time +* prior to its first use (PreviousWakeTime = osKernelSysTick() ) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec); + +/** +* @brief Abort the delay for a specific thread +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId +* @retval status code that indicates the execution status of the function. +*/ +osStatus osAbortDelay(osThreadId thread_id); + +/** +* @brief Lists all the current threads, along with their current state +* and stack usage high water mark. +* @param buffer A buffer into which the above mentioned details +* will be written +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadList (uint8_t *buffer); + +/** +* @brief Receive an item from a queue without removing the item from the queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +*/ +osEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec); + +/** +* @brief Get the number of messaged stored in a queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval number of messages stored in a queue. +*/ +uint32_t osMessageWaiting(osMessageQId queue_id); + +/** +* @brief Get the available space in a message queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval available space in a message queue. +*/ +uint32_t osMessageAvailableSpace(osMessageQId queue_id); + +/** +* @brief Delete a Message Queue +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osMessageDelete (osMessageQId queue_id); + +/** +* @brief Create and Initialize a Recursive Mutex +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error.. +*/ +osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def); + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexRelease (osMutexId mutex_id); + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec); + +/** +* @brief Returns the current count value of a counting semaphore +* @param semaphore_id semaphore_id ID obtained by \ref osSemaphoreCreate. +* @retval count value +*/ +uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id); + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c new file mode 100644 index 0000000..b995073 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + + +/* Lists for ready and blocked co-routines. --------------------*/ +static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ +static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ +static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ +static List_t * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ +static List_t * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ +static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ +CRCB_t * pxCurrentCoRoutine = NULL; +static UBaseType_t uxTopCoRoutineReadyPriority = 0; +static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ +#define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ +#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ +{ \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ +} + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ +static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ +static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ +static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ) +{ +BaseType_t xReturn; +CRCB_t *pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + This is so we can get back to the containing CRCB from a generic item + in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ) +{ +TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckPendingReadyList( void ) +{ + /* Are there any co-routines waiting to get moved to the ready list? These + are co-routines that have been readied by an ISR. The ISR cannot access + the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t *pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckDelayedList( void ) +{ +CRCB_t *pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + section. If this is the case then the generic list item will + have been moved to the pending ready list and the following + line is still valid. Also the pvContainer parameter will have + been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pvContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineSchedule( void ) +{ + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + + return; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseCoRoutineLists( void ) +{ +UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; +} +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ) +{ +CRCB_t *pxUnblockedCRCB; +BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + event lists and the pending ready list. This function assumes that a + check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} + +#endif /* configUSE_CO_ROUTINES == 0 */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c new file mode 100644 index 0000000..4257950 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c @@ -0,0 +1,738 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining +all the API functions to use the MPU wrappers. That should only be done when +task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961 and e750 are suppressed as a MISRA exception justified because the +MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the +header files above, but not in this file, in order to generate the correct +privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */ + +/* The following bit fields convey control information in a task's event list +item value. It is important they don't clash with the +taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct xEventGroupDefinition +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) + { + EventGroup_t *pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticEventGroup_t equals the size of the real + event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + this event group was created statically in case the event group + is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); + } + + return ( EventGroupHandle_t ) pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t *pxEventBits; + + /* Allocate the event group. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + event group was allocated statically in case the event group is + later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); + } + + return ( EventGroupHandle_t ) pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) +{ +EventBits_t uxOriginalBitValue, uxReturn; +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +BaseType_t xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + the task unblocks, but some compilers mistakenly generate a + warning about uxReturn being returned without being set if the + assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + bits it was waiting for were set, it is possible that since it + unblocked another task has set the bits. If this is the case + then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) +{ +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventBits_t uxReturn, uxControlBits = 0; +BaseType_t xWaitConditionMet, xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + set. uxControlBits are used to remember the specified behaviour of + this call to xEventGroupWaitBits() - for use when the event bits + unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + some compilers mistakenly generate a warning about the variable + being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) +{ +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ +UBaseType_t uxSavedInterruptStatus; +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) +{ +ListItem_t *pxListItem, *pxNext; +ListItem_t const *pxListEnd; +List_t *pxList; +EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + item before removing the task from the event list. The + eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + that is was unblocked due to its required bits matching, rather + than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + used here as the list item may have been removed from the event list + and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ +EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + it again. */ + vPortFree( pxEventBits ); + } + #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from +an interrupt. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from +an interrupt. */ +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) +{ +BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h new file mode 100644 index 0000000..f974c73 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h @@ -0,0 +1,1168 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifndef INCLUDE_vTaskDelayUntil + #define INCLUDE_vTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + /* Used to perform any necessary initialisation - for example, open a file + into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + /* Use to close a trace, for example close a file into which trace has been + written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + /* Called after a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + /* Called before stepping the tick count after waking from tickless idle + sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + /* Called before a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + /* Called when a task attempts to take a mutex that is already held by a + lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + that holds the mutex. uxInheritedPriority is the priority the mutex holder + will inherit (the priority of the task that is attempting to obtain the + muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + /* Called when a task releases a mutex, the holding of which had resulted in + the task inheriting the priority of a higher priority task. + pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + /* Task is about to block because it cannot write to a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the write was attempted. pxCurrentTCB points to the TCB of the + task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE() +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT() +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY() +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR() +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR() +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portTASK_CALLS_SECURE_FUNCTIONS + #define portTASK_CALLS_SECURE_FUNCTIONS() +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + /* Defaults to uint16_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +/* Sanity check the configuration. */ +#if( configUSE_TICKLESS_IDLE != 0 ) + #if( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if( portTICK_TYPE_IS_ATOMIC == 0 ) + /* Either variables of tick type cannot be read atomically, or + portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + /* The tick type can be read atomically, so critical sections used when the + tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to +V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + /* configPRINTF() was not defined, so define it away to nothing. To use + configPRINTF() then define it as follows (where MyPrintFunction() is + provided by the application writer): + + void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + + Then call like a standard printf() function, but placing brackets around + all parameters so they are passed as a single parameter. For example: + configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + + /* Backward compatibility within the scheduler code only - these definitions + are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even +if floating point hardware is otherwise supported by the FreeRTOS port in use. +This constant is not supported by all FreeRTOS ports that include floating +point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + TickType_t xDummy1; + void *pvDummy2[ 4 ]; +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + TickType_t xDummy1; + void *pvDummy2[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + UBaseType_t uxDummy1; + void *pvDummy2; + StaticMiniListItem_t xDummy3; +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void *pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void *pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void *pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void *pxDummy14; + #endif + #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18; + uint8_t ucDummy19; + #endif + #if( ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) || ( portUSING_MPU_WRAPPERS == 1 ) ) + uint8_t uxDummy20; + #endif + + #if( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void *pvDummy1[ 3 ]; + + union + { + void *pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void *pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif + +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif + +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void *pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + UBaseType_t uxDummy4; + void *pvDummy5[ 2 ]; + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy6; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy7; + #endif + +} StaticTimer_t; + +/* +* In line with software engineering best practice, especially when supplying a +* library that is likely to change in future versions, FreeRTOS implements a +* strict data hiding policy. This means the stream buffer structure used +* internally by FreeRTOS is not accessible to application code. However, if +* the application writer wants to statically allocate the memory required to +* create a stream buffer then the size of the stream buffer object needs to be +* know. The StaticStreamBuffer_t structure below is provided for this purpose. +* Its size and alignment requirements are guaranteed to match those of the +* genuine structure, no matter which architecture is being used, and no matter +* how the values in FreeRTOSConfig.h are set. Its contents are somewhat +* obfuscated in the hope users will recognise that it would be unwise to make +* direct use of the structure members. +*/ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +#ifdef __cplusplus +} +#endif + +#endif /* INC_FREERTOS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h new file mode 100644 index 0000000..fd6b340 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h new file mode 100644 index 0000000..aa132bb --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h @@ -0,0 +1,720 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Used to hide the implementation of the co-routine control block. The +control block structure however has to be included in the header due to +the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + *
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );
+ * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+
+ * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ); + + +/** + * croutine. h + *
+ void vCoRoutineSchedule( void );
+ * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + 
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
+ crSTART( CoRoutineHandle_t xHandle );
+ * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0: + +/** + * croutine. h + * 
+ crEND();
+ * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): +#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): + +/** + * croutine. h + *
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * 
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + 
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }
+ * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + 
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + 
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ); + +#ifdef __cplusplus +} +#endif + +#endif /* CO_ROUTINE_H */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h new file mode 100644 index 0000000..9dfdf21 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. The +definitions below remain in the code for backward compatibility only. New +projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h new file mode 100644 index 0000000..5064404 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h @@ -0,0 +1,756 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +typedef void * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreate( void );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See http://www.freertos.org/a00111.html + * + * Example usage: + 
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+
+ * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + 
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+
+ */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+
+ * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+
+ * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+
+ * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+
+ * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+
+ * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+
+ * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + 
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+
+ * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+
+ * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
+ * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+
+ * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* EVENT_GROUPS_H */ + + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h new file mode 100644 index 0000000..431443f --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h @@ -0,0 +1,411 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + +#ifndef INC_FREERTOS_H + #error FreeRTOS.h must be included before list.h +#endif + +#ifndef LIST_H +#define LIST_H + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros that can be used to place known values within the list structures, +then check that the known values do not get corrupted during the execution of +the application. These may catch the list data structures being overwritten in +memory. They will not catch data errors caused by incorrect configuration or +use of FreeRTOS.*/ +#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + + /* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + + /* Define macros that will assert if one of the structure members does not + contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + void * configLIST_VOLATILE pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ +{ \ +List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ +} + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h new file mode 100644 index 0000000..8be9740 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h @@ -0,0 +1,779 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +#if defined( __cplusplus ) +extern "C" { +#endif + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+
+ * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: +
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+
+ * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+
+ * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: +
+
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * +
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+

+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+

+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+

+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+

+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 0000000..a08d748
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,155 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask );
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer );
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete );
+void MPU_vTaskDelay( const TickType_t xTicksToDelay );
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement );
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask );
+UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t xTask );
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask );
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend );
+void MPU_vTaskResume( TaskHandle_t xTaskToResume );
+void MPU_vTaskStartScheduler( void );
+void MPU_vTaskSuspendAll( void );
+BaseType_t MPU_xTaskResumeAll( void );
+TickType_t MPU_xTaskGetTickCount( void );
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void );
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery );
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery );
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue );
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex );
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );
+void MPU_vTaskList( char * pcWriteBuffer );
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask );
+BaseType_t MPU_xTaskIncrementTick( void );
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
+void MPU_vTaskMissedYield( void );
+BaseType_t MPU_xTaskGetSchedulerState( void );
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition );
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait );
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+void MPU_vQueueDelete( QueueHandle_t xQueue );
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType );
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue );
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount );
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue );
+void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait );
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex );
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName );
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue );
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue );
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType );
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType );
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength );
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait );
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue );
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber );
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue );
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue );
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer );
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer );
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void );
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer );
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer );
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer );
+BaseType_t MPU_xTimerCreateTimerTask( void );
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait );
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void );
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer );
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait );
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait );
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup );
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup );
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait );
+size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait );
+size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer );
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer );
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000..1e97ae4
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,181 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferSendFromISR				MPU_xStreamBufferSendFromISR
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferReceiveFromISR				MPU_xStreamBufferReceiveFromISR
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000..8aac353
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+#endif
+
+/* Used by heap_5.c. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000..d4aa198
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000..2895205
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1653 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+typedef void * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef void * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef void * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * 

+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ 

+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * 

+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );

+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);

+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);

+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );

+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );

+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
void vQueueDelete( QueueHandle_t xQueue );

+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * 

+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ 

+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ 

+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		taskYIELD_YIELD_FROM_ISR();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * 

+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000..0f58285
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )

+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ 

+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )

+ *
+ * Macro to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * Macro to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )

+ *
+ * Macro to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )

+ *
+ * Macro to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ 

+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );

+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );

+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 0000000..e8515b3
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||												\
+			( pulStack[ 1 ] != ulCheckValue ) ||												\
+			( pulStack[ 2 ] != ulCheckValue ) ||												\
+			( pulStack[ 3 ] != ulCheckValue ) )												\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 0000000..f967dd2
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,852 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+typedef void * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+

+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+

+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+

+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
+
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+

+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+
+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+

+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+

+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+

+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+

+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000..df7ce95
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
@@ -0,0 +1,2338 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.0.1"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 0
+#define tskKERNEL_VERSION_BUILD 1
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+typedef void * TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid			/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	uint16_t usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	uint16_t usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+     configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+     if( xHandle != NULL )
+     {
+	     vTaskDelete( xHandle );
+     }
+ }
+   

+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and pdPASS is returned.  If either pxStackBuffer or pxTaskBuffer
+ * are NULL then the task will not be created and
+ * errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY is returned.
+ *
+ * Example usage:
+   
+
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   

+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );

+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelete( TaskHandle_t xTask );

+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   

+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskDelay( const TickType_t xTicksToDelay );

+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );

+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   

+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskAbortDelay( TaskHandle_t xTask );

+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   

+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask );

+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
eTaskState eTaskGetState( TaskHandle_t xTask );

+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );

+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   

+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );

+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   

+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspend( TaskHandle_t xTaskToSuspend );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   

+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskResume( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   

+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void xTaskResumeFromISR( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskStartScheduler( void );

+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   

+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskEndScheduler( void );

+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   

+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspendAll( void );

+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   

+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskResumeAll( void );

+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   

+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCount( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCountFromISR( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint16_t uxTaskGetNumberOfTasks( void );

+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );

+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );

+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * 
void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );

+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * 
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );

+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	

+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskList( char *pcWriteBuffer );

+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );

+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );

+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Capture the current time status for future reference.
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/*
+ * Compare the time status now with that previously captured to see if the
+ * timeout has expired.
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only avilable when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+void *pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000..7e2eceb
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1277 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+typedef void * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/list.c b/Middlewares/Third_Party/FreeRTOS/Source/list.c
new file mode 100644
index 0000000..e3a54e3
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include 
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pvContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pvContainer = ( void * ) pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCB's which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see http://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		http://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   http://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pvContainer = ( void * ) pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pvContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
new file mode 100644
index 0000000..b17f1c7
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -0,0 +1,717 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+defined.  The value should also ensure backward compatibility.
+FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000UL )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11}				\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	orr r14, #0xd					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11}					\n" /* Save the remaining registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r3, r14}				\n"
+	"	mov r0, %0							\n"
+	"	msr basepri, r0						\n"
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r3, r14}				\n"
+	"										\n" /* Restore the context, including the critical nesting count. */
+	"	ldr r1, [r3]						\n"
+	"	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldmia r0!, {r4-r11}					\n" /* Pop the registers. */
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" ::: "memory" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( &xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" ::: "memory" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( &xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm volatile( "cpsid i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
new file mode 100644
index 0000000..860ad5b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -0,0 +1,242 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n" \
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n" \
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..9ec5af5
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,436 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000..f6d1450
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
@@ -0,0 +1,2908 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+pcTail pointer actually points to the mutex holder (if any).  Map alternative
+names to the pcHead and pcTail structure members to ensure the readability of
+the code is maintained despite this dual use of two structure members.  An
+alternative implementation would be to use a union, but use of a union is
+against the coding standard (although an exception to the standard has been
+permitted where the dual use also significantly changes the type of the
+structure member). */
+#define pxMutexHolder					pcTail
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union							/* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */
+	{
+		int8_t *pcReadFrom;			/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+		UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		if( uxItemSize == ( UBaseType_t ) 0 )
+		{
+			/* There is not going to be a queue storage area. */
+			xQueueSizeInBytes = ( size_t ) 0;
+		}
+		else
+		{
+			/* Allocate enough space to hold the maximum number of items that
+			can be in the queue at any time. */
+			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		}
+
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( ( uint8_t * ) pxNewQueue ) + sizeof( Queue_t );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->pxMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		pxNewQueue = ( Queue_t * ) xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( pxNewQueue );
+
+		return pxNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	Queue_t *pxNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		pxNewQueue = ( Queue_t * ) xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( pxNewQueue );
+
+		return pxNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	void *pxReturn;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	void *pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then pxMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+		{
+			( pxMutex->u.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+				xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( ( void * ) pxQueue->pxMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t *pxQueue;
+
+	pxQueue = ( Queue_t * ) xQueue;
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0 )
+		{
+			uxHighestPriorityOfWaitingTasks = configMAX_PRIORITIES - listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );
+				pxQueue->pxMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize;
+		if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+		if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+
+	configASSERT( xQueue );
+	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+
+	configASSERT( xQueue );
+	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+				{
+					pxQueue->u.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+			{
+				pxQueue->u.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 0000000..c0ef727
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1199 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( size_t ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct xSTREAM_BUFFER /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ); PRIVILEGED_FUNCTION
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   xIsMessageBuffer );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t * ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Function parameter deliberately modified to ensure it is in range. */
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  xIsMessageBuffer );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn = pdFAIL, xIsMessageBuffer;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+	{
+		if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+		{
+			if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+			{
+				xIsMessageBuffer = pdTRUE;
+			}
+			else
+			{
+				xIsMessageBuffer = pdFALSE;
+			}
+
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pxStreamBuffer->pucBuffer,
+										  pxStreamBuffer->xLength,
+										  pxStreamBuffer->xTriggerLevelBytes,
+										  xIsMessageBuffer );
+			xReturn = pdPASS;
+
+			#if( configUSE_TRACE_FACILITY == 1 )
+			{
+				pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+			}
+			#endif
+
+			traceSTREAM_BUFFER_RESET( xStreamBuffer );
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); /*lint !e9044 Function parameter modified to ensure it is capped to available space. */
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  BaseType_t xIsMessageBuffer )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	}
+	#endif
+
+	memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+
+	if( xIsMessageBuffer != pdFALSE )
+	{
+		pxStreamBuffer->ucFlags |= sbFLAGS_IS_MESSAGE_BUFFER;
+	}
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( ( StreamBuffer_t * )xStreamBuffer )->ucFlags | sbFLAGS_IS_MESSAGE_BUFFER;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000..9e1cb9b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5039 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include 
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+dynamically allocated RAM, in which case when any task is deleted it is known
+that both the task's stack and TCB need to be freed.  Sometimes the
+FreeRTOSConfig.h settings only allow a task to be created using statically
+allocated RAM, in which case when any task is deleted it is known that neither
+the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
+settings allow a task to be created using either statically or dynamically
+allocated RAM, in which case a member of the TCB is used to record whether the
+stack and/or TCB were allocated statically or dynamically, so when a task is
+deleted the RAM that was allocated dynamically is freed again and no attempt is
+made to free the RAM that was allocated statically.
+tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+task to be created using either statically or dynamically allocated RAM.  Note
+that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+a statically allocated stack and a dynamically allocated TCB.
+!!!NOTE!!! If the definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is
+changed then the definition of StaticTask_t must also be updated. */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE	( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments above the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------*/
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ] = {0};	/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1 = {0};								/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2 = {0};								/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList = NULL;					/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList = NULL;			/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList = {0};								/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination = {0};					/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList = {0};						/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks 			= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+	extern void vApplicationTickHook( void );
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+
+	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e961 MISRA exception as the casts are only redundant for some paths. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type. */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+	{
+		pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+		/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+		configMAX_TASK_NAME_LEN characters just in case the memory after the
+		string is not accessible (extremely unlikely). */
+		if( pcName[ x ] == 0x00 )
+		{
+			break;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	/* Ensure the name string is terminated in the case that the string length
+	was greater or equal to configMAX_TASK_NAME_LEN. */
+	pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( ( void * ) pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+
+			traceTASK_DELETE( pxTCB );
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t *pxStateList;
+	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it block
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						eReturn = eSuspended;
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the that
+			called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) 0U;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+	++uxSchedulerSuspended;
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
+
+					if( uxPendedCounts > ( UBaseType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--uxPendedCounts;
+						} while( uxPendedCounts > ( UBaseType_t ) 0U );
+
+						uxPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						break;
+					}
+					else if( cNextChar == 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						break;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return ( TaskHandle_t ) pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = ( TCB_t * ) xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( uxPendedTicks == ( UBaseType_t ) 0U )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+	}
+	else
+	{
+		++uxPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	#if ( configUSE_PREEMPTION == 1 )
+	{
+		if( xYieldPending != pdFALSE )
+		{
+			xSwitchRequired = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_PREEMPTION */
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = ( TCB_t * ) xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+			xTCB->pxTaskTag = pxHookFunction;
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *xTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then we are setting our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = ( TCB_t * ) xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = xTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = ( TCB_t * ) xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+				#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+					portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+				#else
+					ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+				#endif
+
+				/* Add the amount of time the task has been running to the
+				accumulated time so far.  The time the task started running was
+				stored in ulTaskSwitchedInTime.  Note that there is no overflow
+				protection here so count values are only valid until the timer
+				overflows.  The guard against negative values is to protect
+				against suspect run time stat counter implementations - which
+				are provided by the application, not the kernel. */
+				if( ulTotalRunTime > ulTaskSwitchedInTime )
+				{
+					pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK();
+		traceTASK_SWITCHED_IN();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	#if( configUSE_TICKLESS_IDLE != 0 )
+	{
+		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+		might be set to the blocked task's time out time.  If the task is
+		unblocked for a reason other than a timeout xNextTaskUnblockTime is
+		normally left unchanged, because it is automatically reset to a new
+		value when the tick count equals xNextTaskUnblockTime.  However if
+		tickless idling is used it might be more important to enter sleep mode
+		at the earliest possible time - so reset xNextTaskUnblockTime here to
+		ensure it is updated at the earliest possible time. */
+		prvResetNextTaskUnblockTime();
+	}
+	#endif
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = ( TCB_t * ) xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = ( TCB_t * ) xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portTASK_CALLS_SECURE_FUNCTIONS();
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent vTaskSuspendAll()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+
+	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( uint16_t ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = ( TCB_t * ) pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
+				pcWriteBuffer += strlen( pcWriteBuffer );
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0 )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void *pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = ( TCB_t * ) xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = ( TCB_t * ) xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+					else
+					{
+						/* Mark that a yield is pending in case the user is not
+						using the "xHigherPriorityTaskWoken" parameter to an ISR
+						safe FreeRTOS function. */
+						xYieldPending = pdTRUE;
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = ( TCB_t * ) xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+					else
+					{
+						/* Mark that a yield is pending in case the user is not
+						using the "xHigherPriorityTaskWoken" parameter in an ISR
+						safe FreeRTOS function. */
+						xYieldPending = pdTRUE;
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	static void freertos_tasks_c_additions_init( void )
+	{
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		#endif
+	}
+
+#endif
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000..8a5d99c
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
@@ -0,0 +1,1076 @@
+/*
+ * FreeRTOS Kernel V10.0.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	UBaseType_t				uxAutoReload;		/*<< Set to pdTRUE if the timer should be automatically restarted once expired.  Set to pdFALSE if the timer is, in effect, a one-shot timer. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t 			ucStaticallyAllocated; /*<< Set to pdTRUE if the timer was created statically so no attempt is made to free the memory again if the timer is later deleted. */
+	#endif
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists. */
+PRIVILEGED_DATA static List_t xActiveTimerList1 = {0};
+PRIVILEGED_DATA static List_t xActiveTimerList2 = {0};
+PRIVILEGED_DATA static List_t *pxCurrentTimerList = NULL;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList = NULL;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
+
+		if( pxNewTimer != NULL )
+		{
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Timers can be created statically or dynamically, so note this
+				timer was created dynamically in case the timer is later
+				deleted. */
+				pxNewTimer->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewTimer != NULL )
+		{
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Timers can be created statically or dynamically so note this
+				timer was created statically in case it is later deleted. */
+				pxNewTimer->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->uxAutoReload = uxAutoReload;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer = ( Timer_t * ) xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTimerTask( void *pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+			    case tmrCOMMAND_START_FROM_ISR :
+			    case tmrCOMMAND_RESET :
+			    case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list.
+					There is nothing to do here. */
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					/* The timer has already been removed from the active list,
+					just free up the memory if the memory was dynamically
+					allocated. */
+					#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+					{
+						/* The timer can only have been allocated dynamically -
+						free it again. */
+						vPortFree( pxTimer );
+					}
+					#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+					{
+						/* The timer could have been allocated statically or
+						dynamically, so check before attempting to free the
+						memory. */
+						if( pxTimer->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xTimerIsInActiveList;
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		/* Checking to see if it is in the NULL list in effect checks to see if
+		it is referenced from either the current or the overflow timer lists in
+		one go, but the logic has to be reversed, hence the '!'. */
+		xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) ); /*lint !e961. Cast is only redundant when NULL is passed into the macro. */
+	}
+	taskEXIT_CRITICAL();
+
+	return xTimerIsInActiveList;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/Release/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk b/Release/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk
new file mode 100644
index 0000000..bc64591
--- /dev/null
+++ b/Release/Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk
@@ -0,0 +1,119 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c \
+../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c 
+
+OBJS += \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.o 
+
+C_DEPS += \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d \
+./Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.o: ../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Release/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk b/Release/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk
new file mode 100644
index 0000000..6c6d0bf
--- /dev/null
+++ b/Release/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk
@@ -0,0 +1,19 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c 
+
+OBJS += \
+./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o 
+
+C_DEPS += \
+./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o: ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk b/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk
new file mode 100644
index 0000000..9341ba8
--- /dev/null
+++ b/Release/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk
@@ -0,0 +1,29 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \
+../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \
+../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c 
+
+OBJS += \
+./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o \
+./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o \
+./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o 
+
+C_DEPS += \
+./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d \
+./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d \
+./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o: ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o: ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o: ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Release/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk b/Release/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk
new file mode 100644
index 0000000..34a3644
--- /dev/null
+++ b/Release/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk
@@ -0,0 +1,19 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Release/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/subdir.mk b/Release/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/subdir.mk
new file mode 100644
index 0000000..0ef5ec2
--- /dev/null
+++ b/Release/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/subdir.mk
@@ -0,0 +1,19 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Release/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk b/Release/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
new file mode 100644
index 0000000..0806be8
--- /dev/null
+++ b/Release/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
@@ -0,0 +1,19 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Release/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk b/Release/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
new file mode 100644
index 0000000..da74f4d
--- /dev/null
+++ b/Release/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
@@ -0,0 +1,49 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \
+../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \
+../Middlewares/Third_Party/FreeRTOS/Source/list.c \
+../Middlewares/Third_Party/FreeRTOS/Source/queue.c \
+../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \
+../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \
+../Middlewares/Third_Party/FreeRTOS/Source/timers.c 
+
+OBJS += \
+./Middlewares/Third_Party/FreeRTOS/Source/croutine.o \
+./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o \
+./Middlewares/Third_Party/FreeRTOS/Source/list.o \
+./Middlewares/Third_Party/FreeRTOS/Source/queue.o \
+./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o \
+./Middlewares/Third_Party/FreeRTOS/Source/tasks.o \
+./Middlewares/Third_Party/FreeRTOS/Source/timers.o 
+
+C_DEPS += \
+./Middlewares/Third_Party/FreeRTOS/Source/croutine.d \
+./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d \
+./Middlewares/Third_Party/FreeRTOS/Source/list.d \
+./Middlewares/Third_Party/FreeRTOS/Source/queue.d \
+./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d \
+./Middlewares/Third_Party/FreeRTOS/Source/tasks.d \
+./Middlewares/Third_Party/FreeRTOS/Source/timers.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Middlewares/Third_Party/FreeRTOS/Source/croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/croutine.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Middlewares/Third_Party/FreeRTOS/Source/event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/event_groups.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Middlewares/Third_Party/FreeRTOS/Source/list.o: ../Middlewares/Third_Party/FreeRTOS/Source/list.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/list.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Middlewares/Third_Party/FreeRTOS/Source/queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/queue.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/queue.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Middlewares/Third_Party/FreeRTOS/Source/tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/tasks.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Middlewares/Third_Party/FreeRTOS/Source/timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/timers.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/timers.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Release/STM32Display.bin b/Release/STM32Display.bin
new file mode 100755
index 0000000..b3fdee0
Binary files /dev/null and b/Release/STM32Display.bin differ
diff --git a/Release/STM32Display.list b/Release/STM32Display.list
new file mode 100644
index 0000000..32a16b9
--- /dev/null
+++ b/Release/STM32Display.list
@@ -0,0 +1,6869 @@
+
+STM32Display.elf:     file format elf32-littlearm
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .isr_vector   0000010c  08000000  08000000  00010000  2**0
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  1 .text         0000432c  08000110  08000110  00010110  2**4
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .rodata       000000c4  0800443c  0800443c  0001443c  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 .ARM.extab    00000000  08004500  08004500  00020180  2**0
+                  CONTENTS
+  4 .ARM          00000000  08004500  08004500  00020180  2**0
+                  CONTENTS
+  5 .preinit_array 00000000  08004500  08004500  00020180  2**0
+                  CONTENTS, ALLOC, LOAD, DATA
+  6 .init_array   00000004  08004500  08004500  00014500  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  7 .fini_array   00000004  08004504  08004504  00014504  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  8 .data         00000180  20000000  08004508  00020000  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  9 .bss          00001f98  20000180  08004688  00020180  2**2
+                  ALLOC
+ 10 ._user_heap_stack 00000600  20002118  08004688  00022118  2**0
+                  ALLOC
+ 11 .ARM.attributes 00000029  00000000  00000000  00020180  2**0
+                  CONTENTS, READONLY
+ 12 .comment      0000007b  00000000  00000000  000201a9  2**0
+                  CONTENTS, READONLY
+ 13 .debug_frame  0000002c  00000000  00000000  00020224  2**2
+                  CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+08000110 <__do_global_dtors_aux>:
+ 8000110:	b510      	push	{r4, lr}
+ 8000112:	4c05      	ldr	r4, [pc, #20]	; (8000128 <__do_global_dtors_aux+0x18>)
+ 8000114:	7823      	ldrb	r3, [r4, #0]
+ 8000116:	b933      	cbnz	r3, 8000126 <__do_global_dtors_aux+0x16>
+ 8000118:	4b04      	ldr	r3, [pc, #16]	; (800012c <__do_global_dtors_aux+0x1c>)
+ 800011a:	b113      	cbz	r3, 8000122 <__do_global_dtors_aux+0x12>
+ 800011c:	4804      	ldr	r0, [pc, #16]	; (8000130 <__do_global_dtors_aux+0x20>)
+ 800011e:	f3af 8000 	nop.w
+ 8000122:	2301      	movs	r3, #1
+ 8000124:	7023      	strb	r3, [r4, #0]
+ 8000126:	bd10      	pop	{r4, pc}
+ 8000128:	20000180 	.word	0x20000180
+ 800012c:	00000000 	.word	0x00000000
+ 8000130:	08004424 	.word	0x08004424
+
+08000134 :
+ 8000134:	b508      	push	{r3, lr}
+ 8000136:	4b03      	ldr	r3, [pc, #12]	; (8000144 )
+ 8000138:	b11b      	cbz	r3, 8000142 
+ 800013a:	4903      	ldr	r1, [pc, #12]	; (8000148 )
+ 800013c:	4803      	ldr	r0, [pc, #12]	; (800014c )
+ 800013e:	f3af 8000 	nop.w
+ 8000142:	bd08      	pop	{r3, pc}
+ 8000144:	00000000 	.word	0x00000000
+ 8000148:	20000184 	.word	0x20000184
+ 800014c:	08004424 	.word	0x08004424
+
+08000150 :
+ 8000150:	b538      	push	{r3, r4, r5, lr}
+ 8000152:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
+ 8000156:	490d      	ldr	r1, [pc, #52]	; (800018c )
+ 8000158:	4a0d      	ldr	r2, [pc, #52]	; (8000190 )
+ 800015a:	7809      	ldrb	r1, [r1, #0]
+ 800015c:	6812      	ldr	r2, [r2, #0]
+ 800015e:	fbb3 f3f1 	udiv	r3, r3, r1
+ 8000162:	4605      	mov	r5, r0
+ 8000164:	fbb2 f0f3 	udiv	r0, r2, r3
+ 8000168:	f000 f890 	bl	800028c 
+ 800016c:	b908      	cbnz	r0, 8000172 
+ 800016e:	2d0f      	cmp	r5, #15
+ 8000170:	d901      	bls.n	8000176 
+ 8000172:	2001      	movs	r0, #1
+ 8000174:	bd38      	pop	{r3, r4, r5, pc}
+ 8000176:	4604      	mov	r4, r0
+ 8000178:	4602      	mov	r2, r0
+ 800017a:	4629      	mov	r1, r5
+ 800017c:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+ 8000180:	f000 f840 	bl	8000204 
+ 8000184:	4b03      	ldr	r3, [pc, #12]	; (8000194 )
+ 8000186:	4620      	mov	r0, r4
+ 8000188:	601d      	str	r5, [r3, #0]
+ 800018a:	bd38      	pop	{r3, r4, r5, pc}
+ 800018c:	20000000 	.word	0x20000000
+ 8000190:	2000011c 	.word	0x2000011c
+ 8000194:	20000004 	.word	0x20000004
+
+08000198 :
+ 8000198:	4a07      	ldr	r2, [pc, #28]	; (80001b8 )
+ 800019a:	b508      	push	{r3, lr}
+ 800019c:	6813      	ldr	r3, [r2, #0]
+ 800019e:	2003      	movs	r0, #3
+ 80001a0:	f043 0310 	orr.w	r3, r3, #16
+ 80001a4:	6013      	str	r3, [r2, #0]
+ 80001a6:	f000 f81b 	bl	80001e0 
+ 80001aa:	200f      	movs	r0, #15
+ 80001ac:	f7ff ffd0 	bl	8000150 
+ 80001b0:	f003 fd62 	bl	8003c78 
+ 80001b4:	2000      	movs	r0, #0
+ 80001b6:	bd08      	pop	{r3, pc}
+ 80001b8:	40022000 	.word	0x40022000
+
+080001bc :
+ 80001bc:	4a03      	ldr	r2, [pc, #12]	; (80001cc )
+ 80001be:	4b04      	ldr	r3, [pc, #16]	; (80001d0 )
+ 80001c0:	6811      	ldr	r1, [r2, #0]
+ 80001c2:	781b      	ldrb	r3, [r3, #0]
+ 80001c4:	440b      	add	r3, r1
+ 80001c6:	6013      	str	r3, [r2, #0]
+ 80001c8:	4770      	bx	lr
+ 80001ca:	bf00      	nop
+ 80001cc:	2000110c 	.word	0x2000110c
+ 80001d0:	20000000 	.word	0x20000000
+
+080001d4 :
+ 80001d4:	4b01      	ldr	r3, [pc, #4]	; (80001dc )
+ 80001d6:	6818      	ldr	r0, [r3, #0]
+ 80001d8:	4770      	bx	lr
+ 80001da:	bf00      	nop
+ 80001dc:	2000110c 	.word	0x2000110c
+
+080001e0 :
+ 80001e0:	f64f 01ff 	movw	r1, #63743	; 0xf8ff
+ 80001e4:	4a06      	ldr	r2, [pc, #24]	; (8000200 )
+ 80001e6:	0200      	lsls	r0, r0, #8
+ 80001e8:	68d3      	ldr	r3, [r2, #12]
+ 80001ea:	f400 60e0 	and.w	r0, r0, #1792	; 0x700
+ 80001ee:	400b      	ands	r3, r1
+ 80001f0:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
+ 80001f4:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
+ 80001f8:	4303      	orrs	r3, r0
+ 80001fa:	60d3      	str	r3, [r2, #12]
+ 80001fc:	4770      	bx	lr
+ 80001fe:	bf00      	nop
+ 8000200:	e000ed00 	.word	0xe000ed00
+
+08000204 :
+ 8000204:	4b18      	ldr	r3, [pc, #96]	; (8000268 )
+ 8000206:	b430      	push	{r4, r5}
+ 8000208:	68db      	ldr	r3, [r3, #12]
+ 800020a:	f3c3 2302 	ubfx	r3, r3, #8, #3
+ 800020e:	f1c3 0507 	rsb	r5, r3, #7
+ 8000212:	2d04      	cmp	r5, #4
+ 8000214:	f103 0404 	add.w	r4, r3, #4
+ 8000218:	bf28      	it	cs
+ 800021a:	2504      	movcs	r5, #4
+ 800021c:	2c06      	cmp	r4, #6
+ 800021e:	d919      	bls.n	8000254 
+ 8000220:	f04f 34ff 	mov.w	r4, #4294967295	; 0xffffffff
+ 8000224:	3b03      	subs	r3, #3
+ 8000226:	409c      	lsls	r4, r3
+ 8000228:	ea22 0404 	bic.w	r4, r2, r4
+ 800022c:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
+ 8000230:	40aa      	lsls	r2, r5
+ 8000232:	ea21 0102 	bic.w	r1, r1, r2
+ 8000236:	fa01 f203 	lsl.w	r2, r1, r3
+ 800023a:	4322      	orrs	r2, r4
+ 800023c:	0112      	lsls	r2, r2, #4
+ 800023e:	2800      	cmp	r0, #0
+ 8000240:	b2d2      	uxtb	r2, r2
+ 8000242:	db0a      	blt.n	800025a 
+ 8000244:	f100 4060 	add.w	r0, r0, #3758096384	; 0xe0000000
+ 8000248:	f500 4061 	add.w	r0, r0, #57600	; 0xe100
+ 800024c:	f880 2300 	strb.w	r2, [r0, #768]	; 0x300
+ 8000250:	bc30      	pop	{r4, r5}
+ 8000252:	4770      	bx	lr
+ 8000254:	2400      	movs	r4, #0
+ 8000256:	4623      	mov	r3, r4
+ 8000258:	e7e8      	b.n	800022c 
+ 800025a:	4b04      	ldr	r3, [pc, #16]	; (800026c )
+ 800025c:	f000 000f 	and.w	r0, r0, #15
+ 8000260:	4403      	add	r3, r0
+ 8000262:	761a      	strb	r2, [r3, #24]
+ 8000264:	bc30      	pop	{r4, r5}
+ 8000266:	4770      	bx	lr
+ 8000268:	e000ed00 	.word	0xe000ed00
+ 800026c:	e000ecfc 	.word	0xe000ecfc
+
+08000270 :
+ 8000270:	2800      	cmp	r0, #0
+ 8000272:	db07      	blt.n	8000284 
+ 8000274:	2301      	movs	r3, #1
+ 8000276:	f000 011f 	and.w	r1, r0, #31
+ 800027a:	4a03      	ldr	r2, [pc, #12]	; (8000288 )
+ 800027c:	408b      	lsls	r3, r1
+ 800027e:	0940      	lsrs	r0, r0, #5
+ 8000280:	f842 3020 	str.w	r3, [r2, r0, lsl #2]
+ 8000284:	4770      	bx	lr
+ 8000286:	bf00      	nop
+ 8000288:	e000e100 	.word	0xe000e100
+
+0800028c :
+ 800028c:	3801      	subs	r0, #1
+ 800028e:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
+ 8000292:	d20d      	bcs.n	80002b0 
+ 8000294:	b430      	push	{r4, r5}
+ 8000296:	25f0      	movs	r5, #240	; 0xf0
+ 8000298:	2200      	movs	r2, #0
+ 800029a:	2107      	movs	r1, #7
+ 800029c:	4b05      	ldr	r3, [pc, #20]	; (80002b4 )
+ 800029e:	4c06      	ldr	r4, [pc, #24]	; (80002b8 )
+ 80002a0:	6058      	str	r0, [r3, #4]
+ 80002a2:	f884 5023 	strb.w	r5, [r4, #35]	; 0x23
+ 80002a6:	4610      	mov	r0, r2
+ 80002a8:	bc30      	pop	{r4, r5}
+ 80002aa:	609a      	str	r2, [r3, #8]
+ 80002ac:	6019      	str	r1, [r3, #0]
+ 80002ae:	4770      	bx	lr
+ 80002b0:	2001      	movs	r0, #1
+ 80002b2:	4770      	bx	lr
+ 80002b4:	e000e010 	.word	0xe000e010
+ 80002b8:	e000ed00 	.word	0xe000ed00
+
+080002bc :
+ 80002bc:	680a      	ldr	r2, [r1, #0]
+ 80002be:	2a00      	cmp	r2, #0
+ 80002c0:	f000 80db 	beq.w	800047a 
+ 80002c4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 80002c8:	f04f 0a00 	mov.w	sl, #0
+ 80002cc:	b085      	sub	sp, #20
+ 80002ce:	4655      	mov	r5, sl
+ 80002d0:	f8df c1d0 	ldr.w	ip, [pc, #464]	; 80004a4 
+ 80002d4:	f8df e1d0 	ldr.w	lr, [pc, #464]	; 80004a8 
+ 80002d8:	4f6d      	ldr	r7, [pc, #436]	; (8000490 )
+ 80002da:	f8df 81d0 	ldr.w	r8, [pc, #464]	; 80004ac 
+ 80002de:	e003      	b.n	80002e8 
+ 80002e0:	3501      	adds	r5, #1
+ 80002e2:	fa32 f305 	lsrs.w	r3, r2, r5
+ 80002e6:	d078      	beq.n	80003da 
+ 80002e8:	2301      	movs	r3, #1
+ 80002ea:	40ab      	lsls	r3, r5
+ 80002ec:	ea02 0403 	and.w	r4, r2, r3
+ 80002f0:	42a3      	cmp	r3, r4
+ 80002f2:	d1f5      	bne.n	80002e0 
+ 80002f4:	684a      	ldr	r2, [r1, #4]
+ 80002f6:	2a12      	cmp	r2, #18
+ 80002f8:	f000 809e 	beq.w	8000438 
+ 80002fc:	f200 8087 	bhi.w	800040e 
+ 8000300:	2a02      	cmp	r2, #2
+ 8000302:	f000 809d 	beq.w	8000440 
+ 8000306:	d97c      	bls.n	8000402 
+ 8000308:	2a03      	cmp	r2, #3
+ 800030a:	d069      	beq.n	80003e0 
+ 800030c:	2a11      	cmp	r2, #17
+ 800030e:	d102      	bne.n	8000316 
+ 8000310:	68cb      	ldr	r3, [r1, #12]
+ 8000312:	f103 0a04 	add.w	sl, r3, #4
+ 8000316:	2cff      	cmp	r4, #255	; 0xff
+ 8000318:	d866      	bhi.n	80003e8 
+ 800031a:	4681      	mov	r9, r0
+ 800031c:	6803      	ldr	r3, [r0, #0]
+ 800031e:	00aa      	lsls	r2, r5, #2
+ 8000320:	260f      	movs	r6, #15
+ 8000322:	fa06 fb02 	lsl.w	fp, r6, r2
+ 8000326:	ea23 030b 	bic.w	r3, r3, fp
+ 800032a:	fa0a f202 	lsl.w	r2, sl, r2
+ 800032e:	4313      	orrs	r3, r2
+ 8000330:	f8c9 3000 	str.w	r3, [r9]
+ 8000334:	684a      	ldr	r2, [r1, #4]
+ 8000336:	00d3      	lsls	r3, r2, #3
+ 8000338:	d561      	bpl.n	80003fe 
+ 800033a:	f8dc 9018 	ldr.w	r9, [ip, #24]
+ 800033e:	f025 0303 	bic.w	r3, r5, #3
+ 8000342:	f049 0901 	orr.w	r9, r9, #1
+ 8000346:	f8cc 9018 	str.w	r9, [ip, #24]
+ 800034a:	f8dc 9018 	ldr.w	r9, [ip, #24]
+ 800034e:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
+ 8000352:	f009 0901 	and.w	r9, r9, #1
+ 8000356:	f8cd 900c 	str.w	r9, [sp, #12]
+ 800035a:	f503 3380 	add.w	r3, r3, #65536	; 0x10000
+ 800035e:	f005 0903 	and.w	r9, r5, #3
+ 8000362:	f8dd b00c 	ldr.w	fp, [sp, #12]
+ 8000366:	ea4f 0989 	mov.w	r9, r9, lsl #2
+ 800036a:	f8d3 b008 	ldr.w	fp, [r3, #8]
+ 800036e:	fa06 f609 	lsl.w	r6, r6, r9
+ 8000372:	ea2b 0606 	bic.w	r6, fp, r6
+ 8000376:	4570      	cmp	r0, lr
+ 8000378:	9601      	str	r6, [sp, #4]
+ 800037a:	d011      	beq.n	80003a0 
+ 800037c:	4540      	cmp	r0, r8
+ 800037e:	d063      	beq.n	8000448 
+ 8000380:	4e44      	ldr	r6, [pc, #272]	; (8000494 )
+ 8000382:	42b0      	cmp	r0, r6
+ 8000384:	d07a      	beq.n	800047c 
+ 8000386:	4e44      	ldr	r6, [pc, #272]	; (8000498 )
+ 8000388:	42b0      	cmp	r0, r6
+ 800038a:	bf0c      	ite	eq
+ 800038c:	f04f 0b03 	moveq.w	fp, #3
+ 8000390:	f04f 0b04 	movne.w	fp, #4
+ 8000394:	9e01      	ldr	r6, [sp, #4]
+ 8000396:	fa0b f909 	lsl.w	r9, fp, r9
+ 800039a:	ea46 0609 	orr.w	r6, r6, r9
+ 800039e:	9601      	str	r6, [sp, #4]
+ 80003a0:	609e      	str	r6, [r3, #8]
+ 80003a2:	683b      	ldr	r3, [r7, #0]
+ 80003a4:	03d6      	lsls	r6, r2, #15
+ 80003a6:	bf4c      	ite	mi
+ 80003a8:	4323      	orrmi	r3, r4
+ 80003aa:	43a3      	bicpl	r3, r4
+ 80003ac:	603b      	str	r3, [r7, #0]
+ 80003ae:	687b      	ldr	r3, [r7, #4]
+ 80003b0:	0396      	lsls	r6, r2, #14
+ 80003b2:	bf4c      	ite	mi
+ 80003b4:	4323      	orrmi	r3, r4
+ 80003b6:	43a3      	bicpl	r3, r4
+ 80003b8:	607b      	str	r3, [r7, #4]
+ 80003ba:	68bb      	ldr	r3, [r7, #8]
+ 80003bc:	02d6      	lsls	r6, r2, #11
+ 80003be:	bf4c      	ite	mi
+ 80003c0:	4323      	orrmi	r3, r4
+ 80003c2:	43a3      	bicpl	r3, r4
+ 80003c4:	60bb      	str	r3, [r7, #8]
+ 80003c6:	0292      	lsls	r2, r2, #10
+ 80003c8:	68fb      	ldr	r3, [r7, #12]
+ 80003ca:	d515      	bpl.n	80003f8 
+ 80003cc:	431c      	orrs	r4, r3
+ 80003ce:	60fc      	str	r4, [r7, #12]
+ 80003d0:	680a      	ldr	r2, [r1, #0]
+ 80003d2:	3501      	adds	r5, #1
+ 80003d4:	fa32 f305 	lsrs.w	r3, r2, r5
+ 80003d8:	d186      	bne.n	80002e8 
+ 80003da:	b005      	add	sp, #20
+ 80003dc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 80003e0:	2cff      	cmp	r4, #255	; 0xff
+ 80003e2:	f04f 0a00 	mov.w	sl, #0
+ 80003e6:	d998      	bls.n	800031a 
+ 80003e8:	f105 4280 	add.w	r2, r5, #1073741824	; 0x40000000
+ 80003ec:	3a08      	subs	r2, #8
+ 80003ee:	6843      	ldr	r3, [r0, #4]
+ 80003f0:	0092      	lsls	r2, r2, #2
+ 80003f2:	f100 0904 	add.w	r9, r0, #4
+ 80003f6:	e793      	b.n	8000320 
+ 80003f8:	ea23 0404 	bic.w	r4, r3, r4
+ 80003fc:	60fc      	str	r4, [r7, #12]
+ 80003fe:	680a      	ldr	r2, [r1, #0]
+ 8000400:	e76e      	b.n	80002e0 
+ 8000402:	b1a2      	cbz	r2, 800042e 
+ 8000404:	2a01      	cmp	r2, #1
+ 8000406:	d186      	bne.n	8000316 
+ 8000408:	f8d1 a00c 	ldr.w	sl, [r1, #12]
+ 800040c:	e783      	b.n	8000316 
+ 800040e:	4e23      	ldr	r6, [pc, #140]	; (800049c )
+ 8000410:	42b2      	cmp	r2, r6
+ 8000412:	d00c      	beq.n	800042e 
+ 8000414:	d920      	bls.n	8000458 
+ 8000416:	4e22      	ldr	r6, [pc, #136]	; (80004a0 )
+ 8000418:	42b2      	cmp	r2, r6
+ 800041a:	d008      	beq.n	800042e 
+ 800041c:	f506 3680 	add.w	r6, r6, #65536	; 0x10000
+ 8000420:	42b2      	cmp	r2, r6
+ 8000422:	d004      	beq.n	800042e 
+ 8000424:	f5a6 1680 	sub.w	r6, r6, #1048576	; 0x100000
+ 8000428:	42b2      	cmp	r2, r6
+ 800042a:	f47f af74 	bne.w	8000316 
+ 800042e:	688a      	ldr	r2, [r1, #8]
+ 8000430:	b9e2      	cbnz	r2, 800046c 
+ 8000432:	f04f 0a04 	mov.w	sl, #4
+ 8000436:	e76e      	b.n	8000316 
+ 8000438:	68cb      	ldr	r3, [r1, #12]
+ 800043a:	f103 0a0c 	add.w	sl, r3, #12
+ 800043e:	e76a      	b.n	8000316 
+ 8000440:	68cb      	ldr	r3, [r1, #12]
+ 8000442:	f103 0a08 	add.w	sl, r3, #8
+ 8000446:	e766      	b.n	8000316 
+ 8000448:	f04f 0b01 	mov.w	fp, #1
+ 800044c:	fa0b f909 	lsl.w	r9, fp, r9
+ 8000450:	ea46 0609 	orr.w	r6, r6, r9
+ 8000454:	9601      	str	r6, [sp, #4]
+ 8000456:	e7a3      	b.n	80003a0 
+ 8000458:	f5a6 1680 	sub.w	r6, r6, #1048576	; 0x100000
+ 800045c:	42b2      	cmp	r2, r6
+ 800045e:	d0e6      	beq.n	800042e 
+ 8000460:	f506 3680 	add.w	r6, r6, #65536	; 0x10000
+ 8000464:	42b2      	cmp	r2, r6
+ 8000466:	f47f af56 	bne.w	8000316 
+ 800046a:	e7e0      	b.n	800042e 
+ 800046c:	2a01      	cmp	r2, #1
+ 800046e:	bf0c      	ite	eq
+ 8000470:	6103      	streq	r3, [r0, #16]
+ 8000472:	6143      	strne	r3, [r0, #20]
+ 8000474:	f04f 0a08 	mov.w	sl, #8
+ 8000478:	e74d      	b.n	8000316 
+ 800047a:	4770      	bx	lr
+ 800047c:	f04f 0b02 	mov.w	fp, #2
+ 8000480:	9e01      	ldr	r6, [sp, #4]
+ 8000482:	fa0b f909 	lsl.w	r9, fp, r9
+ 8000486:	ea46 0609 	orr.w	r6, r6, r9
+ 800048a:	9601      	str	r6, [sp, #4]
+ 800048c:	e788      	b.n	80003a0 
+ 800048e:	bf00      	nop
+ 8000490:	40010400 	.word	0x40010400
+ 8000494:	40011000 	.word	0x40011000
+ 8000498:	40011400 	.word	0x40011400
+ 800049c:	10210000 	.word	0x10210000
+ 80004a0:	10310000 	.word	0x10310000
+ 80004a4:	40021000 	.word	0x40021000
+ 80004a8:	40010800 	.word	0x40010800
+ 80004ac:	40010c00 	.word	0x40010c00
+
+080004b0 :
+ 80004b0:	2800      	cmp	r0, #0
+ 80004b2:	f000 8097 	beq.w	80005e4 
+ 80004b6:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 80004b8:	f890 303d 	ldrb.w	r3, [r0, #61]	; 0x3d
+ 80004bc:	4604      	mov	r4, r0
+ 80004be:	f003 02ff 	and.w	r2, r3, #255	; 0xff
+ 80004c2:	2b00      	cmp	r3, #0
+ 80004c4:	f000 8087 	beq.w	80005d6 
+ 80004c8:	2324      	movs	r3, #36	; 0x24
+ 80004ca:	6822      	ldr	r2, [r4, #0]
+ 80004cc:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
+ 80004d0:	6813      	ldr	r3, [r2, #0]
+ 80004d2:	f023 0301 	bic.w	r3, r3, #1
+ 80004d6:	6013      	str	r3, [r2, #0]
+ 80004d8:	f000 ffa8 	bl	800142c 
+ 80004dc:	6862      	ldr	r2, [r4, #4]
+ 80004de:	4b4b      	ldr	r3, [pc, #300]	; (800060c )
+ 80004e0:	429a      	cmp	r2, r3
+ 80004e2:	d84b      	bhi.n	800057c 
+ 80004e4:	4b4a      	ldr	r3, [pc, #296]	; (8000610 )
+ 80004e6:	4298      	cmp	r0, r3
+ 80004e8:	d97a      	bls.n	80005e0 
+ 80004ea:	1e43      	subs	r3, r0, #1
+ 80004ec:	0052      	lsls	r2, r2, #1
+ 80004ee:	fbb3 f2f2 	udiv	r2, r3, r2
+ 80004f2:	4948      	ldr	r1, [pc, #288]	; (8000614 )
+ 80004f4:	6823      	ldr	r3, [r4, #0]
+ 80004f6:	fba1 1000 	umull	r1, r0, r1, r0
+ 80004fa:	6859      	ldr	r1, [r3, #4]
+ 80004fc:	0c80      	lsrs	r0, r0, #18
+ 80004fe:	f021 013f 	bic.w	r1, r1, #63	; 0x3f
+ 8000502:	4301      	orrs	r1, r0
+ 8000504:	6059      	str	r1, [r3, #4]
+ 8000506:	6a19      	ldr	r1, [r3, #32]
+ 8000508:	3001      	adds	r0, #1
+ 800050a:	f021 013f 	bic.w	r1, r1, #63	; 0x3f
+ 800050e:	4308      	orrs	r0, r1
+ 8000510:	6218      	str	r0, [r3, #32]
+ 8000512:	1c50      	adds	r0, r2, #1
+ 8000514:	f3c0 000b 	ubfx	r0, r0, #0, #12
+ 8000518:	2804      	cmp	r0, #4
+ 800051a:	bf38      	it	cc
+ 800051c:	2004      	movcc	r0, #4
+ 800051e:	69d9      	ldr	r1, [r3, #28]
+ 8000520:	f421 414f 	bic.w	r1, r1, #52992	; 0xcf00
+ 8000524:	f021 01ff 	bic.w	r1, r1, #255	; 0xff
+ 8000528:	2500      	movs	r5, #0
+ 800052a:	2620      	movs	r6, #32
+ 800052c:	4308      	orrs	r0, r1
+ 800052e:	61d8      	str	r0, [r3, #28]
+ 8000530:	6819      	ldr	r1, [r3, #0]
+ 8000532:	e9d4 2007 	ldrd	r2, r0, [r4, #28]
+ 8000536:	f021 01c0 	bic.w	r1, r1, #192	; 0xc0
+ 800053a:	4302      	orrs	r2, r0
+ 800053c:	430a      	orrs	r2, r1
+ 800053e:	601a      	str	r2, [r3, #0]
+ 8000540:	6899      	ldr	r1, [r3, #8]
+ 8000542:	e9d4 0203 	ldrd	r0, r2, [r4, #12]
+ 8000546:	f421 4103 	bic.w	r1, r1, #33536	; 0x8300
+ 800054a:	f021 01ff 	bic.w	r1, r1, #255	; 0xff
+ 800054e:	4302      	orrs	r2, r0
+ 8000550:	430a      	orrs	r2, r1
+ 8000552:	609a      	str	r2, [r3, #8]
+ 8000554:	68d9      	ldr	r1, [r3, #12]
+ 8000556:	e9d4 2005 	ldrd	r2, r0, [r4, #20]
+ 800055a:	f021 01ff 	bic.w	r1, r1, #255	; 0xff
+ 800055e:	4302      	orrs	r2, r0
+ 8000560:	430a      	orrs	r2, r1
+ 8000562:	60da      	str	r2, [r3, #12]
+ 8000564:	681a      	ldr	r2, [r3, #0]
+ 8000566:	4628      	mov	r0, r5
+ 8000568:	f042 0201 	orr.w	r2, r2, #1
+ 800056c:	601a      	str	r2, [r3, #0]
+ 800056e:	6425      	str	r5, [r4, #64]	; 0x40
+ 8000570:	f884 603d 	strb.w	r6, [r4, #61]	; 0x3d
+ 8000574:	6325      	str	r5, [r4, #48]	; 0x30
+ 8000576:	f884 503e 	strb.w	r5, [r4, #62]	; 0x3e
+ 800057a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 800057c:	4b26      	ldr	r3, [pc, #152]	; (8000618 )
+ 800057e:	4298      	cmp	r0, r3
+ 8000580:	d92e      	bls.n	80005e0 
+ 8000582:	f44f 7196 	mov.w	r1, #300	; 0x12c
+ 8000586:	4d23      	ldr	r5, [pc, #140]	; (8000614 )
+ 8000588:	6823      	ldr	r3, [r4, #0]
+ 800058a:	fba5 6500 	umull	r6, r5, r5, r0
+ 800058e:	0cad      	lsrs	r5, r5, #18
+ 8000590:	fb01 f105 	mul.w	r1, r1, r5
+ 8000594:	685e      	ldr	r6, [r3, #4]
+ 8000596:	4f21      	ldr	r7, [pc, #132]	; (800061c )
+ 8000598:	f026 063f 	bic.w	r6, r6, #63	; 0x3f
+ 800059c:	fba7 7101 	umull	r7, r1, r7, r1
+ 80005a0:	4335      	orrs	r5, r6
+ 80005a2:	605d      	str	r5, [r3, #4]
+ 80005a4:	6a1d      	ldr	r5, [r3, #32]
+ 80005a6:	0989      	lsrs	r1, r1, #6
+ 80005a8:	f025 053f 	bic.w	r5, r5, #63	; 0x3f
+ 80005ac:	3101      	adds	r1, #1
+ 80005ae:	4329      	orrs	r1, r5
+ 80005b0:	6219      	str	r1, [r3, #32]
+ 80005b2:	69d9      	ldr	r1, [r3, #28]
+ 80005b4:	68a5      	ldr	r5, [r4, #8]
+ 80005b6:	f421 414f 	bic.w	r1, r1, #52992	; 0xcf00
+ 80005ba:	3801      	subs	r0, #1
+ 80005bc:	f021 01ff 	bic.w	r1, r1, #255	; 0xff
+ 80005c0:	b995      	cbnz	r5, 80005e8 
+ 80005c2:	eb02 0242 	add.w	r2, r2, r2, lsl #1
+ 80005c6:	fbb0 f0f2 	udiv	r0, r0, r2
+ 80005ca:	3001      	adds	r0, #1
+ 80005cc:	f3c0 000b 	ubfx	r0, r0, #0, #12
+ 80005d0:	b9c0      	cbnz	r0, 8000604 
+ 80005d2:	2001      	movs	r0, #1
+ 80005d4:	e7a8      	b.n	8000528 
+ 80005d6:	f880 203c 	strb.w	r2, [r0, #60]	; 0x3c
+ 80005da:	f003 fb75 	bl	8003cc8 
+ 80005de:	e773      	b.n	80004c8 
+ 80005e0:	2001      	movs	r0, #1
+ 80005e2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 80005e4:	2001      	movs	r0, #1
+ 80005e6:	4770      	bx	lr
+ 80005e8:	eb02 0282 	add.w	r2, r2, r2, lsl #2
+ 80005ec:	eb02 0282 	add.w	r2, r2, r2, lsl #2
+ 80005f0:	fbb0 f0f2 	udiv	r0, r0, r2
+ 80005f4:	3001      	adds	r0, #1
+ 80005f6:	f3c0 000b 	ubfx	r0, r0, #0, #12
+ 80005fa:	2800      	cmp	r0, #0
+ 80005fc:	d0e9      	beq.n	80005d2 
+ 80005fe:	f440 4040 	orr.w	r0, r0, #49152	; 0xc000
+ 8000602:	e791      	b.n	8000528 
+ 8000604:	f440 4000 	orr.w	r0, r0, #32768	; 0x8000
+ 8000608:	e78e      	b.n	8000528 
+ 800060a:	bf00      	nop
+ 800060c:	000186a0 	.word	0x000186a0
+ 8000610:	001e847f 	.word	0x001e847f
+ 8000614:	431bde83 	.word	0x431bde83
+ 8000618:	003d08ff 	.word	0x003d08ff
+ 800061c:	10624dd3 	.word	0x10624dd3
+
+08000620 :
+ 8000620:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 8000622:	b087      	sub	sp, #28
+ 8000624:	2800      	cmp	r0, #0
+ 8000626:	d074      	beq.n	8000712 
+ 8000628:	f890 3229 	ldrb.w	r3, [r0, #553]	; 0x229
+ 800062c:	4604      	mov	r4, r0
+ 800062e:	f003 02ff 	and.w	r2, r3, #255	; 0xff
+ 8000632:	2b00      	cmp	r3, #0
+ 8000634:	d068      	beq.n	8000708 
+ 8000636:	2303      	movs	r3, #3
+ 8000638:	4626      	mov	r6, r4
+ 800063a:	f884 3229 	strb.w	r3, [r4, #553]	; 0x229
+ 800063e:	6820      	ldr	r0, [r4, #0]
+ 8000640:	f001 f948 	bl	80018d4 
+ 8000644:	f856 cb10 	ldr.w	ip, [r6], #16
+ 8000648:	466d      	mov	r5, sp
+ 800064a:	4637      	mov	r7, r6
+ 800064c:	cf0f      	ldmia	r7!, {r0, r1, r2, r3}
+ 800064e:	c50f      	stmia	r5!, {r0, r1, r2, r3}
+ 8000650:	683b      	ldr	r3, [r7, #0]
+ 8000652:	1d27      	adds	r7, r4, #4
+ 8000654:	602b      	str	r3, [r5, #0]
+ 8000656:	4660      	mov	r0, ip
+ 8000658:	e897 000e 	ldmia.w	r7, {r1, r2, r3}
+ 800065c:	f001 f928 	bl	80018b0 
+ 8000660:	4605      	mov	r5, r0
+ 8000662:	b130      	cbz	r0, 8000672 
+ 8000664:	2302      	movs	r3, #2
+ 8000666:	2501      	movs	r5, #1
+ 8000668:	f884 3229 	strb.w	r3, [r4, #553]	; 0x229
+ 800066c:	4628      	mov	r0, r5
+ 800066e:	b007      	add	sp, #28
+ 8000670:	bdf0      	pop	{r4, r5, r6, r7, pc}
+ 8000672:	4601      	mov	r1, r0
+ 8000674:	6820      	ldr	r0, [r4, #0]
+ 8000676:	f001 f937 	bl	80018e8 
+ 800067a:	f8d4 c004 	ldr.w	ip, [r4, #4]
+ 800067e:	f1bc 0f00 	cmp.w	ip, #0
+ 8000682:	d029      	beq.n	80006d8 
+ 8000684:	4628      	mov	r0, r5
+ 8000686:	f04f 0e01 	mov.w	lr, #1
+ 800068a:	462a      	mov	r2, r5
+ 800068c:	eb04 1340 	add.w	r3, r4, r0, lsl #5
+ 8000690:	1c45      	adds	r5, r0, #1
+ 8000692:	f883 0028 	strb.w	r0, [r3, #40]	; 0x28
+ 8000696:	86d8      	strh	r0, [r3, #54]	; 0x36
+ 8000698:	b2e8      	uxtb	r0, r5
+ 800069a:	4560      	cmp	r0, ip
+ 800069c:	f883 e029 	strb.w	lr, [r3, #41]	; 0x29
+ 80006a0:	f883 202b 	strb.w	r2, [r3, #43]	; 0x2b
+ 80006a4:	e9c3 220e 	strd	r2, r2, [r3, #56]	; 0x38
+ 80006a8:	641a      	str	r2, [r3, #64]	; 0x40
+ 80006aa:	d3ef      	bcc.n	800068c 
+ 80006ac:	2300      	movs	r3, #0
+ 80006ae:	4619      	mov	r1, r3
+ 80006b0:	eb04 1243 	add.w	r2, r4, r3, lsl #5
+ 80006b4:	1c5d      	adds	r5, r3, #1
+ 80006b6:	f103 000a 	add.w	r0, r3, #10
+ 80006ba:	f882 3128 	strb.w	r3, [r2, #296]	; 0x128
+ 80006be:	b2eb      	uxtb	r3, r5
+ 80006c0:	0140      	lsls	r0, r0, #5
+ 80006c2:	4563      	cmp	r3, ip
+ 80006c4:	f882 1129 	strb.w	r1, [r2, #297]	; 0x129
+ 80006c8:	f882 112b 	strb.w	r1, [r2, #299]	; 0x12b
+ 80006cc:	f8c2 1138 	str.w	r1, [r2, #312]	; 0x138
+ 80006d0:	f8c2 113c 	str.w	r1, [r2, #316]	; 0x13c
+ 80006d4:	5021      	str	r1, [r4, r0]
+ 80006d6:	d3eb      	bcc.n	80006b0 
+ 80006d8:	ce0f      	ldmia	r6!, {r0, r1, r2, r3}
+ 80006da:	466d      	mov	r5, sp
+ 80006dc:	f8d4 c000 	ldr.w	ip, [r4]
+ 80006e0:	c50f      	stmia	r5!, {r0, r1, r2, r3}
+ 80006e2:	6833      	ldr	r3, [r6, #0]
+ 80006e4:	4660      	mov	r0, ip
+ 80006e6:	602b      	str	r3, [r5, #0]
+ 80006e8:	e897 000e 	ldmia.w	r7, {r1, r2, r3}
+ 80006ec:	f001 f8fe 	bl	80018ec 
+ 80006f0:	4605      	mov	r5, r0
+ 80006f2:	2800      	cmp	r0, #0
+ 80006f4:	d1b6      	bne.n	8000664 
+ 80006f6:	2301      	movs	r3, #1
+ 80006f8:	f884 0024 	strb.w	r0, [r4, #36]	; 0x24
+ 80006fc:	6820      	ldr	r0, [r4, #0]
+ 80006fe:	f884 3229 	strb.w	r3, [r4, #553]	; 0x229
+ 8000702:	f001 fd11 	bl	8002128 
+ 8000706:	e7b1      	b.n	800066c 
+ 8000708:	f880 2228 	strb.w	r2, [r0, #552]	; 0x228
+ 800070c:	f003 fc3a 	bl	8003f84 
+ 8000710:	e791      	b.n	8000636 
+ 8000712:	2501      	movs	r5, #1
+ 8000714:	4628      	mov	r0, r5
+ 8000716:	b007      	add	sp, #28
+ 8000718:	bdf0      	pop	{r4, r5, r6, r7, pc}
+ 800071a:	bf00      	nop
+
+0800071c :
+ 800071c:	f890 3228 	ldrb.w	r3, [r0, #552]	; 0x228
+ 8000720:	2b01      	cmp	r3, #1
+ 8000722:	d010      	beq.n	8000746 
+ 8000724:	2101      	movs	r1, #1
+ 8000726:	b510      	push	{r4, lr}
+ 8000728:	4604      	mov	r4, r0
+ 800072a:	f880 1228 	strb.w	r1, [r0, #552]	; 0x228
+ 800072e:	f003 fd57 	bl	80041e0 
+ 8000732:	6820      	ldr	r0, [r4, #0]
+ 8000734:	f001 fcf6 	bl	8002124 
+ 8000738:	6820      	ldr	r0, [r4, #0]
+ 800073a:	f001 f8c1 	bl	80018c0 
+ 800073e:	2000      	movs	r0, #0
+ 8000740:	f884 0228 	strb.w	r0, [r4, #552]	; 0x228
+ 8000744:	bd10      	pop	{r4, pc}
+ 8000746:	2002      	movs	r0, #2
+ 8000748:	4770      	bx	lr
+ 800074a:	bf00      	nop
+
+0800074c :
+ 800074c:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 8000750:	4604      	mov	r4, r0
+ 8000752:	6800      	ldr	r0, [r0, #0]
+ 8000754:	f001 fcea 	bl	800212c 
+ 8000758:	0401      	lsls	r1, r0, #16
+ 800075a:	6822      	ldr	r2, [r4, #0]
+ 800075c:	d443      	bmi.n	80007e6 
+ 800075e:	4610      	mov	r0, r2
+ 8000760:	f001 fce4 	bl	800212c 
+ 8000764:	0546      	lsls	r6, r0, #21
+ 8000766:	f100 8171 	bmi.w	8000a4c 
+ 800076a:	6820      	ldr	r0, [r4, #0]
+ 800076c:	f001 fcde 	bl	800212c 
+ 8000770:	f410 4f80 	tst.w	r0, #16384	; 0x4000
+ 8000774:	6820      	ldr	r0, [r4, #0]
+ 8000776:	d007      	beq.n	8000788 
+ 8000778:	f8b0 3044 	ldrh.w	r3, [r0, #68]	; 0x44
+ 800077c:	f423 4380 	bic.w	r3, r3, #16384	; 0x4000
+ 8000780:	041b      	lsls	r3, r3, #16
+ 8000782:	0c1b      	lsrs	r3, r3, #16
+ 8000784:	f8a0 3044 	strh.w	r3, [r0, #68]	; 0x44
+ 8000788:	f001 fcd0 	bl	800212c 
+ 800078c:	f410 5f00 	tst.w	r0, #8192	; 0x2000
+ 8000790:	6820      	ldr	r0, [r4, #0]
+ 8000792:	d007      	beq.n	80007a4 
+ 8000794:	f8b0 3044 	ldrh.w	r3, [r0, #68]	; 0x44
+ 8000798:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
+ 800079c:	041b      	lsls	r3, r3, #16
+ 800079e:	0c1b      	lsrs	r3, r3, #16
+ 80007a0:	f8a0 3044 	strh.w	r3, [r0, #68]	; 0x44
+ 80007a4:	f001 fcc2 	bl	800212c 
+ 80007a8:	04c5      	lsls	r5, r0, #19
+ 80007aa:	f100 8131 	bmi.w	8000a10 
+ 80007ae:	6820      	ldr	r0, [r4, #0]
+ 80007b0:	f001 fcbc 	bl	800212c 
+ 80007b4:	0500      	lsls	r0, r0, #20
+ 80007b6:	f100 8104 	bmi.w	80009c2 
+ 80007ba:	6820      	ldr	r0, [r4, #0]
+ 80007bc:	f001 fcb6 	bl	800212c 
+ 80007c0:	0582      	lsls	r2, r0, #22
+ 80007c2:	f100 80f1 	bmi.w	80009a8 
+ 80007c6:	6820      	ldr	r0, [r4, #0]
+ 80007c8:	f001 fcb0 	bl	800212c 
+ 80007cc:	05c3      	lsls	r3, r0, #23
+ 80007ce:	d508      	bpl.n	80007e2 
+ 80007d0:	6822      	ldr	r2, [r4, #0]
+ 80007d2:	f8b2 3044 	ldrh.w	r3, [r2, #68]	; 0x44
+ 80007d6:	f423 7380 	bic.w	r3, r3, #256	; 0x100
+ 80007da:	041b      	lsls	r3, r3, #16
+ 80007dc:	0c1b      	lsrs	r3, r3, #16
+ 80007de:	f8a2 3044 	strh.w	r3, [r2, #68]	; 0x44
+ 80007e2:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 80007e6:	f8df a414 	ldr.w	sl, [pc, #1044]	; 8000bfc 
+ 80007ea:	f8df b414 	ldr.w	fp, [pc, #1044]	; 8000c00 
+ 80007ee:	f8b2 3044 	ldrh.w	r3, [r2, #68]	; 0x44
+ 80007f2:	041f      	lsls	r7, r3, #16
+ 80007f4:	d5b3      	bpl.n	800075e 
+ 80007f6:	f8b2 1044 	ldrh.w	r1, [r2, #68]	; 0x44
+ 80007fa:	b289      	uxth	r1, r1
+ 80007fc:	f011 050f 	ands.w	r5, r1, #15
+ 8000800:	d157      	bne.n	80008b2 
+ 8000802:	f011 0110 	ands.w	r1, r1, #16
+ 8000806:	8813      	ldrh	r3, [r2, #0]
+ 8000808:	f000 813e 	beq.w	8000a88 
+ 800080c:	b29b      	uxth	r3, r3
+ 800080e:	f413 6500 	ands.w	r5, r3, #2048	; 0x800
+ 8000812:	f040 817a 	bne.w	8000b0a 
+ 8000816:	041b      	lsls	r3, r3, #16
+ 8000818:	d5e9      	bpl.n	80007ee 
+ 800081a:	f640 738f 	movw	r3, #3983	; 0xf8f
+ 800081e:	8811      	ldrh	r1, [r2, #0]
+ 8000820:	400b      	ands	r3, r1
+ 8000822:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8000826:	8013      	strh	r3, [r2, #0]
+ 8000828:	f8b2 3050 	ldrh.w	r3, [r2, #80]	; 0x50
+ 800082c:	f894 1128 	ldrb.w	r1, [r4, #296]	; 0x128
+ 8000830:	eb03 03c1 	add.w	r3, r3, r1, lsl #3
+ 8000834:	eb02 0343 	add.w	r3, r2, r3, lsl #1
+ 8000838:	f8b3 340c 	ldrh.w	r3, [r3, #1036]	; 0x40c
+ 800083c:	f3c3 0309 	ubfx	r3, r3, #0, #10
+ 8000840:	f8c4 3144 	str.w	r3, [r4, #324]	; 0x144
+ 8000844:	b19b      	cbz	r3, 800086e 
+ 8000846:	f8d4 113c 	ldr.w	r1, [r4, #316]	; 0x13c
+ 800084a:	b181      	cbz	r1, 800086e 
+ 800084c:	4610      	mov	r0, r2
+ 800084e:	f8b4 212e 	ldrh.w	r2, [r4, #302]	; 0x12e
+ 8000852:	f001 fc71 	bl	8002138 
+ 8000856:	f8d4 313c 	ldr.w	r3, [r4, #316]	; 0x13c
+ 800085a:	f8d4 2144 	ldr.w	r2, [r4, #324]	; 0x144
+ 800085e:	4629      	mov	r1, r5
+ 8000860:	4413      	add	r3, r2
+ 8000862:	f8c4 313c 	str.w	r3, [r4, #316]	; 0x13c
+ 8000866:	4620      	mov	r0, r4
+ 8000868:	f003 fbb2 	bl	8003fd0 
+ 800086c:	6822      	ldr	r2, [r4, #0]
+ 800086e:	f8b2 3050 	ldrh.w	r3, [r2, #80]	; 0x50
+ 8000872:	f8d4 1138 	ldr.w	r1, [r4, #312]	; 0x138
+ 8000876:	b29b      	uxth	r3, r3
+ 8000878:	f202 400c 	addw	r0, r2, #1036	; 0x40c
+ 800087c:	2900      	cmp	r1, #0
+ 800087e:	f040 8198 	bne.w	8000bb2 
+ 8000882:	5ac1      	ldrh	r1, [r0, r3]
+ 8000884:	f421 41f8 	bic.w	r1, r1, #31744	; 0x7c00
+ 8000888:	0409      	lsls	r1, r1, #16
+ 800088a:	0c09      	lsrs	r1, r1, #16
+ 800088c:	52c1      	strh	r1, [r0, r3]
+ 800088e:	5ac1      	ldrh	r1, [r0, r3]
+ 8000890:	ea6f 4141 	mvn.w	r1, r1, lsl #17
+ 8000894:	ea6f 4151 	mvn.w	r1, r1, lsr #17
+ 8000898:	b289      	uxth	r1, r1
+ 800089a:	52c1      	strh	r1, [r0, r3]
+ 800089c:	8811      	ldrh	r1, [r2, #0]
+ 800089e:	4bd6      	ldr	r3, [pc, #856]	; (8000bf8 )
+ 80008a0:	400b      	ands	r3, r1
+ 80008a2:	f483 5340 	eor.w	r3, r3, #12288	; 0x3000
+ 80008a6:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 80008aa:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 80008ae:	8013      	strh	r3, [r2, #0]
+ 80008b0:	e79d      	b.n	80007ee 
+ 80008b2:	f832 6025 	ldrh.w	r6, [r2, r5, lsl #2]
+ 80008b6:	b2b6      	uxth	r6, r6
+ 80008b8:	0431      	lsls	r1, r6, #16
+ 80008ba:	d426      	bmi.n	800090a 
+ 80008bc:	0633      	lsls	r3, r6, #24
+ 80008be:	d596      	bpl.n	80007ee 
+ 80008c0:	f832 1025 	ldrh.w	r1, [r2, r5, lsl #2]
+ 80008c4:	eb04 1345 	add.w	r3, r4, r5, lsl #5
+ 80008c8:	ea0a 0101 	and.w	r1, sl, r1
+ 80008cc:	f441 4100 	orr.w	r1, r1, #32768	; 0x8000
+ 80008d0:	f822 1025 	strh.w	r1, [r2, r5, lsl #2]
+ 80008d4:	f8b2 1050 	ldrh.w	r1, [r2, #80]	; 0x50
+ 80008d8:	f893 5028 	ldrb.w	r5, [r3, #40]	; 0x28
+ 80008dc:	6bd8      	ldr	r0, [r3, #60]	; 0x3c
+ 80008de:	eb01 01c5 	add.w	r1, r1, r5, lsl #3
+ 80008e2:	eb02 0141 	add.w	r1, r2, r1, lsl #1
+ 80008e6:	f8b1 1404 	ldrh.w	r1, [r1, #1028]	; 0x404
+ 80008ea:	6c1d      	ldr	r5, [r3, #64]	; 0x40
+ 80008ec:	f3c1 0109 	ubfx	r1, r1, #0, #10
+ 80008f0:	1846      	adds	r6, r0, r1
+ 80008f2:	6459      	str	r1, [r3, #68]	; 0x44
+ 80008f4:	63de      	str	r6, [r3, #60]	; 0x3c
+ 80008f6:	2d00      	cmp	r5, #0
+ 80008f8:	f040 80ef 	bne.w	8000ada 
+ 80008fc:	f893 1028 	ldrb.w	r1, [r3, #40]	; 0x28
+ 8000900:	4620      	mov	r0, r4
+ 8000902:	f003 fb6d 	bl	8003fe0 
+ 8000906:	6822      	ldr	r2, [r4, #0]
+ 8000908:	e771      	b.n	80007ee 
+ 800090a:	f640 738f 	movw	r3, #3983	; 0xf8f
+ 800090e:	f832 1025 	ldrh.w	r1, [r2, r5, lsl #2]
+ 8000912:	016f      	lsls	r7, r5, #5
+ 8000914:	400b      	ands	r3, r1
+ 8000916:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 800091a:	f822 3025 	strh.w	r3, [r2, r5, lsl #2]
+ 800091e:	eb04 0907 	add.w	r9, r4, r7
+ 8000922:	f899 3134 	ldrb.w	r3, [r9, #308]	; 0x134
+ 8000926:	f502 6080 	add.w	r0, r2, #1024	; 0x400
+ 800092a:	2b00      	cmp	r3, #0
+ 800092c:	f000 810f 	beq.w	8000b4e 
+ 8000930:	f899 3128 	ldrb.w	r3, [r9, #296]	; 0x128
+ 8000934:	f832 c023 	ldrh.w	ip, [r2, r3, lsl #2]
+ 8000938:	eb02 0183 	add.w	r1, r2, r3, lsl #2
+ 800093c:	f41c 4f80 	tst.w	ip, #16384	; 0x4000
+ 8000940:	f8b2 c050 	ldrh.w	ip, [r2, #80]	; 0x50
+ 8000944:	ea4f 03c3 	mov.w	r3, r3, lsl #3
+ 8000948:	4463      	add	r3, ip
+ 800094a:	f000 811b 	beq.w	8000b84 
+ 800094e:	3302      	adds	r3, #2
+ 8000950:	f830 8013 	ldrh.w	r8, [r0, r3, lsl #1]
+ 8000954:	f3c8 0809 	ubfx	r8, r8, #0, #10
+ 8000958:	f1b8 0f00 	cmp.w	r8, #0
+ 800095c:	f040 815d 	bne.w	8000c1a 
+ 8000960:	880b      	ldrh	r3, [r1, #0]
+ 8000962:	ea0b 0303 	and.w	r3, fp, r3
+ 8000966:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 800096a:	f043 03c0 	orr.w	r3, r3, #192	; 0xc0
+ 800096e:	800b      	strh	r3, [r1, #0]
+ 8000970:	4427      	add	r7, r4
+ 8000972:	f8d7 2144 	ldr.w	r2, [r7, #324]	; 0x144
+ 8000976:	f8d7 313c 	ldr.w	r3, [r7, #316]	; 0x13c
+ 800097a:	f8d7 0140 	ldr.w	r0, [r7, #320]	; 0x140
+ 800097e:	4442      	add	r2, r8
+ 8000980:	4443      	add	r3, r8
+ 8000982:	f8c7 2144 	str.w	r2, [r7, #324]	; 0x144
+ 8000986:	f8c7 313c 	str.w	r3, [r7, #316]	; 0x13c
+ 800098a:	2800      	cmp	r0, #0
+ 800098c:	f000 80f7 	beq.w	8000b7e 
+ 8000990:	f8d7 2138 	ldr.w	r2, [r7, #312]	; 0x138
+ 8000994:	f897 1128 	ldrb.w	r1, [r7, #296]	; 0x128
+ 8000998:	4590      	cmp	r8, r2
+ 800099a:	f080 8114 	bcs.w	8000bc6 
+ 800099e:	4620      	mov	r0, r4
+ 80009a0:	f003 fb16 	bl	8003fd0 
+ 80009a4:	6822      	ldr	r2, [r4, #0]
+ 80009a6:	e789      	b.n	80008bc 
+ 80009a8:	6822      	ldr	r2, [r4, #0]
+ 80009aa:	4620      	mov	r0, r4
+ 80009ac:	f8b2 3044 	ldrh.w	r3, [r2, #68]	; 0x44
+ 80009b0:	f423 7300 	bic.w	r3, r3, #512	; 0x200
+ 80009b4:	041b      	lsls	r3, r3, #16
+ 80009b6:	0c1b      	lsrs	r3, r3, #16
+ 80009b8:	f8a2 3044 	strh.w	r3, [r2, #68]	; 0x44
+ 80009bc:	f003 fb18 	bl	8003ff0 
+ 80009c0:	e701      	b.n	80007c6 
+ 80009c2:	6823      	ldr	r3, [r4, #0]
+ 80009c4:	f8b3 2040 	ldrh.w	r2, [r3, #64]	; 0x40
+ 80009c8:	4618      	mov	r0, r3
+ 80009ca:	f042 0208 	orr.w	r2, r2, #8
+ 80009ce:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
+ 80009d2:	f8b3 2044 	ldrh.w	r2, [r3, #68]	; 0x44
+ 80009d6:	f422 6200 	bic.w	r2, r2, #2048	; 0x800
+ 80009da:	0412      	lsls	r2, r2, #16
+ 80009dc:	0c12      	lsrs	r2, r2, #16
+ 80009de:	f8a3 2044 	strh.w	r2, [r3, #68]	; 0x44
+ 80009e2:	f8b3 2040 	ldrh.w	r2, [r3, #64]	; 0x40
+ 80009e6:	f042 0204 	orr.w	r2, r2, #4
+ 80009ea:	f8a3 2040 	strh.w	r2, [r3, #64]	; 0x40
+ 80009ee:	f001 fb9d 	bl	800212c 
+ 80009f2:	04c1      	lsls	r1, r0, #19
+ 80009f4:	d508      	bpl.n	8000a08 
+ 80009f6:	6822      	ldr	r2, [r4, #0]
+ 80009f8:	f8b2 3044 	ldrh.w	r3, [r2, #68]	; 0x44
+ 80009fc:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
+ 8000a00:	041b      	lsls	r3, r3, #16
+ 8000a02:	0c1b      	lsrs	r3, r3, #16
+ 8000a04:	f8a2 3044 	strh.w	r3, [r2, #68]	; 0x44
+ 8000a08:	4620      	mov	r0, r4
+ 8000a0a:	f003 fb07 	bl	800401c 
+ 8000a0e:	e6d4      	b.n	80007ba 
+ 8000a10:	6822      	ldr	r2, [r4, #0]
+ 8000a12:	4620      	mov	r0, r4
+ 8000a14:	f8b2 3040 	ldrh.w	r3, [r2, #64]	; 0x40
+ 8000a18:	f023 0304 	bic.w	r3, r3, #4
+ 8000a1c:	041b      	lsls	r3, r3, #16
+ 8000a1e:	0c1b      	lsrs	r3, r3, #16
+ 8000a20:	f8a2 3040 	strh.w	r3, [r2, #64]	; 0x40
+ 8000a24:	f8b2 3040 	ldrh.w	r3, [r2, #64]	; 0x40
+ 8000a28:	f023 0308 	bic.w	r3, r3, #8
+ 8000a2c:	041b      	lsls	r3, r3, #16
+ 8000a2e:	0c1b      	lsrs	r3, r3, #16
+ 8000a30:	f8a2 3040 	strh.w	r3, [r2, #64]	; 0x40
+ 8000a34:	f003 fb02 	bl	800403c 
+ 8000a38:	6820      	ldr	r0, [r4, #0]
+ 8000a3a:	f8b0 3044 	ldrh.w	r3, [r0, #68]	; 0x44
+ 8000a3e:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
+ 8000a42:	041b      	lsls	r3, r3, #16
+ 8000a44:	0c1b      	lsrs	r3, r3, #16
+ 8000a46:	f8a0 3044 	strh.w	r3, [r0, #68]	; 0x44
+ 8000a4a:	e6b1      	b.n	80007b0 
+ 8000a4c:	6822      	ldr	r2, [r4, #0]
+ 8000a4e:	4620      	mov	r0, r4
+ 8000a50:	f8b2 3044 	ldrh.w	r3, [r2, #68]	; 0x44
+ 8000a54:	f423 6380 	bic.w	r3, r3, #1024	; 0x400
+ 8000a58:	041b      	lsls	r3, r3, #16
+ 8000a5a:	0c1b      	lsrs	r3, r3, #16
+ 8000a5c:	f8a2 3044 	strh.w	r3, [r2, #68]	; 0x44
+ 8000a60:	f003 faca 	bl	8003ff8 
+ 8000a64:	f894 3228 	ldrb.w	r3, [r4, #552]	; 0x228
+ 8000a68:	2b01      	cmp	r3, #1
+ 8000a6a:	f43f ae7e 	beq.w	800076a 
+ 8000a6e:	2500      	movs	r5, #0
+ 8000a70:	2301      	movs	r3, #1
+ 8000a72:	f884 5024 	strb.w	r5, [r4, #36]	; 0x24
+ 8000a76:	f884 3228 	strb.w	r3, [r4, #552]	; 0x228
+ 8000a7a:	4629      	mov	r1, r5
+ 8000a7c:	6820      	ldr	r0, [r4, #0]
+ 8000a7e:	f001 fb4b 	bl	8002118 
+ 8000a82:	f884 5228 	strb.w	r5, [r4, #552]	; 0x228
+ 8000a86:	e670      	b.n	800076a 
+ 8000a88:	ea0a 0303 	and.w	r3, sl, r3
+ 8000a8c:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 8000a90:	8013      	strh	r3, [r2, #0]
+ 8000a92:	f8b2 3050 	ldrh.w	r3, [r2, #80]	; 0x50
+ 8000a96:	f894 0028 	ldrb.w	r0, [r4, #40]	; 0x28
+ 8000a9a:	6be5      	ldr	r5, [r4, #60]	; 0x3c
+ 8000a9c:	eb03 03c0 	add.w	r3, r3, r0, lsl #3
+ 8000aa0:	eb02 0243 	add.w	r2, r2, r3, lsl #1
+ 8000aa4:	f8b2 3404 	ldrh.w	r3, [r2, #1028]	; 0x404
+ 8000aa8:	4620      	mov	r0, r4
+ 8000aaa:	f3c3 0309 	ubfx	r3, r3, #0, #10
+ 8000aae:	441d      	add	r5, r3
+ 8000ab0:	6463      	str	r3, [r4, #68]	; 0x44
+ 8000ab2:	63e5      	str	r5, [r4, #60]	; 0x3c
+ 8000ab4:	f003 fa94 	bl	8003fe0 
+ 8000ab8:	f894 3024 	ldrb.w	r3, [r4, #36]	; 0x24
+ 8000abc:	b31b      	cbz	r3, 8000b06 
+ 8000abe:	6c23      	ldr	r3, [r4, #64]	; 0x40
+ 8000ac0:	6822      	ldr	r2, [r4, #0]
+ 8000ac2:	2b00      	cmp	r3, #0
+ 8000ac4:	f47f ae93 	bne.w	80007ee 
+ 8000ac8:	f894 1024 	ldrb.w	r1, [r4, #36]	; 0x24
+ 8000acc:	f041 0180 	orr.w	r1, r1, #128	; 0x80
+ 8000ad0:	f8a2 104c 	strh.w	r1, [r2, #76]	; 0x4c
+ 8000ad4:	f884 3024 	strb.w	r3, [r4, #36]	; 0x24
+ 8000ad8:	e689      	b.n	80007ee 
+ 8000ada:	f04f 0c00 	mov.w	ip, #0
+ 8000ade:	2701      	movs	r7, #1
+ 8000ae0:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
+ 8000ae4:	4610      	mov	r0, r2
+ 8000ae6:	f003 0207 	and.w	r2, r3, #7
+ 8000aea:	0151      	lsls	r1, r2, #5
+ 8000aec:	1863      	adds	r3, r4, r1
+ 8000aee:	3128      	adds	r1, #40	; 0x28
+ 8000af0:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
+ 8000af4:	e9c3 650f 	strd	r6, r5, [r3, #60]	; 0x3c
+ 8000af8:	4421      	add	r1, r4
+ 8000afa:	f8c3 c044 	str.w	ip, [r3, #68]	; 0x44
+ 8000afe:	f883 7029 	strb.w	r7, [r3, #41]	; 0x29
+ 8000b02:	f001 f96b 	bl	8001ddc 
+ 8000b06:	6822      	ldr	r2, [r4, #0]
+ 8000b08:	e671      	b.n	80007ee 
+ 8000b0a:	f8b2 3050 	ldrh.w	r3, [r2, #80]	; 0x50
+ 8000b0e:	f894 1128 	ldrb.w	r1, [r4, #296]	; 0x128
+ 8000b12:	4610      	mov	r0, r2
+ 8000b14:	eb03 03c1 	add.w	r3, r3, r1, lsl #3
+ 8000b18:	eb02 0243 	add.w	r2, r2, r3, lsl #1
+ 8000b1c:	f8b2 340c 	ldrh.w	r3, [r2, #1036]	; 0x40c
+ 8000b20:	f504 710c 	add.w	r1, r4, #560	; 0x230
+ 8000b24:	f3c3 0309 	ubfx	r3, r3, #0, #10
+ 8000b28:	f8b4 212e 	ldrh.w	r2, [r4, #302]	; 0x12e
+ 8000b2c:	f8c4 3144 	str.w	r3, [r4, #324]	; 0x144
+ 8000b30:	f001 fb02 	bl	8002138 
+ 8000b34:	f640 738f 	movw	r3, #3983	; 0xf8f
+ 8000b38:	6822      	ldr	r2, [r4, #0]
+ 8000b3a:	4620      	mov	r0, r4
+ 8000b3c:	8811      	ldrh	r1, [r2, #0]
+ 8000b3e:	400b      	ands	r3, r1
+ 8000b40:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8000b44:	8013      	strh	r3, [r2, #0]
+ 8000b46:	f003 fa3d 	bl	8003fc4 
+ 8000b4a:	6822      	ldr	r2, [r4, #0]
+ 8000b4c:	e64f      	b.n	80007ee 
+ 8000b4e:	f8b2 3050 	ldrh.w	r3, [r2, #80]	; 0x50
+ 8000b52:	f899 1128 	ldrb.w	r1, [r9, #296]	; 0x128
+ 8000b56:	3306      	adds	r3, #6
+ 8000b58:	eb03 03c1 	add.w	r3, r3, r1, lsl #3
+ 8000b5c:	f830 8013 	ldrh.w	r8, [r0, r3, lsl #1]
+ 8000b60:	f3c8 0809 	ubfx	r8, r8, #0, #10
+ 8000b64:	f1b8 0f00 	cmp.w	r8, #0
+ 8000b68:	f43f af02 	beq.w	8000970 
+ 8000b6c:	4610      	mov	r0, r2
+ 8000b6e:	4643      	mov	r3, r8
+ 8000b70:	f8b9 212e 	ldrh.w	r2, [r9, #302]	; 0x12e
+ 8000b74:	f8d9 113c 	ldr.w	r1, [r9, #316]	; 0x13c
+ 8000b78:	f001 fade 	bl	8002138 
+ 8000b7c:	e6f8      	b.n	8000970 
+ 8000b7e:	f897 1128 	ldrb.w	r1, [r7, #296]	; 0x128
+ 8000b82:	e70c      	b.n	800099e 
+ 8000b84:	3306      	adds	r3, #6
+ 8000b86:	f830 8013 	ldrh.w	r8, [r0, r3, lsl #1]
+ 8000b8a:	f3c8 0809 	ubfx	r8, r8, #0, #10
+ 8000b8e:	f1b8 0f00 	cmp.w	r8, #0
+ 8000b92:	f43f aee5 	beq.w	8000960 
+ 8000b96:	4643      	mov	r3, r8
+ 8000b98:	4610      	mov	r0, r2
+ 8000b9a:	f8b9 2132 	ldrh.w	r2, [r9, #306]	; 0x132
+ 8000b9e:	f8d9 113c 	ldr.w	r1, [r9, #316]	; 0x13c
+ 8000ba2:	f001 fac9 	bl	8002138 
+ 8000ba6:	f899 3128 	ldrb.w	r3, [r9, #296]	; 0x128
+ 8000baa:	6821      	ldr	r1, [r4, #0]
+ 8000bac:	eb01 0183 	add.w	r1, r1, r3, lsl #2
+ 8000bb0:	e6d6      	b.n	8000960 
+ 8000bb2:	293e      	cmp	r1, #62	; 0x3e
+ 8000bb4:	d826      	bhi.n	8000c04 
+ 8000bb6:	084d      	lsrs	r5, r1, #1
+ 8000bb8:	07cf      	lsls	r7, r1, #31
+ 8000bba:	bf48      	it	mi
+ 8000bbc:	3501      	addmi	r5, #1
+ 8000bbe:	02ad      	lsls	r5, r5, #10
+ 8000bc0:	b2ad      	uxth	r5, r5
+ 8000bc2:	52c5      	strh	r5, [r0, r3]
+ 8000bc4:	e66a      	b.n	800089c 
+ 8000bc6:	f04f 0c00 	mov.w	ip, #0
+ 8000bca:	f001 0107 	and.w	r1, r1, #7
+ 8000bce:	014f      	lsls	r7, r1, #5
+ 8000bd0:	19e2      	adds	r2, r4, r7
+ 8000bd2:	f507 7794 	add.w	r7, r7, #296	; 0x128
+ 8000bd6:	f882 1128 	strb.w	r1, [r2, #296]	; 0x128
+ 8000bda:	f8c2 0140 	str.w	r0, [r2, #320]	; 0x140
+ 8000bde:	f8c2 313c 	str.w	r3, [r2, #316]	; 0x13c
+ 8000be2:	f8c2 c144 	str.w	ip, [r2, #324]	; 0x144
+ 8000be6:	f882 c129 	strb.w	ip, [r2, #297]	; 0x129
+ 8000bea:	19e1      	adds	r1, r4, r7
+ 8000bec:	6820      	ldr	r0, [r4, #0]
+ 8000bee:	f001 f8f5 	bl	8001ddc 
+ 8000bf2:	6822      	ldr	r2, [r4, #0]
+ 8000bf4:	e662      	b.n	80008bc 
+ 8000bf6:	bf00      	nop
+ 8000bf8:	ffffbf8f 	.word	0xffffbf8f
+ 8000bfc:	ffff8f0f 	.word	0xffff8f0f
+ 8000c00:	ffff8f8f 	.word	0xffff8f8f
+ 8000c04:	094d      	lsrs	r5, r1, #5
+ 8000c06:	06ce      	lsls	r6, r1, #27
+ 8000c08:	4906      	ldr	r1, [pc, #24]	; (8000c24 )
+ 8000c0a:	bf08      	it	eq
+ 8000c0c:	f105 35ff 	addeq.w	r5, r5, #4294967295	; 0xffffffff
+ 8000c10:	ea41 2585 	orr.w	r5, r1, r5, lsl #10
+ 8000c14:	b2ad      	uxth	r5, r5
+ 8000c16:	52c5      	strh	r5, [r0, r3]
+ 8000c18:	e640      	b.n	800089c 
+ 8000c1a:	4610      	mov	r0, r2
+ 8000c1c:	4643      	mov	r3, r8
+ 8000c1e:	f8b9 2130 	ldrh.w	r2, [r9, #304]	; 0x130
+ 8000c22:	e7bc      	b.n	8000b9e 
+ 8000c24:	ffff8000 	.word	0xffff8000
+
+08000c28 :
+ 8000c28:	f890 2228 	ldrb.w	r2, [r0, #552]	; 0x228
+ 8000c2c:	2a01      	cmp	r2, #1
+ 8000c2e:	d00d      	beq.n	8000c4c 
+ 8000c30:	b510      	push	{r4, lr}
+ 8000c32:	4604      	mov	r4, r0
+ 8000c34:	2201      	movs	r2, #1
+ 8000c36:	f884 1024 	strb.w	r1, [r4, #36]	; 0x24
+ 8000c3a:	f880 2228 	strb.w	r2, [r0, #552]	; 0x228
+ 8000c3e:	6800      	ldr	r0, [r0, #0]
+ 8000c40:	f001 fa6a 	bl	8002118 
+ 8000c44:	2000      	movs	r0, #0
+ 8000c46:	f884 0228 	strb.w	r0, [r4, #552]	; 0x228
+ 8000c4a:	bd10      	pop	{r4, pc}
+ 8000c4c:	2002      	movs	r0, #2
+ 8000c4e:	4770      	bx	lr
+
+08000c50 :
+ 8000c50:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8000c52:	f001 0507 	and.w	r5, r1, #7
+ 8000c56:	0609      	lsls	r1, r1, #24
+ 8000c58:	ea4f 1445 	mov.w	r4, r5, lsl #5
+ 8000c5c:	d41f      	bmi.n	8000c9e 
+ 8000c5e:	2700      	movs	r7, #0
+ 8000c60:	1906      	adds	r6, r0, r4
+ 8000c62:	f504 7194 	add.w	r1, r4, #296	; 0x128
+ 8000c66:	f886 7129 	strb.w	r7, [r6, #297]	; 0x129
+ 8000c6a:	4401      	add	r1, r0
+ 8000c6c:	784c      	ldrb	r4, [r1, #1]
+ 8000c6e:	700d      	strb	r5, [r1, #0]
+ 8000c70:	610a      	str	r2, [r1, #16]
+ 8000c72:	70cb      	strb	r3, [r1, #3]
+ 8000c74:	b104      	cbz	r4, 8000c78 
+ 8000c76:	81cd      	strh	r5, [r1, #14]
+ 8000c78:	2b02      	cmp	r3, #2
+ 8000c7a:	bf04      	itt	eq
+ 8000c7c:	2300      	moveq	r3, #0
+ 8000c7e:	710b      	strbeq	r3, [r1, #4]
+ 8000c80:	f890 3228 	ldrb.w	r3, [r0, #552]	; 0x228
+ 8000c84:	2b01      	cmp	r3, #1
+ 8000c86:	d012      	beq.n	8000cae 
+ 8000c88:	2301      	movs	r3, #1
+ 8000c8a:	4604      	mov	r4, r0
+ 8000c8c:	f880 3228 	strb.w	r3, [r0, #552]	; 0x228
+ 8000c90:	6800      	ldr	r0, [r0, #0]
+ 8000c92:	f000 fe45 	bl	8001920 
+ 8000c96:	2000      	movs	r0, #0
+ 8000c98:	f884 0228 	strb.w	r0, [r4, #552]	; 0x228
+ 8000c9c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 8000c9e:	2701      	movs	r7, #1
+ 8000ca0:	1906      	adds	r6, r0, r4
+ 8000ca2:	f104 0128 	add.w	r1, r4, #40	; 0x28
+ 8000ca6:	f886 7029 	strb.w	r7, [r6, #41]	; 0x29
+ 8000caa:	4401      	add	r1, r0
+ 8000cac:	e7de      	b.n	8000c6c 
+ 8000cae:	2002      	movs	r0, #2
+ 8000cb0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 8000cb2:	bf00      	nop
+
+08000cb4 :
+ 8000cb4:	f001 0207 	and.w	r2, r1, #7
+ 8000cb8:	0609      	lsls	r1, r1, #24
+ 8000cba:	b510      	push	{r4, lr}
+ 8000cbc:	ea4f 1342 	mov.w	r3, r2, lsl #5
+ 8000cc0:	d416      	bmi.n	8000cf0 
+ 8000cc2:	2400      	movs	r4, #0
+ 8000cc4:	18c1      	adds	r1, r0, r3
+ 8000cc6:	f503 7394 	add.w	r3, r3, #296	; 0x128
+ 8000cca:	f881 4129 	strb.w	r4, [r1, #297]	; 0x129
+ 8000cce:	18c1      	adds	r1, r0, r3
+ 8000cd0:	700a      	strb	r2, [r1, #0]
+ 8000cd2:	f890 3228 	ldrb.w	r3, [r0, #552]	; 0x228
+ 8000cd6:	2b01      	cmp	r3, #1
+ 8000cd8:	d015      	beq.n	8000d06 
+ 8000cda:	2301      	movs	r3, #1
+ 8000cdc:	4604      	mov	r4, r0
+ 8000cde:	f880 3228 	strb.w	r3, [r0, #552]	; 0x228
+ 8000ce2:	6800      	ldr	r0, [r0, #0]
+ 8000ce4:	f000 ffa4 	bl	8001c30 
+ 8000ce8:	2000      	movs	r0, #0
+ 8000cea:	f884 0228 	strb.w	r0, [r4, #552]	; 0x228
+ 8000cee:	bd10      	pop	{r4, pc}
+ 8000cf0:	2401      	movs	r4, #1
+ 8000cf2:	18c1      	adds	r1, r0, r3
+ 8000cf4:	3328      	adds	r3, #40	; 0x28
+ 8000cf6:	f881 4029 	strb.w	r4, [r1, #41]	; 0x29
+ 8000cfa:	18c1      	adds	r1, r0, r3
+ 8000cfc:	700a      	strb	r2, [r1, #0]
+ 8000cfe:	f890 3228 	ldrb.w	r3, [r0, #552]	; 0x228
+ 8000d02:	2b01      	cmp	r3, #1
+ 8000d04:	d1e9      	bne.n	8000cda 
+ 8000d06:	2002      	movs	r0, #2
+ 8000d08:	bd10      	pop	{r4, pc}
+ 8000d0a:	bf00      	nop
+
+08000d0c :
+ 8000d0c:	b570      	push	{r4, r5, r6, lr}
+ 8000d0e:	2600      	movs	r6, #0
+ 8000d10:	f001 0107 	and.w	r1, r1, #7
+ 8000d14:	014d      	lsls	r5, r1, #5
+ 8000d16:	1944      	adds	r4, r0, r5
+ 8000d18:	f505 7594 	add.w	r5, r5, #296	; 0x128
+ 8000d1c:	f884 1128 	strb.w	r1, [r4, #296]	; 0x128
+ 8000d20:	f8c4 213c 	str.w	r2, [r4, #316]	; 0x13c
+ 8000d24:	1941      	adds	r1, r0, r5
+ 8000d26:	f8c4 3140 	str.w	r3, [r4, #320]	; 0x140
+ 8000d2a:	6800      	ldr	r0, [r0, #0]
+ 8000d2c:	f8c4 6144 	str.w	r6, [r4, #324]	; 0x144
+ 8000d30:	f884 6129 	strb.w	r6, [r4, #297]	; 0x129
+ 8000d34:	f001 f852 	bl	8001ddc 
+ 8000d38:	4630      	mov	r0, r6
+ 8000d3a:	bd70      	pop	{r4, r5, r6, pc}
+
+08000d3c :
+ 8000d3c:	f001 0107 	and.w	r1, r1, #7
+ 8000d40:	eb00 1141 	add.w	r1, r0, r1, lsl #5
+ 8000d44:	f8d1 0144 	ldr.w	r0, [r1, #324]	; 0x144
+ 8000d48:	4770      	bx	lr
+ 8000d4a:	bf00      	nop
+
+08000d4c :
+ 8000d4c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8000d4e:	2600      	movs	r6, #0
+ 8000d50:	2701      	movs	r7, #1
+ 8000d52:	f001 0107 	and.w	r1, r1, #7
+ 8000d56:	014d      	lsls	r5, r1, #5
+ 8000d58:	1944      	adds	r4, r0, r5
+ 8000d5a:	3528      	adds	r5, #40	; 0x28
+ 8000d5c:	f884 1028 	strb.w	r1, [r4, #40]	; 0x28
+ 8000d60:	e9c4 230f 	strd	r2, r3, [r4, #60]	; 0x3c
+ 8000d64:	1941      	adds	r1, r0, r5
+ 8000d66:	6800      	ldr	r0, [r0, #0]
+ 8000d68:	f884 7029 	strb.w	r7, [r4, #41]	; 0x29
+ 8000d6c:	6466      	str	r6, [r4, #68]	; 0x44
+ 8000d6e:	f001 f835 	bl	8001ddc 
+ 8000d72:	4630      	mov	r0, r6
+ 8000d74:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 8000d76:	bf00      	nop
+
+08000d78 :
+ 8000d78:	b538      	push	{r3, r4, r5, lr}
+ 8000d7a:	6843      	ldr	r3, [r0, #4]
+ 8000d7c:	f001 0507 	and.w	r5, r1, #7
+ 8000d80:	429d      	cmp	r5, r3
+ 8000d82:	d81b      	bhi.n	8000dbc 
+ 8000d84:	060b      	lsls	r3, r1, #24
+ 8000d86:	d41b      	bmi.n	8000dc0 
+ 8000d88:	2400      	movs	r4, #0
+ 8000d8a:	0149      	lsls	r1, r1, #5
+ 8000d8c:	1843      	adds	r3, r0, r1
+ 8000d8e:	f883 4129 	strb.w	r4, [r3, #297]	; 0x129
+ 8000d92:	2301      	movs	r3, #1
+ 8000d94:	f501 7294 	add.w	r2, r1, #296	; 0x128
+ 8000d98:	1881      	adds	r1, r0, r2
+ 8000d9a:	700d      	strb	r5, [r1, #0]
+ 8000d9c:	708b      	strb	r3, [r1, #2]
+ 8000d9e:	f890 2228 	ldrb.w	r2, [r0, #552]	; 0x228
+ 8000da2:	429a      	cmp	r2, r3
+ 8000da4:	d01b      	beq.n	8000dde 
+ 8000da6:	4604      	mov	r4, r0
+ 8000da8:	f880 3228 	strb.w	r3, [r0, #552]	; 0x228
+ 8000dac:	6800      	ldr	r0, [r0, #0]
+ 8000dae:	f001 f93d 	bl	800202c 
+ 8000db2:	b1b5      	cbz	r5, 8000de2 
+ 8000db4:	2000      	movs	r0, #0
+ 8000db6:	f884 0228 	strb.w	r0, [r4, #552]	; 0x228
+ 8000dba:	bd38      	pop	{r3, r4, r5, pc}
+ 8000dbc:	2001      	movs	r0, #1
+ 8000dbe:	bd38      	pop	{r3, r4, r5, pc}
+ 8000dc0:	2201      	movs	r2, #1
+ 8000dc2:	016b      	lsls	r3, r5, #5
+ 8000dc4:	f103 0128 	add.w	r1, r3, #40	; 0x28
+ 8000dc8:	4403      	add	r3, r0
+ 8000dca:	f883 2029 	strb.w	r2, [r3, #41]	; 0x29
+ 8000dce:	2301      	movs	r3, #1
+ 8000dd0:	4401      	add	r1, r0
+ 8000dd2:	700d      	strb	r5, [r1, #0]
+ 8000dd4:	708b      	strb	r3, [r1, #2]
+ 8000dd6:	f890 2228 	ldrb.w	r2, [r0, #552]	; 0x228
+ 8000dda:	429a      	cmp	r2, r3
+ 8000ddc:	d1e3      	bne.n	8000da6 
+ 8000dde:	2002      	movs	r0, #2
+ 8000de0:	bd38      	pop	{r3, r4, r5, pc}
+ 8000de2:	f504 710c 	add.w	r1, r4, #560	; 0x230
+ 8000de6:	6820      	ldr	r0, [r4, #0]
+ 8000de8:	f001 f9a4 	bl	8002134 
+ 8000dec:	e7e2      	b.n	8000db4 
+ 8000dee:	bf00      	nop
+
+08000df0 :
+ 8000df0:	b538      	push	{r3, r4, r5, lr}
+ 8000df2:	6843      	ldr	r3, [r0, #4]
+ 8000df4:	f001 020f 	and.w	r2, r1, #15
+ 8000df8:	429a      	cmp	r2, r3
+ 8000dfa:	d81e      	bhi.n	8000e3a 
+ 8000dfc:	f001 0207 	and.w	r2, r1, #7
+ 8000e00:	0609      	lsls	r1, r1, #24
+ 8000e02:	ea4f 1342 	mov.w	r3, r2, lsl #5
+ 8000e06:	d41a      	bmi.n	8000e3e 
+ 8000e08:	2500      	movs	r5, #0
+ 8000e0a:	18c4      	adds	r4, r0, r3
+ 8000e0c:	f884 5129 	strb.w	r5, [r4, #297]	; 0x129
+ 8000e10:	2500      	movs	r5, #0
+ 8000e12:	f503 7194 	add.w	r1, r3, #296	; 0x128
+ 8000e16:	4401      	add	r1, r0
+ 8000e18:	700a      	strb	r2, [r1, #0]
+ 8000e1a:	708d      	strb	r5, [r1, #2]
+ 8000e1c:	f890 3228 	ldrb.w	r3, [r0, #552]	; 0x228
+ 8000e20:	2b01      	cmp	r3, #1
+ 8000e22:	d01a      	beq.n	8000e5a 
+ 8000e24:	2301      	movs	r3, #1
+ 8000e26:	4604      	mov	r4, r0
+ 8000e28:	f880 3228 	strb.w	r3, [r0, #552]	; 0x228
+ 8000e2c:	6800      	ldr	r0, [r0, #0]
+ 8000e2e:	f001 f91f 	bl	8002070 
+ 8000e32:	f884 5228 	strb.w	r5, [r4, #552]	; 0x228
+ 8000e36:	4628      	mov	r0, r5
+ 8000e38:	bd38      	pop	{r3, r4, r5, pc}
+ 8000e3a:	2001      	movs	r0, #1
+ 8000e3c:	bd38      	pop	{r3, r4, r5, pc}
+ 8000e3e:	2501      	movs	r5, #1
+ 8000e40:	18c4      	adds	r4, r0, r3
+ 8000e42:	f884 5029 	strb.w	r5, [r4, #41]	; 0x29
+ 8000e46:	2500      	movs	r5, #0
+ 8000e48:	f103 0128 	add.w	r1, r3, #40	; 0x28
+ 8000e4c:	4401      	add	r1, r0
+ 8000e4e:	700a      	strb	r2, [r1, #0]
+ 8000e50:	708d      	strb	r5, [r1, #2]
+ 8000e52:	f890 3228 	ldrb.w	r3, [r0, #552]	; 0x228
+ 8000e56:	2b01      	cmp	r3, #1
+ 8000e58:	d1e4      	bne.n	8000e24 
+ 8000e5a:	2002      	movs	r0, #2
+ 8000e5c:	bd38      	pop	{r3, r4, r5, pc}
+ 8000e5e:	bf00      	nop
+
+08000e60 :
+ 8000e60:	f011 0f80 	tst.w	r1, #128	; 0x80
+ 8000e64:	d00d      	beq.n	8000e82 
+ 8000e66:	f001 0107 	and.w	r1, r1, #7
+ 8000e6a:	eb00 1041 	add.w	r0, r0, r1, lsl #5
+ 8000e6e:	3028      	adds	r0, #40	; 0x28
+ 8000e70:	b299      	uxth	r1, r3
+ 8000e72:	b16a      	cbz	r2, 8000e90 
+ 8000e74:	2201      	movs	r2, #1
+ 8000e76:	0c1b      	lsrs	r3, r3, #16
+ 8000e78:	8143      	strh	r3, [r0, #10]
+ 8000e7a:	8101      	strh	r1, [r0, #8]
+ 8000e7c:	7302      	strb	r2, [r0, #12]
+ 8000e7e:	2000      	movs	r0, #0
+ 8000e80:	4770      	bx	lr
+ 8000e82:	eb00 1041 	add.w	r0, r0, r1, lsl #5
+ 8000e86:	f500 7094 	add.w	r0, r0, #296	; 0x128
+ 8000e8a:	b299      	uxth	r1, r3
+ 8000e8c:	2a00      	cmp	r2, #0
+ 8000e8e:	d1f1      	bne.n	8000e74 
+ 8000e90:	80c1      	strh	r1, [r0, #6]
+ 8000e92:	7302      	strb	r2, [r0, #12]
+ 8000e94:	2000      	movs	r0, #0
+ 8000e96:	4770      	bx	lr
+
+08000e98 :
+ 8000e98:	2201      	movs	r2, #1
+ 8000e9a:	4b01      	ldr	r3, [pc, #4]	; (8000ea0 )
+ 8000e9c:	601a      	str	r2, [r3, #0]
+ 8000e9e:	4770      	bx	lr
+ 8000ea0:	420e0020 	.word	0x420e0020
+
+08000ea4 :
+ 8000ea4:	2800      	cmp	r0, #0
+ 8000ea6:	f000 8155 	beq.w	8001154 
+ 8000eaa:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 8000eae:	6803      	ldr	r3, [r0, #0]
+ 8000eb0:	b082      	sub	sp, #8
+ 8000eb2:	07dd      	lsls	r5, r3, #31
+ 8000eb4:	4604      	mov	r4, r0
+ 8000eb6:	d535      	bpl.n	8000f24 
+ 8000eb8:	49a8      	ldr	r1, [pc, #672]	; (800115c )
+ 8000eba:	684a      	ldr	r2, [r1, #4]
+ 8000ebc:	f002 020c 	and.w	r2, r2, #12
+ 8000ec0:	2a04      	cmp	r2, #4
+ 8000ec2:	f000 8105 	beq.w	80010d0 
+ 8000ec6:	684a      	ldr	r2, [r1, #4]
+ 8000ec8:	f002 020c 	and.w	r2, r2, #12
+ 8000ecc:	2a08      	cmp	r2, #8
+ 8000ece:	f000 80fb 	beq.w	80010c8 
+ 8000ed2:	6863      	ldr	r3, [r4, #4]
+ 8000ed4:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
+ 8000ed8:	d010      	beq.n	8000efc 
+ 8000eda:	2b00      	cmp	r3, #0
+ 8000edc:	f000 8120 	beq.w	8001120 
+ 8000ee0:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
+ 8000ee4:	f000 8178 	beq.w	80011d8 
+ 8000ee8:	4b9c      	ldr	r3, [pc, #624]	; (800115c )
+ 8000eea:	681a      	ldr	r2, [r3, #0]
+ 8000eec:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
+ 8000ef0:	601a      	str	r2, [r3, #0]
+ 8000ef2:	681a      	ldr	r2, [r3, #0]
+ 8000ef4:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
+ 8000ef8:	601a      	str	r2, [r3, #0]
+ 8000efa:	e004      	b.n	8000f06 
+ 8000efc:	4a97      	ldr	r2, [pc, #604]	; (800115c )
+ 8000efe:	6813      	ldr	r3, [r2, #0]
+ 8000f00:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
+ 8000f04:	6013      	str	r3, [r2, #0]
+ 8000f06:	f7ff f965 	bl	80001d4 
+ 8000f0a:	4d94      	ldr	r5, [pc, #592]	; (800115c )
+ 8000f0c:	4606      	mov	r6, r0
+ 8000f0e:	e005      	b.n	8000f1c 
+ 8000f10:	f7ff f960 	bl	80001d4 
+ 8000f14:	1b80      	subs	r0, r0, r6
+ 8000f16:	2864      	cmp	r0, #100	; 0x64
+ 8000f18:	f200 80f5 	bhi.w	8001106 
+ 8000f1c:	682b      	ldr	r3, [r5, #0]
+ 8000f1e:	039a      	lsls	r2, r3, #14
+ 8000f20:	d5f6      	bpl.n	8000f10 
+ 8000f22:	6823      	ldr	r3, [r4, #0]
+ 8000f24:	079f      	lsls	r7, r3, #30
+ 8000f26:	d44d      	bmi.n	8000fc4 
+ 8000f28:	071a      	lsls	r2, r3, #28
+ 8000f2a:	d522      	bpl.n	8000f72 
+ 8000f2c:	69a3      	ldr	r3, [r4, #24]
+ 8000f2e:	2b00      	cmp	r3, #0
+ 8000f30:	f000 80ba 	beq.w	80010a8 
+ 8000f34:	2201      	movs	r2, #1
+ 8000f36:	4b8a      	ldr	r3, [pc, #552]	; (8001160 )
+ 8000f38:	4d88      	ldr	r5, [pc, #544]	; (800115c )
+ 8000f3a:	601a      	str	r2, [r3, #0]
+ 8000f3c:	f7ff f94a 	bl	80001d4 
+ 8000f40:	4606      	mov	r6, r0
+ 8000f42:	e005      	b.n	8000f50 
+ 8000f44:	f7ff f946 	bl	80001d4 
+ 8000f48:	1b80      	subs	r0, r0, r6
+ 8000f4a:	2802      	cmp	r0, #2
+ 8000f4c:	f200 80db 	bhi.w	8001106 
+ 8000f50:	6a6b      	ldr	r3, [r5, #36]	; 0x24
+ 8000f52:	079b      	lsls	r3, r3, #30
+ 8000f54:	d5f6      	bpl.n	8000f44 
+ 8000f56:	4b83      	ldr	r3, [pc, #524]	; (8001164 )
+ 8000f58:	4a83      	ldr	r2, [pc, #524]	; (8001168 )
+ 8000f5a:	681b      	ldr	r3, [r3, #0]
+ 8000f5c:	fba2 2303 	umull	r2, r3, r2, r3
+ 8000f60:	0a5b      	lsrs	r3, r3, #9
+ 8000f62:	9301      	str	r3, [sp, #4]
+ 8000f64:	bf00      	nop
+ 8000f66:	9b01      	ldr	r3, [sp, #4]
+ 8000f68:	1e5a      	subs	r2, r3, #1
+ 8000f6a:	9201      	str	r2, [sp, #4]
+ 8000f6c:	2b00      	cmp	r3, #0
+ 8000f6e:	d1f9      	bne.n	8000f64 
+ 8000f70:	6823      	ldr	r3, [r4, #0]
+ 8000f72:	075d      	lsls	r5, r3, #29
+ 8000f74:	d569      	bpl.n	800104a 
+ 8000f76:	4b79      	ldr	r3, [pc, #484]	; (800115c )
+ 8000f78:	69da      	ldr	r2, [r3, #28]
+ 8000f7a:	00d0      	lsls	r0, r2, #3
+ 8000f7c:	f100 80ec 	bmi.w	8001158 
+ 8000f80:	2501      	movs	r5, #1
+ 8000f82:	69da      	ldr	r2, [r3, #28]
+ 8000f84:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
+ 8000f88:	61da      	str	r2, [r3, #28]
+ 8000f8a:	69db      	ldr	r3, [r3, #28]
+ 8000f8c:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 8000f90:	9300      	str	r3, [sp, #0]
+ 8000f92:	9b00      	ldr	r3, [sp, #0]
+ 8000f94:	4b75      	ldr	r3, [pc, #468]	; (800116c )
+ 8000f96:	681a      	ldr	r2, [r3, #0]
+ 8000f98:	05d1      	lsls	r1, r2, #23
+ 8000f9a:	f140 80a3 	bpl.w	80010e4 
+ 8000f9e:	68e3      	ldr	r3, [r4, #12]
+ 8000fa0:	2b01      	cmp	r3, #1
+ 8000fa2:	d037      	beq.n	8001014 
+ 8000fa4:	2b00      	cmp	r3, #0
+ 8000fa6:	f000 80e7 	beq.w	8001178 
+ 8000faa:	2b05      	cmp	r3, #5
+ 8000fac:	4b6b      	ldr	r3, [pc, #428]	; (800115c )
+ 8000fae:	6a1a      	ldr	r2, [r3, #32]
+ 8000fb0:	f000 811f 	beq.w	80011f2 
+ 8000fb4:	f022 0201 	bic.w	r2, r2, #1
+ 8000fb8:	621a      	str	r2, [r3, #32]
+ 8000fba:	6a1a      	ldr	r2, [r3, #32]
+ 8000fbc:	f022 0204 	bic.w	r2, r2, #4
+ 8000fc0:	621a      	str	r2, [r3, #32]
+ 8000fc2:	e02c      	b.n	800101e 
+ 8000fc4:	4a65      	ldr	r2, [pc, #404]	; (800115c )
+ 8000fc6:	6851      	ldr	r1, [r2, #4]
+ 8000fc8:	f011 0f0c 	tst.w	r1, #12
+ 8000fcc:	d061      	beq.n	8001092 
+ 8000fce:	6851      	ldr	r1, [r2, #4]
+ 8000fd0:	f001 010c 	and.w	r1, r1, #12
+ 8000fd4:	2908      	cmp	r1, #8
+ 8000fd6:	d059      	beq.n	800108c 
+ 8000fd8:	6923      	ldr	r3, [r4, #16]
+ 8000fda:	2b00      	cmp	r3, #0
+ 8000fdc:	f000 80eb 	beq.w	80011b6 
+ 8000fe0:	2201      	movs	r2, #1
+ 8000fe2:	4b63      	ldr	r3, [pc, #396]	; (8001170 )
+ 8000fe4:	4d5d      	ldr	r5, [pc, #372]	; (800115c )
+ 8000fe6:	601a      	str	r2, [r3, #0]
+ 8000fe8:	f7ff f8f4 	bl	80001d4 
+ 8000fec:	4606      	mov	r6, r0
+ 8000fee:	e005      	b.n	8000ffc 
+ 8000ff0:	f7ff f8f0 	bl	80001d4 
+ 8000ff4:	1b80      	subs	r0, r0, r6
+ 8000ff6:	2802      	cmp	r0, #2
+ 8000ff8:	f200 8085 	bhi.w	8001106 
+ 8000ffc:	682b      	ldr	r3, [r5, #0]
+ 8000ffe:	0798      	lsls	r0, r3, #30
+ 8001000:	d5f6      	bpl.n	8000ff0 
+ 8001002:	682b      	ldr	r3, [r5, #0]
+ 8001004:	6962      	ldr	r2, [r4, #20]
+ 8001006:	f023 03f8 	bic.w	r3, r3, #248	; 0xf8
+ 800100a:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
+ 800100e:	602b      	str	r3, [r5, #0]
+ 8001010:	6823      	ldr	r3, [r4, #0]
+ 8001012:	e789      	b.n	8000f28 
+ 8001014:	4a51      	ldr	r2, [pc, #324]	; (800115c )
+ 8001016:	6a13      	ldr	r3, [r2, #32]
+ 8001018:	f043 0301 	orr.w	r3, r3, #1
+ 800101c:	6213      	str	r3, [r2, #32]
+ 800101e:	f7ff f8d9 	bl	80001d4 
+ 8001022:	4e4e      	ldr	r6, [pc, #312]	; (800115c )
+ 8001024:	4680      	mov	r8, r0
+ 8001026:	f241 3788 	movw	r7, #5000	; 0x1388
+ 800102a:	e005      	b.n	8001038 
+ 800102c:	f7ff f8d2 	bl	80001d4 
+ 8001030:	eba0 0008 	sub.w	r0, r0, r8
+ 8001034:	42b8      	cmp	r0, r7
+ 8001036:	d866      	bhi.n	8001106 
+ 8001038:	6a33      	ldr	r3, [r6, #32]
+ 800103a:	079b      	lsls	r3, r3, #30
+ 800103c:	d5f6      	bpl.n	800102c 
+ 800103e:	b125      	cbz	r5, 800104a 
+ 8001040:	4a46      	ldr	r2, [pc, #280]	; (800115c )
+ 8001042:	69d3      	ldr	r3, [r2, #28]
+ 8001044:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
+ 8001048:	61d3      	str	r3, [r2, #28]
+ 800104a:	69e0      	ldr	r0, [r4, #28]
+ 800104c:	b1d0      	cbz	r0, 8001084 
+ 800104e:	4d43      	ldr	r5, [pc, #268]	; (800115c )
+ 8001050:	686a      	ldr	r2, [r5, #4]
+ 8001052:	f002 020c 	and.w	r2, r2, #12
+ 8001056:	2a08      	cmp	r2, #8
+ 8001058:	f000 80d3 	beq.w	8001202 
+ 800105c:	2802      	cmp	r0, #2
+ 800105e:	f04f 0100 	mov.w	r1, #0
+ 8001062:	4a44      	ldr	r2, [pc, #272]	; (8001174 )
+ 8001064:	f000 80de 	beq.w	8001224 
+ 8001068:	6011      	str	r1, [r2, #0]
+ 800106a:	f7ff f8b3 	bl	80001d4 
+ 800106e:	462c      	mov	r4, r5
+ 8001070:	4605      	mov	r5, r0
+ 8001072:	e004      	b.n	800107e 
+ 8001074:	f7ff f8ae 	bl	80001d4 
+ 8001078:	1b40      	subs	r0, r0, r5
+ 800107a:	2802      	cmp	r0, #2
+ 800107c:	d843      	bhi.n	8001106 
+ 800107e:	6823      	ldr	r3, [r4, #0]
+ 8001080:	019b      	lsls	r3, r3, #6
+ 8001082:	d4f7      	bmi.n	8001074 
+ 8001084:	2000      	movs	r0, #0
+ 8001086:	b002      	add	sp, #8
+ 8001088:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 800108c:	6852      	ldr	r2, [r2, #4]
+ 800108e:	03d6      	lsls	r6, r2, #15
+ 8001090:	d4a2      	bmi.n	8000fd8 
+ 8001092:	4a32      	ldr	r2, [pc, #200]	; (800115c )
+ 8001094:	6812      	ldr	r2, [r2, #0]
+ 8001096:	0795      	lsls	r5, r2, #30
+ 8001098:	d539      	bpl.n	800110e 
+ 800109a:	6922      	ldr	r2, [r4, #16]
+ 800109c:	2a01      	cmp	r2, #1
+ 800109e:	d036      	beq.n	800110e 
+ 80010a0:	2001      	movs	r0, #1
+ 80010a2:	b002      	add	sp, #8
+ 80010a4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 80010a8:	4a2d      	ldr	r2, [pc, #180]	; (8001160 )
+ 80010aa:	4d2c      	ldr	r5, [pc, #176]	; (800115c )
+ 80010ac:	6013      	str	r3, [r2, #0]
+ 80010ae:	f7ff f891 	bl	80001d4 
+ 80010b2:	4606      	mov	r6, r0
+ 80010b4:	e004      	b.n	80010c0 
+ 80010b6:	f7ff f88d 	bl	80001d4 
+ 80010ba:	1b80      	subs	r0, r0, r6
+ 80010bc:	2802      	cmp	r0, #2
+ 80010be:	d822      	bhi.n	8001106 
+ 80010c0:	6a6b      	ldr	r3, [r5, #36]	; 0x24
+ 80010c2:	079f      	lsls	r7, r3, #30
+ 80010c4:	d4f7      	bmi.n	80010b6 
+ 80010c6:	e753      	b.n	8000f70 
+ 80010c8:	684a      	ldr	r2, [r1, #4]
+ 80010ca:	03d0      	lsls	r0, r2, #15
+ 80010cc:	f57f af01 	bpl.w	8000ed2 
+ 80010d0:	4a22      	ldr	r2, [pc, #136]	; (800115c )
+ 80010d2:	6812      	ldr	r2, [r2, #0]
+ 80010d4:	0391      	lsls	r1, r2, #14
+ 80010d6:	f57f af25 	bpl.w	8000f24 
+ 80010da:	6862      	ldr	r2, [r4, #4]
+ 80010dc:	2a00      	cmp	r2, #0
+ 80010de:	f47f af21 	bne.w	8000f24 
+ 80010e2:	e7dd      	b.n	80010a0 
+ 80010e4:	681a      	ldr	r2, [r3, #0]
+ 80010e6:	461e      	mov	r6, r3
+ 80010e8:	f442 7280 	orr.w	r2, r2, #256	; 0x100
+ 80010ec:	601a      	str	r2, [r3, #0]
+ 80010ee:	f7ff f871 	bl	80001d4 
+ 80010f2:	4607      	mov	r7, r0
+ 80010f4:	6833      	ldr	r3, [r6, #0]
+ 80010f6:	05da      	lsls	r2, r3, #23
+ 80010f8:	f53f af51 	bmi.w	8000f9e 
+ 80010fc:	f7ff f86a 	bl	80001d4 
+ 8001100:	1bc0      	subs	r0, r0, r7
+ 8001102:	2864      	cmp	r0, #100	; 0x64
+ 8001104:	d9f6      	bls.n	80010f4 
+ 8001106:	2003      	movs	r0, #3
+ 8001108:	b002      	add	sp, #8
+ 800110a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 800110e:	4913      	ldr	r1, [pc, #76]	; (800115c )
+ 8001110:	6960      	ldr	r0, [r4, #20]
+ 8001112:	680a      	ldr	r2, [r1, #0]
+ 8001114:	f022 02f8 	bic.w	r2, r2, #248	; 0xf8
+ 8001118:	ea42 02c0 	orr.w	r2, r2, r0, lsl #3
+ 800111c:	600a      	str	r2, [r1, #0]
+ 800111e:	e703      	b.n	8000f28 
+ 8001120:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
+ 8001124:	f503 3304 	add.w	r3, r3, #135168	; 0x21000
+ 8001128:	681a      	ldr	r2, [r3, #0]
+ 800112a:	461d      	mov	r5, r3
+ 800112c:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
+ 8001130:	601a      	str	r2, [r3, #0]
+ 8001132:	681a      	ldr	r2, [r3, #0]
+ 8001134:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
+ 8001138:	601a      	str	r2, [r3, #0]
+ 800113a:	f7ff f84b 	bl	80001d4 
+ 800113e:	4606      	mov	r6, r0
+ 8001140:	e004      	b.n	800114c 
+ 8001142:	f7ff f847 	bl	80001d4 
+ 8001146:	1b80      	subs	r0, r0, r6
+ 8001148:	2864      	cmp	r0, #100	; 0x64
+ 800114a:	d8dc      	bhi.n	8001106 
+ 800114c:	682b      	ldr	r3, [r5, #0]
+ 800114e:	039b      	lsls	r3, r3, #14
+ 8001150:	d4f7      	bmi.n	8001142 
+ 8001152:	e6e6      	b.n	8000f22 
+ 8001154:	2001      	movs	r0, #1
+ 8001156:	4770      	bx	lr
+ 8001158:	2500      	movs	r5, #0
+ 800115a:	e71b      	b.n	8000f94 
+ 800115c:	40021000 	.word	0x40021000
+ 8001160:	42420480 	.word	0x42420480
+ 8001164:	2000011c 	.word	0x2000011c
+ 8001168:	10624dd3 	.word	0x10624dd3
+ 800116c:	40007000 	.word	0x40007000
+ 8001170:	42420000 	.word	0x42420000
+ 8001174:	42420060 	.word	0x42420060
+ 8001178:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
+ 800117c:	f503 3304 	add.w	r3, r3, #135168	; 0x21000
+ 8001180:	6a1a      	ldr	r2, [r3, #32]
+ 8001182:	461e      	mov	r6, r3
+ 8001184:	f022 0201 	bic.w	r2, r2, #1
+ 8001188:	621a      	str	r2, [r3, #32]
+ 800118a:	6a1a      	ldr	r2, [r3, #32]
+ 800118c:	f241 3888 	movw	r8, #5000	; 0x1388
+ 8001190:	f022 0204 	bic.w	r2, r2, #4
+ 8001194:	621a      	str	r2, [r3, #32]
+ 8001196:	f7ff f81d 	bl	80001d4 
+ 800119a:	4607      	mov	r7, r0
+ 800119c:	e004      	b.n	80011a8 
+ 800119e:	f7ff f819 	bl	80001d4 
+ 80011a2:	1bc0      	subs	r0, r0, r7
+ 80011a4:	4540      	cmp	r0, r8
+ 80011a6:	d8ae      	bhi.n	8001106 
+ 80011a8:	6a33      	ldr	r3, [r6, #32]
+ 80011aa:	0798      	lsls	r0, r3, #30
+ 80011ac:	d4f7      	bmi.n	800119e 
+ 80011ae:	2d00      	cmp	r5, #0
+ 80011b0:	f43f af4b 	beq.w	800104a 
+ 80011b4:	e744      	b.n	8001040 
+ 80011b6:	4a34      	ldr	r2, [pc, #208]	; (8001288 )
+ 80011b8:	4d34      	ldr	r5, [pc, #208]	; (800128c )
+ 80011ba:	6013      	str	r3, [r2, #0]
+ 80011bc:	f7ff f80a 	bl	80001d4 
+ 80011c0:	4606      	mov	r6, r0
+ 80011c2:	e004      	b.n	80011ce 
+ 80011c4:	f7ff f806 	bl	80001d4 
+ 80011c8:	1b80      	subs	r0, r0, r6
+ 80011ca:	2802      	cmp	r0, #2
+ 80011cc:	d89b      	bhi.n	8001106 
+ 80011ce:	682b      	ldr	r3, [r5, #0]
+ 80011d0:	0799      	lsls	r1, r3, #30
+ 80011d2:	d4f7      	bmi.n	80011c4 
+ 80011d4:	6823      	ldr	r3, [r4, #0]
+ 80011d6:	e6a7      	b.n	8000f28 
+ 80011d8:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
+ 80011dc:	f5a3 333c 	sub.w	r3, r3, #192512	; 0x2f000
+ 80011e0:	681a      	ldr	r2, [r3, #0]
+ 80011e2:	f442 2280 	orr.w	r2, r2, #262144	; 0x40000
+ 80011e6:	601a      	str	r2, [r3, #0]
+ 80011e8:	681a      	ldr	r2, [r3, #0]
+ 80011ea:	f442 3280 	orr.w	r2, r2, #65536	; 0x10000
+ 80011ee:	601a      	str	r2, [r3, #0]
+ 80011f0:	e689      	b.n	8000f06 
+ 80011f2:	f042 0204 	orr.w	r2, r2, #4
+ 80011f6:	621a      	str	r2, [r3, #32]
+ 80011f8:	6a1a      	ldr	r2, [r3, #32]
+ 80011fa:	f042 0201 	orr.w	r2, r2, #1
+ 80011fe:	621a      	str	r2, [r3, #32]
+ 8001200:	e70d      	b.n	800101e 
+ 8001202:	2801      	cmp	r0, #1
+ 8001204:	f43f af4d 	beq.w	80010a2 
+ 8001208:	686b      	ldr	r3, [r5, #4]
+ 800120a:	6a22      	ldr	r2, [r4, #32]
+ 800120c:	f403 3180 	and.w	r1, r3, #65536	; 0x10000
+ 8001210:	4291      	cmp	r1, r2
+ 8001212:	f47f af45 	bne.w	80010a0 
+ 8001216:	6a60      	ldr	r0, [r4, #36]	; 0x24
+ 8001218:	f403 1370 	and.w	r3, r3, #3932160	; 0x3c0000
+ 800121c:	1a18      	subs	r0, r3, r0
+ 800121e:	bf18      	it	ne
+ 8001220:	2001      	movne	r0, #1
+ 8001222:	e73e      	b.n	80010a2 
+ 8001224:	6011      	str	r1, [r2, #0]
+ 8001226:	f7fe ffd5 	bl	80001d4 
+ 800122a:	4606      	mov	r6, r0
+ 800122c:	e005      	b.n	800123a 
+ 800122e:	f7fe ffd1 	bl	80001d4 
+ 8001232:	1b80      	subs	r0, r0, r6
+ 8001234:	2802      	cmp	r0, #2
+ 8001236:	f63f af66 	bhi.w	8001106 
+ 800123a:	682b      	ldr	r3, [r5, #0]
+ 800123c:	0199      	lsls	r1, r3, #6
+ 800123e:	d4f6      	bmi.n	800122e 
+ 8001240:	6a22      	ldr	r2, [r4, #32]
+ 8001242:	f5b2 3f80 	cmp.w	r2, #65536	; 0x10000
+ 8001246:	d105      	bne.n	8001254 
+ 8001248:	686b      	ldr	r3, [r5, #4]
+ 800124a:	68a1      	ldr	r1, [r4, #8]
+ 800124c:	f423 3300 	bic.w	r3, r3, #131072	; 0x20000
+ 8001250:	430b      	orrs	r3, r1
+ 8001252:	606b      	str	r3, [r5, #4]
+ 8001254:	2501      	movs	r5, #1
+ 8001256:	4b0d      	ldr	r3, [pc, #52]	; (800128c )
+ 8001258:	6a60      	ldr	r0, [r4, #36]	; 0x24
+ 800125a:	6859      	ldr	r1, [r3, #4]
+ 800125c:	4302      	orrs	r2, r0
+ 800125e:	f421 1174 	bic.w	r1, r1, #3997696	; 0x3d0000
+ 8001262:	480b      	ldr	r0, [pc, #44]	; (8001290 )
+ 8001264:	430a      	orrs	r2, r1
+ 8001266:	605a      	str	r2, [r3, #4]
+ 8001268:	6005      	str	r5, [r0, #0]
+ 800126a:	461c      	mov	r4, r3
+ 800126c:	f7fe ffb2 	bl	80001d4 
+ 8001270:	4605      	mov	r5, r0
+ 8001272:	e005      	b.n	8001280 
+ 8001274:	f7fe ffae 	bl	80001d4 
+ 8001278:	1b40      	subs	r0, r0, r5
+ 800127a:	2802      	cmp	r0, #2
+ 800127c:	f63f af43 	bhi.w	8001106 
+ 8001280:	6823      	ldr	r3, [r4, #0]
+ 8001282:	019a      	lsls	r2, r3, #6
+ 8001284:	d5f6      	bpl.n	8001274 
+ 8001286:	e6fd      	b.n	8001084 
+ 8001288:	42420000 	.word	0x42420000
+ 800128c:	40021000 	.word	0x40021000
+ 8001290:	42420060 	.word	0x42420060
+
+08001294 :
+ 8001294:	b178      	cbz	r0, 80012b6 
+ 8001296:	4a5d      	ldr	r2, [pc, #372]	; (800140c )
+ 8001298:	6813      	ldr	r3, [r2, #0]
+ 800129a:	f003 0307 	and.w	r3, r3, #7
+ 800129e:	428b      	cmp	r3, r1
+ 80012a0:	d20b      	bcs.n	80012ba 
+ 80012a2:	6813      	ldr	r3, [r2, #0]
+ 80012a4:	f023 0307 	bic.w	r3, r3, #7
+ 80012a8:	430b      	orrs	r3, r1
+ 80012aa:	6013      	str	r3, [r2, #0]
+ 80012ac:	6813      	ldr	r3, [r2, #0]
+ 80012ae:	f003 0307 	and.w	r3, r3, #7
+ 80012b2:	428b      	cmp	r3, r1
+ 80012b4:	d001      	beq.n	80012ba 
+ 80012b6:	2001      	movs	r0, #1
+ 80012b8:	4770      	bx	lr
+ 80012ba:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 80012be:	6803      	ldr	r3, [r0, #0]
+ 80012c0:	b086      	sub	sp, #24
+ 80012c2:	079d      	lsls	r5, r3, #30
+ 80012c4:	d514      	bpl.n	80012f0 
+ 80012c6:	075c      	lsls	r4, r3, #29
+ 80012c8:	d504      	bpl.n	80012d4 
+ 80012ca:	4c51      	ldr	r4, [pc, #324]	; (8001410 )
+ 80012cc:	6862      	ldr	r2, [r4, #4]
+ 80012ce:	f442 62e0 	orr.w	r2, r2, #1792	; 0x700
+ 80012d2:	6062      	str	r2, [r4, #4]
+ 80012d4:	071a      	lsls	r2, r3, #28
+ 80012d6:	d504      	bpl.n	80012e2 
+ 80012d8:	4c4d      	ldr	r4, [pc, #308]	; (8001410 )
+ 80012da:	6862      	ldr	r2, [r4, #4]
+ 80012dc:	f442 5260 	orr.w	r2, r2, #14336	; 0x3800
+ 80012e0:	6062      	str	r2, [r4, #4]
+ 80012e2:	4c4b      	ldr	r4, [pc, #300]	; (8001410 )
+ 80012e4:	6885      	ldr	r5, [r0, #8]
+ 80012e6:	6862      	ldr	r2, [r4, #4]
+ 80012e8:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 80012ec:	432a      	orrs	r2, r5
+ 80012ee:	6062      	str	r2, [r4, #4]
+ 80012f0:	07db      	lsls	r3, r3, #31
+ 80012f2:	4604      	mov	r4, r0
+ 80012f4:	460d      	mov	r5, r1
+ 80012f6:	d520      	bpl.n	800133a 
+ 80012f8:	6842      	ldr	r2, [r0, #4]
+ 80012fa:	4b45      	ldr	r3, [pc, #276]	; (8001410 )
+ 80012fc:	2a01      	cmp	r2, #1
+ 80012fe:	681b      	ldr	r3, [r3, #0]
+ 8001300:	d06f      	beq.n	80013e2 
+ 8001302:	2a02      	cmp	r2, #2
+ 8001304:	d07e      	beq.n	8001404 
+ 8001306:	0798      	lsls	r0, r3, #30
+ 8001308:	d527      	bpl.n	800135a 
+ 800130a:	4e41      	ldr	r6, [pc, #260]	; (8001410 )
+ 800130c:	f241 3888 	movw	r8, #5000	; 0x1388
+ 8001310:	6873      	ldr	r3, [r6, #4]
+ 8001312:	f023 0303 	bic.w	r3, r3, #3
+ 8001316:	4313      	orrs	r3, r2
+ 8001318:	6073      	str	r3, [r6, #4]
+ 800131a:	f7fe ff5b 	bl	80001d4 
+ 800131e:	4607      	mov	r7, r0
+ 8001320:	e004      	b.n	800132c 
+ 8001322:	f7fe ff57 	bl	80001d4 
+ 8001326:	1bc0      	subs	r0, r0, r7
+ 8001328:	4540      	cmp	r0, r8
+ 800132a:	d869      	bhi.n	8001400 
+ 800132c:	6873      	ldr	r3, [r6, #4]
+ 800132e:	6862      	ldr	r2, [r4, #4]
+ 8001330:	f003 030c 	and.w	r3, r3, #12
+ 8001334:	ebb3 0f82 	cmp.w	r3, r2, lsl #2
+ 8001338:	d1f3      	bne.n	8001322 
+ 800133a:	4a34      	ldr	r2, [pc, #208]	; (800140c )
+ 800133c:	6813      	ldr	r3, [r2, #0]
+ 800133e:	f003 0307 	and.w	r3, r3, #7
+ 8001342:	42ab      	cmp	r3, r5
+ 8001344:	d90d      	bls.n	8001362 
+ 8001346:	6813      	ldr	r3, [r2, #0]
+ 8001348:	f023 0307 	bic.w	r3, r3, #7
+ 800134c:	432b      	orrs	r3, r5
+ 800134e:	6013      	str	r3, [r2, #0]
+ 8001350:	6813      	ldr	r3, [r2, #0]
+ 8001352:	f003 0307 	and.w	r3, r3, #7
+ 8001356:	42ab      	cmp	r3, r5
+ 8001358:	d003      	beq.n	8001362 
+ 800135a:	2001      	movs	r0, #1
+ 800135c:	b006      	add	sp, #24
+ 800135e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 8001362:	6823      	ldr	r3, [r4, #0]
+ 8001364:	0759      	lsls	r1, r3, #29
+ 8001366:	d506      	bpl.n	8001376 
+ 8001368:	4929      	ldr	r1, [pc, #164]	; (8001410 )
+ 800136a:	68e0      	ldr	r0, [r4, #12]
+ 800136c:	684a      	ldr	r2, [r1, #4]
+ 800136e:	f422 62e0 	bic.w	r2, r2, #1792	; 0x700
+ 8001372:	4302      	orrs	r2, r0
+ 8001374:	604a      	str	r2, [r1, #4]
+ 8001376:	071a      	lsls	r2, r3, #28
+ 8001378:	d507      	bpl.n	800138a 
+ 800137a:	4a25      	ldr	r2, [pc, #148]	; (8001410 )
+ 800137c:	6921      	ldr	r1, [r4, #16]
+ 800137e:	6853      	ldr	r3, [r2, #4]
+ 8001380:	f423 5360 	bic.w	r3, r3, #14336	; 0x3800
+ 8001384:	ea43 03c1 	orr.w	r3, r3, r1, lsl #3
+ 8001388:	6053      	str	r3, [r2, #4]
+ 800138a:	f240 2201 	movw	r2, #513	; 0x201
+ 800138e:	4b21      	ldr	r3, [pc, #132]	; (8001414 )
+ 8001390:	ac06      	add	r4, sp, #24
+ 8001392:	f8ad 2004 	strh.w	r2, [sp, #4]
+ 8001396:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
+ 8001398:	e904 000f 	stmdb	r4, {r0, r1, r2, r3}
+ 800139c:	491c      	ldr	r1, [pc, #112]	; (8001410 )
+ 800139e:	684a      	ldr	r2, [r1, #4]
+ 80013a0:	f002 030c 	and.w	r3, r2, #12
+ 80013a4:	2b08      	cmp	r3, #8
+ 80013a6:	d11a      	bne.n	80013de 
+ 80013a8:	f3c2 4383 	ubfx	r3, r2, #18, #4
+ 80013ac:	4423      	add	r3, r4
+ 80013ae:	f813 0c10 	ldrb.w	r0, [r3, #-16]
+ 80013b2:	03d3      	lsls	r3, r2, #15
+ 80013b4:	d418      	bmi.n	80013e8 
+ 80013b6:	4b18      	ldr	r3, [pc, #96]	; (8001418 )
+ 80013b8:	fb03 f300 	mul.w	r3, r3, r0
+ 80013bc:	4a14      	ldr	r2, [pc, #80]	; (8001410 )
+ 80013be:	4817      	ldr	r0, [pc, #92]	; (800141c )
+ 80013c0:	6852      	ldr	r2, [r2, #4]
+ 80013c2:	4917      	ldr	r1, [pc, #92]	; (8001420 )
+ 80013c4:	f3c2 1203 	ubfx	r2, r2, #4, #4
+ 80013c8:	5c80      	ldrb	r0, [r0, r2]
+ 80013ca:	4a16      	ldr	r2, [pc, #88]	; (8001424 )
+ 80013cc:	40c3      	lsrs	r3, r0
+ 80013ce:	6808      	ldr	r0, [r1, #0]
+ 80013d0:	6013      	str	r3, [r2, #0]
+ 80013d2:	f7fe febd 	bl	8000150 
+ 80013d6:	2000      	movs	r0, #0
+ 80013d8:	b006      	add	sp, #24
+ 80013da:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 80013de:	4b12      	ldr	r3, [pc, #72]	; (8001428 )
+ 80013e0:	e7ec      	b.n	80013bc 
+ 80013e2:	039f      	lsls	r7, r3, #14
+ 80013e4:	d491      	bmi.n	800130a 
+ 80013e6:	e7b8      	b.n	800135a 
+ 80013e8:	684a      	ldr	r2, [r1, #4]
+ 80013ea:	4b0f      	ldr	r3, [pc, #60]	; (8001428 )
+ 80013ec:	f3c2 4240 	ubfx	r2, r2, #17, #1
+ 80013f0:	fb03 f300 	mul.w	r3, r3, r0
+ 80013f4:	4422      	add	r2, r4
+ 80013f6:	f812 2c14 	ldrb.w	r2, [r2, #-20]
+ 80013fa:	fbb3 f3f2 	udiv	r3, r3, r2
+ 80013fe:	e7dd      	b.n	80013bc 
+ 8001400:	2003      	movs	r0, #3
+ 8001402:	e7ab      	b.n	800135c 
+ 8001404:	019e      	lsls	r6, r3, #6
+ 8001406:	d480      	bmi.n	800130a 
+ 8001408:	e7a7      	b.n	800135a 
+ 800140a:	bf00      	nop
+ 800140c:	40022000 	.word	0x40022000
+ 8001410:	40021000 	.word	0x40021000
+ 8001414:	0800443c 	.word	0x0800443c
+ 8001418:	003d0900 	.word	0x003d0900
+ 800141c:	0800449c 	.word	0x0800449c
+ 8001420:	20000004 	.word	0x20000004
+ 8001424:	2000011c 	.word	0x2000011c
+ 8001428:	007a1200 	.word	0x007a1200
+
+0800142c :
+ 800142c:	4b04      	ldr	r3, [pc, #16]	; (8001440 )
+ 800142e:	4905      	ldr	r1, [pc, #20]	; (8001444 )
+ 8001430:	685b      	ldr	r3, [r3, #4]
+ 8001432:	4a05      	ldr	r2, [pc, #20]	; (8001448 )
+ 8001434:	f3c3 2302 	ubfx	r3, r3, #8, #3
+ 8001438:	5ccb      	ldrb	r3, [r1, r3]
+ 800143a:	6810      	ldr	r0, [r2, #0]
+ 800143c:	40d8      	lsrs	r0, r3
+ 800143e:	4770      	bx	lr
+ 8001440:	40021000 	.word	0x40021000
+ 8001444:	080044ac 	.word	0x080044ac
+ 8001448:	2000011c 	.word	0x2000011c
+
+0800144c :
+ 800144c:	4b04      	ldr	r3, [pc, #16]	; (8001460 )
+ 800144e:	4905      	ldr	r1, [pc, #20]	; (8001464 )
+ 8001450:	685b      	ldr	r3, [r3, #4]
+ 8001452:	4a05      	ldr	r2, [pc, #20]	; (8001468 )
+ 8001454:	f3c3 23c2 	ubfx	r3, r3, #11, #3
+ 8001458:	5ccb      	ldrb	r3, [r1, r3]
+ 800145a:	6810      	ldr	r0, [r2, #0]
+ 800145c:	40d8      	lsrs	r0, r3
+ 800145e:	4770      	bx	lr
+ 8001460:	40021000 	.word	0x40021000
+ 8001464:	080044ac 	.word	0x080044ac
+ 8001468:	2000011c 	.word	0x2000011c
+
+0800146c :
+ 800146c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 8001470:	4604      	mov	r4, r0
+ 8001472:	6800      	ldr	r0, [r0, #0]
+ 8001474:	b082      	sub	sp, #8
+ 8001476:	07c5      	lsls	r5, r0, #31
+ 8001478:	d52a      	bpl.n	80014d0 
+ 800147a:	4b3a      	ldr	r3, [pc, #232]	; (8001564 )
+ 800147c:	69da      	ldr	r2, [r3, #28]
+ 800147e:	00d1      	lsls	r1, r2, #3
+ 8001480:	d53d      	bpl.n	80014fe 
+ 8001482:	4b39      	ldr	r3, [pc, #228]	; (8001568 )
+ 8001484:	2500      	movs	r5, #0
+ 8001486:	681a      	ldr	r2, [r3, #0]
+ 8001488:	05d2      	lsls	r2, r2, #23
+ 800148a:	d546      	bpl.n	800151a 
+ 800148c:	4935      	ldr	r1, [pc, #212]	; (8001564 )
+ 800148e:	6860      	ldr	r0, [r4, #4]
+ 8001490:	6a0a      	ldr	r2, [r1, #32]
+ 8001492:	f412 7240 	ands.w	r2, r2, #768	; 0x300
+ 8001496:	d00f      	beq.n	80014b8 
+ 8001498:	f400 7340 	and.w	r3, r0, #768	; 0x300
+ 800149c:	4293      	cmp	r3, r2
+ 800149e:	d00b      	beq.n	80014b8 
+ 80014a0:	2701      	movs	r7, #1
+ 80014a2:	2600      	movs	r6, #0
+ 80014a4:	6a0b      	ldr	r3, [r1, #32]
+ 80014a6:	4a31      	ldr	r2, [pc, #196]	; (800156c )
+ 80014a8:	f423 7040 	bic.w	r0, r3, #768	; 0x300
+ 80014ac:	6017      	str	r7, [r2, #0]
+ 80014ae:	6016      	str	r6, [r2, #0]
+ 80014b0:	6208      	str	r0, [r1, #32]
+ 80014b2:	07d8      	lsls	r0, r3, #31
+ 80014b4:	d445      	bmi.n	8001542 
+ 80014b6:	6860      	ldr	r0, [r4, #4]
+ 80014b8:	4a2a      	ldr	r2, [pc, #168]	; (8001564 )
+ 80014ba:	6a13      	ldr	r3, [r2, #32]
+ 80014bc:	f423 7340 	bic.w	r3, r3, #768	; 0x300
+ 80014c0:	4303      	orrs	r3, r0
+ 80014c2:	6213      	str	r3, [r2, #32]
+ 80014c4:	b11d      	cbz	r5, 80014ce 
+ 80014c6:	69d3      	ldr	r3, [r2, #28]
+ 80014c8:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
+ 80014cc:	61d3      	str	r3, [r2, #28]
+ 80014ce:	6820      	ldr	r0, [r4, #0]
+ 80014d0:	0783      	lsls	r3, r0, #30
+ 80014d2:	d506      	bpl.n	80014e2 
+ 80014d4:	4a23      	ldr	r2, [pc, #140]	; (8001564 )
+ 80014d6:	68a1      	ldr	r1, [r4, #8]
+ 80014d8:	6853      	ldr	r3, [r2, #4]
+ 80014da:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
+ 80014de:	430b      	orrs	r3, r1
+ 80014e0:	6053      	str	r3, [r2, #4]
+ 80014e2:	f010 0010 	ands.w	r0, r0, #16
+ 80014e6:	d007      	beq.n	80014f8 
+ 80014e8:	2000      	movs	r0, #0
+ 80014ea:	4a1e      	ldr	r2, [pc, #120]	; (8001564 )
+ 80014ec:	68e1      	ldr	r1, [r4, #12]
+ 80014ee:	6853      	ldr	r3, [r2, #4]
+ 80014f0:	f423 0380 	bic.w	r3, r3, #4194304	; 0x400000
+ 80014f4:	430b      	orrs	r3, r1
+ 80014f6:	6053      	str	r3, [r2, #4]
+ 80014f8:	b002      	add	sp, #8
+ 80014fa:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 80014fe:	69da      	ldr	r2, [r3, #28]
+ 8001500:	2501      	movs	r5, #1
+ 8001502:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
+ 8001506:	61da      	str	r2, [r3, #28]
+ 8001508:	69db      	ldr	r3, [r3, #28]
+ 800150a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 800150e:	9301      	str	r3, [sp, #4]
+ 8001510:	9b01      	ldr	r3, [sp, #4]
+ 8001512:	4b15      	ldr	r3, [pc, #84]	; (8001568 )
+ 8001514:	681a      	ldr	r2, [r3, #0]
+ 8001516:	05d2      	lsls	r2, r2, #23
+ 8001518:	d4b8      	bmi.n	800148c 
+ 800151a:	681a      	ldr	r2, [r3, #0]
+ 800151c:	461e      	mov	r6, r3
+ 800151e:	f442 7280 	orr.w	r2, r2, #256	; 0x100
+ 8001522:	601a      	str	r2, [r3, #0]
+ 8001524:	f7fe fe56 	bl	80001d4 
+ 8001528:	4607      	mov	r7, r0
+ 800152a:	6833      	ldr	r3, [r6, #0]
+ 800152c:	05db      	lsls	r3, r3, #23
+ 800152e:	d4ad      	bmi.n	800148c 
+ 8001530:	f7fe fe50 	bl	80001d4 
+ 8001534:	1bc0      	subs	r0, r0, r7
+ 8001536:	2864      	cmp	r0, #100	; 0x64
+ 8001538:	d9f7      	bls.n	800152a 
+ 800153a:	2003      	movs	r0, #3
+ 800153c:	b002      	add	sp, #8
+ 800153e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 8001542:	460e      	mov	r6, r1
+ 8001544:	f7fe fe46 	bl	80001d4 
+ 8001548:	f241 3788 	movw	r7, #5000	; 0x1388
+ 800154c:	4680      	mov	r8, r0
+ 800154e:	6a33      	ldr	r3, [r6, #32]
+ 8001550:	079a      	lsls	r2, r3, #30
+ 8001552:	d4b0      	bmi.n	80014b6 
+ 8001554:	f7fe fe3e 	bl	80001d4 
+ 8001558:	eba0 0008 	sub.w	r0, r0, r8
+ 800155c:	42b8      	cmp	r0, r7
+ 800155e:	d9f6      	bls.n	800154e 
+ 8001560:	e7eb      	b.n	800153a 
+ 8001562:	bf00      	nop
+ 8001564:	40021000 	.word	0x40021000
+ 8001568:	40007000 	.word	0x40007000
+ 800156c:	42420440 	.word	0x42420440
+
+08001570 :
+ 8001570:	b510      	push	{r4, lr}
+ 8001572:	4604      	mov	r4, r0
+ 8001574:	f240 2201 	movw	r2, #513	; 0x201
+ 8001578:	b086      	sub	sp, #24
+ 800157a:	4b34      	ldr	r3, [pc, #208]	; (800164c )
+ 800157c:	f10d 0c18 	add.w	ip, sp, #24
+ 8001580:	2c02      	cmp	r4, #2
+ 8001582:	f8ad 2004 	strh.w	r2, [sp, #4]
+ 8001586:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
+ 8001588:	e90c 000f 	stmdb	ip, {r0, r1, r2, r3}
+ 800158c:	d042      	beq.n	8001614 
+ 800158e:	2c10      	cmp	r4, #16
+ 8001590:	d01c      	beq.n	80015cc 
+ 8001592:	2c01      	cmp	r4, #1
+ 8001594:	d002      	beq.n	800159c 
+ 8001596:	2000      	movs	r0, #0
+ 8001598:	b006      	add	sp, #24
+ 800159a:	bd10      	pop	{r4, pc}
+ 800159c:	f240 3202 	movw	r2, #770	; 0x302
+ 80015a0:	492b      	ldr	r1, [pc, #172]	; (8001650 )
+ 80015a2:	6a0b      	ldr	r3, [r1, #32]
+ 80015a4:	401a      	ands	r2, r3
+ 80015a6:	f5b2 7f81 	cmp.w	r2, #258	; 0x102
+ 80015aa:	d04b      	beq.n	8001644 
+ 80015ac:	f403 7340 	and.w	r3, r3, #768	; 0x300
+ 80015b0:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
+ 80015b4:	d03a      	beq.n	800162c 
+ 80015b6:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
+ 80015ba:	d1ec      	bne.n	8001596 
+ 80015bc:	680b      	ldr	r3, [r1, #0]
+ 80015be:	f24f 4024 	movw	r0, #62500	; 0xf424
+ 80015c2:	f413 3f00 	tst.w	r3, #131072	; 0x20000
+ 80015c6:	bf08      	it	eq
+ 80015c8:	2000      	moveq	r0, #0
+ 80015ca:	e7e5      	b.n	8001598 
+ 80015cc:	4b20      	ldr	r3, [pc, #128]	; (8001650 )
+ 80015ce:	6859      	ldr	r1, [r3, #4]
+ 80015d0:	6818      	ldr	r0, [r3, #0]
+ 80015d2:	f010 7080 	ands.w	r0, r0, #16777216	; 0x1000000
+ 80015d6:	d0df      	beq.n	8001598 
+ 80015d8:	a806      	add	r0, sp, #24
+ 80015da:	f3c1 4283 	ubfx	r2, r1, #18, #4
+ 80015de:	4402      	add	r2, r0
+ 80015e0:	f812 0c10 	ldrb.w	r0, [r2, #-16]
+ 80015e4:	03ca      	lsls	r2, r1, #15
+ 80015e6:	d529      	bpl.n	800163c 
+ 80015e8:	685b      	ldr	r3, [r3, #4]
+ 80015ea:	a906      	add	r1, sp, #24
+ 80015ec:	f3c3 4340 	ubfx	r3, r3, #17, #1
+ 80015f0:	440b      	add	r3, r1
+ 80015f2:	4a18      	ldr	r2, [pc, #96]	; (8001654 )
+ 80015f4:	f813 3c14 	ldrb.w	r3, [r3, #-20]
+ 80015f8:	fbb2 f3f3 	udiv	r3, r2, r3
+ 80015fc:	fb00 f003 	mul.w	r0, r0, r3
+ 8001600:	4b13      	ldr	r3, [pc, #76]	; (8001650 )
+ 8001602:	685b      	ldr	r3, [r3, #4]
+ 8001604:	025b      	lsls	r3, r3, #9
+ 8001606:	d4c7      	bmi.n	8001598 
+ 8001608:	4b13      	ldr	r3, [pc, #76]	; (8001658 )
+ 800160a:	0040      	lsls	r0, r0, #1
+ 800160c:	fba3 3000 	umull	r3, r0, r3, r0
+ 8001610:	0840      	lsrs	r0, r0, #1
+ 8001612:	e7c1      	b.n	8001598 
+ 8001614:	f7ff ff1a 	bl	800144c 
+ 8001618:	4b0d      	ldr	r3, [pc, #52]	; (8001650 )
+ 800161a:	685b      	ldr	r3, [r3, #4]
+ 800161c:	f3c3 3381 	ubfx	r3, r3, #14, #2
+ 8001620:	3301      	adds	r3, #1
+ 8001622:	005b      	lsls	r3, r3, #1
+ 8001624:	fbb0 f0f3 	udiv	r0, r0, r3
+ 8001628:	b006      	add	sp, #24
+ 800162a:	bd10      	pop	{r4, pc}
+ 800162c:	6a4b      	ldr	r3, [r1, #36]	; 0x24
+ 800162e:	f649 4040 	movw	r0, #40000	; 0x9c40
+ 8001632:	f013 0f02 	tst.w	r3, #2
+ 8001636:	bf08      	it	eq
+ 8001638:	2000      	moveq	r0, #0
+ 800163a:	e7ad      	b.n	8001598 
+ 800163c:	4b07      	ldr	r3, [pc, #28]	; (800165c )
+ 800163e:	fb03 f000 	mul.w	r0, r3, r0
+ 8001642:	e7dd      	b.n	8001600 
+ 8001644:	f44f 4000 	mov.w	r0, #32768	; 0x8000
+ 8001648:	e7a6      	b.n	8001598 
+ 800164a:	bf00      	nop
+ 800164c:	0800444c 	.word	0x0800444c
+ 8001650:	40021000 	.word	0x40021000
+ 8001654:	007a1200 	.word	0x007a1200
+ 8001658:	aaaaaaab 	.word	0xaaaaaaab
+ 800165c:	003d0900 	.word	0x003d0900
+
+08001660 :
+ 8001660:	2800      	cmp	r0, #0
+ 8001662:	d06e      	beq.n	8001742 
+ 8001664:	b538      	push	{r3, r4, r5, lr}
+ 8001666:	7c43      	ldrb	r3, [r0, #17]
+ 8001668:	4604      	mov	r4, r0
+ 800166a:	f003 02ff 	and.w	r2, r3, #255	; 0xff
+ 800166e:	2b00      	cmp	r3, #0
+ 8001670:	d063      	beq.n	800173a 
+ 8001672:	2302      	movs	r3, #2
+ 8001674:	6822      	ldr	r2, [r4, #0]
+ 8001676:	7463      	strb	r3, [r4, #17]
+ 8001678:	6853      	ldr	r3, [r2, #4]
+ 800167a:	f023 0308 	bic.w	r3, r3, #8
+ 800167e:	6053      	str	r3, [r2, #4]
+ 8001680:	f7fe fda8 	bl	80001d4 
+ 8001684:	4605      	mov	r5, r0
+ 8001686:	e005      	b.n	8001694 
+ 8001688:	f7fe fda4 	bl	80001d4 
+ 800168c:	1b40      	subs	r0, r0, r5
+ 800168e:	f5b0 7f7a 	cmp.w	r0, #1000	; 0x3e8
+ 8001692:	d84e      	bhi.n	8001732 
+ 8001694:	6823      	ldr	r3, [r4, #0]
+ 8001696:	685b      	ldr	r3, [r3, #4]
+ 8001698:	0718      	lsls	r0, r3, #28
+ 800169a:	d5f5      	bpl.n	8001688 
+ 800169c:	f7fe fd9a 	bl	80001d4 
+ 80016a0:	4605      	mov	r5, r0
+ 80016a2:	e005      	b.n	80016b0 
+ 80016a4:	f7fe fd96 	bl	80001d4 
+ 80016a8:	1b40      	subs	r0, r0, r5
+ 80016aa:	f5b0 7f7a 	cmp.w	r0, #1000	; 0x3e8
+ 80016ae:	d840      	bhi.n	8001732 
+ 80016b0:	6823      	ldr	r3, [r4, #0]
+ 80016b2:	685a      	ldr	r2, [r3, #4]
+ 80016b4:	0691      	lsls	r1, r2, #26
+ 80016b6:	d5f5      	bpl.n	80016a4 
+ 80016b8:	6859      	ldr	r1, [r3, #4]
+ 80016ba:	68a0      	ldr	r0, [r4, #8]
+ 80016bc:	f041 0110 	orr.w	r1, r1, #16
+ 80016c0:	6059      	str	r1, [r3, #4]
+ 80016c2:	6859      	ldr	r1, [r3, #4]
+ 80016c4:	f021 0107 	bic.w	r1, r1, #7
+ 80016c8:	6059      	str	r1, [r3, #4]
+ 80016ca:	b120      	cbz	r0, 80016d6 
+ 80016cc:	4922      	ldr	r1, [pc, #136]	; (8001758 )
+ 80016ce:	6b0a      	ldr	r2, [r1, #48]	; 0x30
+ 80016d0:	f022 0201 	bic.w	r2, r2, #1
+ 80016d4:	630a      	str	r2, [r1, #48]	; 0x30
+ 80016d6:	4920      	ldr	r1, [pc, #128]	; (8001758 )
+ 80016d8:	6aca      	ldr	r2, [r1, #44]	; 0x2c
+ 80016da:	f422 7260 	bic.w	r2, r2, #896	; 0x380
+ 80016de:	4302      	orrs	r2, r0
+ 80016e0:	62ca      	str	r2, [r1, #44]	; 0x2c
+ 80016e2:	6860      	ldr	r0, [r4, #4]
+ 80016e4:	1c42      	adds	r2, r0, #1
+ 80016e6:	d02e      	beq.n	8001746 
+ 80016e8:	6899      	ldr	r1, [r3, #8]
+ 80016ea:	b285      	uxth	r5, r0
+ 80016ec:	f021 010f 	bic.w	r1, r1, #15
+ 80016f0:	ea41 4110 	orr.w	r1, r1, r0, lsr #16
+ 80016f4:	6099      	str	r1, [r3, #8]
+ 80016f6:	68da      	ldr	r2, [r3, #12]
+ 80016f8:	0c12      	lsrs	r2, r2, #16
+ 80016fa:	0412      	lsls	r2, r2, #16
+ 80016fc:	432a      	orrs	r2, r5
+ 80016fe:	60da      	str	r2, [r3, #12]
+ 8001700:	685a      	ldr	r2, [r3, #4]
+ 8001702:	f022 0210 	bic.w	r2, r2, #16
+ 8001706:	605a      	str	r2, [r3, #4]
+ 8001708:	f7fe fd64 	bl	80001d4 
+ 800170c:	4605      	mov	r5, r0
+ 800170e:	e005      	b.n	800171c 
+ 8001710:	f7fe fd60 	bl	80001d4 
+ 8001714:	1b40      	subs	r0, r0, r5
+ 8001716:	f5b0 7f7a 	cmp.w	r0, #1000	; 0x3e8
+ 800171a:	d80a      	bhi.n	8001732 
+ 800171c:	6823      	ldr	r3, [r4, #0]
+ 800171e:	685b      	ldr	r3, [r3, #4]
+ 8001720:	069b      	lsls	r3, r3, #26
+ 8001722:	d5f5      	bpl.n	8001710 
+ 8001724:	2301      	movs	r3, #1
+ 8001726:	2000      	movs	r0, #0
+ 8001728:	7363      	strb	r3, [r4, #13]
+ 800172a:	73e0      	strb	r0, [r4, #15]
+ 800172c:	73a3      	strb	r3, [r4, #14]
+ 800172e:	7463      	strb	r3, [r4, #17]
+ 8001730:	bd38      	pop	{r3, r4, r5, pc}
+ 8001732:	2304      	movs	r3, #4
+ 8001734:	2001      	movs	r0, #1
+ 8001736:	7463      	strb	r3, [r4, #17]
+ 8001738:	bd38      	pop	{r3, r4, r5, pc}
+ 800173a:	7402      	strb	r2, [r0, #16]
+ 800173c:	f002 faf6 	bl	8003d2c 
+ 8001740:	e797      	b.n	8001672 
+ 8001742:	2001      	movs	r0, #1
+ 8001744:	4770      	bx	lr
+ 8001746:	2001      	movs	r0, #1
+ 8001748:	f7ff ff12 	bl	8001570 
+ 800174c:	2800      	cmp	r0, #0
+ 800174e:	d0f0      	beq.n	8001732 
+ 8001750:	6823      	ldr	r3, [r4, #0]
+ 8001752:	3801      	subs	r0, #1
+ 8001754:	e7c8      	b.n	80016e8 
+ 8001756:	bf00      	nop
+ 8001758:	40006c00 	.word	0x40006c00
+
+0800175c :
+ 800175c:	2800      	cmp	r0, #0
+ 800175e:	d03b      	beq.n	80017d8 
+ 8001760:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8001762:	2300      	movs	r3, #0
+ 8001764:	f890 1051 	ldrb.w	r1, [r0, #81]	; 0x51
+ 8001768:	4604      	mov	r4, r0
+ 800176a:	6283      	str	r3, [r0, #40]	; 0x28
+ 800176c:	f001 02ff 	and.w	r2, r1, #255	; 0xff
+ 8001770:	b361      	cbz	r1, 80017cc 
+ 8001772:	461a      	mov	r2, r3
+ 8001774:	e9d4 3601 	ldrd	r3, r6, [r4, #4]
+ 8001778:	2702      	movs	r7, #2
+ 800177a:	2100      	movs	r1, #0
+ 800177c:	2501      	movs	r5, #1
+ 800177e:	68e0      	ldr	r0, [r4, #12]
+ 8001780:	4333      	orrs	r3, r6
+ 8001782:	6926      	ldr	r6, [r4, #16]
+ 8001784:	4303      	orrs	r3, r0
+ 8001786:	6960      	ldr	r0, [r4, #20]
+ 8001788:	4333      	orrs	r3, r6
+ 800178a:	69e6      	ldr	r6, [r4, #28]
+ 800178c:	f8d4 c018 	ldr.w	ip, [r4, #24]
+ 8001790:	4303      	orrs	r3, r0
+ 8001792:	6a20      	ldr	r0, [r4, #32]
+ 8001794:	4333      	orrs	r3, r6
+ 8001796:	6826      	ldr	r6, [r4, #0]
+ 8001798:	f884 7051 	strb.w	r7, [r4, #81]	; 0x51
+ 800179c:	4303      	orrs	r3, r0
+ 800179e:	f40c 7000 	and.w	r0, ip, #512	; 0x200
+ 80017a2:	4303      	orrs	r3, r0
+ 80017a4:	6830      	ldr	r0, [r6, #0]
+ 80017a6:	ea4f 4c1c 	mov.w	ip, ip, lsr #16
+ 80017aa:	4313      	orrs	r3, r2
+ 80017ac:	f020 0040 	bic.w	r0, r0, #64	; 0x40
+ 80017b0:	f00c 0204 	and.w	r2, ip, #4
+ 80017b4:	6030      	str	r0, [r6, #0]
+ 80017b6:	6033      	str	r3, [r6, #0]
+ 80017b8:	6072      	str	r2, [r6, #4]
+ 80017ba:	69f3      	ldr	r3, [r6, #28]
+ 80017bc:	4608      	mov	r0, r1
+ 80017be:	f423 6300 	bic.w	r3, r3, #2048	; 0x800
+ 80017c2:	61f3      	str	r3, [r6, #28]
+ 80017c4:	6561      	str	r1, [r4, #84]	; 0x54
+ 80017c6:	f884 5051 	strb.w	r5, [r4, #81]	; 0x51
+ 80017ca:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 80017cc:	f880 2050 	strb.w	r2, [r0, #80]	; 0x50
+ 80017d0:	f002 facc 	bl	8003d6c 
+ 80017d4:	6aa2      	ldr	r2, [r4, #40]	; 0x28
+ 80017d6:	e7cd      	b.n	8001774 
+ 80017d8:	2001      	movs	r0, #1
+ 80017da:	4770      	bx	lr
+
+080017dc :
+ 80017dc:	2800      	cmp	r0, #0
+ 80017de:	d05e      	beq.n	800189e 
+ 80017e0:	b538      	push	{r3, r4, r5, lr}
+ 80017e2:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
+ 80017e6:	4604      	mov	r4, r0
+ 80017e8:	f003 02ff 	and.w	r2, r3, #255	; 0xff
+ 80017ec:	2b00      	cmp	r3, #0
+ 80017ee:	d051      	beq.n	8001894 
+ 80017f0:	2224      	movs	r2, #36	; 0x24
+ 80017f2:	6823      	ldr	r3, [r4, #0]
+ 80017f4:	f884 2039 	strb.w	r2, [r4, #57]	; 0x39
+ 80017f8:	68da      	ldr	r2, [r3, #12]
+ 80017fa:	68e0      	ldr	r0, [r4, #12]
+ 80017fc:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
+ 8001800:	60da      	str	r2, [r3, #12]
+ 8001802:	6919      	ldr	r1, [r3, #16]
+ 8001804:	68a2      	ldr	r2, [r4, #8]
+ 8001806:	f421 5140 	bic.w	r1, r1, #12288	; 0x3000
+ 800180a:	4301      	orrs	r1, r0
+ 800180c:	6119      	str	r1, [r3, #16]
+ 800180e:	68d9      	ldr	r1, [r3, #12]
+ 8001810:	e9d4 5004 	ldrd	r5, r0, [r4, #16]
+ 8001814:	f421 51b0 	bic.w	r1, r1, #5632	; 0x1600
+ 8001818:	432a      	orrs	r2, r5
+ 800181a:	f021 010c 	bic.w	r1, r1, #12
+ 800181e:	4302      	orrs	r2, r0
+ 8001820:	430a      	orrs	r2, r1
+ 8001822:	60da      	str	r2, [r3, #12]
+ 8001824:	695a      	ldr	r2, [r3, #20]
+ 8001826:	69a0      	ldr	r0, [r4, #24]
+ 8001828:	491f      	ldr	r1, [pc, #124]	; (80018a8 )
+ 800182a:	f422 7240 	bic.w	r2, r2, #768	; 0x300
+ 800182e:	4302      	orrs	r2, r0
+ 8001830:	428b      	cmp	r3, r1
+ 8001832:	615a      	str	r2, [r3, #20]
+ 8001834:	d035      	beq.n	80018a2 
+ 8001836:	f7ff fdf9 	bl	800142c 
+ 800183a:	6862      	ldr	r2, [r4, #4]
+ 800183c:	eb00 0080 	add.w	r0, r0, r0, lsl #2
+ 8001840:	0092      	lsls	r2, r2, #2
+ 8001842:	eb00 0080 	add.w	r0, r0, r0, lsl #2
+ 8001846:	fbb0 f0f2 	udiv	r0, r0, r2
+ 800184a:	2264      	movs	r2, #100	; 0x64
+ 800184c:	4d17      	ldr	r5, [pc, #92]	; (80018ac )
+ 800184e:	6823      	ldr	r3, [r4, #0]
+ 8001850:	fba5 c100 	umull	ip, r1, r5, r0
+ 8001854:	0949      	lsrs	r1, r1, #5
+ 8001856:	fb02 0211 	mls	r2, r2, r1, r0
+ 800185a:	0112      	lsls	r2, r2, #4
+ 800185c:	3232      	adds	r2, #50	; 0x32
+ 800185e:	fba5 0202 	umull	r0, r2, r5, r2
+ 8001862:	0109      	lsls	r1, r1, #4
+ 8001864:	eb01 1252 	add.w	r2, r1, r2, lsr #5
+ 8001868:	2500      	movs	r5, #0
+ 800186a:	2120      	movs	r1, #32
+ 800186c:	609a      	str	r2, [r3, #8]
+ 800186e:	691a      	ldr	r2, [r3, #16]
+ 8001870:	4628      	mov	r0, r5
+ 8001872:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
+ 8001876:	611a      	str	r2, [r3, #16]
+ 8001878:	695a      	ldr	r2, [r3, #20]
+ 800187a:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
+ 800187e:	615a      	str	r2, [r3, #20]
+ 8001880:	68da      	ldr	r2, [r3, #12]
+ 8001882:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
+ 8001886:	60da      	str	r2, [r3, #12]
+ 8001888:	63e5      	str	r5, [r4, #60]	; 0x3c
+ 800188a:	f884 1039 	strb.w	r1, [r4, #57]	; 0x39
+ 800188e:	f884 103a 	strb.w	r1, [r4, #58]	; 0x3a
+ 8001892:	bd38      	pop	{r3, r4, r5, pc}
+ 8001894:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
+ 8001898:	f002 faa4 	bl	8003de4 
+ 800189c:	e7a8      	b.n	80017f0 
+ 800189e:	2001      	movs	r0, #1
+ 80018a0:	4770      	bx	lr
+ 80018a2:	f7ff fdd3 	bl	800144c 
+ 80018a6:	e7c8      	b.n	800183a 
+ 80018a8:	40013800 	.word	0x40013800
+ 80018ac:	51eb851f 	.word	0x51eb851f
+
+080018b0 :
+ 80018b0:	b084      	sub	sp, #16
+ 80018b2:	a801      	add	r0, sp, #4
+ 80018b4:	e880 000e 	stmia.w	r0, {r1, r2, r3}
+ 80018b8:	b004      	add	sp, #16
+ 80018ba:	2000      	movs	r0, #0
+ 80018bc:	4770      	bx	lr
+ 80018be:	bf00      	nop
+
+080018c0 :
+ 80018c0:	4602      	mov	r2, r0
+ 80018c2:	f8b0 3040 	ldrh.w	r3, [r0, #64]	; 0x40
+ 80018c6:	2000      	movs	r0, #0
+ 80018c8:	f443 433f 	orr.w	r3, r3, #48896	; 0xbf00
+ 80018cc:	f8a2 3040 	strh.w	r3, [r2, #64]	; 0x40
+ 80018d0:	4770      	bx	lr
+ 80018d2:	bf00      	nop
+
+080018d4 :
+ 80018d4:	f244 03ff 	movw	r3, #16639	; 0x40ff
+ 80018d8:	4602      	mov	r2, r0
+ 80018da:	f8b0 1040 	ldrh.w	r1, [r0, #64]	; 0x40
+ 80018de:	2000      	movs	r0, #0
+ 80018e0:	400b      	ands	r3, r1
+ 80018e2:	f8a2 3040 	strh.w	r3, [r2, #64]	; 0x40
+ 80018e6:	4770      	bx	lr
+
+080018e8 :
+ 80018e8:	2000      	movs	r0, #0
+ 80018ea:	4770      	bx	lr
+
+080018ec :
+ 80018ec:	b084      	sub	sp, #16
+ 80018ee:	b470      	push	{r4, r5, r6}
+ 80018f0:	4604      	mov	r4, r0
+ 80018f2:	2501      	movs	r5, #1
+ 80018f4:	2000      	movs	r0, #0
+ 80018f6:	f8a4 5040 	strh.w	r5, [r4, #64]	; 0x40
+ 80018fa:	f8a4 0040 	strh.w	r0, [r4, #64]	; 0x40
+ 80018fe:	f8a4 0044 	strh.w	r0, [r4, #68]	; 0x44
+ 8001902:	f8a4 0050 	strh.w	r0, [r4, #80]	; 0x50
+ 8001906:	f8b4 6040 	ldrh.w	r6, [r4, #64]	; 0x40
+ 800190a:	ad04      	add	r5, sp, #16
+ 800190c:	f446 463f 	orr.w	r6, r6, #48896	; 0xbf00
+ 8001910:	f8a4 6040 	strh.w	r6, [r4, #64]	; 0x40
+ 8001914:	e885 000e 	stmia.w	r5, {r1, r2, r3}
+ 8001918:	bc70      	pop	{r4, r5, r6}
+ 800191a:	b004      	add	sp, #16
+ 800191c:	4770      	bx	lr
+ 800191e:	bf00      	nop
+
+08001920 :
+ 8001920:	b470      	push	{r4, r5, r6}
+ 8001922:	780d      	ldrb	r5, [r1, #0]
+ 8001924:	4603      	mov	r3, r0
+ 8001926:	f830 4025 	ldrh.w	r4, [r0, r5, lsl #2]
+ 800192a:	4abc      	ldr	r2, [pc, #752]	; (8001c1c )
+ 800192c:	78c8      	ldrb	r0, [r1, #3]
+ 800192e:	4022      	ands	r2, r4
+ 8001930:	2803      	cmp	r0, #3
+ 8001932:	f200 8142 	bhi.w	8001bba 
+ 8001936:	e8df f000 	tbb	[pc, r0]
+ 800193a:	464e      	.short	0x464e
+ 800193c:	4a02      	.short	0x4a02
+ 800193e:	2000      	movs	r0, #0
+ 8001940:	f248 0480 	movw	r4, #32896	; 0x8080
+ 8001944:	4322      	orrs	r2, r4
+ 8001946:	f823 2025 	strh.w	r2, [r3, r5, lsl #2]
+ 800194a:	780d      	ldrb	r5, [r1, #0]
+ 800194c:	4eb4      	ldr	r6, [pc, #720]	; (8001c20 )
+ 800194e:	f833 2025 	ldrh.w	r2, [r3, r5, lsl #2]
+ 8001952:	432c      	orrs	r4, r5
+ 8001954:	4032      	ands	r2, r6
+ 8001956:	4322      	orrs	r2, r4
+ 8001958:	f823 2025 	strh.w	r2, [r3, r5, lsl #2]
+ 800195c:	7b0a      	ldrb	r2, [r1, #12]
+ 800195e:	2a00      	cmp	r2, #0
+ 8001960:	d13d      	bne.n	80019de 
+ 8001962:	88cc      	ldrh	r4, [r1, #6]
+ 8001964:	780a      	ldrb	r2, [r1, #0]
+ 8001966:	784d      	ldrb	r5, [r1, #1]
+ 8001968:	0864      	lsrs	r4, r4, #1
+ 800196a:	0064      	lsls	r4, r4, #1
+ 800196c:	eb03 1202 	add.w	r2, r3, r2, lsl #4
+ 8001970:	2d00      	cmp	r5, #0
+ 8001972:	f000 80e8 	beq.w	8001b46 
+ 8001976:	f8b3 5050 	ldrh.w	r5, [r3, #80]	; 0x50
+ 800197a:	442a      	add	r2, r5
+ 800197c:	f8a2 4400 	strh.w	r4, [r2, #1024]	; 0x400
+ 8001980:	780a      	ldrb	r2, [r1, #0]
+ 8001982:	f833 5022 	ldrh.w	r5, [r3, r2, lsl #2]
+ 8001986:	eb03 0482 	add.w	r4, r3, r2, lsl #2
+ 800198a:	066d      	lsls	r5, r5, #25
+ 800198c:	d50b      	bpl.n	80019a6 
+ 800198e:	f833 4022 	ldrh.w	r4, [r3, r2, lsl #2]
+ 8001992:	4026      	ands	r6, r4
+ 8001994:	f446 4600 	orr.w	r6, r6, #32768	; 0x8000
+ 8001998:	f046 06c0 	orr.w	r6, r6, #192	; 0xc0
+ 800199c:	f823 6022 	strh.w	r6, [r3, r2, lsl #2]
+ 80019a0:	780c      	ldrb	r4, [r1, #0]
+ 80019a2:	eb03 0484 	add.w	r4, r3, r4, lsl #2
+ 80019a6:	78cb      	ldrb	r3, [r1, #3]
+ 80019a8:	2b01      	cmp	r3, #1
+ 80019aa:	f000 8120 	beq.w	8001bee 
+ 80019ae:	8822      	ldrh	r2, [r4, #0]
+ 80019b0:	4b9c      	ldr	r3, [pc, #624]	; (8001c24 )
+ 80019b2:	4013      	ands	r3, r2
+ 80019b4:	f083 0320 	eor.w	r3, r3, #32
+ 80019b8:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 80019bc:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 80019c0:	8023      	strh	r3, [r4, #0]
+ 80019c2:	bc70      	pop	{r4, r5, r6}
+ 80019c4:	4770      	bx	lr
+ 80019c6:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
+ 80019ca:	2000      	movs	r0, #0
+ 80019cc:	e7b8      	b.n	8001940 
+ 80019ce:	f442 62c0 	orr.w	r2, r2, #1536	; 0x600
+ 80019d2:	2000      	movs	r0, #0
+ 80019d4:	e7b4      	b.n	8001940 
+ 80019d6:	f442 7200 	orr.w	r2, r2, #512	; 0x200
+ 80019da:	2000      	movs	r0, #0
+ 80019dc:	e7b0      	b.n	8001940 
+ 80019de:	780c      	ldrb	r4, [r1, #0]
+ 80019e0:	f833 2024 	ldrh.w	r2, [r3, r4, lsl #2]
+ 80019e4:	4032      	ands	r2, r6
+ 80019e6:	f442 4201 	orr.w	r2, r2, #33024	; 0x8100
+ 80019ea:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 80019ee:	f823 2024 	strh.w	r2, [r3, r4, lsl #2]
+ 80019f2:	780a      	ldrb	r2, [r1, #0]
+ 80019f4:	890c      	ldrh	r4, [r1, #8]
+ 80019f6:	f8b3 5050 	ldrh.w	r5, [r3, #80]	; 0x50
+ 80019fa:	eb03 1202 	add.w	r2, r3, r2, lsl #4
+ 80019fe:	0864      	lsrs	r4, r4, #1
+ 8001a00:	f502 6280 	add.w	r2, r2, #1024	; 0x400
+ 8001a04:	0064      	lsls	r4, r4, #1
+ 8001a06:	b2ad      	uxth	r5, r5
+ 8001a08:	5354      	strh	r4, [r2, r5]
+ 8001a0a:	780a      	ldrb	r2, [r1, #0]
+ 8001a0c:	894c      	ldrh	r4, [r1, #10]
+ 8001a0e:	f8b3 5050 	ldrh.w	r5, [r3, #80]	; 0x50
+ 8001a12:	eb03 1202 	add.w	r2, r3, r2, lsl #4
+ 8001a16:	0864      	lsrs	r4, r4, #1
+ 8001a18:	f502 6281 	add.w	r2, r2, #1032	; 0x408
+ 8001a1c:	0064      	lsls	r4, r4, #1
+ 8001a1e:	b2ad      	uxth	r5, r5
+ 8001a20:	5354      	strh	r4, [r2, r5]
+ 8001a22:	784a      	ldrb	r2, [r1, #1]
+ 8001a24:	2a00      	cmp	r2, #0
+ 8001a26:	d142      	bne.n	8001aae 
+ 8001a28:	780a      	ldrb	r2, [r1, #0]
+ 8001a2a:	f833 5022 	ldrh.w	r5, [r3, r2, lsl #2]
+ 8001a2e:	eb03 0482 	add.w	r4, r3, r2, lsl #2
+ 8001a32:	046d      	lsls	r5, r5, #17
+ 8001a34:	d50b      	bpl.n	8001a4e 
+ 8001a36:	f833 4022 	ldrh.w	r4, [r3, r2, lsl #2]
+ 8001a3a:	4026      	ands	r6, r4
+ 8001a3c:	f446 4640 	orr.w	r6, r6, #49152	; 0xc000
+ 8001a40:	f046 0680 	orr.w	r6, r6, #128	; 0x80
+ 8001a44:	f823 6022 	strh.w	r6, [r3, r2, lsl #2]
+ 8001a48:	780c      	ldrb	r4, [r1, #0]
+ 8001a4a:	eb03 0484 	add.w	r4, r3, r4, lsl #2
+ 8001a4e:	8822      	ldrh	r2, [r4, #0]
+ 8001a50:	0656      	lsls	r6, r2, #25
+ 8001a52:	d50c      	bpl.n	8001a6e 
+ 8001a54:	8822      	ldrh	r2, [r4, #0]
+ 8001a56:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001a5a:	0512      	lsls	r2, r2, #20
+ 8001a5c:	0d12      	lsrs	r2, r2, #20
+ 8001a5e:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001a62:	f042 02c0 	orr.w	r2, r2, #192	; 0xc0
+ 8001a66:	8022      	strh	r2, [r4, #0]
+ 8001a68:	780c      	ldrb	r4, [r1, #0]
+ 8001a6a:	eb03 0484 	add.w	r4, r3, r4, lsl #2
+ 8001a6e:	f248 0680 	movw	r6, #32896	; 0x8080
+ 8001a72:	8822      	ldrh	r2, [r4, #0]
+ 8001a74:	4d6c      	ldr	r5, [pc, #432]	; (8001c28 )
+ 8001a76:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001a7a:	0512      	lsls	r2, r2, #20
+ 8001a7c:	0d12      	lsrs	r2, r2, #20
+ 8001a7e:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001a82:	f042 02c0 	orr.w	r2, r2, #192	; 0xc0
+ 8001a86:	8022      	strh	r2, [r4, #0]
+ 8001a88:	780c      	ldrb	r4, [r1, #0]
+ 8001a8a:	f833 2024 	ldrh.w	r2, [r3, r4, lsl #2]
+ 8001a8e:	402a      	ands	r2, r5
+ 8001a90:	f482 5240 	eor.w	r2, r2, #12288	; 0x3000
+ 8001a94:	4332      	orrs	r2, r6
+ 8001a96:	f823 2024 	strh.w	r2, [r3, r4, lsl #2]
+ 8001a9a:	7809      	ldrb	r1, [r1, #0]
+ 8001a9c:	4a61      	ldr	r2, [pc, #388]	; (8001c24 )
+ 8001a9e:	f833 4021 	ldrh.w	r4, [r3, r1, lsl #2]
+ 8001aa2:	4022      	ands	r2, r4
+ 8001aa4:	4332      	orrs	r2, r6
+ 8001aa6:	f823 2021 	strh.w	r2, [r3, r1, lsl #2]
+ 8001aaa:	bc70      	pop	{r4, r5, r6}
+ 8001aac:	4770      	bx	lr
+ 8001aae:	780a      	ldrb	r2, [r1, #0]
+ 8001ab0:	f833 5022 	ldrh.w	r5, [r3, r2, lsl #2]
+ 8001ab4:	eb03 0482 	add.w	r4, r3, r2, lsl #2
+ 8001ab8:	046d      	lsls	r5, r5, #17
+ 8001aba:	d50b      	bpl.n	8001ad4 
+ 8001abc:	f833 4022 	ldrh.w	r4, [r3, r2, lsl #2]
+ 8001ac0:	4026      	ands	r6, r4
+ 8001ac2:	f446 4640 	orr.w	r6, r6, #49152	; 0xc000
+ 8001ac6:	f046 0680 	orr.w	r6, r6, #128	; 0x80
+ 8001aca:	f823 6022 	strh.w	r6, [r3, r2, lsl #2]
+ 8001ace:	780c      	ldrb	r4, [r1, #0]
+ 8001ad0:	eb03 0484 	add.w	r4, r3, r4, lsl #2
+ 8001ad4:	8822      	ldrh	r2, [r4, #0]
+ 8001ad6:	0652      	lsls	r2, r2, #25
+ 8001ad8:	d50c      	bpl.n	8001af4 
+ 8001ada:	8822      	ldrh	r2, [r4, #0]
+ 8001adc:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001ae0:	0512      	lsls	r2, r2, #20
+ 8001ae2:	0d12      	lsrs	r2, r2, #20
+ 8001ae4:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001ae8:	f042 02c0 	orr.w	r2, r2, #192	; 0xc0
+ 8001aec:	8022      	strh	r2, [r4, #0]
+ 8001aee:	780c      	ldrb	r4, [r1, #0]
+ 8001af0:	eb03 0484 	add.w	r4, r3, r4, lsl #2
+ 8001af4:	8822      	ldrh	r2, [r4, #0]
+ 8001af6:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001afa:	0512      	lsls	r2, r2, #20
+ 8001afc:	0d12      	lsrs	r2, r2, #20
+ 8001afe:	f442 4240 	orr.w	r2, r2, #49152	; 0xc000
+ 8001b02:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8001b06:	8022      	strh	r2, [r4, #0]
+ 8001b08:	78ca      	ldrb	r2, [r1, #3]
+ 8001b0a:	780c      	ldrb	r4, [r1, #0]
+ 8001b0c:	2a01      	cmp	r2, #1
+ 8001b0e:	d061      	beq.n	8001bd4 
+ 8001b10:	f833 5024 	ldrh.w	r5, [r3, r4, lsl #2]
+ 8001b14:	4a43      	ldr	r2, [pc, #268]	; (8001c24 )
+ 8001b16:	402a      	ands	r2, r5
+ 8001b18:	f082 0220 	eor.w	r2, r2, #32
+ 8001b1c:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001b20:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8001b24:	f823 2024 	strh.w	r2, [r3, r4, lsl #2]
+ 8001b28:	7809      	ldrb	r1, [r1, #0]
+ 8001b2a:	bc70      	pop	{r4, r5, r6}
+ 8001b2c:	f833 2021 	ldrh.w	r2, [r3, r1, lsl #2]
+ 8001b30:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001b34:	0492      	lsls	r2, r2, #18
+ 8001b36:	0c92      	lsrs	r2, r2, #18
+ 8001b38:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001b3c:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8001b40:	f823 2021 	strh.w	r2, [r3, r1, lsl #2]
+ 8001b44:	4770      	bx	lr
+ 8001b46:	f8b3 6050 	ldrh.w	r6, [r3, #80]	; 0x50
+ 8001b4a:	690d      	ldr	r5, [r1, #16]
+ 8001b4c:	4432      	add	r2, r6
+ 8001b4e:	f8a2 4408 	strh.w	r4, [r2, #1032]	; 0x408
+ 8001b52:	780a      	ldrb	r2, [r1, #0]
+ 8001b54:	f8b3 4050 	ldrh.w	r4, [r3, #80]	; 0x50
+ 8001b58:	eb03 1202 	add.w	r2, r3, r2, lsl #4
+ 8001b5c:	f202 420c 	addw	r2, r2, #1036	; 0x40c
+ 8001b60:	b2a4      	uxth	r4, r4
+ 8001b62:	b365      	cbz	r5, 8001bbe 
+ 8001b64:	2d3e      	cmp	r5, #62	; 0x3e
+ 8001b66:	d84d      	bhi.n	8001c04 
+ 8001b68:	086e      	lsrs	r6, r5, #1
+ 8001b6a:	07ed      	lsls	r5, r5, #31
+ 8001b6c:	bf48      	it	mi
+ 8001b6e:	3601      	addmi	r6, #1
+ 8001b70:	02b6      	lsls	r6, r6, #10
+ 8001b72:	b2b6      	uxth	r6, r6
+ 8001b74:	5316      	strh	r6, [r2, r4]
+ 8001b76:	780c      	ldrb	r4, [r1, #0]
+ 8001b78:	f833 5024 	ldrh.w	r5, [r3, r4, lsl #2]
+ 8001b7c:	eb03 0284 	add.w	r2, r3, r4, lsl #2
+ 8001b80:	046e      	lsls	r6, r5, #17
+ 8001b82:	d50e      	bpl.n	8001ba2 
+ 8001b84:	f833 2024 	ldrh.w	r2, [r3, r4, lsl #2]
+ 8001b88:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001b8c:	0512      	lsls	r2, r2, #20
+ 8001b8e:	0d12      	lsrs	r2, r2, #20
+ 8001b90:	f442 4240 	orr.w	r2, r2, #49152	; 0xc000
+ 8001b94:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8001b98:	f823 2024 	strh.w	r2, [r3, r4, lsl #2]
+ 8001b9c:	780a      	ldrb	r2, [r1, #0]
+ 8001b9e:	eb03 0282 	add.w	r2, r3, r2, lsl #2
+ 8001ba2:	8811      	ldrh	r1, [r2, #0]
+ 8001ba4:	4b20      	ldr	r3, [pc, #128]	; (8001c28 )
+ 8001ba6:	bc70      	pop	{r4, r5, r6}
+ 8001ba8:	400b      	ands	r3, r1
+ 8001baa:	f483 5340 	eor.w	r3, r3, #12288	; 0x3000
+ 8001bae:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 8001bb2:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8001bb6:	8013      	strh	r3, [r2, #0]
+ 8001bb8:	4770      	bx	lr
+ 8001bba:	2001      	movs	r0, #1
+ 8001bbc:	e6c0      	b.n	8001940 
+ 8001bbe:	5b15      	ldrh	r5, [r2, r4]
+ 8001bc0:	f425 45f8 	bic.w	r5, r5, #31744	; 0x7c00
+ 8001bc4:	042d      	lsls	r5, r5, #16
+ 8001bc6:	0c2d      	lsrs	r5, r5, #16
+ 8001bc8:	5315      	strh	r5, [r2, r4]
+ 8001bca:	5b15      	ldrh	r5, [r2, r4]
+ 8001bcc:	f445 4500 	orr.w	r5, r5, #32768	; 0x8000
+ 8001bd0:	5315      	strh	r5, [r2, r4]
+ 8001bd2:	e7d0      	b.n	8001b76 
+ 8001bd4:	f833 2024 	ldrh.w	r2, [r3, r4, lsl #2]
+ 8001bd8:	f022 02c0 	bic.w	r2, r2, #192	; 0xc0
+ 8001bdc:	0512      	lsls	r2, r2, #20
+ 8001bde:	0d12      	lsrs	r2, r2, #20
+ 8001be0:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001be4:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8001be8:	f823 2024 	strh.w	r2, [r3, r4, lsl #2]
+ 8001bec:	e79c      	b.n	8001b28 
+ 8001bee:	8823      	ldrh	r3, [r4, #0]
+ 8001bf0:	f023 03c0 	bic.w	r3, r3, #192	; 0xc0
+ 8001bf4:	051b      	lsls	r3, r3, #20
+ 8001bf6:	0d1b      	lsrs	r3, r3, #20
+ 8001bf8:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 8001bfc:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8001c00:	8023      	strh	r3, [r4, #0]
+ 8001c02:	e752      	b.n	8001aaa 
+ 8001c04:	096e      	lsrs	r6, r5, #5
+ 8001c06:	06ed      	lsls	r5, r5, #27
+ 8001c08:	4d08      	ldr	r5, [pc, #32]	; (8001c2c )
+ 8001c0a:	bf08      	it	eq
+ 8001c0c:	f106 36ff 	addeq.w	r6, r6, #4294967295	; 0xffffffff
+ 8001c10:	ea45 2586 	orr.w	r5, r5, r6, lsl #10
+ 8001c14:	b2ad      	uxth	r5, r5
+ 8001c16:	5315      	strh	r5, [r2, r4]
+ 8001c18:	e7ad      	b.n	8001b76 
+ 8001c1a:	bf00      	nop
+ 8001c1c:	ffff898f 	.word	0xffff898f
+ 8001c20:	ffff8f8f 	.word	0xffff8f8f
+ 8001c24:	ffff8fbf 	.word	0xffff8fbf
+ 8001c28:	ffffbf8f 	.word	0xffffbf8f
+ 8001c2c:	ffff8000 	.word	0xffff8000
+
+08001c30 :
+ 8001c30:	b430      	push	{r4, r5}
+ 8001c32:	780a      	ldrb	r2, [r1, #0]
+ 8001c34:	7b0d      	ldrb	r5, [r1, #12]
+ 8001c36:	eb00 0382 	add.w	r3, r0, r2, lsl #2
+ 8001c3a:	784c      	ldrb	r4, [r1, #1]
+ 8001c3c:	bb15      	cbnz	r5, 8001c84 
+ 8001c3e:	2c00      	cmp	r4, #0
+ 8001c40:	f000 8099 	beq.w	8001d76 
+ 8001c44:	f830 4022 	ldrh.w	r4, [r0, r2, lsl #2]
+ 8001c48:	0664      	lsls	r4, r4, #25
+ 8001c4a:	d50e      	bpl.n	8001c6a 
+ 8001c4c:	f830 3022 	ldrh.w	r3, [r0, r2, lsl #2]
+ 8001c50:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
+ 8001c54:	051b      	lsls	r3, r3, #20
+ 8001c56:	0d1b      	lsrs	r3, r3, #20
+ 8001c58:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 8001c5c:	f043 03c0 	orr.w	r3, r3, #192	; 0xc0
+ 8001c60:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 8001c64:	780b      	ldrb	r3, [r1, #0]
+ 8001c66:	eb00 0383 	add.w	r3, r0, r3, lsl #2
+ 8001c6a:	881a      	ldrh	r2, [r3, #0]
+ 8001c6c:	2000      	movs	r0, #0
+ 8001c6e:	bc30      	pop	{r4, r5}
+ 8001c70:	f022 02c0 	bic.w	r2, r2, #192	; 0xc0
+ 8001c74:	0512      	lsls	r2, r2, #20
+ 8001c76:	0d12      	lsrs	r2, r2, #20
+ 8001c78:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001c7c:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8001c80:	801a      	strh	r2, [r3, #0]
+ 8001c82:	4770      	bx	lr
+ 8001c84:	2c00      	cmp	r4, #0
+ 8001c86:	d141      	bne.n	8001d0c 
+ 8001c88:	f830 4022 	ldrh.w	r4, [r0, r2, lsl #2]
+ 8001c8c:	0464      	lsls	r4, r4, #17
+ 8001c8e:	d50e      	bpl.n	8001cae 
+ 8001c90:	f830 3022 	ldrh.w	r3, [r0, r2, lsl #2]
+ 8001c94:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
+ 8001c98:	051b      	lsls	r3, r3, #20
+ 8001c9a:	0d1b      	lsrs	r3, r3, #20
+ 8001c9c:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
+ 8001ca0:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8001ca4:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 8001ca8:	780b      	ldrb	r3, [r1, #0]
+ 8001caa:	eb00 0383 	add.w	r3, r0, r3, lsl #2
+ 8001cae:	881a      	ldrh	r2, [r3, #0]
+ 8001cb0:	0655      	lsls	r5, r2, #25
+ 8001cb2:	d50c      	bpl.n	8001cce 
+ 8001cb4:	881a      	ldrh	r2, [r3, #0]
+ 8001cb6:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001cba:	0512      	lsls	r2, r2, #20
+ 8001cbc:	0d12      	lsrs	r2, r2, #20
+ 8001cbe:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001cc2:	f042 02c0 	orr.w	r2, r2, #192	; 0xc0
+ 8001cc6:	801a      	strh	r2, [r3, #0]
+ 8001cc8:	780b      	ldrb	r3, [r1, #0]
+ 8001cca:	eb00 0383 	add.w	r3, r0, r3, lsl #2
+ 8001cce:	f248 0580 	movw	r5, #32896	; 0x8080
+ 8001cd2:	881a      	ldrh	r2, [r3, #0]
+ 8001cd4:	4c3f      	ldr	r4, [pc, #252]	; (8001dd4 )
+ 8001cd6:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001cda:	0512      	lsls	r2, r2, #20
+ 8001cdc:	0d12      	lsrs	r2, r2, #20
+ 8001cde:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001ce2:	f042 02c0 	orr.w	r2, r2, #192	; 0xc0
+ 8001ce6:	801a      	strh	r2, [r3, #0]
+ 8001ce8:	780a      	ldrb	r2, [r1, #0]
+ 8001cea:	f830 3022 	ldrh.w	r3, [r0, r2, lsl #2]
+ 8001cee:	4023      	ands	r3, r4
+ 8001cf0:	432b      	orrs	r3, r5
+ 8001cf2:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 8001cf6:	780a      	ldrb	r2, [r1, #0]
+ 8001cf8:	4b37      	ldr	r3, [pc, #220]	; (8001dd8 )
+ 8001cfa:	f830 1022 	ldrh.w	r1, [r0, r2, lsl #2]
+ 8001cfe:	400b      	ands	r3, r1
+ 8001d00:	431d      	orrs	r5, r3
+ 8001d02:	f820 5022 	strh.w	r5, [r0, r2, lsl #2]
+ 8001d06:	2000      	movs	r0, #0
+ 8001d08:	bc30      	pop	{r4, r5}
+ 8001d0a:	4770      	bx	lr
+ 8001d0c:	f830 4022 	ldrh.w	r4, [r0, r2, lsl #2]
+ 8001d10:	0464      	lsls	r4, r4, #17
+ 8001d12:	d50e      	bpl.n	8001d32 
+ 8001d14:	f830 3022 	ldrh.w	r3, [r0, r2, lsl #2]
+ 8001d18:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
+ 8001d1c:	051b      	lsls	r3, r3, #20
+ 8001d1e:	0d1b      	lsrs	r3, r3, #20
+ 8001d20:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
+ 8001d24:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8001d28:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 8001d2c:	780b      	ldrb	r3, [r1, #0]
+ 8001d2e:	eb00 0383 	add.w	r3, r0, r3, lsl #2
+ 8001d32:	881a      	ldrh	r2, [r3, #0]
+ 8001d34:	0652      	lsls	r2, r2, #25
+ 8001d36:	d43e      	bmi.n	8001db6 
+ 8001d38:	f248 0580 	movw	r5, #32896	; 0x8080
+ 8001d3c:	881a      	ldrh	r2, [r3, #0]
+ 8001d3e:	4c26      	ldr	r4, [pc, #152]	; (8001dd8 )
+ 8001d40:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001d44:	0512      	lsls	r2, r2, #20
+ 8001d46:	0d12      	lsrs	r2, r2, #20
+ 8001d48:	f442 4240 	orr.w	r2, r2, #49152	; 0xc000
+ 8001d4c:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8001d50:	801a      	strh	r2, [r3, #0]
+ 8001d52:	780a      	ldrb	r2, [r1, #0]
+ 8001d54:	f830 3022 	ldrh.w	r3, [r0, r2, lsl #2]
+ 8001d58:	4023      	ands	r3, r4
+ 8001d5a:	432b      	orrs	r3, r5
+ 8001d5c:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 8001d60:	780a      	ldrb	r2, [r1, #0]
+ 8001d62:	4b1c      	ldr	r3, [pc, #112]	; (8001dd4 )
+ 8001d64:	f830 1022 	ldrh.w	r1, [r0, r2, lsl #2]
+ 8001d68:	400b      	ands	r3, r1
+ 8001d6a:	431d      	orrs	r5, r3
+ 8001d6c:	f820 5022 	strh.w	r5, [r0, r2, lsl #2]
+ 8001d70:	2000      	movs	r0, #0
+ 8001d72:	bc30      	pop	{r4, r5}
+ 8001d74:	4770      	bx	lr
+ 8001d76:	f830 4022 	ldrh.w	r4, [r0, r2, lsl #2]
+ 8001d7a:	0465      	lsls	r5, r4, #17
+ 8001d7c:	d50e      	bpl.n	8001d9c 
+ 8001d7e:	f830 3022 	ldrh.w	r3, [r0, r2, lsl #2]
+ 8001d82:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
+ 8001d86:	051b      	lsls	r3, r3, #20
+ 8001d88:	0d1b      	lsrs	r3, r3, #20
+ 8001d8a:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
+ 8001d8e:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8001d92:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 8001d96:	780b      	ldrb	r3, [r1, #0]
+ 8001d98:	eb00 0383 	add.w	r3, r0, r3, lsl #2
+ 8001d9c:	881a      	ldrh	r2, [r3, #0]
+ 8001d9e:	2000      	movs	r0, #0
+ 8001da0:	bc30      	pop	{r4, r5}
+ 8001da2:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001da6:	0492      	lsls	r2, r2, #18
+ 8001da8:	0c92      	lsrs	r2, r2, #18
+ 8001daa:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001dae:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8001db2:	801a      	strh	r2, [r3, #0]
+ 8001db4:	4770      	bx	lr
+ 8001db6:	881a      	ldrh	r2, [r3, #0]
+ 8001db8:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8001dbc:	0512      	lsls	r2, r2, #20
+ 8001dbe:	0d12      	lsrs	r2, r2, #20
+ 8001dc0:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 8001dc4:	f042 02c0 	orr.w	r2, r2, #192	; 0xc0
+ 8001dc8:	801a      	strh	r2, [r3, #0]
+ 8001dca:	780b      	ldrb	r3, [r1, #0]
+ 8001dcc:	eb00 0383 	add.w	r3, r0, r3, lsl #2
+ 8001dd0:	e7b2      	b.n	8001d38 
+ 8001dd2:	bf00      	nop
+ 8001dd4:	ffffbf8f 	.word	0xffffbf8f
+ 8001dd8:	ffff8fbf 	.word	0xffff8fbf
+
+08001ddc :
+ 8001ddc:	b4f0      	push	{r4, r5, r6, r7}
+ 8001dde:	784c      	ldrb	r4, [r1, #1]
+ 8001de0:	698b      	ldr	r3, [r1, #24]
+ 8001de2:	2c01      	cmp	r4, #1
+ 8001de4:	690a      	ldr	r2, [r1, #16]
+ 8001de6:	d05a      	beq.n	8001e9e 
+ 8001de8:	4293      	cmp	r3, r2
+ 8001dea:	bf98      	it	ls
+ 8001dec:	2600      	movls	r6, #0
+ 8001dee:	7b0d      	ldrb	r5, [r1, #12]
+ 8001df0:	bf88      	it	hi
+ 8001df2:	1a9e      	subhi	r6, r3, r2
+ 8001df4:	618e      	str	r6, [r1, #24]
+ 8001df6:	bf88      	it	hi
+ 8001df8:	4613      	movhi	r3, r2
+ 8001dfa:	780a      	ldrb	r2, [r1, #0]
+ 8001dfc:	bb15      	cbnz	r5, 8001e44 
+ 8001dfe:	f8b0 5050 	ldrh.w	r5, [r0, #80]	; 0x50
+ 8001e02:	f200 440c 	addw	r4, r0, #1036	; 0x40c
+ 8001e06:	0112      	lsls	r2, r2, #4
+ 8001e08:	442c      	add	r4, r5
+ 8001e0a:	2b00      	cmp	r3, #0
+ 8001e0c:	f000 80a8 	beq.w	8001f60 
+ 8001e10:	2b3e      	cmp	r3, #62	; 0x3e
+ 8001e12:	f200 80c9 	bhi.w	8001fa8 
+ 8001e16:	085d      	lsrs	r5, r3, #1
+ 8001e18:	07db      	lsls	r3, r3, #31
+ 8001e1a:	bf48      	it	mi
+ 8001e1c:	3501      	addmi	r5, #1
+ 8001e1e:	02ad      	lsls	r5, r5, #10
+ 8001e20:	b2ad      	uxth	r5, r5
+ 8001e22:	52a5      	strh	r5, [r4, r2]
+ 8001e24:	780a      	ldrb	r2, [r1, #0]
+ 8001e26:	f830 1022 	ldrh.w	r1, [r0, r2, lsl #2]
+ 8001e2a:	4b7d      	ldr	r3, [pc, #500]	; (8002020 )
+ 8001e2c:	bcf0      	pop	{r4, r5, r6, r7}
+ 8001e2e:	400b      	ands	r3, r1
+ 8001e30:	f483 5340 	eor.w	r3, r3, #12288	; 0x3000
+ 8001e34:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 8001e38:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8001e3c:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 8001e40:	2000      	movs	r0, #0
+ 8001e42:	4770      	bx	lr
+ 8001e44:	2c00      	cmp	r4, #0
+ 8001e46:	d1ee      	bne.n	8001e26 
+ 8001e48:	f8b0 5050 	ldrh.w	r5, [r0, #80]	; 0x50
+ 8001e4c:	f200 4404 	addw	r4, r0, #1028	; 0x404
+ 8001e50:	0112      	lsls	r2, r2, #4
+ 8001e52:	442c      	add	r4, r5
+ 8001e54:	2b00      	cmp	r3, #0
+ 8001e56:	f040 80b3 	bne.w	8001fc0 
+ 8001e5a:	5aa5      	ldrh	r5, [r4, r2]
+ 8001e5c:	4e71      	ldr	r6, [pc, #452]	; (8002024 )
+ 8001e5e:	f425 45f8 	bic.w	r5, r5, #31744	; 0x7c00
+ 8001e62:	042d      	lsls	r5, r5, #16
+ 8001e64:	0c2d      	lsrs	r5, r5, #16
+ 8001e66:	52a5      	strh	r5, [r4, r2]
+ 8001e68:	5aa5      	ldrh	r5, [r4, r2]
+ 8001e6a:	f445 4500 	orr.w	r5, r5, #32768	; 0x8000
+ 8001e6e:	52a5      	strh	r5, [r4, r2]
+ 8001e70:	784c      	ldrb	r4, [r1, #1]
+ 8001e72:	2c00      	cmp	r4, #0
+ 8001e74:	f040 80af 	bne.w	8001fd6 
+ 8001e78:	f8b0 3050 	ldrh.w	r3, [r0, #80]	; 0x50
+ 8001e7c:	780a      	ldrb	r2, [r1, #0]
+ 8001e7e:	f200 440c 	addw	r4, r0, #1036	; 0x40c
+ 8001e82:	0112      	lsls	r2, r2, #4
+ 8001e84:	441c      	add	r4, r3
+ 8001e86:	5aa3      	ldrh	r3, [r4, r2]
+ 8001e88:	f423 43f8 	bic.w	r3, r3, #31744	; 0x7c00
+ 8001e8c:	041b      	lsls	r3, r3, #16
+ 8001e8e:	0c1b      	lsrs	r3, r3, #16
+ 8001e90:	52a3      	strh	r3, [r4, r2]
+ 8001e92:	5aa3      	ldrh	r3, [r4, r2]
+ 8001e94:	4333      	orrs	r3, r6
+ 8001e96:	b29b      	uxth	r3, r3
+ 8001e98:	52a3      	strh	r3, [r4, r2]
+ 8001e9a:	780a      	ldrb	r2, [r1, #0]
+ 8001e9c:	e7c3      	b.n	8001e26 
+ 8001e9e:	4293      	cmp	r3, r2
+ 8001ea0:	bf86      	itte	hi
+ 8001ea2:	1a9c      	subhi	r4, r3, r2
+ 8001ea4:	4613      	movhi	r3, r2
+ 8001ea6:	2400      	movls	r4, #0
+ 8001ea8:	b29a      	uxth	r2, r3
+ 8001eaa:	7b0d      	ldrb	r5, [r1, #12]
+ 8001eac:	3201      	adds	r2, #1
+ 8001eae:	0856      	lsrs	r6, r2, #1
+ 8001eb0:	618c      	str	r4, [r1, #24]
+ 8001eb2:	b29b      	uxth	r3, r3
+ 8001eb4:	694a      	ldr	r2, [r1, #20]
+ 8001eb6:	f500 6780 	add.w	r7, r0, #1024	; 0x400
+ 8001eba:	b36d      	cbz	r5, 8001f18 
+ 8001ebc:	780d      	ldrb	r5, [r1, #0]
+ 8001ebe:	f830 4025 	ldrh.w	r4, [r0, r5, lsl #2]
+ 8001ec2:	012d      	lsls	r5, r5, #4
+ 8001ec4:	0664      	lsls	r4, r4, #25
+ 8001ec6:	f8b0 c050 	ldrh.w	ip, [r0, #80]	; 0x50
+ 8001eca:	d555      	bpl.n	8001f78 
+ 8001ecc:	f200 440c 	addw	r4, r0, #1036	; 0x40c
+ 8001ed0:	4464      	add	r4, ip
+ 8001ed2:	5363      	strh	r3, [r4, r5]
+ 8001ed4:	894c      	ldrh	r4, [r1, #10]
+ 8001ed6:	eb07 0444 	add.w	r4, r7, r4, lsl #1
+ 8001eda:	b13e      	cbz	r6, 8001eec 
+ 8001edc:	eb02 0346 	add.w	r3, r2, r6, lsl #1
+ 8001ee0:	f832 5b02 	ldrh.w	r5, [r2], #2
+ 8001ee4:	4293      	cmp	r3, r2
+ 8001ee6:	f824 5b04 	strh.w	r5, [r4], #4
+ 8001eea:	d1f9      	bne.n	8001ee0 
+ 8001eec:	780c      	ldrb	r4, [r1, #0]
+ 8001eee:	784b      	ldrb	r3, [r1, #1]
+ 8001ef0:	eb00 0284 	add.w	r2, r0, r4, lsl #2
+ 8001ef4:	2b00      	cmp	r3, #0
+ 8001ef6:	d145      	bne.n	8001f84 
+ 8001ef8:	f830 3024 	ldrh.w	r3, [r0, r4, lsl #2]
+ 8001efc:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
+ 8001f00:	051b      	lsls	r3, r3, #20
+ 8001f02:	0d1b      	lsrs	r3, r3, #20
+ 8001f04:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 8001f08:	f043 03c0 	orr.w	r3, r3, #192	; 0xc0
+ 8001f0c:	f820 3024 	strh.w	r3, [r0, r4, lsl #2]
+ 8001f10:	780a      	ldrb	r2, [r1, #0]
+ 8001f12:	eb00 0282 	add.w	r2, r0, r2, lsl #2
+ 8001f16:	e016      	b.n	8001f46 
+ 8001f18:	88cc      	ldrh	r4, [r1, #6]
+ 8001f1a:	eb07 0444 	add.w	r4, r7, r4, lsl #1
+ 8001f1e:	b13e      	cbz	r6, 8001f30 
+ 8001f20:	eb04 0686 	add.w	r6, r4, r6, lsl #2
+ 8001f24:	f832 5b02 	ldrh.w	r5, [r2], #2
+ 8001f28:	f824 5b04 	strh.w	r5, [r4], #4
+ 8001f2c:	42a6      	cmp	r6, r4
+ 8001f2e:	d1f9      	bne.n	8001f24 
+ 8001f30:	f8b0 5050 	ldrh.w	r5, [r0, #80]	; 0x50
+ 8001f34:	780c      	ldrb	r4, [r1, #0]
+ 8001f36:	f200 4204 	addw	r2, r0, #1028	; 0x404
+ 8001f3a:	442a      	add	r2, r5
+ 8001f3c:	0124      	lsls	r4, r4, #4
+ 8001f3e:	52a3      	strh	r3, [r4, r2]
+ 8001f40:	780a      	ldrb	r2, [r1, #0]
+ 8001f42:	eb00 0282 	add.w	r2, r0, r2, lsl #2
+ 8001f46:	8811      	ldrh	r1, [r2, #0]
+ 8001f48:	4b37      	ldr	r3, [pc, #220]	; (8002028 )
+ 8001f4a:	2000      	movs	r0, #0
+ 8001f4c:	bcf0      	pop	{r4, r5, r6, r7}
+ 8001f4e:	400b      	ands	r3, r1
+ 8001f50:	f083 0330 	eor.w	r3, r3, #48	; 0x30
+ 8001f54:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 8001f58:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8001f5c:	8013      	strh	r3, [r2, #0]
+ 8001f5e:	4770      	bx	lr
+ 8001f60:	5aa3      	ldrh	r3, [r4, r2]
+ 8001f62:	f423 43f8 	bic.w	r3, r3, #31744	; 0x7c00
+ 8001f66:	041b      	lsls	r3, r3, #16
+ 8001f68:	0c1b      	lsrs	r3, r3, #16
+ 8001f6a:	52a3      	strh	r3, [r4, r2]
+ 8001f6c:	5aa3      	ldrh	r3, [r4, r2]
+ 8001f6e:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 8001f72:	52a3      	strh	r3, [r4, r2]
+ 8001f74:	780a      	ldrb	r2, [r1, #0]
+ 8001f76:	e756      	b.n	8001e26 
+ 8001f78:	f200 4404 	addw	r4, r0, #1028	; 0x404
+ 8001f7c:	4464      	add	r4, ip
+ 8001f7e:	5363      	strh	r3, [r4, r5]
+ 8001f80:	890c      	ldrh	r4, [r1, #8]
+ 8001f82:	e7a8      	b.n	8001ed6 
+ 8001f84:	2b01      	cmp	r3, #1
+ 8001f86:	d1de      	bne.n	8001f46 
+ 8001f88:	f830 3024 	ldrh.w	r3, [r0, r4, lsl #2]
+ 8001f8c:	f023 03f0 	bic.w	r3, r3, #240	; 0xf0
+ 8001f90:	051b      	lsls	r3, r3, #20
+ 8001f92:	0d1b      	lsrs	r3, r3, #20
+ 8001f94:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
+ 8001f98:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8001f9c:	f820 3024 	strh.w	r3, [r0, r4, lsl #2]
+ 8001fa0:	780a      	ldrb	r2, [r1, #0]
+ 8001fa2:	eb00 0282 	add.w	r2, r0, r2, lsl #2
+ 8001fa6:	e7ce      	b.n	8001f46 
+ 8001fa8:	095d      	lsrs	r5, r3, #5
+ 8001faa:	06df      	lsls	r7, r3, #27
+ 8001fac:	4b1d      	ldr	r3, [pc, #116]	; (8002024 )
+ 8001fae:	bf08      	it	eq
+ 8001fb0:	f105 35ff 	addeq.w	r5, r5, #4294967295	; 0xffffffff
+ 8001fb4:	ea43 2385 	orr.w	r3, r3, r5, lsl #10
+ 8001fb8:	b29b      	uxth	r3, r3
+ 8001fba:	52a3      	strh	r3, [r4, r2]
+ 8001fbc:	780a      	ldrb	r2, [r1, #0]
+ 8001fbe:	e732      	b.n	8001e26 
+ 8001fc0:	2b3e      	cmp	r3, #62	; 0x3e
+ 8001fc2:	d816      	bhi.n	8001ff2 
+ 8001fc4:	085d      	lsrs	r5, r3, #1
+ 8001fc6:	07de      	lsls	r6, r3, #31
+ 8001fc8:	bf48      	it	mi
+ 8001fca:	3501      	addmi	r5, #1
+ 8001fcc:	02ad      	lsls	r5, r5, #10
+ 8001fce:	b2ad      	uxth	r5, r5
+ 8001fd0:	52a5      	strh	r5, [r4, r2]
+ 8001fd2:	784c      	ldrb	r4, [r1, #1]
+ 8001fd4:	b1d4      	cbz	r4, 800200c 
+ 8001fd6:	2c01      	cmp	r4, #1
+ 8001fd8:	780a      	ldrb	r2, [r1, #0]
+ 8001fda:	f47f af24 	bne.w	8001e26 
+ 8001fde:	f8b0 5050 	ldrh.w	r5, [r0, #80]	; 0x50
+ 8001fe2:	f200 440c 	addw	r4, r0, #1036	; 0x40c
+ 8001fe6:	0112      	lsls	r2, r2, #4
+ 8001fe8:	b29b      	uxth	r3, r3
+ 8001fea:	442c      	add	r4, r5
+ 8001fec:	52a3      	strh	r3, [r4, r2]
+ 8001fee:	780a      	ldrb	r2, [r1, #0]
+ 8001ff0:	e719      	b.n	8001e26 
+ 8001ff2:	095e      	lsrs	r6, r3, #5
+ 8001ff4:	06dd      	lsls	r5, r3, #27
+ 8001ff6:	4d0b      	ldr	r5, [pc, #44]	; (8002024 )
+ 8001ff8:	bf08      	it	eq
+ 8001ffa:	f106 36ff 	addeq.w	r6, r6, #4294967295	; 0xffffffff
+ 8001ffe:	ea45 2586 	orr.w	r5, r5, r6, lsl #10
+ 8002002:	b2ad      	uxth	r5, r5
+ 8002004:	52a5      	strh	r5, [r4, r2]
+ 8002006:	784c      	ldrb	r4, [r1, #1]
+ 8002008:	2c00      	cmp	r4, #0
+ 800200a:	d1e4      	bne.n	8001fd6 
+ 800200c:	f8b0 4050 	ldrh.w	r4, [r0, #80]	; 0x50
+ 8002010:	780b      	ldrb	r3, [r1, #0]
+ 8002012:	f200 420c 	addw	r2, r0, #1036	; 0x40c
+ 8002016:	4422      	add	r2, r4
+ 8002018:	011b      	lsls	r3, r3, #4
+ 800201a:	52d5      	strh	r5, [r2, r3]
+ 800201c:	780a      	ldrb	r2, [r1, #0]
+ 800201e:	e702      	b.n	8001e26 
+ 8002020:	ffffbf8f 	.word	0xffffbf8f
+ 8002024:	ffff8000 	.word	0xffff8000
+ 8002028:	ffff8fbf 	.word	0xffff8fbf
+
+0800202c :
+ 800202c:	784b      	ldrb	r3, [r1, #1]
+ 800202e:	780a      	ldrb	r2, [r1, #0]
+ 8002030:	f830 1022 	ldrh.w	r1, [r0, r2, lsl #2]
+ 8002034:	b95b      	cbnz	r3, 800204e 
+ 8002036:	4b0c      	ldr	r3, [pc, #48]	; (8002068 )
+ 8002038:	400b      	ands	r3, r1
+ 800203a:	f483 5380 	eor.w	r3, r3, #4096	; 0x1000
+ 800203e:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 8002042:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 8002046:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 800204a:	2000      	movs	r0, #0
+ 800204c:	4770      	bx	lr
+ 800204e:	4b07      	ldr	r3, [pc, #28]	; (800206c )
+ 8002050:	400b      	ands	r3, r1
+ 8002052:	f083 0310 	eor.w	r3, r3, #16
+ 8002056:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 800205a:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 800205e:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 8002062:	2000      	movs	r0, #0
+ 8002064:	4770      	bx	lr
+ 8002066:	bf00      	nop
+ 8002068:	ffffbf8f 	.word	0xffffbf8f
+ 800206c:	ffff8fbf 	.word	0xffff8fbf
+
+08002070 :
+ 8002070:	7b0b      	ldrb	r3, [r1, #12]
+ 8002072:	2b00      	cmp	r3, #0
+ 8002074:	d139      	bne.n	80020ea 
+ 8002076:	b410      	push	{r4}
+ 8002078:	780b      	ldrb	r3, [r1, #0]
+ 800207a:	784c      	ldrb	r4, [r1, #1]
+ 800207c:	eb00 0283 	add.w	r2, r0, r3, lsl #2
+ 8002080:	b314      	cbz	r4, 80020c8 
+ 8002082:	f830 2023 	ldrh.w	r2, [r0, r3, lsl #2]
+ 8002086:	0652      	lsls	r2, r2, #25
+ 8002088:	d50b      	bpl.n	80020a2 
+ 800208a:	f830 2023 	ldrh.w	r2, [r0, r3, lsl #2]
+ 800208e:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 8002092:	0512      	lsls	r2, r2, #20
+ 8002094:	0d12      	lsrs	r2, r2, #20
+ 8002096:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
+ 800209a:	f042 02c0 	orr.w	r2, r2, #192	; 0xc0
+ 800209e:	f820 2023 	strh.w	r2, [r0, r3, lsl #2]
+ 80020a2:	78cb      	ldrb	r3, [r1, #3]
+ 80020a4:	2b01      	cmp	r3, #1
+ 80020a6:	d01d      	beq.n	80020e4 
+ 80020a8:	780a      	ldrb	r2, [r1, #0]
+ 80020aa:	4b19      	ldr	r3, [pc, #100]	; (8002110 )
+ 80020ac:	f830 1022 	ldrh.w	r1, [r0, r2, lsl #2]
+ 80020b0:	bc10      	pop	{r4}
+ 80020b2:	400b      	ands	r3, r1
+ 80020b4:	f083 0320 	eor.w	r3, r3, #32
+ 80020b8:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 80020bc:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 80020c0:	f820 3022 	strh.w	r3, [r0, r2, lsl #2]
+ 80020c4:	2000      	movs	r0, #0
+ 80020c6:	4770      	bx	lr
+ 80020c8:	f830 4023 	ldrh.w	r4, [r0, r3, lsl #2]
+ 80020cc:	0464      	lsls	r4, r4, #17
+ 80020ce:	d40e      	bmi.n	80020ee 
+ 80020d0:	8811      	ldrh	r1, [r2, #0]
+ 80020d2:	4b10      	ldr	r3, [pc, #64]	; (8002114 )
+ 80020d4:	400b      	ands	r3, r1
+ 80020d6:	f483 5340 	eor.w	r3, r3, #12288	; 0x3000
+ 80020da:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
+ 80020de:	f043 0380 	orr.w	r3, r3, #128	; 0x80
+ 80020e2:	8013      	strh	r3, [r2, #0]
+ 80020e4:	2000      	movs	r0, #0
+ 80020e6:	bc10      	pop	{r4}
+ 80020e8:	4770      	bx	lr
+ 80020ea:	2000      	movs	r0, #0
+ 80020ec:	4770      	bx	lr
+ 80020ee:	f830 2023 	ldrh.w	r2, [r0, r3, lsl #2]
+ 80020f2:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
+ 80020f6:	0512      	lsls	r2, r2, #20
+ 80020f8:	0d12      	lsrs	r2, r2, #20
+ 80020fa:	f442 4240 	orr.w	r2, r2, #49152	; 0xc000
+ 80020fe:	f042 0280 	orr.w	r2, r2, #128	; 0x80
+ 8002102:	f820 2023 	strh.w	r2, [r0, r3, lsl #2]
+ 8002106:	780a      	ldrb	r2, [r1, #0]
+ 8002108:	eb00 0282 	add.w	r2, r0, r2, lsl #2
+ 800210c:	e7e0      	b.n	80020d0 
+ 800210e:	bf00      	nop
+ 8002110:	ffff8fbf 	.word	0xffff8fbf
+ 8002114:	ffffbf8f 	.word	0xffffbf8f
+
+08002118 :
+ 8002118:	b911      	cbnz	r1, 8002120 
+ 800211a:	2380      	movs	r3, #128	; 0x80
+ 800211c:	f8a0 304c 	strh.w	r3, [r0, #76]	; 0x4c
+ 8002120:	2000      	movs	r0, #0
+ 8002122:	4770      	bx	lr
+
+08002124 :
+ 8002124:	2000      	movs	r0, #0
+ 8002126:	4770      	bx	lr
+
+08002128 :
+ 8002128:	2000      	movs	r0, #0
+ 800212a:	4770      	bx	lr
+
+0800212c :
+ 800212c:	f8b0 0044 	ldrh.w	r0, [r0, #68]	; 0x44
+ 8002130:	4770      	bx	lr
+ 8002132:	bf00      	nop
+
+08002134 :
+ 8002134:	2000      	movs	r0, #0
+ 8002136:	4770      	bx	lr
+
+08002138 :
+ 8002138:	eb00 0242 	add.w	r2, r0, r2, lsl #1
+ 800213c:	0858      	lsrs	r0, r3, #1
+ 800213e:	f502 6280 	add.w	r2, r2, #1024	; 0x400
+ 8002142:	d01a      	beq.n	800217a 
+ 8002144:	b4f0      	push	{r4, r5, r6, r7}
+ 8002146:	4617      	mov	r7, r2
+ 8002148:	4606      	mov	r6, r0
+ 800214a:	1c8d      	adds	r5, r1, #2
+ 800214c:	f837 4b04 	ldrh.w	r4, [r7], #4
+ 8002150:	3e01      	subs	r6, #1
+ 8002152:	b2a4      	uxth	r4, r4
+ 8002154:	ea4f 2c14 	mov.w	ip, r4, lsr #8
+ 8002158:	f805 4c02 	strb.w	r4, [r5, #-2]
+ 800215c:	f805 cc01 	strb.w	ip, [r5, #-1]
+ 8002160:	f105 0502 	add.w	r5, r5, #2
+ 8002164:	d1f2      	bne.n	800214c 
+ 8002166:	bcf0      	pop	{r4, r5, r6, r7}
+ 8002168:	eb01 0140 	add.w	r1, r1, r0, lsl #1
+ 800216c:	eb02 0280 	add.w	r2, r2, r0, lsl #2
+ 8002170:	07d8      	lsls	r0, r3, #31
+ 8002172:	bf44      	itt	mi
+ 8002174:	8813      	ldrhmi	r3, [r2, #0]
+ 8002176:	700b      	strbmi	r3, [r1, #0]
+ 8002178:	4770      	bx	lr
+ 800217a:	07db      	lsls	r3, r3, #31
+ 800217c:	bf44      	itt	mi
+ 800217e:	8813      	ldrhmi	r3, [r2, #0]
+ 8002180:	700b      	strbmi	r3, [r1, #0]
+ 8002182:	4770      	bx	lr
+
+08002184 :
+ 8002184:	f8d0 32bc 	ldr.w	r3, [r0, #700]	; 0x2bc
+ 8002188:	b183      	cbz	r3, 80021ac 
+ 800218a:	b510      	push	{r4, lr}
+ 800218c:	f8d0 42b8 	ldr.w	r4, [r0, #696]	; 0x2b8
+ 8002190:	f894 0200 	ldrb.w	r0, [r4, #512]	; 0x200
+ 8002194:	28ff      	cmp	r0, #255	; 0xff
+ 8002196:	d007      	beq.n	80021a8 
+ 8002198:	689b      	ldr	r3, [r3, #8]
+ 800219a:	f894 2201 	ldrb.w	r2, [r4, #513]	; 0x201
+ 800219e:	4621      	mov	r1, r4
+ 80021a0:	4798      	blx	r3
+ 80021a2:	23ff      	movs	r3, #255	; 0xff
+ 80021a4:	f884 3200 	strb.w	r3, [r4, #512]	; 0x200
+ 80021a8:	2000      	movs	r0, #0
+ 80021aa:	bd10      	pop	{r4, pc}
+ 80021ac:	2000      	movs	r0, #0
+ 80021ae:	4770      	bx	lr
+
+080021b0 :
+ 80021b0:	2343      	movs	r3, #67	; 0x43
+ 80021b2:	8003      	strh	r3, [r0, #0]
+ 80021b4:	4800      	ldr	r0, [pc, #0]	; (80021b8 )
+ 80021b6:	4770      	bx	lr
+ 80021b8:	20000040 	.word	0x20000040
+
+080021bc :
+ 80021bc:	2343      	movs	r3, #67	; 0x43
+ 80021be:	8003      	strh	r3, [r0, #0]
+ 80021c0:	4800      	ldr	r0, [pc, #0]	; (80021c4 )
+ 80021c2:	4770      	bx	lr
+ 80021c4:	20000084 	.word	0x20000084
+
+080021c8 :
+ 80021c8:	2343      	movs	r3, #67	; 0x43
+ 80021ca:	8003      	strh	r3, [r0, #0]
+ 80021cc:	4800      	ldr	r0, [pc, #0]	; (80021d0 )
+ 80021ce:	4770      	bx	lr
+ 80021d0:	200000d4 	.word	0x200000d4
+
+080021d4 :
+ 80021d4:	230a      	movs	r3, #10
+ 80021d6:	8003      	strh	r3, [r0, #0]
+ 80021d8:	4800      	ldr	r0, [pc, #0]	; (80021dc )
+ 80021da:	4770      	bx	lr
+ 80021dc:	200000c8 	.word	0x200000c8
+
+080021e0 :
+ 80021e0:	b538      	push	{r3, r4, r5, lr}
+ 80021e2:	4604      	mov	r4, r0
+ 80021e4:	f8d0 52b8 	ldr.w	r5, [r0, #696]	; 0x2b8
+ 80021e8:	f001 fff0 	bl	80041cc 
+ 80021ec:	f8d4 32b8 	ldr.w	r3, [r4, #696]	; 0x2b8
+ 80021f0:	f8c5 020c 	str.w	r0, [r5, #524]	; 0x20c
+ 80021f4:	b14b      	cbz	r3, 800220a 
+ 80021f6:	f8d4 32bc 	ldr.w	r3, [r4, #700]	; 0x2bc
+ 80021fa:	f505 7103 	add.w	r1, r5, #524	; 0x20c
+ 80021fe:	68db      	ldr	r3, [r3, #12]
+ 8002200:	f8d5 0204 	ldr.w	r0, [r5, #516]	; 0x204
+ 8002204:	4798      	blx	r3
+ 8002206:	2000      	movs	r0, #0
+ 8002208:	bd38      	pop	{r3, r4, r5, pc}
+ 800220a:	2002      	movs	r0, #2
+ 800220c:	bd38      	pop	{r3, r4, r5, pc}
+ 800220e:	bf00      	nop
+
+08002210 :
+ 8002210:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8002212:	f8d0 62b8 	ldr.w	r6, [r0, #696]	; 0x2b8
+ 8002216:	b1d6      	cbz	r6, 800224e 
+ 8002218:	eb01 0381 	add.w	r3, r1, r1, lsl #2
+ 800221c:	eb00 0383 	add.w	r3, r0, r3, lsl #2
+ 8002220:	69df      	ldr	r7, [r3, #28]
+ 8002222:	b14f      	cbz	r7, 8002238 
+ 8002224:	f8d0 22c0 	ldr.w	r2, [r0, #704]	; 0x2c0
+ 8002228:	eb02 1541 	add.w	r5, r2, r1, lsl #5
+ 800222c:	6baa      	ldr	r2, [r5, #56]	; 0x38
+ 800222e:	fbb7 f4f2 	udiv	r4, r7, r2
+ 8002232:	fb02 7414 	mls	r4, r2, r4, r7
+ 8002236:	b11c      	cbz	r4, 8002240 
+ 8002238:	2000      	movs	r0, #0
+ 800223a:	f8c6 0214 	str.w	r0, [r6, #532]	; 0x214
+ 800223e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 8002240:	61dc      	str	r4, [r3, #28]
+ 8002242:	4622      	mov	r2, r4
+ 8002244:	4623      	mov	r3, r4
+ 8002246:	f001 ffa5 	bl	8004194 
+ 800224a:	4620      	mov	r0, r4
+ 800224c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 800224e:	2002      	movs	r0, #2
+ 8002250:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 8002252:	bf00      	nop
+
+08002254 :
+ 8002254:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 8002258:	2700      	movs	r7, #0
+ 800225a:	780b      	ldrb	r3, [r1, #0]
+ 800225c:	b082      	sub	sp, #8
+ 800225e:	f013 0460 	ands.w	r4, r3, #96	; 0x60
+ 8002262:	460d      	mov	r5, r1
+ 8002264:	4606      	mov	r6, r0
+ 8002266:	f8d0 82b8 	ldr.w	r8, [r0, #696]	; 0x2b8
+ 800226a:	f88d 7005 	strb.w	r7, [sp, #5]
+ 800226e:	f8ad 7006 	strh.w	r7, [sp, #6]
+ 8002272:	d00f      	beq.n	8002294 
+ 8002274:	2c20      	cmp	r4, #32
+ 8002276:	d117      	bne.n	80022a8 
+ 8002278:	88cc      	ldrh	r4, [r1, #6]
+ 800227a:	f891 c001 	ldrb.w	ip, [r1, #1]
+ 800227e:	bb64      	cbnz	r4, 80022da 
+ 8002280:	f8d0 32bc 	ldr.w	r3, [r0, #700]	; 0x2bc
+ 8002284:	4622      	mov	r2, r4
+ 8002286:	4660      	mov	r0, ip
+ 8002288:	689b      	ldr	r3, [r3, #8]
+ 800228a:	4798      	blx	r3
+ 800228c:	4620      	mov	r0, r4
+ 800228e:	b002      	add	sp, #8
+ 8002290:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 8002294:	784f      	ldrb	r7, [r1, #1]
+ 8002296:	2f0a      	cmp	r7, #10
+ 8002298:	d014      	beq.n	80022c4 
+ 800229a:	2f0b      	cmp	r7, #11
+ 800229c:	d00c      	beq.n	80022b8 
+ 800229e:	b91f      	cbnz	r7, 80022a8 
+ 80022a0:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 80022a4:	2b03      	cmp	r3, #3
+ 80022a6:	d028      	beq.n	80022fa 
+ 80022a8:	4630      	mov	r0, r6
+ 80022aa:	4629      	mov	r1, r5
+ 80022ac:	f000 fc84 	bl	8002bb8 
+ 80022b0:	2002      	movs	r0, #2
+ 80022b2:	b002      	add	sp, #8
+ 80022b4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 80022b8:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 80022bc:	2b03      	cmp	r3, #3
+ 80022be:	d1f3      	bne.n	80022a8 
+ 80022c0:	4620      	mov	r0, r4
+ 80022c2:	e7f6      	b.n	80022b2 
+ 80022c4:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 80022c8:	2b03      	cmp	r3, #3
+ 80022ca:	d1ed      	bne.n	80022a8 
+ 80022cc:	2201      	movs	r2, #1
+ 80022ce:	f10d 0105 	add.w	r1, sp, #5
+ 80022d2:	f000 fca3 	bl	8002c1c 
+ 80022d6:	4620      	mov	r0, r4
+ 80022d8:	e7eb      	b.n	80022b2 
+ 80022da:	061b      	lsls	r3, r3, #24
+ 80022dc:	d514      	bpl.n	8002308 
+ 80022de:	f8d0 32bc 	ldr.w	r3, [r0, #700]	; 0x2bc
+ 80022e2:	4622      	mov	r2, r4
+ 80022e4:	4660      	mov	r0, ip
+ 80022e6:	689b      	ldr	r3, [r3, #8]
+ 80022e8:	4641      	mov	r1, r8
+ 80022ea:	4798      	blx	r3
+ 80022ec:	88ea      	ldrh	r2, [r5, #6]
+ 80022ee:	4641      	mov	r1, r8
+ 80022f0:	4630      	mov	r0, r6
+ 80022f2:	f000 fc93 	bl	8002c1c 
+ 80022f6:	4638      	mov	r0, r7
+ 80022f8:	e7db      	b.n	80022b2 
+ 80022fa:	2202      	movs	r2, #2
+ 80022fc:	f10d 0106 	add.w	r1, sp, #6
+ 8002300:	f000 fc8c 	bl	8002c1c 
+ 8002304:	4638      	mov	r0, r7
+ 8002306:	e7d4      	b.n	80022b2 
+ 8002308:	f888 c200 	strb.w	ip, [r8, #512]	; 0x200
+ 800230c:	f888 4201 	strb.w	r4, [r8, #513]	; 0x201
+ 8002310:	4622      	mov	r2, r4
+ 8002312:	4641      	mov	r1, r8
+ 8002314:	f000 fc98 	bl	8002c48 
+ 8002318:	4638      	mov	r0, r7
+ 800231a:	e7ca      	b.n	80022b2 
+
+0800231c :
+ 800231c:	b538      	push	{r3, r4, r5, lr}
+ 800231e:	4604      	mov	r4, r0
+ 8002320:	2500      	movs	r5, #0
+ 8002322:	2181      	movs	r1, #129	; 0x81
+ 8002324:	f001 feee 	bl	8004104 
+ 8002328:	2101      	movs	r1, #1
+ 800232a:	62e5      	str	r5, [r4, #44]	; 0x2c
+ 800232c:	4620      	mov	r0, r4
+ 800232e:	f001 fee9 	bl	8004104 
+ 8002332:	f8c4 516c 	str.w	r5, [r4, #364]	; 0x16c
+ 8002336:	4620      	mov	r0, r4
+ 8002338:	2182      	movs	r1, #130	; 0x82
+ 800233a:	f001 fee3 	bl	8004104 
+ 800233e:	f8d4 32b8 	ldr.w	r3, [r4, #696]	; 0x2b8
+ 8002342:	6425      	str	r5, [r4, #64]	; 0x40
+ 8002344:	b14b      	cbz	r3, 800235a 
+ 8002346:	f8d4 32bc 	ldr.w	r3, [r4, #700]	; 0x2bc
+ 800234a:	685b      	ldr	r3, [r3, #4]
+ 800234c:	4798      	blx	r3
+ 800234e:	f8d4 02b8 	ldr.w	r0, [r4, #696]	; 0x2b8
+ 8002352:	f001 ff43 	bl	80041dc 
+ 8002356:	f8c4 52b8 	str.w	r5, [r4, #696]	; 0x2b8
+ 800235a:	2000      	movs	r0, #0
+ 800235c:	bd38      	pop	{r3, r4, r5, pc}
+ 800235e:	bf00      	nop
+
+08002360 :
+ 8002360:	7c03      	ldrb	r3, [r0, #16]
+ 8002362:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 8002366:	4604      	mov	r4, r0
+ 8002368:	2501      	movs	r5, #1
+ 800236a:	bbbb      	cbnz	r3, 80023dc 
+ 800236c:	f44f 7300 	mov.w	r3, #512	; 0x200
+ 8002370:	2202      	movs	r2, #2
+ 8002372:	2181      	movs	r1, #129	; 0x81
+ 8002374:	f001 feb6 	bl	80040e4 
+ 8002378:	62e5      	str	r5, [r4, #44]	; 0x2c
+ 800237a:	4629      	mov	r1, r5
+ 800237c:	f44f 7300 	mov.w	r3, #512	; 0x200
+ 8002380:	2202      	movs	r2, #2
+ 8002382:	4620      	mov	r0, r4
+ 8002384:	f001 feae 	bl	80040e4 
+ 8002388:	f8c4 516c 	str.w	r5, [r4, #364]	; 0x16c
+ 800238c:	2701      	movs	r7, #1
+ 800238e:	2308      	movs	r3, #8
+ 8002390:	2203      	movs	r2, #3
+ 8002392:	2182      	movs	r1, #130	; 0x82
+ 8002394:	4620      	mov	r0, r4
+ 8002396:	f001 fea5 	bl	80040e4 
+ 800239a:	6427      	str	r7, [r4, #64]	; 0x40
+ 800239c:	f44f 7007 	mov.w	r0, #540	; 0x21c
+ 80023a0:	f001 ff18 	bl	80041d4 
+ 80023a4:	4605      	mov	r5, r0
+ 80023a6:	f8c4 02b8 	str.w	r0, [r4, #696]	; 0x2b8
+ 80023aa:	b368      	cbz	r0, 8002408 
+ 80023ac:	2600      	movs	r6, #0
+ 80023ae:	f8d4 32bc 	ldr.w	r3, [r4, #700]	; 0x2bc
+ 80023b2:	681b      	ldr	r3, [r3, #0]
+ 80023b4:	4798      	blx	r3
+ 80023b6:	f894 8010 	ldrb.w	r8, [r4, #16]
+ 80023ba:	f8d5 2204 	ldr.w	r2, [r5, #516]	; 0x204
+ 80023be:	f8c5 6214 	str.w	r6, [r5, #532]	; 0x214
+ 80023c2:	4639      	mov	r1, r7
+ 80023c4:	f8c5 6218 	str.w	r6, [r5, #536]	; 0x218
+ 80023c8:	4620      	mov	r0, r4
+ 80023ca:	f1b8 0f00 	cmp.w	r8, #0
+ 80023ce:	d014      	beq.n	80023fa 
+ 80023d0:	2340      	movs	r3, #64	; 0x40
+ 80023d2:	f001 feed 	bl	80041b0 
+ 80023d6:	4630      	mov	r0, r6
+ 80023d8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 80023dc:	2340      	movs	r3, #64	; 0x40
+ 80023de:	2202      	movs	r2, #2
+ 80023e0:	2181      	movs	r1, #129	; 0x81
+ 80023e2:	f001 fe7f 	bl	80040e4 
+ 80023e6:	62e5      	str	r5, [r4, #44]	; 0x2c
+ 80023e8:	4629      	mov	r1, r5
+ 80023ea:	2340      	movs	r3, #64	; 0x40
+ 80023ec:	2202      	movs	r2, #2
+ 80023ee:	4620      	mov	r0, r4
+ 80023f0:	f001 fe78 	bl	80040e4 
+ 80023f4:	f8c4 516c 	str.w	r5, [r4, #364]	; 0x16c
+ 80023f8:	e7c8      	b.n	800238c 
+ 80023fa:	f44f 7300 	mov.w	r3, #512	; 0x200
+ 80023fe:	f001 fed7 	bl	80041b0 
+ 8002402:	4640      	mov	r0, r8
+ 8002404:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 8002408:	4638      	mov	r0, r7
+ 800240a:	e7e5      	b.n	80023d8 
+
+0800240c :
+ 800240c:	b119      	cbz	r1, 8002416 
+ 800240e:	f8c0 12bc 	str.w	r1, [r0, #700]	; 0x2bc
+ 8002412:	2000      	movs	r0, #0
+ 8002414:	4770      	bx	lr
+ 8002416:	2002      	movs	r0, #2
+ 8002418:	4770      	bx	lr
+ 800241a:	bf00      	nop
+
+0800241c :
+ 800241c:	f8d0 32b8 	ldr.w	r3, [r0, #696]	; 0x2b8
+ 8002420:	2000      	movs	r0, #0
+ 8002422:	f8c3 1208 	str.w	r1, [r3, #520]	; 0x208
+ 8002426:	f8c3 2210 	str.w	r2, [r3, #528]	; 0x210
+ 800242a:	4770      	bx	lr
+
+0800242c :
+ 800242c:	f8d0 32b8 	ldr.w	r3, [r0, #696]	; 0x2b8
+ 8002430:	2000      	movs	r0, #0
+ 8002432:	f8c3 1204 	str.w	r1, [r3, #516]	; 0x204
+ 8002436:	4770      	bx	lr
+
+08002438 :
+ 8002438:	f8d0 22b8 	ldr.w	r2, [r0, #696]	; 0x2b8
+ 800243c:	b18a      	cbz	r2, 8002462 
+ 800243e:	b510      	push	{r4, lr}
+ 8002440:	7c04      	ldrb	r4, [r0, #16]
+ 8002442:	f8d2 2204 	ldr.w	r2, [r2, #516]	; 0x204
+ 8002446:	b12c      	cbz	r4, 8002454 
+ 8002448:	2340      	movs	r3, #64	; 0x40
+ 800244a:	2101      	movs	r1, #1
+ 800244c:	f001 feb0 	bl	80041b0 
+ 8002450:	2000      	movs	r0, #0
+ 8002452:	bd10      	pop	{r4, pc}
+ 8002454:	f44f 7300 	mov.w	r3, #512	; 0x200
+ 8002458:	2101      	movs	r1, #1
+ 800245a:	f001 fea9 	bl	80041b0 
+ 800245e:	4620      	mov	r0, r4
+ 8002460:	bd10      	pop	{r4, pc}
+ 8002462:	2002      	movs	r0, #2
+ 8002464:	4770      	bx	lr
+ 8002466:	bf00      	nop
+
+08002468 :
+ 8002468:	b188      	cbz	r0, 800248e 
+ 800246a:	b508      	push	{r3, lr}
+ 800246c:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 8002470:	b113      	cbz	r3, 8002478 
+ 8002472:	2300      	movs	r3, #0
+ 8002474:	f8c0 32b4 	str.w	r3, [r0, #692]	; 0x2b4
+ 8002478:	b109      	cbz	r1, 800247e 
+ 800247a:	f8c0 12b0 	str.w	r1, [r0, #688]	; 0x2b0
+ 800247e:	2301      	movs	r3, #1
+ 8002480:	7002      	strb	r2, [r0, #0]
+ 8002482:	f880 329c 	strb.w	r3, [r0, #668]	; 0x29c
+ 8002486:	f001 fddd 	bl	8004044 
+ 800248a:	2000      	movs	r0, #0
+ 800248c:	bd08      	pop	{r3, pc}
+ 800248e:	2002      	movs	r0, #2
+ 8002490:	4770      	bx	lr
+ 8002492:	bf00      	nop
+
+08002494 :
+ 8002494:	b119      	cbz	r1, 800249e 
+ 8002496:	f8c0 12b4 	str.w	r1, [r0, #692]	; 0x2b4
+ 800249a:	2000      	movs	r0, #0
+ 800249c:	4770      	bx	lr
+ 800249e:	2002      	movs	r0, #2
+ 80024a0:	4770      	bx	lr
+ 80024a2:	bf00      	nop
+
+080024a4 :
+ 80024a4:	b508      	push	{r3, lr}
+ 80024a6:	f001 fe0f 	bl	80040c8 
+ 80024aa:	2000      	movs	r0, #0
+ 80024ac:	bd08      	pop	{r3, pc}
+ 80024ae:	bf00      	nop
+
+080024b0 :
+ 80024b0:	b508      	push	{r3, lr}
+ 80024b2:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 80024b6:	b11b      	cbz	r3, 80024c0 
+ 80024b8:	681b      	ldr	r3, [r3, #0]
+ 80024ba:	4798      	blx	r3
+ 80024bc:	b900      	cbnz	r0, 80024c0 
+ 80024be:	bd08      	pop	{r3, pc}
+ 80024c0:	2002      	movs	r0, #2
+ 80024c2:	bd08      	pop	{r3, pc}
+
+080024c4 :
+ 80024c4:	b508      	push	{r3, lr}
+ 80024c6:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 80024ca:	685b      	ldr	r3, [r3, #4]
+ 80024cc:	4798      	blx	r3
+ 80024ce:	2000      	movs	r0, #0
+ 80024d0:	bd08      	pop	{r3, pc}
+ 80024d2:	bf00      	nop
+
+080024d4 :
+ 80024d4:	b538      	push	{r3, r4, r5, lr}
+ 80024d6:	4604      	mov	r4, r0
+ 80024d8:	f500 752a 	add.w	r5, r0, #680	; 0x2a8
+ 80024dc:	4628      	mov	r0, r5
+ 80024de:	f000 fb57 	bl	8002b90 
+ 80024e2:	2001      	movs	r0, #1
+ 80024e4:	f894 12a8 	ldrb.w	r1, [r4, #680]	; 0x2a8
+ 80024e8:	f8b4 22ae 	ldrh.w	r2, [r4, #686]	; 0x2ae
+ 80024ec:	f001 031f 	and.w	r3, r1, #31
+ 80024f0:	4283      	cmp	r3, r0
+ 80024f2:	f8c4 0294 	str.w	r0, [r4, #660]	; 0x294
+ 80024f6:	f8c4 2298 	str.w	r2, [r4, #664]	; 0x298
+ 80024fa:	d015      	beq.n	8002528 
+ 80024fc:	d30e      	bcc.n	800251c 
+ 80024fe:	2b02      	cmp	r3, #2
+ 8002500:	d006      	beq.n	8002510 
+ 8002502:	f001 0180 	and.w	r1, r1, #128	; 0x80
+ 8002506:	4620      	mov	r0, r4
+ 8002508:	f001 fe0a 	bl	8004120 
+ 800250c:	2000      	movs	r0, #0
+ 800250e:	bd38      	pop	{r3, r4, r5, pc}
+ 8002510:	4629      	mov	r1, r5
+ 8002512:	4620      	mov	r0, r4
+ 8002514:	f000 faa6 	bl	8002a64 
+ 8002518:	2000      	movs	r0, #0
+ 800251a:	bd38      	pop	{r3, r4, r5, pc}
+ 800251c:	4629      	mov	r1, r5
+ 800251e:	4620      	mov	r0, r4
+ 8002520:	f000 f8f6 	bl	8002710 
+ 8002524:	2000      	movs	r0, #0
+ 8002526:	bd38      	pop	{r3, r4, r5, pc}
+ 8002528:	4629      	mov	r1, r5
+ 800252a:	4620      	mov	r0, r4
+ 800252c:	f000 fa6e 	bl	8002a0c 
+ 8002530:	2000      	movs	r0, #0
+ 8002532:	bd38      	pop	{r3, r4, r5, pc}
+
+08002534 :
+ 8002534:	b570      	push	{r4, r5, r6, lr}
+ 8002536:	4605      	mov	r5, r0
+ 8002538:	b941      	cbnz	r1, 800254c 
+ 800253a:	f8d0 3294 	ldr.w	r3, [r0, #660]	; 0x294
+ 800253e:	2b03      	cmp	r3, #3
+ 8002540:	d00f      	beq.n	8002562 
+ 8002542:	2b05      	cmp	r3, #5
+ 8002544:	460c      	mov	r4, r1
+ 8002546:	d02e      	beq.n	80025a6 
+ 8002548:	2000      	movs	r0, #0
+ 800254a:	bd70      	pop	{r4, r5, r6, pc}
+ 800254c:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 8002550:	699b      	ldr	r3, [r3, #24]
+ 8002552:	b1c3      	cbz	r3, 8002586 
+ 8002554:	f890 229c 	ldrb.w	r2, [r0, #668]	; 0x29c
+ 8002558:	2a03      	cmp	r2, #3
+ 800255a:	d114      	bne.n	8002586 
+ 800255c:	4798      	blx	r3
+ 800255e:	2000      	movs	r0, #0
+ 8002560:	bd70      	pop	{r4, r5, r6, pc}
+ 8002562:	4616      	mov	r6, r2
+ 8002564:	f8d0 3160 	ldr.w	r3, [r0, #352]	; 0x160
+ 8002568:	f8d0 2164 	ldr.w	r2, [r0, #356]	; 0x164
+ 800256c:	4293      	cmp	r3, r2
+ 800256e:	d90c      	bls.n	800258a 
+ 8002570:	1a9b      	subs	r3, r3, r2
+ 8002572:	429a      	cmp	r2, r3
+ 8002574:	f8c0 3160 	str.w	r3, [r0, #352]	; 0x160
+ 8002578:	bf8c      	ite	hi
+ 800257a:	b29a      	uxthhi	r2, r3
+ 800257c:	b292      	uxthls	r2, r2
+ 800257e:	4631      	mov	r1, r6
+ 8002580:	f000 fb72 	bl	8002c68 
+ 8002584:	e7e0      	b.n	8002548 
+ 8002586:	2002      	movs	r0, #2
+ 8002588:	bd70      	pop	{r4, r5, r6, pc}
+ 800258a:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 800258e:	691b      	ldr	r3, [r3, #16]
+ 8002590:	b123      	cbz	r3, 800259c 
+ 8002592:	f890 229c 	ldrb.w	r2, [r0, #668]	; 0x29c
+ 8002596:	2a03      	cmp	r2, #3
+ 8002598:	d100      	bne.n	800259c 
+ 800259a:	4798      	blx	r3
+ 800259c:	4628      	mov	r0, r5
+ 800259e:	f000 fb6b 	bl	8002c78 
+ 80025a2:	2000      	movs	r0, #0
+ 80025a4:	bd70      	pop	{r4, r5, r6, pc}
+ 80025a6:	f8c5 1294 	str.w	r1, [r5, #660]	; 0x294
+ 80025aa:	f001 fdb9 	bl	8004120 
+ 80025ae:	4620      	mov	r0, r4
+ 80025b0:	bd70      	pop	{r4, r5, r6, pc}
+ 80025b2:	bf00      	nop
+
+080025b4 :
+ 80025b4:	b570      	push	{r4, r5, r6, lr}
+ 80025b6:	4604      	mov	r4, r0
+ 80025b8:	b981      	cbnz	r1, 80025dc 
+ 80025ba:	4613      	mov	r3, r2
+ 80025bc:	f8d0 2294 	ldr.w	r2, [r0, #660]	; 0x294
+ 80025c0:	2a02      	cmp	r2, #2
+ 80025c2:	d019      	beq.n	80025f8 
+ 80025c4:	f032 0304 	bics.w	r3, r2, #4
+ 80025c8:	d102      	bne.n	80025d0 
+ 80025ca:	2180      	movs	r1, #128	; 0x80
+ 80025cc:	f001 fda8 	bl	8004120 
+ 80025d0:	f894 32a0 	ldrb.w	r3, [r4, #672]	; 0x2a0
+ 80025d4:	2000      	movs	r0, #0
+ 80025d6:	2b01      	cmp	r3, #1
+ 80025d8:	d00b      	beq.n	80025f2 
+ 80025da:	bd70      	pop	{r4, r5, r6, pc}
+ 80025dc:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 80025e0:	695b      	ldr	r3, [r3, #20]
+ 80025e2:	b363      	cbz	r3, 800263e 
+ 80025e4:	f890 229c 	ldrb.w	r2, [r0, #668]	; 0x29c
+ 80025e8:	2a03      	cmp	r2, #3
+ 80025ea:	d128      	bne.n	800263e 
+ 80025ec:	4798      	blx	r3
+ 80025ee:	2000      	movs	r0, #0
+ 80025f0:	bd70      	pop	{r4, r5, r6, pc}
+ 80025f2:	f884 02a0 	strb.w	r0, [r4, #672]	; 0x2a0
+ 80025f6:	bd70      	pop	{r4, r5, r6, pc}
+ 80025f8:	e9d0 6208 	ldrd	r6, r2, [r0, #32]
+ 80025fc:	4296      	cmp	r6, r2
+ 80025fe:	d820      	bhi.n	8002642 
+ 8002600:	69c3      	ldr	r3, [r0, #28]
+ 8002602:	fbb3 f5f2 	udiv	r5, r3, r2
+ 8002606:	fb02 3515 	mls	r5, r2, r5, r3
+ 800260a:	b90d      	cbnz	r5, 8002610 
+ 800260c:	429a      	cmp	r2, r3
+ 800260e:	d926      	bls.n	800265e 
+ 8002610:	f8d4 32b4 	ldr.w	r3, [r4, #692]	; 0x2b4
+ 8002614:	68db      	ldr	r3, [r3, #12]
+ 8002616:	b12b      	cbz	r3, 8002624 
+ 8002618:	f894 229c 	ldrb.w	r2, [r4, #668]	; 0x29c
+ 800261c:	2a03      	cmp	r2, #3
+ 800261e:	d101      	bne.n	8002624 
+ 8002620:	4620      	mov	r0, r4
+ 8002622:	4798      	blx	r3
+ 8002624:	2180      	movs	r1, #128	; 0x80
+ 8002626:	4620      	mov	r0, r4
+ 8002628:	f001 fd7a 	bl	8004120 
+ 800262c:	4620      	mov	r0, r4
+ 800262e:	f000 fb2f 	bl	8002c90 
+ 8002632:	f894 32a0 	ldrb.w	r3, [r4, #672]	; 0x2a0
+ 8002636:	2000      	movs	r0, #0
+ 8002638:	2b01      	cmp	r3, #1
+ 800263a:	d1ce      	bne.n	80025da 
+ 800263c:	e7d9      	b.n	80025f2 
+ 800263e:	2002      	movs	r0, #2
+ 8002640:	bd70      	pop	{r4, r5, r6, pc}
+ 8002642:	1ab2      	subs	r2, r6, r2
+ 8002644:	460d      	mov	r5, r1
+ 8002646:	6202      	str	r2, [r0, #32]
+ 8002648:	4619      	mov	r1, r3
+ 800264a:	b292      	uxth	r2, r2
+ 800264c:	f000 faf4 	bl	8002c38 
+ 8002650:	462b      	mov	r3, r5
+ 8002652:	462a      	mov	r2, r5
+ 8002654:	4629      	mov	r1, r5
+ 8002656:	4620      	mov	r0, r4
+ 8002658:	f001 fdaa 	bl	80041b0 
+ 800265c:	e7b8      	b.n	80025d0 
+ 800265e:	f8d0 2298 	ldr.w	r2, [r0, #664]	; 0x298
+ 8002662:	4293      	cmp	r3, r2
+ 8002664:	d2d4      	bcs.n	8002610 
+ 8002666:	462a      	mov	r2, r5
+ 8002668:	f000 fae6 	bl	8002c38 
+ 800266c:	f8c4 5298 	str.w	r5, [r4, #664]	; 0x298
+ 8002670:	e7ee      	b.n	8002650 
+ 8002672:	bf00      	nop
+
+08002674 :
+ 8002674:	b570      	push	{r4, r5, r6, lr}
+ 8002676:	2200      	movs	r2, #0
+ 8002678:	2640      	movs	r6, #64	; 0x40
+ 800267a:	4604      	mov	r4, r0
+ 800267c:	2501      	movs	r5, #1
+ 800267e:	4611      	mov	r1, r2
+ 8002680:	4633      	mov	r3, r6
+ 8002682:	f001 fd2f 	bl	80040e4 
+ 8002686:	4633      	mov	r3, r6
+ 8002688:	2180      	movs	r1, #128	; 0x80
+ 800268a:	f8c4 5158 	str.w	r5, [r4, #344]	; 0x158
+ 800268e:	f8c4 6164 	str.w	r6, [r4, #356]	; 0x164
+ 8002692:	4620      	mov	r0, r4
+ 8002694:	2200      	movs	r2, #0
+ 8002696:	f001 fd25 	bl	80040e4 
+ 800269a:	2100      	movs	r1, #0
+ 800269c:	f8d4 32b8 	ldr.w	r3, [r4, #696]	; 0x2b8
+ 80026a0:	61a5      	str	r5, [r4, #24]
+ 80026a2:	6266      	str	r6, [r4, #36]	; 0x24
+ 80026a4:	f884 529c 	strb.w	r5, [r4, #668]	; 0x29c
+ 80026a8:	f8c4 1294 	str.w	r1, [r4, #660]	; 0x294
+ 80026ac:	6061      	str	r1, [r4, #4]
+ 80026ae:	f8c4 12a4 	str.w	r1, [r4, #676]	; 0x2a4
+ 80026b2:	b123      	cbz	r3, 80026be 
+ 80026b4:	f8d4 32b4 	ldr.w	r3, [r4, #692]	; 0x2b4
+ 80026b8:	4620      	mov	r0, r4
+ 80026ba:	685b      	ldr	r3, [r3, #4]
+ 80026bc:	4798      	blx	r3
+ 80026be:	2000      	movs	r0, #0
+ 80026c0:	bd70      	pop	{r4, r5, r6, pc}
+ 80026c2:	bf00      	nop
+
+080026c4 :
+ 80026c4:	7401      	strb	r1, [r0, #16]
+ 80026c6:	2000      	movs	r0, #0
+ 80026c8:	4770      	bx	lr
+ 80026ca:	bf00      	nop
+
+080026cc :
+ 80026cc:	4603      	mov	r3, r0
+ 80026ce:	2204      	movs	r2, #4
+ 80026d0:	f890 129c 	ldrb.w	r1, [r0, #668]	; 0x29c
+ 80026d4:	2000      	movs	r0, #0
+ 80026d6:	f883 129d 	strb.w	r1, [r3, #669]	; 0x29d
+ 80026da:	f883 229c 	strb.w	r2, [r3, #668]	; 0x29c
+ 80026de:	4770      	bx	lr
+
+080026e0 :
+ 80026e0:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 80026e4:	2b04      	cmp	r3, #4
+ 80026e6:	bf04      	itt	eq
+ 80026e8:	f890 329d 	ldrbeq.w	r3, [r0, #669]	; 0x29d
+ 80026ec:	f880 329c 	strbeq.w	r3, [r0, #668]	; 0x29c
+ 80026f0:	2000      	movs	r0, #0
+ 80026f2:	4770      	bx	lr
+
+080026f4 :
+ 80026f4:	f890 229c 	ldrb.w	r2, [r0, #668]	; 0x29c
+ 80026f8:	2a03      	cmp	r2, #3
+ 80026fa:	d001      	beq.n	8002700 
+ 80026fc:	2000      	movs	r0, #0
+ 80026fe:	4770      	bx	lr
+ 8002700:	b508      	push	{r3, lr}
+ 8002702:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 8002706:	69db      	ldr	r3, [r3, #28]
+ 8002708:	b103      	cbz	r3, 800270c 
+ 800270a:	4798      	blx	r3
+ 800270c:	2000      	movs	r0, #0
+ 800270e:	bd08      	pop	{r3, pc}
+
+08002710 :
+ 8002710:	b530      	push	{r4, r5, lr}
+ 8002712:	780b      	ldrb	r3, [r1, #0]
+ 8002714:	b083      	sub	sp, #12
+ 8002716:	f003 0360 	and.w	r3, r3, #96	; 0x60
+ 800271a:	2b20      	cmp	r3, #32
+ 800271c:	460d      	mov	r5, r1
+ 800271e:	4604      	mov	r4, r0
+ 8002720:	d028      	beq.n	8002774 
+ 8002722:	2b40      	cmp	r3, #64	; 0x40
+ 8002724:	d026      	beq.n	8002774 
+ 8002726:	b153      	cbz	r3, 800273e 
+ 8002728:	2180      	movs	r1, #128	; 0x80
+ 800272a:	4620      	mov	r0, r4
+ 800272c:	f001 fcf8 	bl	8004120 
+ 8002730:	4620      	mov	r0, r4
+ 8002732:	2100      	movs	r1, #0
+ 8002734:	f001 fcf4 	bl	8004120 
+ 8002738:	2000      	movs	r0, #0
+ 800273a:	b003      	add	sp, #12
+ 800273c:	bd30      	pop	{r4, r5, pc}
+ 800273e:	784b      	ldrb	r3, [r1, #1]
+ 8002740:	2b09      	cmp	r3, #9
+ 8002742:	d8f1      	bhi.n	8002728 
+ 8002744:	a201      	add	r2, pc, #4	; (adr r2, 800274c )
+ 8002746:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 800274a:	bf00      	nop
+ 800274c:	080027c9 	.word	0x080027c9
+ 8002750:	080027f5 	.word	0x080027f5
+ 8002754:	08002729 	.word	0x08002729
+ 8002758:	08002811 	.word	0x08002811
+ 800275c:	08002729 	.word	0x08002729
+ 8002760:	0800281d 	.word	0x0800281d
+ 8002764:	0800285b 	.word	0x0800285b
+ 8002768:	08002729 	.word	0x08002729
+ 800276c:	08002891 	.word	0x08002891
+ 8002770:	08002787 	.word	0x08002787
+ 8002774:	f8d4 32b4 	ldr.w	r3, [r4, #692]	; 0x2b4
+ 8002778:	4629      	mov	r1, r5
+ 800277a:	689b      	ldr	r3, [r3, #8]
+ 800277c:	4620      	mov	r0, r4
+ 800277e:	4798      	blx	r3
+ 8002780:	2000      	movs	r0, #0
+ 8002782:	b003      	add	sp, #12
+ 8002784:	bd30      	pop	{r4, r5, pc}
+ 8002786:	7889      	ldrb	r1, [r1, #2]
+ 8002788:	4d9f      	ldr	r5, [pc, #636]	; (8002a08 )
+ 800278a:	2901      	cmp	r1, #1
+ 800278c:	7029      	strb	r1, [r5, #0]
+ 800278e:	d8cb      	bhi.n	8002728 
+ 8002790:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 8002794:	2b02      	cmp	r3, #2
+ 8002796:	f000 810d 	beq.w	80029b4 
+ 800279a:	2b03      	cmp	r3, #3
+ 800279c:	f040 80fe 	bne.w	800299c 
+ 80027a0:	2900      	cmp	r1, #0
+ 80027a2:	f000 8127 	beq.w	80029f4 
+ 80027a6:	6841      	ldr	r1, [r0, #4]
+ 80027a8:	2901      	cmp	r1, #1
+ 80027aa:	d009      	beq.n	80027c0 
+ 80027ac:	b2c9      	uxtb	r1, r1
+ 80027ae:	f7ff fe89 	bl	80024c4 
+ 80027b2:	7829      	ldrb	r1, [r5, #0]
+ 80027b4:	4620      	mov	r0, r4
+ 80027b6:	6061      	str	r1, [r4, #4]
+ 80027b8:	f7ff fe7a 	bl	80024b0 
+ 80027bc:	2802      	cmp	r0, #2
+ 80027be:	d0b3      	beq.n	8002728 
+ 80027c0:	4620      	mov	r0, r4
+ 80027c2:	f000 fa59 	bl	8002c78 
+ 80027c6:	e7b7      	b.n	8002738 
+ 80027c8:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 80027cc:	2203      	movs	r2, #3
+ 80027ce:	3b01      	subs	r3, #1
+ 80027d0:	2b02      	cmp	r3, #2
+ 80027d2:	d8a9      	bhi.n	8002728 
+ 80027d4:	88cb      	ldrh	r3, [r1, #6]
+ 80027d6:	2b02      	cmp	r3, #2
+ 80027d8:	d1a6      	bne.n	8002728 
+ 80027da:	2101      	movs	r1, #1
+ 80027dc:	f8d0 32a4 	ldr.w	r3, [r0, #676]	; 0x2a4
+ 80027e0:	60c1      	str	r1, [r0, #12]
+ 80027e2:	b103      	cbz	r3, 80027e6 
+ 80027e4:	60c2      	str	r2, [r0, #12]
+ 80027e6:	2202      	movs	r2, #2
+ 80027e8:	f104 010c 	add.w	r1, r4, #12
+ 80027ec:	4620      	mov	r0, r4
+ 80027ee:	f000 fa15 	bl	8002c1c 
+ 80027f2:	e7a1      	b.n	8002738 
+ 80027f4:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 80027f8:	3b01      	subs	r3, #1
+ 80027fa:	2b02      	cmp	r3, #2
+ 80027fc:	d894      	bhi.n	8002728 
+ 80027fe:	884b      	ldrh	r3, [r1, #2]
+ 8002800:	2b01      	cmp	r3, #1
+ 8002802:	d199      	bne.n	8002738 
+ 8002804:	2300      	movs	r3, #0
+ 8002806:	f8c0 32a4 	str.w	r3, [r0, #676]	; 0x2a4
+ 800280a:	f000 fa35 	bl	8002c78 
+ 800280e:	e793      	b.n	8002738 
+ 8002810:	884b      	ldrh	r3, [r1, #2]
+ 8002812:	2b01      	cmp	r3, #1
+ 8002814:	d190      	bne.n	8002738 
+ 8002816:	f8c0 32a4 	str.w	r3, [r0, #676]	; 0x2a4
+ 800281a:	e7d1      	b.n	80027c0 
+ 800281c:	888b      	ldrh	r3, [r1, #4]
+ 800281e:	2b00      	cmp	r3, #0
+ 8002820:	d182      	bne.n	8002728 
+ 8002822:	88cb      	ldrh	r3, [r1, #6]
+ 8002824:	2b00      	cmp	r3, #0
+ 8002826:	f47f af7f 	bne.w	8002728 
+ 800282a:	884d      	ldrh	r5, [r1, #2]
+ 800282c:	2d7f      	cmp	r5, #127	; 0x7f
+ 800282e:	f63f af7b 	bhi.w	8002728 
+ 8002832:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 8002836:	2b03      	cmp	r3, #3
+ 8002838:	f43f af76 	beq.w	8002728 
+ 800283c:	b2e9      	uxtb	r1, r5
+ 800283e:	f880 129e 	strb.w	r1, [r0, #670]	; 0x29e
+ 8002842:	f001 fc99 	bl	8004178 
+ 8002846:	4620      	mov	r0, r4
+ 8002848:	f000 fa16 	bl	8002c78 
+ 800284c:	2d00      	cmp	r5, #0
+ 800284e:	f000 80cd 	beq.w	80029ec 
+ 8002852:	2302      	movs	r3, #2
+ 8002854:	f884 329c 	strb.w	r3, [r4, #668]	; 0x29c
+ 8002858:	e76e      	b.n	8002738 
+ 800285a:	2300      	movs	r3, #0
+ 800285c:	884a      	ldrh	r2, [r1, #2]
+ 800285e:	f8ad 3006 	strh.w	r3, [sp, #6]
+ 8002862:	0a13      	lsrs	r3, r2, #8
+ 8002864:	3b01      	subs	r3, #1
+ 8002866:	2b06      	cmp	r3, #6
+ 8002868:	f63f af5e 	bhi.w	8002728 
+ 800286c:	a101      	add	r1, pc, #4	; (adr r1, 8002874 )
+ 800286e:	f851 f023 	ldr.w	pc, [r1, r3, lsl #2]
+ 8002872:	bf00      	nop
+ 8002874:	08002929 	.word	0x08002929
+ 8002878:	08002911 	.word	0x08002911
+ 800287c:	08002939 	.word	0x08002939
+ 8002880:	08002729 	.word	0x08002729
+ 8002884:	08002729 	.word	0x08002729
+ 8002888:	080028fb 	.word	0x080028fb
+ 800288c:	080028b7 	.word	0x080028b7
+ 8002890:	88ca      	ldrh	r2, [r1, #6]
+ 8002892:	2a01      	cmp	r2, #1
+ 8002894:	f47f af48 	bne.w	8002728 
+ 8002898:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 800289c:	2b00      	cmp	r3, #0
+ 800289e:	f43f af43 	beq.w	8002728 
+ 80028a2:	2b02      	cmp	r3, #2
+ 80028a4:	f240 8094 	bls.w	80029d0 
+ 80028a8:	2b03      	cmp	r3, #3
+ 80028aa:	f47f af3d 	bne.w	8002728 
+ 80028ae:	1d01      	adds	r1, r0, #4
+ 80028b0:	f000 f9b4 	bl	8002c1c 
+ 80028b4:	e740      	b.n	8002738 
+ 80028b6:	7c03      	ldrb	r3, [r0, #16]
+ 80028b8:	2b00      	cmp	r3, #0
+ 80028ba:	f47f af35 	bne.w	8002728 
+ 80028be:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 80028c2:	f10d 0006 	add.w	r0, sp, #6
+ 80028c6:	6b1b      	ldr	r3, [r3, #48]	; 0x30
+ 80028c8:	4798      	blx	r3
+ 80028ca:	2307      	movs	r3, #7
+ 80028cc:	7043      	strb	r3, [r0, #1]
+ 80028ce:	f8bd 3006 	ldrh.w	r3, [sp, #6]
+ 80028d2:	88ea      	ldrh	r2, [r5, #6]
+ 80028d4:	b16b      	cbz	r3, 80028f2 
+ 80028d6:	2a00      	cmp	r2, #0
+ 80028d8:	f43f af72 	beq.w	80027c0 
+ 80028dc:	4293      	cmp	r3, r2
+ 80028de:	bf28      	it	cs
+ 80028e0:	4613      	movcs	r3, r2
+ 80028e2:	4601      	mov	r1, r0
+ 80028e4:	461a      	mov	r2, r3
+ 80028e6:	4620      	mov	r0, r4
+ 80028e8:	f8ad 3006 	strh.w	r3, [sp, #6]
+ 80028ec:	f000 f996 	bl	8002c1c 
+ 80028f0:	88ea      	ldrh	r2, [r5, #6]
+ 80028f2:	2a00      	cmp	r2, #0
+ 80028f4:	f47f af20 	bne.w	8002738 
+ 80028f8:	e762      	b.n	80027c0 
+ 80028fa:	7c03      	ldrb	r3, [r0, #16]
+ 80028fc:	2b00      	cmp	r3, #0
+ 80028fe:	f47f af13 	bne.w	8002728 
+ 8002902:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 8002906:	f10d 0006 	add.w	r0, sp, #6
+ 800290a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
+ 800290c:	4798      	blx	r3
+ 800290e:	e7de      	b.n	80028ce 
+ 8002910:	7c02      	ldrb	r2, [r0, #16]
+ 8002912:	f8d0 32b4 	ldr.w	r3, [r0, #692]	; 0x2b4
+ 8002916:	2a00      	cmp	r2, #0
+ 8002918:	d161      	bne.n	80029de 
+ 800291a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
+ 800291c:	f10d 0006 	add.w	r0, sp, #6
+ 8002920:	4798      	blx	r3
+ 8002922:	2302      	movs	r3, #2
+ 8002924:	7043      	strb	r3, [r0, #1]
+ 8002926:	e7d2      	b.n	80028ce 
+ 8002928:	f8d0 32b0 	ldr.w	r3, [r0, #688]	; 0x2b0
+ 800292c:	f10d 0106 	add.w	r1, sp, #6
+ 8002930:	681b      	ldr	r3, [r3, #0]
+ 8002932:	7c00      	ldrb	r0, [r0, #16]
+ 8002934:	4798      	blx	r3
+ 8002936:	e7ca      	b.n	80028ce 
+ 8002938:	b2d2      	uxtb	r2, r2
+ 800293a:	2a05      	cmp	r2, #5
+ 800293c:	f63f aef4 	bhi.w	8002728 
+ 8002940:	e8df f002 	tbb	[pc, r2]
+ 8002944:	141a2026 	.word	0x141a2026
+ 8002948:	030e      	.short	0x030e
+ 800294a:	f8d0 32b0 	ldr.w	r3, [r0, #688]	; 0x2b0
+ 800294e:	699b      	ldr	r3, [r3, #24]
+ 8002950:	2b00      	cmp	r3, #0
+ 8002952:	f43f aee9 	beq.w	8002728 
+ 8002956:	f10d 0106 	add.w	r1, sp, #6
+ 800295a:	7c20      	ldrb	r0, [r4, #16]
+ 800295c:	4798      	blx	r3
+ 800295e:	e7b6      	b.n	80028ce 
+ 8002960:	f8d0 32b0 	ldr.w	r3, [r0, #688]	; 0x2b0
+ 8002964:	695b      	ldr	r3, [r3, #20]
+ 8002966:	2b00      	cmp	r3, #0
+ 8002968:	d1f5      	bne.n	8002956 
+ 800296a:	e6dd      	b.n	8002728 
+ 800296c:	f8d0 32b0 	ldr.w	r3, [r0, #688]	; 0x2b0
+ 8002970:	691b      	ldr	r3, [r3, #16]
+ 8002972:	2b00      	cmp	r3, #0
+ 8002974:	d1ef      	bne.n	8002956 
+ 8002976:	e6d7      	b.n	8002728 
+ 8002978:	f8d0 32b0 	ldr.w	r3, [r0, #688]	; 0x2b0
+ 800297c:	68db      	ldr	r3, [r3, #12]
+ 800297e:	2b00      	cmp	r3, #0
+ 8002980:	d1e9      	bne.n	8002956 
+ 8002982:	e6d1      	b.n	8002728 
+ 8002984:	f8d0 32b0 	ldr.w	r3, [r0, #688]	; 0x2b0
+ 8002988:	689b      	ldr	r3, [r3, #8]
+ 800298a:	2b00      	cmp	r3, #0
+ 800298c:	d1e3      	bne.n	8002956 
+ 800298e:	e6cb      	b.n	8002728 
+ 8002990:	f8d0 32b0 	ldr.w	r3, [r0, #688]	; 0x2b0
+ 8002994:	685b      	ldr	r3, [r3, #4]
+ 8002996:	2b00      	cmp	r3, #0
+ 8002998:	d1dd      	bne.n	8002956 
+ 800299a:	e6c5      	b.n	8002728 
+ 800299c:	2180      	movs	r1, #128	; 0x80
+ 800299e:	f001 fbbf 	bl	8004120 
+ 80029a2:	2100      	movs	r1, #0
+ 80029a4:	4620      	mov	r0, r4
+ 80029a6:	f001 fbbb 	bl	8004120 
+ 80029aa:	7829      	ldrb	r1, [r5, #0]
+ 80029ac:	4620      	mov	r0, r4
+ 80029ae:	f7ff fd89 	bl	80024c4 
+ 80029b2:	e6c1      	b.n	8002738 
+ 80029b4:	2900      	cmp	r1, #0
+ 80029b6:	f43f af03 	beq.w	80027c0 
+ 80029ba:	2101      	movs	r1, #1
+ 80029bc:	2303      	movs	r3, #3
+ 80029be:	6041      	str	r1, [r0, #4]
+ 80029c0:	f880 329c 	strb.w	r3, [r0, #668]	; 0x29c
+ 80029c4:	f7ff fd74 	bl	80024b0 
+ 80029c8:	2802      	cmp	r0, #2
+ 80029ca:	f47f aef9 	bne.w	80027c0 
+ 80029ce:	e6ab      	b.n	8002728 
+ 80029d0:	2300      	movs	r3, #0
+ 80029d2:	4601      	mov	r1, r0
+ 80029d4:	f841 3f08 	str.w	r3, [r1, #8]!
+ 80029d8:	f000 f920 	bl	8002c1c 
+ 80029dc:	e6ac      	b.n	8002738 
+ 80029de:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80029e0:	f10d 0006 	add.w	r0, sp, #6
+ 80029e4:	4798      	blx	r3
+ 80029e6:	2302      	movs	r3, #2
+ 80029e8:	7043      	strb	r3, [r0, #1]
+ 80029ea:	e770      	b.n	80028ce 
+ 80029ec:	2301      	movs	r3, #1
+ 80029ee:	f884 329c 	strb.w	r3, [r4, #668]	; 0x29c
+ 80029f2:	e6a1      	b.n	8002738 
+ 80029f4:	2302      	movs	r3, #2
+ 80029f6:	6041      	str	r1, [r0, #4]
+ 80029f8:	f880 329c 	strb.w	r3, [r0, #668]	; 0x29c
+ 80029fc:	f7ff fd62 	bl	80024c4 
+ 8002a00:	4620      	mov	r0, r4
+ 8002a02:	f000 f939 	bl	8002c78 
+ 8002a06:	e697      	b.n	8002738 
+ 8002a08:	2000019c 	.word	0x2000019c
+
+08002a0c :
+ 8002a0c:	b538      	push	{r3, r4, r5, lr}
+ 8002a0e:	780b      	ldrb	r3, [r1, #0]
+ 8002a10:	460d      	mov	r5, r1
+ 8002a12:	f003 0360 	and.w	r3, r3, #96	; 0x60
+ 8002a16:	2b20      	cmp	r3, #32
+ 8002a18:	4604      	mov	r4, r0
+ 8002a1a:	d00c      	beq.n	8002a36 
+ 8002a1c:	2b40      	cmp	r3, #64	; 0x40
+ 8002a1e:	d00a      	beq.n	8002a36 
+ 8002a20:	b14b      	cbz	r3, 8002a36 
+ 8002a22:	2180      	movs	r1, #128	; 0x80
+ 8002a24:	4620      	mov	r0, r4
+ 8002a26:	f001 fb7b 	bl	8004120 
+ 8002a2a:	4620      	mov	r0, r4
+ 8002a2c:	2100      	movs	r1, #0
+ 8002a2e:	f001 fb77 	bl	8004120 
+ 8002a32:	2000      	movs	r0, #0
+ 8002a34:	bd38      	pop	{r3, r4, r5, pc}
+ 8002a36:	f894 329c 	ldrb.w	r3, [r4, #668]	; 0x29c
+ 8002a3a:	3b01      	subs	r3, #1
+ 8002a3c:	2b02      	cmp	r3, #2
+ 8002a3e:	d8f0      	bhi.n	8002a22 
+ 8002a40:	792b      	ldrb	r3, [r5, #4]
+ 8002a42:	2b01      	cmp	r3, #1
+ 8002a44:	d8ed      	bhi.n	8002a22 
+ 8002a46:	f8d4 32b4 	ldr.w	r3, [r4, #692]	; 0x2b4
+ 8002a4a:	4629      	mov	r1, r5
+ 8002a4c:	689b      	ldr	r3, [r3, #8]
+ 8002a4e:	4620      	mov	r0, r4
+ 8002a50:	4798      	blx	r3
+ 8002a52:	88eb      	ldrh	r3, [r5, #6]
+ 8002a54:	2b00      	cmp	r3, #0
+ 8002a56:	d1ec      	bne.n	8002a32 
+ 8002a58:	2800      	cmp	r0, #0
+ 8002a5a:	d1ea      	bne.n	8002a32 
+ 8002a5c:	4620      	mov	r0, r4
+ 8002a5e:	f000 f90b 	bl	8002c78 
+ 8002a62:	e7e6      	b.n	8002a32 
+
+08002a64 :
+ 8002a64:	b570      	push	{r4, r5, r6, lr}
+ 8002a66:	780b      	ldrb	r3, [r1, #0]
+ 8002a68:	4604      	mov	r4, r0
+ 8002a6a:	f003 0360 	and.w	r3, r3, #96	; 0x60
+ 8002a6e:	2b20      	cmp	r3, #32
+ 8002a70:	d00c      	beq.n	8002a8c 
+ 8002a72:	2b40      	cmp	r3, #64	; 0x40
+ 8002a74:	d00a      	beq.n	8002a8c 
+ 8002a76:	b183      	cbz	r3, 8002a9a 
+ 8002a78:	2180      	movs	r1, #128	; 0x80
+ 8002a7a:	4620      	mov	r0, r4
+ 8002a7c:	f001 fb50 	bl	8004120 
+ 8002a80:	4620      	mov	r0, r4
+ 8002a82:	2100      	movs	r1, #0
+ 8002a84:	f001 fb4c 	bl	8004120 
+ 8002a88:	2000      	movs	r0, #0
+ 8002a8a:	bd70      	pop	{r4, r5, r6, pc}
+ 8002a8c:	f8d4 32b4 	ldr.w	r3, [r4, #692]	; 0x2b4
+ 8002a90:	4620      	mov	r0, r4
+ 8002a92:	689b      	ldr	r3, [r3, #8]
+ 8002a94:	4798      	blx	r3
+ 8002a96:	2000      	movs	r0, #0
+ 8002a98:	bd70      	pop	{r4, r5, r6, pc}
+ 8002a9a:	784b      	ldrb	r3, [r1, #1]
+ 8002a9c:	888a      	ldrh	r2, [r1, #4]
+ 8002a9e:	2b01      	cmp	r3, #1
+ 8002aa0:	b2d5      	uxtb	r5, r2
+ 8002aa2:	d03e      	beq.n	8002b22 
+ 8002aa4:	d314      	bcc.n	8002ad0 
+ 8002aa6:	2b03      	cmp	r3, #3
+ 8002aa8:	d1e6      	bne.n	8002a78 
+ 8002aaa:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 8002aae:	2b02      	cmp	r3, #2
+ 8002ab0:	d046      	beq.n	8002b40 
+ 8002ab2:	2b03      	cmp	r3, #3
+ 8002ab4:	d1e0      	bne.n	8002a78 
+ 8002ab6:	884b      	ldrh	r3, [r1, #2]
+ 8002ab8:	b933      	cbnz	r3, 8002ac8 
+ 8002aba:	066a      	lsls	r2, r5, #25
+ 8002abc:	d004      	beq.n	8002ac8 
+ 8002abe:	88cb      	ldrh	r3, [r1, #6]
+ 8002ac0:	b913      	cbnz	r3, 8002ac8 
+ 8002ac2:	4629      	mov	r1, r5
+ 8002ac4:	f001 fb2c 	bl	8004120 
+ 8002ac8:	4620      	mov	r0, r4
+ 8002aca:	f000 f8d5 	bl	8002c78 
+ 8002ace:	e7db      	b.n	8002a88 
+ 8002ad0:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 8002ad4:	2b02      	cmp	r3, #2
+ 8002ad6:	d03d      	beq.n	8002b54 
+ 8002ad8:	2b03      	cmp	r3, #3
+ 8002ada:	d1cd      	bne.n	8002a78 
+ 8002adc:	f005 030f 	and.w	r3, r5, #15
+ 8002ae0:	eb03 0383 	add.w	r3, r3, r3, lsl #2
+ 8002ae4:	0612      	lsls	r2, r2, #24
+ 8002ae6:	eb00 0383 	add.w	r3, r0, r3, lsl #2
+ 8002aea:	d442      	bmi.n	8002b72 
+ 8002aec:	f8d3 3158 	ldr.w	r3, [r3, #344]	; 0x158
+ 8002af0:	2b00      	cmp	r3, #0
+ 8002af2:	d0c1      	beq.n	8002a78 
+ 8002af4:	f005 037f 	and.w	r3, r5, #127	; 0x7f
+ 8002af8:	eb03 0683 	add.w	r6, r3, r3, lsl #2
+ 8002afc:	eb00 0686 	add.w	r6, r0, r6, lsl #2
+ 8002b00:	f506 76aa 	add.w	r6, r6, #340	; 0x154
+ 8002b04:	b133      	cbz	r3, 8002b14 
+ 8002b06:	4629      	mov	r1, r5
+ 8002b08:	4620      	mov	r0, r4
+ 8002b0a:	f001 fb25 	bl	8004158 
+ 8002b0e:	2800      	cmp	r0, #0
+ 8002b10:	d03b      	beq.n	8002b8a 
+ 8002b12:	2301      	movs	r3, #1
+ 8002b14:	6033      	str	r3, [r6, #0]
+ 8002b16:	4631      	mov	r1, r6
+ 8002b18:	4620      	mov	r0, r4
+ 8002b1a:	2202      	movs	r2, #2
+ 8002b1c:	f000 f87e 	bl	8002c1c 
+ 8002b20:	e7b2      	b.n	8002a88 
+ 8002b22:	f890 329c 	ldrb.w	r3, [r0, #668]	; 0x29c
+ 8002b26:	2b02      	cmp	r3, #2
+ 8002b28:	d00a      	beq.n	8002b40 
+ 8002b2a:	2b03      	cmp	r3, #3
+ 8002b2c:	d1a4      	bne.n	8002a78 
+ 8002b2e:	884b      	ldrh	r3, [r1, #2]
+ 8002b30:	2b00      	cmp	r3, #0
+ 8002b32:	d1a9      	bne.n	8002a88 
+ 8002b34:	066e      	lsls	r6, r5, #25
+ 8002b36:	d0c7      	beq.n	8002ac8 
+ 8002b38:	4629      	mov	r1, r5
+ 8002b3a:	f001 faff 	bl	800413c 
+ 8002b3e:	e7c3      	b.n	8002ac8 
+ 8002b40:	066b      	lsls	r3, r5, #25
+ 8002b42:	d099      	beq.n	8002a78 
+ 8002b44:	4629      	mov	r1, r5
+ 8002b46:	f001 faeb 	bl	8004120 
+ 8002b4a:	4620      	mov	r0, r4
+ 8002b4c:	2180      	movs	r1, #128	; 0x80
+ 8002b4e:	f001 fae7 	bl	8004120 
+ 8002b52:	e799      	b.n	8002a88 
+ 8002b54:	0668      	lsls	r0, r5, #25
+ 8002b56:	d18f      	bne.n	8002a78 
+ 8002b58:	2300      	movs	r3, #0
+ 8002b5a:	0611      	lsls	r1, r2, #24
+ 8002b5c:	bf4c      	ite	mi
+ 8002b5e:	f104 0114 	addmi.w	r1, r4, #20
+ 8002b62:	f504 71aa 	addpl.w	r1, r4, #340	; 0x154
+ 8002b66:	4620      	mov	r0, r4
+ 8002b68:	600b      	str	r3, [r1, #0]
+ 8002b6a:	2202      	movs	r2, #2
+ 8002b6c:	f000 f856 	bl	8002c1c 
+ 8002b70:	e78a      	b.n	8002a88 
+ 8002b72:	699b      	ldr	r3, [r3, #24]
+ 8002b74:	2b00      	cmp	r3, #0
+ 8002b76:	f43f af7f 	beq.w	8002a78 
+ 8002b7a:	f005 037f 	and.w	r3, r5, #127	; 0x7f
+ 8002b7e:	1c5e      	adds	r6, r3, #1
+ 8002b80:	eb06 0686 	add.w	r6, r6, r6, lsl #2
+ 8002b84:	eb00 0686 	add.w	r6, r0, r6, lsl #2
+ 8002b88:	e7bc      	b.n	8002b04 
+ 8002b8a:	6030      	str	r0, [r6, #0]
+ 8002b8c:	e7c3      	b.n	8002b16 
+ 8002b8e:	bf00      	nop
+
+08002b90 :
+ 8002b90:	780b      	ldrb	r3, [r1, #0]
+ 8002b92:	7003      	strb	r3, [r0, #0]
+ 8002b94:	784b      	ldrb	r3, [r1, #1]
+ 8002b96:	7043      	strb	r3, [r0, #1]
+ 8002b98:	78ca      	ldrb	r2, [r1, #3]
+ 8002b9a:	788b      	ldrb	r3, [r1, #2]
+ 8002b9c:	eb03 2302 	add.w	r3, r3, r2, lsl #8
+ 8002ba0:	8043      	strh	r3, [r0, #2]
+ 8002ba2:	794a      	ldrb	r2, [r1, #5]
+ 8002ba4:	790b      	ldrb	r3, [r1, #4]
+ 8002ba6:	eb03 2302 	add.w	r3, r3, r2, lsl #8
+ 8002baa:	8083      	strh	r3, [r0, #4]
+ 8002bac:	79ca      	ldrb	r2, [r1, #7]
+ 8002bae:	798b      	ldrb	r3, [r1, #6]
+ 8002bb0:	eb03 2302 	add.w	r3, r3, r2, lsl #8
+ 8002bb4:	80c3      	strh	r3, [r0, #6]
+ 8002bb6:	4770      	bx	lr
+
+08002bb8 :
+ 8002bb8:	b510      	push	{r4, lr}
+ 8002bba:	4604      	mov	r4, r0
+ 8002bbc:	2180      	movs	r1, #128	; 0x80
+ 8002bbe:	f001 faaf 	bl	8004120 
+ 8002bc2:	4620      	mov	r0, r4
+ 8002bc4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+ 8002bc8:	2100      	movs	r1, #0
+ 8002bca:	f001 baa9 	b.w	8004120 
+ 8002bce:	bf00      	nop
+
+08002bd0 :
+ 8002bd0:	b300      	cbz	r0, 8002c14 
+ 8002bd2:	7803      	ldrb	r3, [r0, #0]
+ 8002bd4:	b430      	push	{r4, r5}
+ 8002bd6:	b1f3      	cbz	r3, 8002c16 
+ 8002bd8:	4604      	mov	r4, r0
+ 8002bda:	2300      	movs	r3, #0
+ 8002bdc:	f814 5f01 	ldrb.w	r5, [r4, #1]!
+ 8002be0:	3301      	adds	r3, #1
+ 8002be2:	b2db      	uxtb	r3, r3
+ 8002be4:	2d00      	cmp	r5, #0
+ 8002be6:	d1f9      	bne.n	8002bdc 
+ 8002be8:	005b      	lsls	r3, r3, #1
+ 8002bea:	3302      	adds	r3, #2
+ 8002bec:	2403      	movs	r4, #3
+ 8002bee:	8013      	strh	r3, [r2, #0]
+ 8002bf0:	700b      	strb	r3, [r1, #0]
+ 8002bf2:	704c      	strb	r4, [r1, #1]
+ 8002bf4:	7804      	ldrb	r4, [r0, #0]
+ 8002bf6:	b15c      	cbz	r4, 8002c10 
+ 8002bf8:	2302      	movs	r3, #2
+ 8002bfa:	2500      	movs	r5, #0
+ 8002bfc:	1c5a      	adds	r2, r3, #1
+ 8002bfe:	b2d2      	uxtb	r2, r2
+ 8002c00:	54cc      	strb	r4, [r1, r3]
+ 8002c02:	548d      	strb	r5, [r1, r2]
+ 8002c04:	f810 4f01 	ldrb.w	r4, [r0, #1]!
+ 8002c08:	3302      	adds	r3, #2
+ 8002c0a:	b2db      	uxtb	r3, r3
+ 8002c0c:	2c00      	cmp	r4, #0
+ 8002c0e:	d1f5      	bne.n	8002bfc 
+ 8002c10:	bc30      	pop	{r4, r5}
+ 8002c12:	4770      	bx	lr
+ 8002c14:	4770      	bx	lr
+ 8002c16:	2302      	movs	r3, #2
+ 8002c18:	e7e8      	b.n	8002bec 
+ 8002c1a:	bf00      	nop
+
+08002c1c :
+ 8002c1c:	b538      	push	{r3, r4, r5, lr}
+ 8002c1e:	4613      	mov	r3, r2
+ 8002c20:	2502      	movs	r5, #2
+ 8002c22:	460a      	mov	r2, r1
+ 8002c24:	e9c0 3307 	strd	r3, r3, [r0, #28]
+ 8002c28:	f8c0 5294 	str.w	r5, [r0, #660]	; 0x294
+ 8002c2c:	2100      	movs	r1, #0
+ 8002c2e:	f001 fab1 	bl	8004194 
+ 8002c32:	2000      	movs	r0, #0
+ 8002c34:	bd38      	pop	{r3, r4, r5, pc}
+ 8002c36:	bf00      	nop
+
+08002c38 :
+ 8002c38:	b508      	push	{r3, lr}
+ 8002c3a:	4613      	mov	r3, r2
+ 8002c3c:	460a      	mov	r2, r1
+ 8002c3e:	2100      	movs	r1, #0
+ 8002c40:	f001 faa8 	bl	8004194 
+ 8002c44:	2000      	movs	r0, #0
+ 8002c46:	bd08      	pop	{r3, pc}
+
+08002c48 :
+ 8002c48:	b538      	push	{r3, r4, r5, lr}
+ 8002c4a:	4613      	mov	r3, r2
+ 8002c4c:	2503      	movs	r5, #3
+ 8002c4e:	460a      	mov	r2, r1
+ 8002c50:	f8c0 315c 	str.w	r3, [r0, #348]	; 0x15c
+ 8002c54:	f8c0 3160 	str.w	r3, [r0, #352]	; 0x160
+ 8002c58:	f8c0 5294 	str.w	r5, [r0, #660]	; 0x294
+ 8002c5c:	2100      	movs	r1, #0
+ 8002c5e:	f001 faa7 	bl	80041b0 
+ 8002c62:	2000      	movs	r0, #0
+ 8002c64:	bd38      	pop	{r3, r4, r5, pc}
+ 8002c66:	bf00      	nop
+
+08002c68 :
+ 8002c68:	b508      	push	{r3, lr}
+ 8002c6a:	4613      	mov	r3, r2
+ 8002c6c:	460a      	mov	r2, r1
+ 8002c6e:	2100      	movs	r1, #0
+ 8002c70:	f001 fa9e 	bl	80041b0 
+ 8002c74:	2000      	movs	r0, #0
+ 8002c76:	bd08      	pop	{r3, pc}
+
+08002c78 :
+ 8002c78:	b508      	push	{r3, lr}
+ 8002c7a:	2204      	movs	r2, #4
+ 8002c7c:	2300      	movs	r3, #0
+ 8002c7e:	f8c0 2294 	str.w	r2, [r0, #660]	; 0x294
+ 8002c82:	4619      	mov	r1, r3
+ 8002c84:	461a      	mov	r2, r3
+ 8002c86:	f001 fa85 	bl	8004194 
+ 8002c8a:	2000      	movs	r0, #0
+ 8002c8c:	bd08      	pop	{r3, pc}
+ 8002c8e:	bf00      	nop
+
+08002c90 :
+ 8002c90:	b508      	push	{r3, lr}
+ 8002c92:	2205      	movs	r2, #5
+ 8002c94:	2300      	movs	r3, #0
+ 8002c96:	f8c0 2294 	str.w	r2, [r0, #660]	; 0x294
+ 8002c9a:	4619      	mov	r1, r3
+ 8002c9c:	461a      	mov	r2, r3
+ 8002c9e:	f001 fa87 	bl	80041b0 
+ 8002ca2:	2000      	movs	r0, #0
+ 8002ca4:	bd08      	pop	{r3, pc}
+ 8002ca6:	bf00      	nop
+
+08002ca8 :
+ 8002ca8:	b508      	push	{r3, lr}
+ 8002caa:	f000 fa25 	bl	80030f8 
+ 8002cae:	2000      	movs	r0, #0
+ 8002cb0:	bd08      	pop	{r3, pc}
+ 8002cb2:	bf00      	nop
+
+08002cb4 :
+ 8002cb4:	b530      	push	{r4, r5, lr}
+ 8002cb6:	f9b0 4008 	ldrsh.w	r4, [r0, #8]
+ 8002cba:	4602      	mov	r2, r0
+ 8002cbc:	2c84      	cmp	r4, #132	; 0x84
+ 8002cbe:	bf08      	it	eq
+ 8002cc0:	2400      	moveq	r4, #0
+ 8002cc2:	b085      	sub	sp, #20
+ 8002cc4:	bf18      	it	ne
+ 8002cc6:	3403      	addne	r4, #3
+ 8002cc8:	ad03      	add	r5, sp, #12
+ 8002cca:	460b      	mov	r3, r1
+ 8002ccc:	6840      	ldr	r0, [r0, #4]
+ 8002cce:	6811      	ldr	r1, [r2, #0]
+ 8002cd0:	8a12      	ldrh	r2, [r2, #16]
+ 8002cd2:	e9cd 4500 	strd	r4, r5, [sp]
+ 8002cd6:	f000 f8d9 	bl	8002e8c 
+ 8002cda:	2801      	cmp	r0, #1
+ 8002cdc:	bf14      	ite	ne
+ 8002cde:	2000      	movne	r0, #0
+ 8002ce0:	9803      	ldreq	r0, [sp, #12]
+ 8002ce2:	b005      	add	sp, #20
+ 8002ce4:	bd30      	pop	{r4, r5, pc}
+ 8002ce6:	bf00      	nop
+
+08002ce8 :
+ 8002ce8:	b508      	push	{r3, lr}
+ 8002cea:	2800      	cmp	r0, #0
+ 8002cec:	bf08      	it	eq
+ 8002cee:	2001      	moveq	r0, #1
+ 8002cf0:	f000 fc30 	bl	8003554 
+ 8002cf4:	2000      	movs	r0, #0
+ 8002cf6:	bd08      	pop	{r3, pc}
+
+08002cf8 :
+ 8002cf8:	f04f 31ff 	mov.w	r1, #4294967295	; 0xffffffff
+ 8002cfc:	2200      	movs	r2, #0
+ 8002cfe:	f100 0308 	add.w	r3, r0, #8
+ 8002d02:	6081      	str	r1, [r0, #8]
+ 8002d04:	6002      	str	r2, [r0, #0]
+ 8002d06:	6043      	str	r3, [r0, #4]
+ 8002d08:	e9c0 3303 	strd	r3, r3, [r0, #12]
+ 8002d0c:	4770      	bx	lr
+ 8002d0e:	bf00      	nop
+
+08002d10 :
+ 8002d10:	2300      	movs	r3, #0
+ 8002d12:	6103      	str	r3, [r0, #16]
+ 8002d14:	4770      	bx	lr
+ 8002d16:	bf00      	nop
+
+08002d18 :
+ 8002d18:	6843      	ldr	r3, [r0, #4]
+ 8002d1a:	b410      	push	{r4}
+ 8002d1c:	689c      	ldr	r4, [r3, #8]
+ 8002d1e:	6802      	ldr	r2, [r0, #0]
+ 8002d20:	608c      	str	r4, [r1, #8]
+ 8002d22:	689c      	ldr	r4, [r3, #8]
+ 8002d24:	3201      	adds	r2, #1
+ 8002d26:	604b      	str	r3, [r1, #4]
+ 8002d28:	6061      	str	r1, [r4, #4]
+ 8002d2a:	6099      	str	r1, [r3, #8]
+ 8002d2c:	bc10      	pop	{r4}
+ 8002d2e:	6108      	str	r0, [r1, #16]
+ 8002d30:	6002      	str	r2, [r0, #0]
+ 8002d32:	4770      	bx	lr
+
+08002d34 :
+ 8002d34:	b430      	push	{r4, r5}
+ 8002d36:	680d      	ldr	r5, [r1, #0]
+ 8002d38:	1c6b      	adds	r3, r5, #1
+ 8002d3a:	d011      	beq.n	8002d60 
+ 8002d3c:	f100 0208 	add.w	r2, r0, #8
+ 8002d40:	e000      	b.n	8002d44 
+ 8002d42:	461a      	mov	r2, r3
+ 8002d44:	6853      	ldr	r3, [r2, #4]
+ 8002d46:	681c      	ldr	r4, [r3, #0]
+ 8002d48:	42ac      	cmp	r4, r5
+ 8002d4a:	d9fa      	bls.n	8002d42 
+ 8002d4c:	6804      	ldr	r4, [r0, #0]
+ 8002d4e:	604b      	str	r3, [r1, #4]
+ 8002d50:	3401      	adds	r4, #1
+ 8002d52:	6099      	str	r1, [r3, #8]
+ 8002d54:	608a      	str	r2, [r1, #8]
+ 8002d56:	6051      	str	r1, [r2, #4]
+ 8002d58:	6108      	str	r0, [r1, #16]
+ 8002d5a:	6004      	str	r4, [r0, #0]
+ 8002d5c:	bc30      	pop	{r4, r5}
+ 8002d5e:	4770      	bx	lr
+ 8002d60:	6902      	ldr	r2, [r0, #16]
+ 8002d62:	6853      	ldr	r3, [r2, #4]
+ 8002d64:	e7f2      	b.n	8002d4c 
+ 8002d66:	bf00      	nop
+
+08002d68 :
+ 8002d68:	6903      	ldr	r3, [r0, #16]
+ 8002d6a:	b410      	push	{r4}
+ 8002d6c:	e9d0 2101 	ldrd	r2, r1, [r0, #4]
+ 8002d70:	685c      	ldr	r4, [r3, #4]
+ 8002d72:	6091      	str	r1, [r2, #8]
+ 8002d74:	6881      	ldr	r1, [r0, #8]
+ 8002d76:	4284      	cmp	r4, r0
+ 8002d78:	604a      	str	r2, [r1, #4]
+ 8002d7a:	bf08      	it	eq
+ 8002d7c:	6059      	streq	r1, [r3, #4]
+ 8002d7e:	2100      	movs	r1, #0
+ 8002d80:	681a      	ldr	r2, [r3, #0]
+ 8002d82:	6101      	str	r1, [r0, #16]
+ 8002d84:	3a01      	subs	r2, #1
+ 8002d86:	601a      	str	r2, [r3, #0]
+ 8002d88:	6818      	ldr	r0, [r3, #0]
+ 8002d8a:	bc10      	pop	{r4}
+ 8002d8c:	4770      	bx	lr
+ 8002d8e:	bf00      	nop
+
+08002d90 :
+ 8002d90:	b580      	push	{r7, lr}
+ 8002d92:	f04f 5a80 	mov.w	sl, #268435456	; 0x10000000
+ 8002d96:	4d15      	ldr	r5, [pc, #84]	; (8002dec )
+ 8002d98:	4f15      	ldr	r7, [pc, #84]	; (8002df0 )
+ 8002d9a:	4e16      	ldr	r6, [pc, #88]	; (8002df4 )
+ 8002d9c:	f8df 8058 	ldr.w	r8, [pc, #88]	; 8002df8 
+ 8002da0:	f8df 9058 	ldr.w	r9, [pc, #88]	; 8002dfc 
+ 8002da4:	e014      	b.n	8002dd0 
+ 8002da6:	f000 fc9d 	bl	80036e4 
+ 8002daa:	68fb      	ldr	r3, [r7, #12]
+ 8002dac:	68dc      	ldr	r4, [r3, #12]
+ 8002dae:	1d20      	adds	r0, r4, #4
+ 8002db0:	f7ff ffda 	bl	8002d68 
+ 8002db4:	6833      	ldr	r3, [r6, #0]
+ 8002db6:	3b01      	subs	r3, #1
+ 8002db8:	6033      	str	r3, [r6, #0]
+ 8002dba:	682b      	ldr	r3, [r5, #0]
+ 8002dbc:	3b01      	subs	r3, #1
+ 8002dbe:	602b      	str	r3, [r5, #0]
+ 8002dc0:	f000 fcb2 	bl	8003728 
+ 8002dc4:	6b20      	ldr	r0, [r4, #48]	; 0x30
+ 8002dc6:	f000 fe31 	bl	8003a2c 
+ 8002dca:	4620      	mov	r0, r4
+ 8002dcc:	f000 fe2e 	bl	8003a2c 
+ 8002dd0:	682b      	ldr	r3, [r5, #0]
+ 8002dd2:	2b00      	cmp	r3, #0
+ 8002dd4:	d1e7      	bne.n	8002da6 
+ 8002dd6:	f8d8 3000 	ldr.w	r3, [r8]
+ 8002dda:	2b01      	cmp	r3, #1
+ 8002ddc:	d9f8      	bls.n	8002dd0 
+ 8002dde:	f8c9 a000 	str.w	sl, [r9]
+ 8002de2:	f3bf 8f4f 	dsb	sy
+ 8002de6:	f3bf 8f6f 	isb	sy
+ 8002dea:	e7f1      	b.n	8002dd0 
+ 8002dec:	2000023c 	.word	0x2000023c
+ 8002df0:	200002b0 	.word	0x200002b0
+ 8002df4:	20000238 	.word	0x20000238
+ 8002df8:	200001ac 	.word	0x200001ac
+ 8002dfc:	e000ed04 	.word	0xe000ed04
+
+08002e00 :
+ 8002e00:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8002e02:	4b1b      	ldr	r3, [pc, #108]	; (8002e70 )
+ 8002e04:	4e1b      	ldr	r6, [pc, #108]	; (8002e74 )
+ 8002e06:	681c      	ldr	r4, [r3, #0]
+ 8002e08:	6833      	ldr	r3, [r6, #0]
+ 8002e0a:	4605      	mov	r5, r0
+ 8002e0c:	1d18      	adds	r0, r3, #4
+ 8002e0e:	460f      	mov	r7, r1
+ 8002e10:	f7ff ffaa 	bl	8002d68 
+ 8002e14:	b940      	cbnz	r0, 8002e28 
+ 8002e16:	2201      	movs	r2, #1
+ 8002e18:	6833      	ldr	r3, [r6, #0]
+ 8002e1a:	4917      	ldr	r1, [pc, #92]	; (8002e78 )
+ 8002e1c:	6ad8      	ldr	r0, [r3, #44]	; 0x2c
+ 8002e1e:	680b      	ldr	r3, [r1, #0]
+ 8002e20:	4082      	lsls	r2, r0
+ 8002e22:	ea23 0302 	bic.w	r3, r3, r2
+ 8002e26:	600b      	str	r3, [r1, #0]
+ 8002e28:	1c6b      	adds	r3, r5, #1
+ 8002e2a:	d017      	beq.n	8002e5c 
+ 8002e2c:	6833      	ldr	r3, [r6, #0]
+ 8002e2e:	1964      	adds	r4, r4, r5
+ 8002e30:	605c      	str	r4, [r3, #4]
+ 8002e32:	d20b      	bcs.n	8002e4c 
+ 8002e34:	4b11      	ldr	r3, [pc, #68]	; (8002e7c )
+ 8002e36:	6818      	ldr	r0, [r3, #0]
+ 8002e38:	6831      	ldr	r1, [r6, #0]
+ 8002e3a:	3104      	adds	r1, #4
+ 8002e3c:	f7ff ff7a 	bl	8002d34 
+ 8002e40:	4b0f      	ldr	r3, [pc, #60]	; (8002e80 )
+ 8002e42:	681a      	ldr	r2, [r3, #0]
+ 8002e44:	42a2      	cmp	r2, r4
+ 8002e46:	bf88      	it	hi
+ 8002e48:	601c      	strhi	r4, [r3, #0]
+ 8002e4a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 8002e4c:	4b0d      	ldr	r3, [pc, #52]	; (8002e84 )
+ 8002e4e:	6818      	ldr	r0, [r3, #0]
+ 8002e50:	6831      	ldr	r1, [r6, #0]
+ 8002e52:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
+ 8002e56:	3104      	adds	r1, #4
+ 8002e58:	f7ff bf6c 	b.w	8002d34 
+ 8002e5c:	2f00      	cmp	r7, #0
+ 8002e5e:	d0e5      	beq.n	8002e2c 
+ 8002e60:	6831      	ldr	r1, [r6, #0]
+ 8002e62:	4809      	ldr	r0, [pc, #36]	; (8002e88 )
+ 8002e64:	3104      	adds	r1, #4
+ 8002e66:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
+ 8002e6a:	f7ff bf55 	b.w	8002d18 
+ 8002e6e:	bf00      	nop
+ 8002e70:	200002c4 	.word	0x200002c4
+ 8002e74:	200001a0 	.word	0x200001a0
+ 8002e78:	2000024c 	.word	0x2000024c
+ 8002e7c:	200001a4 	.word	0x200001a4
+ 8002e80:	2000027c 	.word	0x2000027c
+ 8002e84:	200001a8 	.word	0x200001a8
+ 8002e88:	2000029c 	.word	0x2000029c
+
+08002e8c :
+ 8002e8c:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 8002e90:	ea4f 0a82 	mov.w	sl, r2, lsl #2
+ 8002e94:	4680      	mov	r8, r0
+ 8002e96:	4650      	mov	r0, sl
+ 8002e98:	460d      	mov	r5, r1
+ 8002e9a:	4699      	mov	r9, r3
+ 8002e9c:	9f0b      	ldr	r7, [sp, #44]	; 0x2c
+ 8002e9e:	f000 fd31 	bl	8003904 
+ 8002ea2:	2800      	cmp	r0, #0
+ 8002ea4:	f000 8108 	beq.w	80030b8 
+ 8002ea8:	4606      	mov	r6, r0
+ 8002eaa:	2054      	movs	r0, #84	; 0x54
+ 8002eac:	f000 fd2a 	bl	8003904 
+ 8002eb0:	4604      	mov	r4, r0
+ 8002eb2:	2800      	cmp	r0, #0
+ 8002eb4:	f000 80d3 	beq.w	800305e 
+ 8002eb8:	6306      	str	r6, [r0, #48]	; 0x30
+ 8002eba:	782b      	ldrb	r3, [r5, #0]
+ 8002ebc:	f1aa 0a04 	sub.w	sl, sl, #4
+ 8002ec0:	f880 3034 	strb.w	r3, [r0, #52]	; 0x34
+ 8002ec4:	782b      	ldrb	r3, [r5, #0]
+ 8002ec6:	4456      	add	r6, sl
+ 8002ec8:	f026 0a07 	bic.w	sl, r6, #7
+ 8002ecc:	2b00      	cmp	r3, #0
+ 8002ece:	d04d      	beq.n	8002f6c 
+ 8002ed0:	786b      	ldrb	r3, [r5, #1]
+ 8002ed2:	f880 3035 	strb.w	r3, [r0, #53]	; 0x35
+ 8002ed6:	786b      	ldrb	r3, [r5, #1]
+ 8002ed8:	2b00      	cmp	r3, #0
+ 8002eda:	d047      	beq.n	8002f6c 
+ 8002edc:	78ab      	ldrb	r3, [r5, #2]
+ 8002ede:	f880 3036 	strb.w	r3, [r0, #54]	; 0x36
+ 8002ee2:	78ab      	ldrb	r3, [r5, #2]
+ 8002ee4:	2b00      	cmp	r3, #0
+ 8002ee6:	d041      	beq.n	8002f6c 
+ 8002ee8:	78eb      	ldrb	r3, [r5, #3]
+ 8002eea:	f880 3037 	strb.w	r3, [r0, #55]	; 0x37
+ 8002eee:	78eb      	ldrb	r3, [r5, #3]
+ 8002ef0:	2b00      	cmp	r3, #0
+ 8002ef2:	d03b      	beq.n	8002f6c 
+ 8002ef4:	792b      	ldrb	r3, [r5, #4]
+ 8002ef6:	f880 3038 	strb.w	r3, [r0, #56]	; 0x38
+ 8002efa:	792b      	ldrb	r3, [r5, #4]
+ 8002efc:	2b00      	cmp	r3, #0
+ 8002efe:	d035      	beq.n	8002f6c 
+ 8002f00:	796b      	ldrb	r3, [r5, #5]
+ 8002f02:	f880 3039 	strb.w	r3, [r0, #57]	; 0x39
+ 8002f06:	796b      	ldrb	r3, [r5, #5]
+ 8002f08:	2b00      	cmp	r3, #0
+ 8002f0a:	d02f      	beq.n	8002f6c 
+ 8002f0c:	79ab      	ldrb	r3, [r5, #6]
+ 8002f0e:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
+ 8002f12:	79ab      	ldrb	r3, [r5, #6]
+ 8002f14:	b353      	cbz	r3, 8002f6c 
+ 8002f16:	79eb      	ldrb	r3, [r5, #7]
+ 8002f18:	f880 303b 	strb.w	r3, [r0, #59]	; 0x3b
+ 8002f1c:	79eb      	ldrb	r3, [r5, #7]
+ 8002f1e:	b32b      	cbz	r3, 8002f6c 
+ 8002f20:	7a2b      	ldrb	r3, [r5, #8]
+ 8002f22:	f880 303c 	strb.w	r3, [r0, #60]	; 0x3c
+ 8002f26:	7a2b      	ldrb	r3, [r5, #8]
+ 8002f28:	b303      	cbz	r3, 8002f6c 
+ 8002f2a:	7a6b      	ldrb	r3, [r5, #9]
+ 8002f2c:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d
+ 8002f30:	7a6b      	ldrb	r3, [r5, #9]
+ 8002f32:	b1db      	cbz	r3, 8002f6c 
+ 8002f34:	7aab      	ldrb	r3, [r5, #10]
+ 8002f36:	f880 303e 	strb.w	r3, [r0, #62]	; 0x3e
+ 8002f3a:	7aab      	ldrb	r3, [r5, #10]
+ 8002f3c:	b1b3      	cbz	r3, 8002f6c 
+ 8002f3e:	7aeb      	ldrb	r3, [r5, #11]
+ 8002f40:	f880 303f 	strb.w	r3, [r0, #63]	; 0x3f
+ 8002f44:	7aeb      	ldrb	r3, [r5, #11]
+ 8002f46:	b18b      	cbz	r3, 8002f6c 
+ 8002f48:	7b2b      	ldrb	r3, [r5, #12]
+ 8002f4a:	f880 3040 	strb.w	r3, [r0, #64]	; 0x40
+ 8002f4e:	7b2b      	ldrb	r3, [r5, #12]
+ 8002f50:	b163      	cbz	r3, 8002f6c 
+ 8002f52:	7b6b      	ldrb	r3, [r5, #13]
+ 8002f54:	f880 3041 	strb.w	r3, [r0, #65]	; 0x41
+ 8002f58:	7b6b      	ldrb	r3, [r5, #13]
+ 8002f5a:	b13b      	cbz	r3, 8002f6c 
+ 8002f5c:	7bab      	ldrb	r3, [r5, #14]
+ 8002f5e:	f880 3042 	strb.w	r3, [r0, #66]	; 0x42
+ 8002f62:	7bab      	ldrb	r3, [r5, #14]
+ 8002f64:	b113      	cbz	r3, 8002f6c 
+ 8002f66:	7beb      	ldrb	r3, [r5, #15]
+ 8002f68:	f880 3043 	strb.w	r3, [r0, #67]	; 0x43
+ 8002f6c:	9d0a      	ldr	r5, [sp, #40]	; 0x28
+ 8002f6e:	f04f 0b00 	mov.w	fp, #0
+ 8002f72:	2d06      	cmp	r5, #6
+ 8002f74:	bf28      	it	cs
+ 8002f76:	2506      	movcs	r5, #6
+ 8002f78:	1d26      	adds	r6, r4, #4
+ 8002f7a:	62e5      	str	r5, [r4, #44]	; 0x2c
+ 8002f7c:	6465      	str	r5, [r4, #68]	; 0x44
+ 8002f7e:	4630      	mov	r0, r6
+ 8002f80:	f884 b043 	strb.w	fp, [r4, #67]	; 0x43
+ 8002f84:	f8c4 b048 	str.w	fp, [r4, #72]	; 0x48
+ 8002f88:	f7ff fec2 	bl	8002d10 
+ 8002f8c:	f1c5 0507 	rsb	r5, r5, #7
+ 8002f90:	f104 0018 	add.w	r0, r4, #24
+ 8002f94:	f7ff febc 	bl	8002d10 
+ 8002f98:	f8c4 b04c 	str.w	fp, [r4, #76]	; 0x4c
+ 8002f9c:	61a5      	str	r5, [r4, #24]
+ 8002f9e:	6124      	str	r4, [r4, #16]
+ 8002fa0:	f884 b050 	strb.w	fp, [r4, #80]	; 0x50
+ 8002fa4:	6264      	str	r4, [r4, #36]	; 0x24
+ 8002fa6:	464a      	mov	r2, r9
+ 8002fa8:	4641      	mov	r1, r8
+ 8002faa:	4650      	mov	r0, sl
+ 8002fac:	f000 fb74 	bl	8003698 
+ 8002fb0:	6020      	str	r0, [r4, #0]
+ 8002fb2:	b107      	cbz	r7, 8002fb6 
+ 8002fb4:	603c      	str	r4, [r7, #0]
+ 8002fb6:	f000 fb95 	bl	80036e4 
+ 8002fba:	4a41      	ldr	r2, [pc, #260]	; (80030c0 )
+ 8002fbc:	4f41      	ldr	r7, [pc, #260]	; (80030c4 )
+ 8002fbe:	6813      	ldr	r3, [r2, #0]
+ 8002fc0:	3301      	adds	r3, #1
+ 8002fc2:	6013      	str	r3, [r2, #0]
+ 8002fc4:	683b      	ldr	r3, [r7, #0]
+ 8002fc6:	2b00      	cmp	r3, #0
+ 8002fc8:	d03f      	beq.n	800304a 
+ 8002fca:	f8df 8118 	ldr.w	r8, [pc, #280]	; 80030e4 
+ 8002fce:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
+ 8002fd0:	f8d8 2000 	ldr.w	r2, [r8]
+ 8002fd4:	b372      	cbz	r2, 8003034 
+ 8002fd6:	f8df 9110 	ldr.w	r9, [pc, #272]	; 80030e8 
+ 8002fda:	2501      	movs	r5, #1
+ 8002fdc:	f8df e10c 	ldr.w	lr, [pc, #268]	; 80030ec 
+ 8002fe0:	f8df c10c 	ldr.w	ip, [pc, #268]	; 80030f0 
+ 8002fe4:	fa05 f203 	lsl.w	r2, r5, r3
+ 8002fe8:	eb03 0383 	add.w	r3, r3, r3, lsl #2
+ 8002fec:	4631      	mov	r1, r6
+ 8002fee:	eb09 0083 	add.w	r0, r9, r3, lsl #2
+ 8002ff2:	f8de 6000 	ldr.w	r6, [lr]
+ 8002ff6:	f8dc 3000 	ldr.w	r3, [ip]
+ 8002ffa:	4332      	orrs	r2, r6
+ 8002ffc:	442b      	add	r3, r5
+ 8002ffe:	f8cc 3000 	str.w	r3, [ip]
+ 8003002:	f8ce 2000 	str.w	r2, [lr]
+ 8003006:	f7ff fe87 	bl	8002d18 
+ 800300a:	f000 fb8d 	bl	8003728 
+ 800300e:	f8d8 3000 	ldr.w	r3, [r8]
+ 8003012:	b1bb      	cbz	r3, 8003044 
+ 8003014:	683a      	ldr	r2, [r7, #0]
+ 8003016:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
+ 8003018:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
+ 800301a:	429a      	cmp	r2, r3
+ 800301c:	d212      	bcs.n	8003044 
+ 800301e:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8003022:	4b29      	ldr	r3, [pc, #164]	; (80030c8 )
+ 8003024:	601a      	str	r2, [r3, #0]
+ 8003026:	f3bf 8f4f 	dsb	sy
+ 800302a:	f3bf 8f6f 	isb	sy
+ 800302e:	4628      	mov	r0, r5
+ 8003030:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 8003034:	683a      	ldr	r2, [r7, #0]
+ 8003036:	f8df 90b0 	ldr.w	r9, [pc, #176]	; 80030e8 
+ 800303a:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
+ 800303c:	429a      	cmp	r2, r3
+ 800303e:	bf98      	it	ls
+ 8003040:	603c      	strls	r4, [r7, #0]
+ 8003042:	e7ca      	b.n	8002fda 
+ 8003044:	4628      	mov	r0, r5
+ 8003046:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 800304a:	603c      	str	r4, [r7, #0]
+ 800304c:	6813      	ldr	r3, [r2, #0]
+ 800304e:	2b01      	cmp	r3, #1
+ 8003050:	d00c      	beq.n	800306c 
+ 8003052:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
+ 8003054:	f8df 9090 	ldr.w	r9, [pc, #144]	; 80030e8 
+ 8003058:	f8df 8088 	ldr.w	r8, [pc, #136]	; 80030e4 
+ 800305c:	e7bd      	b.n	8002fda 
+ 800305e:	4630      	mov	r0, r6
+ 8003060:	f000 fce4 	bl	8003a2c 
+ 8003064:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+ 8003068:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 800306c:	f8df 9078 	ldr.w	r9, [pc, #120]	; 80030e8 
+ 8003070:	464d      	mov	r5, r9
+ 8003072:	f109 088c 	add.w	r8, r9, #140	; 0x8c
+ 8003076:	4628      	mov	r0, r5
+ 8003078:	3514      	adds	r5, #20
+ 800307a:	f7ff fe3d 	bl	8002cf8 
+ 800307e:	4545      	cmp	r5, r8
+ 8003080:	d1f9      	bne.n	8003076 
+ 8003082:	f8df 8070 	ldr.w	r8, [pc, #112]	; 80030f4 
+ 8003086:	4d11      	ldr	r5, [pc, #68]	; (80030cc )
+ 8003088:	4640      	mov	r0, r8
+ 800308a:	f7ff fe35 	bl	8002cf8 
+ 800308e:	4628      	mov	r0, r5
+ 8003090:	f7ff fe32 	bl	8002cf8 
+ 8003094:	480e      	ldr	r0, [pc, #56]	; (80030d0 )
+ 8003096:	f7ff fe2f 	bl	8002cf8 
+ 800309a:	480e      	ldr	r0, [pc, #56]	; (80030d4 )
+ 800309c:	f7ff fe2c 	bl	8002cf8 
+ 80030a0:	480d      	ldr	r0, [pc, #52]	; (80030d8 )
+ 80030a2:	f7ff fe29 	bl	8002cf8 
+ 80030a6:	4b0d      	ldr	r3, [pc, #52]	; (80030dc )
+ 80030a8:	4a0d      	ldr	r2, [pc, #52]	; (80030e0 )
+ 80030aa:	f8c3 8000 	str.w	r8, [r3]
+ 80030ae:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
+ 80030b0:	6015      	str	r5, [r2, #0]
+ 80030b2:	f8df 8030 	ldr.w	r8, [pc, #48]	; 80030e4 
+ 80030b6:	e790      	b.n	8002fda 
+ 80030b8:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
+ 80030bc:	e7b8      	b.n	8003030 
+ 80030be:	bf00      	nop
+ 80030c0:	20000238 	.word	0x20000238
+ 80030c4:	200001a0 	.word	0x200001a0
+ 80030c8:	e000ed04 	.word	0xe000ed04
+ 80030cc:	20000264 	.word	0x20000264
+ 80030d0:	20000284 	.word	0x20000284
+ 80030d4:	200002b0 	.word	0x200002b0
+ 80030d8:	2000029c 	.word	0x2000029c
+ 80030dc:	200001a4 	.word	0x200001a4
+ 80030e0:	200001a8 	.word	0x200001a8
+ 80030e4:	20000298 	.word	0x20000298
+ 80030e8:	200001ac 	.word	0x200001ac
+ 80030ec:	2000024c 	.word	0x2000024c
+ 80030f0:	20000248 	.word	0x20000248
+ 80030f4:	20000250 	.word	0x20000250
+
+080030f8 :
+ 80030f8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
+ 80030fc:	f44f 7000 	mov.w	r0, #512	; 0x200
+ 8003100:	f000 fc00 	bl	8003904 
+ 8003104:	2800      	cmp	r0, #0
+ 8003106:	f000 8093 	beq.w	8003230 
+ 800310a:	4606      	mov	r6, r0
+ 800310c:	2054      	movs	r0, #84	; 0x54
+ 800310e:	f000 fbf9 	bl	8003904 
+ 8003112:	4604      	mov	r4, r0
+ 8003114:	2800      	cmp	r0, #0
+ 8003116:	f000 8088 	beq.w	800322a 
+ 800311a:	2500      	movs	r5, #0
+ 800311c:	4b5b      	ldr	r3, [pc, #364]	; (800328c )
+ 800311e:	1d07      	adds	r7, r0, #4
+ 8003120:	6343      	str	r3, [r0, #52]	; 0x34
+ 8003122:	6306      	str	r6, [r0, #48]	; 0x30
+ 8003124:	f880 5038 	strb.w	r5, [r0, #56]	; 0x38
+ 8003128:	f880 5043 	strb.w	r5, [r0, #67]	; 0x43
+ 800312c:	62c5      	str	r5, [r0, #44]	; 0x2c
+ 800312e:	e9c0 5511 	strd	r5, r5, [r0, #68]	; 0x44
+ 8003132:	4638      	mov	r0, r7
+ 8003134:	f7ff fdec 	bl	8002d10 
+ 8003138:	f104 0018 	add.w	r0, r4, #24
+ 800313c:	f7ff fde8 	bl	8002d10 
+ 8003140:	2307      	movs	r3, #7
+ 8003142:	f506 76fe 	add.w	r6, r6, #508	; 0x1fc
+ 8003146:	f026 0607 	bic.w	r6, r6, #7
+ 800314a:	462a      	mov	r2, r5
+ 800314c:	64e5      	str	r5, [r4, #76]	; 0x4c
+ 800314e:	61a3      	str	r3, [r4, #24]
+ 8003150:	494f      	ldr	r1, [pc, #316]	; (8003290 )
+ 8003152:	4630      	mov	r0, r6
+ 8003154:	6124      	str	r4, [r4, #16]
+ 8003156:	f884 5050 	strb.w	r5, [r4, #80]	; 0x50
+ 800315a:	6264      	str	r4, [r4, #36]	; 0x24
+ 800315c:	f000 fa9c 	bl	8003698 
+ 8003160:	4b4c      	ldr	r3, [pc, #304]	; (8003294 )
+ 8003162:	6020      	str	r0, [r4, #0]
+ 8003164:	601c      	str	r4, [r3, #0]
+ 8003166:	f000 fabd 	bl	80036e4 
+ 800316a:	4b4b      	ldr	r3, [pc, #300]	; (8003298 )
+ 800316c:	f8df 8158 	ldr.w	r8, [pc, #344]	; 80032c8 
+ 8003170:	681a      	ldr	r2, [r3, #0]
+ 8003172:	3201      	adds	r2, #1
+ 8003174:	601a      	str	r2, [r3, #0]
+ 8003176:	f8d8 2000 	ldr.w	r2, [r8]
+ 800317a:	2a00      	cmp	r2, #0
+ 800317c:	d04c      	beq.n	8003218 
+ 800317e:	4e47      	ldr	r6, [pc, #284]	; (800329c )
+ 8003180:	6ae0      	ldr	r0, [r4, #44]	; 0x2c
+ 8003182:	6833      	ldr	r3, [r6, #0]
+ 8003184:	2b00      	cmp	r3, #0
+ 8003186:	d03e      	beq.n	8003206 
+ 8003188:	4d45      	ldr	r5, [pc, #276]	; (80032a0 )
+ 800318a:	2301      	movs	r3, #1
+ 800318c:	f8df e13c 	ldr.w	lr, [pc, #316]	; 80032cc 
+ 8003190:	f8df c13c 	ldr.w	ip, [pc, #316]	; 80032d0 
+ 8003194:	4083      	lsls	r3, r0
+ 8003196:	eb00 0080 	add.w	r0, r0, r0, lsl #2
+ 800319a:	f8dc 2000 	ldr.w	r2, [ip]
+ 800319e:	eb05 0080 	add.w	r0, r5, r0, lsl #2
+ 80031a2:	f8de 5000 	ldr.w	r5, [lr]
+ 80031a6:	3201      	adds	r2, #1
+ 80031a8:	432b      	orrs	r3, r5
+ 80031aa:	4639      	mov	r1, r7
+ 80031ac:	f8ce 3000 	str.w	r3, [lr]
+ 80031b0:	f8cc 2000 	str.w	r2, [ip]
+ 80031b4:	f7ff fdb0 	bl	8002d18 
+ 80031b8:	f000 fab6 	bl	8003728 
+ 80031bc:	6833      	ldr	r3, [r6, #0]
+ 80031be:	b16b      	cbz	r3, 80031dc 
+ 80031c0:	f8d8 2000 	ldr.w	r2, [r8]
+ 80031c4:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
+ 80031c6:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
+ 80031c8:	429a      	cmp	r2, r3
+ 80031ca:	d207      	bcs.n	80031dc 
+ 80031cc:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 80031d0:	4b34      	ldr	r3, [pc, #208]	; (80032a4 )
+ 80031d2:	601a      	str	r2, [r3, #0]
+ 80031d4:	f3bf 8f4f 	dsb	sy
+ 80031d8:	f3bf 8f6f 	isb	sy
+ 80031dc:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80031e0:	f383 8811 	msr	BASEPRI, r3
+ 80031e4:	f3bf 8f6f 	isb	sy
+ 80031e8:	f3bf 8f4f 	dsb	sy
+ 80031ec:	f04f 34ff 	mov.w	r4, #4294967295	; 0xffffffff
+ 80031f0:	2101      	movs	r1, #1
+ 80031f2:	2200      	movs	r2, #0
+ 80031f4:	4b2c      	ldr	r3, [pc, #176]	; (80032a8 )
+ 80031f6:	482d      	ldr	r0, [pc, #180]	; (80032ac )
+ 80031f8:	6004      	str	r4, [r0, #0]
+ 80031fa:	6031      	str	r1, [r6, #0]
+ 80031fc:	601a      	str	r2, [r3, #0]
+ 80031fe:	e8bd 43f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
+ 8003202:	f000 bafb 	b.w	80037fc 
+ 8003206:	f8d8 3000 	ldr.w	r3, [r8]
+ 800320a:	4d25      	ldr	r5, [pc, #148]	; (80032a0 )
+ 800320c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 800320e:	4283      	cmp	r3, r0
+ 8003210:	bf98      	it	ls
+ 8003212:	f8c8 4000 	strls.w	r4, [r8]
+ 8003216:	e7b8      	b.n	800318a 
+ 8003218:	f8c8 4000 	str.w	r4, [r8]
+ 800321c:	681b      	ldr	r3, [r3, #0]
+ 800321e:	2b01      	cmp	r3, #1
+ 8003220:	d00f      	beq.n	8003242 
+ 8003222:	6ae0      	ldr	r0, [r4, #44]	; 0x2c
+ 8003224:	4d1e      	ldr	r5, [pc, #120]	; (80032a0 )
+ 8003226:	4e1d      	ldr	r6, [pc, #116]	; (800329c )
+ 8003228:	e7af      	b.n	800318a 
+ 800322a:	4630      	mov	r0, r6
+ 800322c:	f000 fbfe 	bl	8003a2c 
+ 8003230:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8003234:	f383 8811 	msr	BASEPRI, r3
+ 8003238:	f3bf 8f6f 	isb	sy
+ 800323c:	f3bf 8f4f 	dsb	sy
+ 8003240:	e7fe      	b.n	8003240 
+ 8003242:	4d17      	ldr	r5, [pc, #92]	; (80032a0 )
+ 8003244:	462e      	mov	r6, r5
+ 8003246:	f105 098c 	add.w	r9, r5, #140	; 0x8c
+ 800324a:	4630      	mov	r0, r6
+ 800324c:	3614      	adds	r6, #20
+ 800324e:	f7ff fd53 	bl	8002cf8 
+ 8003252:	45b1      	cmp	r9, r6
+ 8003254:	d1f9      	bne.n	800324a 
+ 8003256:	f8df 907c 	ldr.w	r9, [pc, #124]	; 80032d4 
+ 800325a:	4e15      	ldr	r6, [pc, #84]	; (80032b0 )
+ 800325c:	4648      	mov	r0, r9
+ 800325e:	f7ff fd4b 	bl	8002cf8 
+ 8003262:	4630      	mov	r0, r6
+ 8003264:	f7ff fd48 	bl	8002cf8 
+ 8003268:	4812      	ldr	r0, [pc, #72]	; (80032b4 )
+ 800326a:	f7ff fd45 	bl	8002cf8 
+ 800326e:	4812      	ldr	r0, [pc, #72]	; (80032b8 )
+ 8003270:	f7ff fd42 	bl	8002cf8 
+ 8003274:	4811      	ldr	r0, [pc, #68]	; (80032bc )
+ 8003276:	f7ff fd3f 	bl	8002cf8 
+ 800327a:	4a11      	ldr	r2, [pc, #68]	; (80032c0 )
+ 800327c:	4b11      	ldr	r3, [pc, #68]	; (80032c4 )
+ 800327e:	f8c2 9000 	str.w	r9, [r2]
+ 8003282:	6ae0      	ldr	r0, [r4, #44]	; 0x2c
+ 8003284:	601e      	str	r6, [r3, #0]
+ 8003286:	4e05      	ldr	r6, [pc, #20]	; (800329c )
+ 8003288:	e77f      	b.n	800318a 
+ 800328a:	bf00      	nop
+ 800328c:	454c4449 	.word	0x454c4449
+ 8003290:	08002d91 	.word	0x08002d91
+ 8003294:	20000278 	.word	0x20000278
+ 8003298:	20000238 	.word	0x20000238
+ 800329c:	20000298 	.word	0x20000298
+ 80032a0:	200001ac 	.word	0x200001ac
+ 80032a4:	e000ed04 	.word	0xe000ed04
+ 80032a8:	200002c4 	.word	0x200002c4
+ 80032ac:	2000027c 	.word	0x2000027c
+ 80032b0:	20000264 	.word	0x20000264
+ 80032b4:	20000284 	.word	0x20000284
+ 80032b8:	200002b0 	.word	0x200002b0
+ 80032bc:	2000029c 	.word	0x2000029c
+ 80032c0:	200001a4 	.word	0x200001a4
+ 80032c4:	200001a8 	.word	0x200001a8
+ 80032c8:	200001a0 	.word	0x200001a0
+ 80032cc:	2000024c 	.word	0x2000024c
+ 80032d0:	20000248 	.word	0x20000248
+ 80032d4:	20000250 	.word	0x20000250
+
+080032d8 :
+ 80032d8:	4a02      	ldr	r2, [pc, #8]	; (80032e4 )
+ 80032da:	6813      	ldr	r3, [r2, #0]
+ 80032dc:	3301      	adds	r3, #1
+ 80032de:	6013      	str	r3, [r2, #0]
+ 80032e0:	4770      	bx	lr
+ 80032e2:	bf00      	nop
+ 80032e4:	20000244 	.word	0x20000244
+
+080032e8 :
+ 80032e8:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 80032ec:	4b49      	ldr	r3, [pc, #292]	; (8003414 )
+ 80032ee:	681b      	ldr	r3, [r3, #0]
+ 80032f0:	b9cb      	cbnz	r3, 8003326 
+ 80032f2:	4b49      	ldr	r3, [pc, #292]	; (8003418 )
+ 80032f4:	681e      	ldr	r6, [r3, #0]
+ 80032f6:	3601      	adds	r6, #1
+ 80032f8:	601e      	str	r6, [r3, #0]
+ 80032fa:	b30e      	cbz	r6, 8003340 
+ 80032fc:	f8df b138 	ldr.w	fp, [pc, #312]	; 8003438 
+ 8003300:	f8db 2000 	ldr.w	r2, [fp]
+ 8003304:	2500      	movs	r5, #0
+ 8003306:	42b2      	cmp	r2, r6
+ 8003308:	d928      	bls.n	800335c 
+ 800330a:	4f44      	ldr	r7, [pc, #272]	; (800341c )
+ 800330c:	f8df 812c 	ldr.w	r8, [pc, #300]	; 800343c 
+ 8003310:	f8d8 3000 	ldr.w	r3, [r8]
+ 8003314:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 8003316:	eb03 0383 	add.w	r3, r3, r3, lsl #2
+ 800331a:	009b      	lsls	r3, r3, #2
+ 800331c:	58fb      	ldr	r3, [r7, r3]
+ 800331e:	2b02      	cmp	r3, #2
+ 8003320:	bf28      	it	cs
+ 8003322:	2501      	movcs	r5, #1
+ 8003324:	e004      	b.n	8003330 
+ 8003326:	2500      	movs	r5, #0
+ 8003328:	4a3d      	ldr	r2, [pc, #244]	; (8003420 )
+ 800332a:	6813      	ldr	r3, [r2, #0]
+ 800332c:	3301      	adds	r3, #1
+ 800332e:	6013      	str	r3, [r2, #0]
+ 8003330:	4b3c      	ldr	r3, [pc, #240]	; (8003424 )
+ 8003332:	681b      	ldr	r3, [r3, #0]
+ 8003334:	2b00      	cmp	r3, #0
+ 8003336:	bf0c      	ite	eq
+ 8003338:	4628      	moveq	r0, r5
+ 800333a:	2001      	movne	r0, #1
+ 800333c:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 8003340:	4c39      	ldr	r4, [pc, #228]	; (8003428 )
+ 8003342:	6823      	ldr	r3, [r4, #0]
+ 8003344:	681b      	ldr	r3, [r3, #0]
+ 8003346:	2b00      	cmp	r3, #0
+ 8003348:	d047      	beq.n	80033da 
+ 800334a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 800334e:	f383 8811 	msr	BASEPRI, r3
+ 8003352:	f3bf 8f6f 	isb	sy
+ 8003356:	f3bf 8f4f 	dsb	sy
+ 800335a:	e7fe      	b.n	800335a 
+ 800335c:	4c32      	ldr	r4, [pc, #200]	; (8003428 )
+ 800335e:	4f2f      	ldr	r7, [pc, #188]	; (800341c )
+ 8003360:	f8df 80d8 	ldr.w	r8, [pc, #216]	; 800343c 
+ 8003364:	e02d      	b.n	80033c2 
+ 8003366:	6822      	ldr	r2, [r4, #0]
+ 8003368:	68d2      	ldr	r2, [r2, #12]
+ 800336a:	f8d2 900c 	ldr.w	r9, [r2, #12]
+ 800336e:	f8d9 1004 	ldr.w	r1, [r9, #4]
+ 8003372:	f109 0a04 	add.w	sl, r9, #4
+ 8003376:	428e      	cmp	r6, r1
+ 8003378:	d32c      	bcc.n	80033d4 
+ 800337a:	4650      	mov	r0, sl
+ 800337c:	f7ff fcf4 	bl	8002d68 
+ 8003380:	f8d9 1028 	ldr.w	r1, [r9, #40]	; 0x28
+ 8003384:	f109 0018 	add.w	r0, r9, #24
+ 8003388:	b109      	cbz	r1, 800338e 
+ 800338a:	f7ff fced 	bl	8002d68 
+ 800338e:	2101      	movs	r1, #1
+ 8003390:	4a26      	ldr	r2, [pc, #152]	; (800342c )
+ 8003392:	f8d9 002c 	ldr.w	r0, [r9, #44]	; 0x2c
+ 8003396:	6813      	ldr	r3, [r2, #0]
+ 8003398:	fa01 fc00 	lsl.w	ip, r1, r0
+ 800339c:	eb00 0080 	add.w	r0, r0, r0, lsl #2
+ 80033a0:	4651      	mov	r1, sl
+ 80033a2:	eb07 0080 	add.w	r0, r7, r0, lsl #2
+ 80033a6:	ea4c 0c03 	orr.w	ip, ip, r3
+ 80033aa:	f8c2 c000 	str.w	ip, [r2]
+ 80033ae:	f7ff fcb3 	bl	8002d18 
+ 80033b2:	f8d8 0000 	ldr.w	r0, [r8]
+ 80033b6:	f8d9 102c 	ldr.w	r1, [r9, #44]	; 0x2c
+ 80033ba:	6ac2      	ldr	r2, [r0, #44]	; 0x2c
+ 80033bc:	4291      	cmp	r1, r2
+ 80033be:	bf28      	it	cs
+ 80033c0:	2501      	movcs	r5, #1
+ 80033c2:	6822      	ldr	r2, [r4, #0]
+ 80033c4:	6812      	ldr	r2, [r2, #0]
+ 80033c6:	2a00      	cmp	r2, #0
+ 80033c8:	d1cd      	bne.n	8003366 
+ 80033ca:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
+ 80033ce:	f8cb 2000 	str.w	r2, [fp]
+ 80033d2:	e79d      	b.n	8003310 
+ 80033d4:	f8cb 1000 	str.w	r1, [fp]
+ 80033d8:	e79a      	b.n	8003310 
+ 80033da:	4b15      	ldr	r3, [pc, #84]	; (8003430 )
+ 80033dc:	6821      	ldr	r1, [r4, #0]
+ 80033de:	6818      	ldr	r0, [r3, #0]
+ 80033e0:	4a14      	ldr	r2, [pc, #80]	; (8003434 )
+ 80033e2:	6020      	str	r0, [r4, #0]
+ 80033e4:	6019      	str	r1, [r3, #0]
+ 80033e6:	6813      	ldr	r3, [r2, #0]
+ 80033e8:	3301      	adds	r3, #1
+ 80033ea:	6013      	str	r3, [r2, #0]
+ 80033ec:	6823      	ldr	r3, [r4, #0]
+ 80033ee:	681b      	ldr	r3, [r3, #0]
+ 80033f0:	b933      	cbnz	r3, 8003400 
+ 80033f2:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
+ 80033f6:	f8df b040 	ldr.w	fp, [pc, #64]	; 8003438 
+ 80033fa:	f8cb 2000 	str.w	r2, [fp]
+ 80033fe:	e77f      	b.n	8003300 
+ 8003400:	6822      	ldr	r2, [r4, #0]
+ 8003402:	f8df b034 	ldr.w	fp, [pc, #52]	; 8003438 
+ 8003406:	68d2      	ldr	r2, [r2, #12]
+ 8003408:	68d2      	ldr	r2, [r2, #12]
+ 800340a:	6852      	ldr	r2, [r2, #4]
+ 800340c:	f8cb 2000 	str.w	r2, [fp]
+ 8003410:	e776      	b.n	8003300 
+ 8003412:	bf00      	nop
+ 8003414:	20000244 	.word	0x20000244
+ 8003418:	200002c4 	.word	0x200002c4
+ 800341c:	200001ac 	.word	0x200001ac
+ 8003420:	20000240 	.word	0x20000240
+ 8003424:	200002c8 	.word	0x200002c8
+ 8003428:	200001a4 	.word	0x200001a4
+ 800342c:	2000024c 	.word	0x2000024c
+ 8003430:	200001a8 	.word	0x200001a8
+ 8003434:	20000280 	.word	0x20000280
+ 8003438:	2000027c 	.word	0x2000027c
+ 800343c:	200001a0 	.word	0x200001a0
+
+08003440 :
+ 8003440:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 8003444:	4c38      	ldr	r4, [pc, #224]	; (8003528 )
+ 8003446:	6823      	ldr	r3, [r4, #0]
+ 8003448:	b943      	cbnz	r3, 800345c 
+ 800344a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 800344e:	f383 8811 	msr	BASEPRI, r3
+ 8003452:	f3bf 8f6f 	isb	sy
+ 8003456:	f3bf 8f4f 	dsb	sy
+ 800345a:	e7fe      	b.n	800345a 
+ 800345c:	f000 f942 	bl	80036e4 
+ 8003460:	6823      	ldr	r3, [r4, #0]
+ 8003462:	3b01      	subs	r3, #1
+ 8003464:	6023      	str	r3, [r4, #0]
+ 8003466:	6824      	ldr	r4, [r4, #0]
+ 8003468:	bb7c      	cbnz	r4, 80034ca 
+ 800346a:	4b30      	ldr	r3, [pc, #192]	; (800352c )
+ 800346c:	681b      	ldr	r3, [r3, #0]
+ 800346e:	b363      	cbz	r3, 80034ca 
+ 8003470:	4d2f      	ldr	r5, [pc, #188]	; (8003530 )
+ 8003472:	f8df a0d4 	ldr.w	sl, [pc, #212]	; 8003548 
+ 8003476:	4e2f      	ldr	r6, [pc, #188]	; (8003534 )
+ 8003478:	f8df 90d0 	ldr.w	r9, [pc, #208]	; 800354c 
+ 800347c:	f8df b0d0 	ldr.w	fp, [pc, #208]	; 8003550 
+ 8003480:	f8da 3000 	ldr.w	r3, [sl]
+ 8003484:	b33b      	cbz	r3, 80034d6 
+ 8003486:	2701      	movs	r7, #1
+ 8003488:	f8da 300c 	ldr.w	r3, [sl, #12]
+ 800348c:	68dc      	ldr	r4, [r3, #12]
+ 800348e:	f104 0804 	add.w	r8, r4, #4
+ 8003492:	f104 0018 	add.w	r0, r4, #24
+ 8003496:	f7ff fc67 	bl	8002d68 
+ 800349a:	4640      	mov	r0, r8
+ 800349c:	f7ff fc64 	bl	8002d68 
+ 80034a0:	6ae0      	ldr	r0, [r4, #44]	; 0x2c
+ 80034a2:	6832      	ldr	r2, [r6, #0]
+ 80034a4:	fa07 f300 	lsl.w	r3, r7, r0
+ 80034a8:	eb00 0080 	add.w	r0, r0, r0, lsl #2
+ 80034ac:	4313      	orrs	r3, r2
+ 80034ae:	4641      	mov	r1, r8
+ 80034b0:	eb09 0080 	add.w	r0, r9, r0, lsl #2
+ 80034b4:	6033      	str	r3, [r6, #0]
+ 80034b6:	f7ff fc2f 	bl	8002d18 
+ 80034ba:	f8db 3000 	ldr.w	r3, [fp]
+ 80034be:	6ae2      	ldr	r2, [r4, #44]	; 0x2c
+ 80034c0:	6adb      	ldr	r3, [r3, #44]	; 0x2c
+ 80034c2:	429a      	cmp	r2, r3
+ 80034c4:	d3dc      	bcc.n	8003480 
+ 80034c6:	602f      	str	r7, [r5, #0]
+ 80034c8:	e7da      	b.n	8003480 
+ 80034ca:	2400      	movs	r4, #0
+ 80034cc:	f000 f92c 	bl	8003728 
+ 80034d0:	4620      	mov	r0, r4
+ 80034d2:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 80034d6:	b13c      	cbz	r4, 80034e8 
+ 80034d8:	4b17      	ldr	r3, [pc, #92]	; (8003538 )
+ 80034da:	681a      	ldr	r2, [r3, #0]
+ 80034dc:	6812      	ldr	r2, [r2, #0]
+ 80034de:	b9da      	cbnz	r2, 8003518 
+ 80034e0:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
+ 80034e4:	4b15      	ldr	r3, [pc, #84]	; (800353c )
+ 80034e6:	601a      	str	r2, [r3, #0]
+ 80034e8:	4e15      	ldr	r6, [pc, #84]	; (8003540 )
+ 80034ea:	6834      	ldr	r4, [r6, #0]
+ 80034ec:	b13c      	cbz	r4, 80034fe 
+ 80034ee:	2701      	movs	r7, #1
+ 80034f0:	f7ff fefa 	bl	80032e8 
+ 80034f4:	b100      	cbz	r0, 80034f8 
+ 80034f6:	602f      	str	r7, [r5, #0]
+ 80034f8:	3c01      	subs	r4, #1
+ 80034fa:	d1f9      	bne.n	80034f0 
+ 80034fc:	6034      	str	r4, [r6, #0]
+ 80034fe:	682b      	ldr	r3, [r5, #0]
+ 8003500:	2b00      	cmp	r3, #0
+ 8003502:	d0e2      	beq.n	80034ca 
+ 8003504:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8003508:	4b0e      	ldr	r3, [pc, #56]	; (8003544 )
+ 800350a:	601a      	str	r2, [r3, #0]
+ 800350c:	f3bf 8f4f 	dsb	sy
+ 8003510:	f3bf 8f6f 	isb	sy
+ 8003514:	2401      	movs	r4, #1
+ 8003516:	e7d9      	b.n	80034cc 
+ 8003518:	681a      	ldr	r2, [r3, #0]
+ 800351a:	4b08      	ldr	r3, [pc, #32]	; (800353c )
+ 800351c:	68d2      	ldr	r2, [r2, #12]
+ 800351e:	68d2      	ldr	r2, [r2, #12]
+ 8003520:	6852      	ldr	r2, [r2, #4]
+ 8003522:	601a      	str	r2, [r3, #0]
+ 8003524:	e7e0      	b.n	80034e8 
+ 8003526:	bf00      	nop
+ 8003528:	20000244 	.word	0x20000244
+ 800352c:	20000238 	.word	0x20000238
+ 8003530:	200002c8 	.word	0x200002c8
+ 8003534:	2000024c 	.word	0x2000024c
+ 8003538:	200001a4 	.word	0x200001a4
+ 800353c:	2000027c 	.word	0x2000027c
+ 8003540:	20000240 	.word	0x20000240
+ 8003544:	e000ed04 	.word	0xe000ed04
+ 8003548:	20000284 	.word	0x20000284
+ 800354c:	200001ac 	.word	0x200001ac
+ 8003550:	200001a0 	.word	0x200001a0
+
+08003554 :
+ 8003554:	b508      	push	{r3, lr}
+ 8003556:	b198      	cbz	r0, 8003580 
+ 8003558:	4b0e      	ldr	r3, [pc, #56]	; (8003594 )
+ 800355a:	6819      	ldr	r1, [r3, #0]
+ 800355c:	b141      	cbz	r1, 8003570 
+ 800355e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8003562:	f383 8811 	msr	BASEPRI, r3
+ 8003566:	f3bf 8f6f 	isb	sy
+ 800356a:	f3bf 8f4f 	dsb	sy
+ 800356e:	e7fe      	b.n	800356e 
+ 8003570:	681a      	ldr	r2, [r3, #0]
+ 8003572:	3201      	adds	r2, #1
+ 8003574:	601a      	str	r2, [r3, #0]
+ 8003576:	f7ff fc43 	bl	8002e00 
+ 800357a:	f7ff ff61 	bl	8003440 
+ 800357e:	b938      	cbnz	r0, 8003590 
+ 8003580:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 8003584:	4b04      	ldr	r3, [pc, #16]	; (8003598 )
+ 8003586:	601a      	str	r2, [r3, #0]
+ 8003588:	f3bf 8f4f 	dsb	sy
+ 800358c:	f3bf 8f6f 	isb	sy
+ 8003590:	bd08      	pop	{r3, pc}
+ 8003592:	bf00      	nop
+ 8003594:	20000244 	.word	0x20000244
+ 8003598:	e000ed04 	.word	0xe000ed04
+
+0800359c :
+ 800359c:	4b19      	ldr	r3, [pc, #100]	; (8003604 )
+ 800359e:	681b      	ldr	r3, [r3, #0]
+ 80035a0:	b9e3      	cbnz	r3, 80035dc 
+ 80035a2:	4919      	ldr	r1, [pc, #100]	; (8003608 )
+ 80035a4:	4a19      	ldr	r2, [pc, #100]	; (800360c )
+ 80035a6:	b410      	push	{r4}
+ 80035a8:	600b      	str	r3, [r1, #0]
+ 80035aa:	6813      	ldr	r3, [r2, #0]
+ 80035ac:	fab3 f383 	clz	r3, r3
+ 80035b0:	b2db      	uxtb	r3, r3
+ 80035b2:	f1c3 031f 	rsb	r3, r3, #31
+ 80035b6:	4816      	ldr	r0, [pc, #88]	; (8003610 )
+ 80035b8:	eb03 0283 	add.w	r2, r3, r3, lsl #2
+ 80035bc:	0092      	lsls	r2, r2, #2
+ 80035be:	5881      	ldr	r1, [r0, r2]
+ 80035c0:	1884      	adds	r4, r0, r2
+ 80035c2:	b179      	cbz	r1, 80035e4 
+ 80035c4:	6861      	ldr	r1, [r4, #4]
+ 80035c6:	3208      	adds	r2, #8
+ 80035c8:	6849      	ldr	r1, [r1, #4]
+ 80035ca:	4402      	add	r2, r0
+ 80035cc:	4291      	cmp	r1, r2
+ 80035ce:	6061      	str	r1, [r4, #4]
+ 80035d0:	d011      	beq.n	80035f6 
+ 80035d2:	68ca      	ldr	r2, [r1, #12]
+ 80035d4:	4b0f      	ldr	r3, [pc, #60]	; (8003614 )
+ 80035d6:	bc10      	pop	{r4}
+ 80035d8:	601a      	str	r2, [r3, #0]
+ 80035da:	4770      	bx	lr
+ 80035dc:	2201      	movs	r2, #1
+ 80035de:	4b0a      	ldr	r3, [pc, #40]	; (8003608 )
+ 80035e0:	601a      	str	r2, [r3, #0]
+ 80035e2:	4770      	bx	lr
+ 80035e4:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80035e8:	f383 8811 	msr	BASEPRI, r3
+ 80035ec:	f3bf 8f6f 	isb	sy
+ 80035f0:	f3bf 8f4f 	dsb	sy
+ 80035f4:	e7fe      	b.n	80035f4 
+ 80035f6:	2214      	movs	r2, #20
+ 80035f8:	fb02 0303 	mla	r3, r2, r3, r0
+ 80035fc:	6849      	ldr	r1, [r1, #4]
+ 80035fe:	6059      	str	r1, [r3, #4]
+ 8003600:	e7e7      	b.n	80035d2 
+ 8003602:	bf00      	nop
+ 8003604:	20000244 	.word	0x20000244
+ 8003608:	200002c8 	.word	0x200002c8
+ 800360c:	2000024c 	.word	0x2000024c
+ 8003610:	200001ac 	.word	0x200001ac
+ 8003614:	200001a0 	.word	0x200001a0
+
+08003618 :
+ 8003618:	4b05      	ldr	r3, [pc, #20]	; (8003630 )
+ 800361a:	681b      	ldr	r3, [r3, #0]
+ 800361c:	b133      	cbz	r3, 800362c 
+ 800361e:	4b05      	ldr	r3, [pc, #20]	; (8003634 )
+ 8003620:	681b      	ldr	r3, [r3, #0]
+ 8003622:	2b00      	cmp	r3, #0
+ 8003624:	bf0c      	ite	eq
+ 8003626:	2002      	moveq	r0, #2
+ 8003628:	2000      	movne	r0, #0
+ 800362a:	4770      	bx	lr
+ 800362c:	2001      	movs	r0, #1
+ 800362e:	4770      	bx	lr
+ 8003630:	20000298 	.word	0x20000298
+ 8003634:	20000244 	.word	0x20000244
+
+08003638 :
+ 8003638:	2200      	movs	r2, #0
+ 800363a:	4b0e      	ldr	r3, [pc, #56]	; (8003674 )
+ 800363c:	b082      	sub	sp, #8
+ 800363e:	681b      	ldr	r3, [r3, #0]
+ 8003640:	9201      	str	r2, [sp, #4]
+ 8003642:	3301      	adds	r3, #1
+ 8003644:	d008      	beq.n	8003658 
+ 8003646:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 800364a:	f383 8811 	msr	BASEPRI, r3
+ 800364e:	f3bf 8f6f 	isb	sy
+ 8003652:	f3bf 8f4f 	dsb	sy
+ 8003656:	e7fe      	b.n	8003656 
+ 8003658:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 800365c:	f383 8811 	msr	BASEPRI, r3
+ 8003660:	f3bf 8f6f 	isb	sy
+ 8003664:	f3bf 8f4f 	dsb	sy
+ 8003668:	9b01      	ldr	r3, [sp, #4]
+ 800366a:	2b00      	cmp	r3, #0
+ 800366c:	d0fc      	beq.n	8003668 
+ 800366e:	b002      	add	sp, #8
+ 8003670:	4770      	bx	lr
+ 8003672:	bf00      	nop
+ 8003674:	20000118 	.word	0x20000118
+
+08003678 :
+ 8003678:	4806      	ldr	r0, [pc, #24]	; (8003694 )
+ 800367a:	6800      	ldr	r0, [r0, #0]
+ 800367c:	6800      	ldr	r0, [r0, #0]
+ 800367e:	f380 8808 	msr	MSP, r0
+ 8003682:	b662      	cpsie	i
+ 8003684:	b661      	cpsie	f
+ 8003686:	f3bf 8f4f 	dsb	sy
+ 800368a:	f3bf 8f6f 	isb	sy
+ 800368e:	df00      	svc	0
+ 8003690:	bf00      	nop
+ 8003692:	0000      	.short	0x0000
+ 8003694:	e000ed08 	.word	0xe000ed08
+
+08003698 :
+ 8003698:	b410      	push	{r4}
+ 800369a:	f04f 7480 	mov.w	r4, #16777216	; 0x1000000
+ 800369e:	4b06      	ldr	r3, [pc, #24]	; (80036b8 )
+ 80036a0:	f021 0101 	bic.w	r1, r1, #1
+ 80036a4:	f840 2c20 	str.w	r2, [r0, #-32]
+ 80036a8:	e940 1402 	strd	r1, r4, [r0, #-8]
+ 80036ac:	f840 3c0c 	str.w	r3, [r0, #-12]
+ 80036b0:	bc10      	pop	{r4}
+ 80036b2:	3840      	subs	r0, #64	; 0x40
+ 80036b4:	4770      	bx	lr
+ 80036b6:	bf00      	nop
+ 80036b8:	08003639 	.word	0x08003639
+ 80036bc:	00000000 	.word	0x00000000
+
+080036c0 :
+ 80036c0:	4b07      	ldr	r3, [pc, #28]	; (80036e0 )
+ 80036c2:	6819      	ldr	r1, [r3, #0]
+ 80036c4:	6808      	ldr	r0, [r1, #0]
+ 80036c6:	e8b0 0ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp}
+ 80036ca:	f380 8809 	msr	PSP, r0
+ 80036ce:	f3bf 8f6f 	isb	sy
+ 80036d2:	f04f 0000 	mov.w	r0, #0
+ 80036d6:	f380 8811 	msr	BASEPRI, r0
+ 80036da:	f04e 0e0d 	orr.w	lr, lr, #13
+ 80036de:	4770      	bx	lr
+
+080036e0 :
+ 80036e0:	200001a0 	.word	0x200001a0
+
+080036e4 :
+ 80036e4:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80036e8:	f383 8811 	msr	BASEPRI, r3
+ 80036ec:	f3bf 8f6f 	isb	sy
+ 80036f0:	f3bf 8f4f 	dsb	sy
+ 80036f4:	4a0a      	ldr	r2, [pc, #40]	; (8003720 )
+ 80036f6:	6813      	ldr	r3, [r2, #0]
+ 80036f8:	3301      	adds	r3, #1
+ 80036fa:	2b01      	cmp	r3, #1
+ 80036fc:	6013      	str	r3, [r2, #0]
+ 80036fe:	d000      	beq.n	8003702 
+ 8003700:	4770      	bx	lr
+ 8003702:	4b08      	ldr	r3, [pc, #32]	; (8003724 )
+ 8003704:	681b      	ldr	r3, [r3, #0]
+ 8003706:	f013 0fff 	tst.w	r3, #255	; 0xff
+ 800370a:	d0f9      	beq.n	8003700 
+ 800370c:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8003710:	f383 8811 	msr	BASEPRI, r3
+ 8003714:	f3bf 8f6f 	isb	sy
+ 8003718:	f3bf 8f4f 	dsb	sy
+ 800371c:	e7fe      	b.n	800371c 
+ 800371e:	bf00      	nop
+ 8003720:	20000118 	.word	0x20000118
+ 8003724:	e000ed04 	.word	0xe000ed04
+
+08003728 :
+ 8003728:	4a08      	ldr	r2, [pc, #32]	; (800374c )
+ 800372a:	6813      	ldr	r3, [r2, #0]
+ 800372c:	b943      	cbnz	r3, 8003740 
+ 800372e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8003732:	f383 8811 	msr	BASEPRI, r3
+ 8003736:	f3bf 8f6f 	isb	sy
+ 800373a:	f3bf 8f4f 	dsb	sy
+ 800373e:	e7fe      	b.n	800373e 
+ 8003740:	3b01      	subs	r3, #1
+ 8003742:	6013      	str	r3, [r2, #0]
+ 8003744:	b90b      	cbnz	r3, 800374a 
+ 8003746:	f383 8811 	msr	BASEPRI, r3
+ 800374a:	4770      	bx	lr
+ 800374c:	20000118 	.word	0x20000118
+
+08003750 :
+ 8003750:	f3ef 8009 	mrs	r0, PSP
+ 8003754:	f3bf 8f6f 	isb	sy
+ 8003758:	4b0d      	ldr	r3, [pc, #52]	; (8003790 )
+ 800375a:	681a      	ldr	r2, [r3, #0]
+ 800375c:	e920 0ff0 	stmdb	r0!, {r4, r5, r6, r7, r8, r9, sl, fp}
+ 8003760:	6010      	str	r0, [r2, #0]
+ 8003762:	e92d 4008 	stmdb	sp!, {r3, lr}
+ 8003766:	f04f 0050 	mov.w	r0, #80	; 0x50
+ 800376a:	f380 8811 	msr	BASEPRI, r0
+ 800376e:	f7ff ff15 	bl	800359c 
+ 8003772:	f04f 0000 	mov.w	r0, #0
+ 8003776:	f380 8811 	msr	BASEPRI, r0
+ 800377a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
+ 800377e:	6819      	ldr	r1, [r3, #0]
+ 8003780:	6808      	ldr	r0, [r1, #0]
+ 8003782:	e8b0 0ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp}
+ 8003786:	f380 8809 	msr	PSP, r0
+ 800378a:	f3bf 8f6f 	isb	sy
+ 800378e:	4770      	bx	lr
+
+08003790 :
+ 8003790:	200001a0 	.word	0x200001a0
+
+08003794 :
+ 8003794:	b508      	push	{r3, lr}
+ 8003796:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 800379a:	f383 8811 	msr	BASEPRI, r3
+ 800379e:	f3bf 8f6f 	isb	sy
+ 80037a2:	f3bf 8f4f 	dsb	sy
+ 80037a6:	f7ff fd9f 	bl	80032e8 
+ 80037aa:	b118      	cbz	r0, 80037b4 
+ 80037ac:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
+ 80037b0:	4b02      	ldr	r3, [pc, #8]	; (80037bc )
+ 80037b2:	601a      	str	r2, [r3, #0]
+ 80037b4:	2300      	movs	r3, #0
+ 80037b6:	f383 8811 	msr	BASEPRI, r3
+ 80037ba:	bd08      	pop	{r3, pc}
+ 80037bc:	e000ed04 	.word	0xe000ed04
+
+080037c0 :
+ 80037c0:	2300      	movs	r3, #0
+ 80037c2:	2107      	movs	r1, #7
+ 80037c4:	b410      	push	{r4}
+ 80037c6:	4a08      	ldr	r2, [pc, #32]	; (80037e8 )
+ 80037c8:	4c08      	ldr	r4, [pc, #32]	; (80037ec )
+ 80037ca:	4809      	ldr	r0, [pc, #36]	; (80037f0 )
+ 80037cc:	6013      	str	r3, [r2, #0]
+ 80037ce:	6023      	str	r3, [r4, #0]
+ 80037d0:	6803      	ldr	r3, [r0, #0]
+ 80037d2:	4c08      	ldr	r4, [pc, #32]	; (80037f4 )
+ 80037d4:	4808      	ldr	r0, [pc, #32]	; (80037f8 )
+ 80037d6:	fba4 4303 	umull	r4, r3, r4, r3
+ 80037da:	099b      	lsrs	r3, r3, #6
+ 80037dc:	3b01      	subs	r3, #1
+ 80037de:	6003      	str	r3, [r0, #0]
+ 80037e0:	bc10      	pop	{r4}
+ 80037e2:	6011      	str	r1, [r2, #0]
+ 80037e4:	4770      	bx	lr
+ 80037e6:	bf00      	nop
+ 80037e8:	e000e010 	.word	0xe000e010
+ 80037ec:	e000e018 	.word	0xe000e018
+ 80037f0:	2000011c 	.word	0x2000011c
+ 80037f4:	10624dd3 	.word	0x10624dd3
+ 80037f8:	e000e014 	.word	0xe000e014
+
+080037fc :
+ 80037fc:	b530      	push	{r4, r5, lr}
+ 80037fe:	25ff      	movs	r5, #255	; 0xff
+ 8003800:	2407      	movs	r4, #7
+ 8003802:	4b27      	ldr	r3, [pc, #156]	; (80038a0 )
+ 8003804:	b083      	sub	sp, #12
+ 8003806:	781a      	ldrb	r2, [r3, #0]
+ 8003808:	4926      	ldr	r1, [pc, #152]	; (80038a4 )
+ 800380a:	b2d2      	uxtb	r2, r2
+ 800380c:	9201      	str	r2, [sp, #4]
+ 800380e:	701d      	strb	r5, [r3, #0]
+ 8003810:	781b      	ldrb	r3, [r3, #0]
+ 8003812:	4825      	ldr	r0, [pc, #148]	; (80038a8 )
+ 8003814:	b2db      	uxtb	r3, r3
+ 8003816:	f88d 3003 	strb.w	r3, [sp, #3]
+ 800381a:	f89d 3003 	ldrb.w	r3, [sp, #3]
+ 800381e:	f89d 2003 	ldrb.w	r2, [sp, #3]
+ 8003822:	f003 0350 	and.w	r3, r3, #80	; 0x50
+ 8003826:	700b      	strb	r3, [r1, #0]
+ 8003828:	0611      	lsls	r1, r2, #24
+ 800382a:	6004      	str	r4, [r0, #0]
+ 800382c:	d510      	bpl.n	8003850 
+ 800382e:	2306      	movs	r3, #6
+ 8003830:	e000      	b.n	8003834 
+ 8003832:	460b      	mov	r3, r1
+ 8003834:	f89d 2003 	ldrb.w	r2, [sp, #3]
+ 8003838:	1e59      	subs	r1, r3, #1
+ 800383a:	0052      	lsls	r2, r2, #1
+ 800383c:	b2d2      	uxtb	r2, r2
+ 800383e:	f88d 2003 	strb.w	r2, [sp, #3]
+ 8003842:	f89d 2003 	ldrb.w	r2, [sp, #3]
+ 8003846:	0612      	lsls	r2, r2, #24
+ 8003848:	d4f3      	bmi.n	8003832 
+ 800384a:	2b03      	cmp	r3, #3
+ 800384c:	6003      	str	r3, [r0, #0]
+ 800384e:	d008      	beq.n	8003862 
+ 8003850:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8003854:	f383 8811 	msr	BASEPRI, r3
+ 8003858:	f3bf 8f6f 	isb	sy
+ 800385c:	f3bf 8f4f 	dsb	sy
+ 8003860:	e7fe      	b.n	8003860 
+ 8003862:	2400      	movs	r4, #0
+ 8003864:	9901      	ldr	r1, [sp, #4]
+ 8003866:	4d0e      	ldr	r5, [pc, #56]	; (80038a0 )
+ 8003868:	021b      	lsls	r3, r3, #8
+ 800386a:	4a10      	ldr	r2, [pc, #64]	; (80038ac )
+ 800386c:	b2c9      	uxtb	r1, r1
+ 800386e:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
+ 8003872:	6003      	str	r3, [r0, #0]
+ 8003874:	7029      	strb	r1, [r5, #0]
+ 8003876:	6813      	ldr	r3, [r2, #0]
+ 8003878:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
+ 800387c:	6013      	str	r3, [r2, #0]
+ 800387e:	6813      	ldr	r3, [r2, #0]
+ 8003880:	f043 4370 	orr.w	r3, r3, #4026531840	; 0xf0000000
+ 8003884:	6013      	str	r3, [r2, #0]
+ 8003886:	f7ff ff9b 	bl	80037c0 
+ 800388a:	4b09      	ldr	r3, [pc, #36]	; (80038b0 )
+ 800388c:	601c      	str	r4, [r3, #0]
+ 800388e:	f7ff fef3 	bl	8003678 
+ 8003892:	f7ff fe83 	bl	800359c 
+ 8003896:	f7ff fecf 	bl	8003638 
+ 800389a:	4620      	mov	r0, r4
+ 800389c:	b003      	add	sp, #12
+ 800389e:	bd30      	pop	{r4, r5, pc}
+ 80038a0:	e000e400 	.word	0xe000e400
+ 80038a4:	200002cc 	.word	0x200002cc
+ 80038a8:	200002d0 	.word	0x200002d0
+ 80038ac:	e000ed20 	.word	0xe000ed20
+ 80038b0:	20000118 	.word	0x20000118
+
+080038b4 :
+ 80038b4:	b430      	push	{r4, r5}
+ 80038b6:	4b11      	ldr	r3, [pc, #68]	; (80038fc )
+ 80038b8:	681a      	ldr	r2, [r3, #0]
+ 80038ba:	4282      	cmp	r2, r0
+ 80038bc:	d201      	bcs.n	80038c2 
+ 80038be:	4613      	mov	r3, r2
+ 80038c0:	e7fa      	b.n	80038b8 
+ 80038c2:	685c      	ldr	r4, [r3, #4]
+ 80038c4:	1919      	adds	r1, r3, r4
+ 80038c6:	4288      	cmp	r0, r1
+ 80038c8:	d103      	bne.n	80038d2 
+ 80038ca:	6841      	ldr	r1, [r0, #4]
+ 80038cc:	4618      	mov	r0, r3
+ 80038ce:	4421      	add	r1, r4
+ 80038d0:	6059      	str	r1, [r3, #4]
+ 80038d2:	6844      	ldr	r4, [r0, #4]
+ 80038d4:	1901      	adds	r1, r0, r4
+ 80038d6:	428a      	cmp	r2, r1
+ 80038d8:	d109      	bne.n	80038ee 
+ 80038da:	4909      	ldr	r1, [pc, #36]	; (8003900 )
+ 80038dc:	6809      	ldr	r1, [r1, #0]
+ 80038de:	428a      	cmp	r2, r1
+ 80038e0:	d005      	beq.n	80038ee 
+ 80038e2:	e9d2 5100 	ldrd	r5, r1, [r2]
+ 80038e6:	4421      	add	r1, r4
+ 80038e8:	e9c0 5100 	strd	r5, r1, [r0]
+ 80038ec:	e000      	b.n	80038f0 
+ 80038ee:	6002      	str	r2, [r0, #0]
+ 80038f0:	4298      	cmp	r0, r3
+ 80038f2:	bf18      	it	ne
+ 80038f4:	6018      	strne	r0, [r3, #0]
+ 80038f6:	bc30      	pop	{r4, r5}
+ 80038f8:	4770      	bx	lr
+ 80038fa:	bf00      	nop
+ 80038fc:	20000ee4 	.word	0x20000ee4
+ 8003900:	200002d4 	.word	0x200002d4
+
+08003904 :
+ 8003904:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 8003908:	4f41      	ldr	r7, [pc, #260]	; (8003a10 )
+ 800390a:	4604      	mov	r4, r0
+ 800390c:	f7ff fce4 	bl	80032d8 
+ 8003910:	683a      	ldr	r2, [r7, #0]
+ 8003912:	2a00      	cmp	r2, #0
+ 8003914:	d05a      	beq.n	80039cc 
+ 8003916:	4b3f      	ldr	r3, [pc, #252]	; (8003a14 )
+ 8003918:	681e      	ldr	r6, [r3, #0]
+ 800391a:	4234      	tst	r4, r6
+ 800391c:	d150      	bne.n	80039c0 
+ 800391e:	2c00      	cmp	r4, #0
+ 8003920:	d04e      	beq.n	80039c0 
+ 8003922:	f104 0308 	add.w	r3, r4, #8
+ 8003926:	0758      	lsls	r0, r3, #29
+ 8003928:	bf1c      	itt	ne
+ 800392a:	f023 0307 	bicne.w	r3, r3, #7
+ 800392e:	3308      	addne	r3, #8
+ 8003930:	2b00      	cmp	r3, #0
+ 8003932:	d045      	beq.n	80039c0 
+ 8003934:	f8df 80f0 	ldr.w	r8, [pc, #240]	; 8003a28 
+ 8003938:	f8d8 5000 	ldr.w	r5, [r8]
+ 800393c:	429d      	cmp	r5, r3
+ 800393e:	d33f      	bcc.n	80039c0 
+ 8003940:	4835      	ldr	r0, [pc, #212]	; (8003a18 )
+ 8003942:	6804      	ldr	r4, [r0, #0]
+ 8003944:	e006      	b.n	8003954 
+ 8003946:	f8d4 c000 	ldr.w	ip, [r4]
+ 800394a:	f1bc 0f00 	cmp.w	ip, #0
+ 800394e:	d004      	beq.n	800395a 
+ 8003950:	4620      	mov	r0, r4
+ 8003952:	4664      	mov	r4, ip
+ 8003954:	6861      	ldr	r1, [r4, #4]
+ 8003956:	4299      	cmp	r1, r3
+ 8003958:	d3f5      	bcc.n	8003946 
+ 800395a:	4294      	cmp	r4, r2
+ 800395c:	d030      	beq.n	80039c0 
+ 800395e:	1aca      	subs	r2, r1, r3
+ 8003960:	6827      	ldr	r7, [r4, #0]
+ 8003962:	2a10      	cmp	r2, #16
+ 8003964:	6007      	str	r7, [r0, #0]
+ 8003966:	d910      	bls.n	800398a 
+ 8003968:	18e0      	adds	r0, r4, r3
+ 800396a:	0741      	lsls	r1, r0, #29
+ 800396c:	d008      	beq.n	8003980 
+ 800396e:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8003972:	f383 8811 	msr	BASEPRI, r3
+ 8003976:	f3bf 8f6f 	isb	sy
+ 800397a:	f3bf 8f4f 	dsb	sy
+ 800397e:	e7fe      	b.n	800397e 
+ 8003980:	6042      	str	r2, [r0, #4]
+ 8003982:	6063      	str	r3, [r4, #4]
+ 8003984:	f7ff ff96 	bl	80038b4 
+ 8003988:	6861      	ldr	r1, [r4, #4]
+ 800398a:	2300      	movs	r3, #0
+ 800398c:	4a23      	ldr	r2, [pc, #140]	; (8003a1c )
+ 800398e:	1a6d      	subs	r5, r5, r1
+ 8003990:	6810      	ldr	r0, [r2, #0]
+ 8003992:	4331      	orrs	r1, r6
+ 8003994:	4285      	cmp	r5, r0
+ 8003996:	e9c4 3100 	strd	r3, r1, [r4]
+ 800399a:	f104 0408 	add.w	r4, r4, #8
+ 800399e:	bf38      	it	cc
+ 80039a0:	6015      	strcc	r5, [r2, #0]
+ 80039a2:	f8c8 5000 	str.w	r5, [r8]
+ 80039a6:	f7ff fd4b 	bl	8003440 
+ 80039aa:	0763      	lsls	r3, r4, #29
+ 80039ac:	d00b      	beq.n	80039c6 
+ 80039ae:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 80039b2:	f383 8811 	msr	BASEPRI, r3
+ 80039b6:	f3bf 8f6f 	isb	sy
+ 80039ba:	f3bf 8f4f 	dsb	sy
+ 80039be:	e7fe      	b.n	80039be 
+ 80039c0:	f7ff fd3e 	bl	8003440 
+ 80039c4:	2400      	movs	r4, #0
+ 80039c6:	4620      	mov	r0, r4
+ 80039c8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 80039cc:	4b14      	ldr	r3, [pc, #80]	; (8003a20 )
+ 80039ce:	2000      	movs	r0, #0
+ 80039d0:	075d      	lsls	r5, r3, #29
+ 80039d2:	bf1c      	itt	ne
+ 80039d4:	3307      	addne	r3, #7
+ 80039d6:	f023 0307 	bicne.w	r3, r3, #7
+ 80039da:	4619      	mov	r1, r3
+ 80039dc:	f04f 4500 	mov.w	r5, #2147483648	; 0x80000000
+ 80039e0:	4a10      	ldr	r2, [pc, #64]	; (8003a24 )
+ 80039e2:	f8df c034 	ldr.w	ip, [pc, #52]	; 8003a18 
+ 80039e6:	f022 0207 	bic.w	r2, r2, #7
+ 80039ea:	1ad3      	subs	r3, r2, r3
+ 80039ec:	f8cc 0004 	str.w	r0, [ip, #4]
+ 80039f0:	f8cc 1000 	str.w	r1, [ip]
+ 80039f4:	603a      	str	r2, [r7, #0]
+ 80039f6:	e9c2 0000 	strd	r0, r0, [r2]
+ 80039fa:	4f08      	ldr	r7, [pc, #32]	; (8003a1c )
+ 80039fc:	e9c1 2300 	strd	r2, r3, [r1]
+ 8003a00:	4809      	ldr	r0, [pc, #36]	; (8003a28 )
+ 8003a02:	4904      	ldr	r1, [pc, #16]	; (8003a14 )
+ 8003a04:	462e      	mov	r6, r5
+ 8003a06:	603b      	str	r3, [r7, #0]
+ 8003a08:	6003      	str	r3, [r0, #0]
+ 8003a0a:	600d      	str	r5, [r1, #0]
+ 8003a0c:	e785      	b.n	800391a 
+ 8003a0e:	bf00      	nop
+ 8003a10:	200002d4 	.word	0x200002d4
+ 8003a14:	20000ed8 	.word	0x20000ed8
+ 8003a18:	20000ee4 	.word	0x20000ee4
+ 8003a1c:	20000ee0 	.word	0x20000ee0
+ 8003a20:	200002d8 	.word	0x200002d8
+ 8003a24:	20000ed0 	.word	0x20000ed0
+ 8003a28:	20000edc 	.word	0x20000edc
+
+08003a2c :
+ 8003a2c:	b1d0      	cbz	r0, 8003a64 
+ 8003a2e:	4a19      	ldr	r2, [pc, #100]	; (8003a94 )
+ 8003a30:	f850 3c04 	ldr.w	r3, [r0, #-4]
+ 8003a34:	6812      	ldr	r2, [r2, #0]
+ 8003a36:	4213      	tst	r3, r2
+ 8003a38:	d108      	bne.n	8003a4c 
+ 8003a3a:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8003a3e:	f383 8811 	msr	BASEPRI, r3
+ 8003a42:	f3bf 8f6f 	isb	sy
+ 8003a46:	f3bf 8f4f 	dsb	sy
+ 8003a4a:	e7fe      	b.n	8003a4a 
+ 8003a4c:	f850 1c08 	ldr.w	r1, [r0, #-8]
+ 8003a50:	b149      	cbz	r1, 8003a66 
+ 8003a52:	f04f 0350 	mov.w	r3, #80	; 0x50
+ 8003a56:	f383 8811 	msr	BASEPRI, r3
+ 8003a5a:	f3bf 8f6f 	isb	sy
+ 8003a5e:	f3bf 8f4f 	dsb	sy
+ 8003a62:	e7fe      	b.n	8003a62 
+ 8003a64:	4770      	bx	lr
+ 8003a66:	b510      	push	{r4, lr}
+ 8003a68:	4604      	mov	r4, r0
+ 8003a6a:	ea23 0302 	bic.w	r3, r3, r2
+ 8003a6e:	f840 3c04 	str.w	r3, [r0, #-4]
+ 8003a72:	f7ff fc31 	bl	80032d8 
+ 8003a76:	4a08      	ldr	r2, [pc, #32]	; (8003a98 )
+ 8003a78:	f854 3c04 	ldr.w	r3, [r4, #-4]
+ 8003a7c:	6811      	ldr	r1, [r2, #0]
+ 8003a7e:	f1a4 0008 	sub.w	r0, r4, #8
+ 8003a82:	440b      	add	r3, r1
+ 8003a84:	6013      	str	r3, [r2, #0]
+ 8003a86:	f7ff ff15 	bl	80038b4 
+ 8003a8a:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+ 8003a8e:	f7ff bcd7 	b.w	8003440 
+ 8003a92:	bf00      	nop
+ 8003a94:	20000ed8 	.word	0x20000ed8
+ 8003a98:	20000edc 	.word	0x20000edc
+
+08003a9c :
+ 8003a9c:	b508      	push	{r3, lr}
+ 8003a9e:	f000 fa1f 	bl	8003ee0 
+ 8003aa2:	2001      	movs	r0, #1
+ 8003aa4:	f7ff f920 	bl	8002ce8 
+ 8003aa8:	e7fb      	b.n	8003aa2 
+ 8003aaa:	bf00      	nop
+
+08003aac :
+ 8003aac:	b508      	push	{r3, lr}
+ 8003aae:	2001      	movs	r0, #1
+ 8003ab0:	f7ff f91a 	bl	8002ce8 
+ 8003ab4:	e7fb      	b.n	8003aae 
+ 8003ab6:	bf00      	nop
+
+08003ab8 :
+ 8003ab8:	b570      	push	{r4, r5, r6, lr}
+ 8003aba:	f44f 3380 	mov.w	r3, #65536	; 0x10000
+ 8003abe:	2400      	movs	r4, #0
+ 8003ac0:	2501      	movs	r5, #1
+ 8003ac2:	2109      	movs	r1, #9
+ 8003ac4:	2602      	movs	r6, #2
+ 8003ac6:	f44f 1280 	mov.w	r2, #1048576	; 0x100000
+ 8003aca:	b094      	sub	sp, #80	; 0x50
+ 8003acc:	a80a      	add	r0, sp, #40	; 0x28
+ 8003ace:	e9cd 130a 	strd	r1, r3, [sp, #40]	; 0x28
+ 8003ad2:	9312      	str	r3, [sp, #72]	; 0x48
+ 8003ad4:	9213      	str	r2, [sp, #76]	; 0x4c
+ 8003ad6:	940c      	str	r4, [sp, #48]	; 0x30
+ 8003ad8:	9405      	str	r4, [sp, #20]
+ 8003ada:	9401      	str	r4, [sp, #4]
+ 8003adc:	940d      	str	r4, [sp, #52]	; 0x34
+ 8003ade:	940f      	str	r4, [sp, #60]	; 0x3c
+ 8003ae0:	e9cd 4406 	strd	r4, r4, [sp, #24]
+ 8003ae4:	e9cd 4408 	strd	r4, r4, [sp, #32]
+ 8003ae8:	e9cd 4402 	strd	r4, r4, [sp, #8]
+ 8003aec:	9404      	str	r4, [sp, #16]
+ 8003aee:	950e      	str	r5, [sp, #56]	; 0x38
+ 8003af0:	e9cd 5610 	strd	r5, r6, [sp, #64]	; 0x40
+ 8003af4:	f7fd f9d6 	bl	8000ea4 
+ 8003af8:	220f      	movs	r2, #15
+ 8003afa:	f44f 6380 	mov.w	r3, #1024	; 0x400
+ 8003afe:	4629      	mov	r1, r5
+ 8003b00:	a805      	add	r0, sp, #20
+ 8003b02:	9205      	str	r2, [sp, #20]
+ 8003b04:	9308      	str	r3, [sp, #32]
+ 8003b06:	e9cd 6406 	strd	r6, r4, [sp, #24]
+ 8003b0a:	9409      	str	r4, [sp, #36]	; 0x24
+ 8003b0c:	f7fd fbc2 	bl	8001294 
+ 8003b10:	2111      	movs	r1, #17
+ 8003b12:	f44f 7200 	mov.w	r2, #512	; 0x200
+ 8003b16:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
+ 8003b1a:	a801      	add	r0, sp, #4
+ 8003b1c:	e9cd 1201 	strd	r1, r2, [sp, #4]
+ 8003b20:	9304      	str	r3, [sp, #16]
+ 8003b22:	f7fd fca3 	bl	800146c 
+ 8003b26:	b014      	add	sp, #80	; 0x50
+ 8003b28:	bd70      	pop	{r4, r5, r6, pc}
+ 8003b2a:	bf00      	nop
+
+08003b2c 
:
+ 8003b2c:	2400      	movs	r4, #0
+ 8003b2e:	b580      	push	{r7, lr}
+ 8003b30:	b08e      	sub	sp, #56	; 0x38
+ 8003b32:	f7fc fb31 	bl	8000198 
+ 8003b36:	f7ff ffbf 	bl	8003ab8 
+ 8003b3a:	4b41      	ldr	r3, [pc, #260]	; (8003c40 )
+ 8003b3c:	f44f 4580 	mov.w	r5, #16384	; 0x4000
+ 8003b40:	699a      	ldr	r2, [r3, #24]
+ 8003b42:	4e40      	ldr	r6, [pc, #256]	; (8003c44 )
+ 8003b44:	f042 0210 	orr.w	r2, r2, #16
+ 8003b48:	619a      	str	r2, [r3, #24]
+ 8003b4a:	6999      	ldr	r1, [r3, #24]
+ 8003b4c:	4a3e      	ldr	r2, [pc, #248]	; (8003c48 )
+ 8003b4e:	f001 0110 	and.w	r1, r1, #16
+ 8003b52:	9100      	str	r1, [sp, #0]
+ 8003b54:	9900      	ldr	r1, [sp, #0]
+ 8003b56:	6999      	ldr	r1, [r3, #24]
+ 8003b58:	4f3c      	ldr	r7, [pc, #240]	; (8003c4c )
+ 8003b5a:	f041 0120 	orr.w	r1, r1, #32
+ 8003b5e:	6199      	str	r1, [r3, #24]
+ 8003b60:	6999      	ldr	r1, [r3, #24]
+ 8003b62:	4610      	mov	r0, r2
+ 8003b64:	f001 0120 	and.w	r1, r1, #32
+ 8003b68:	9101      	str	r1, [sp, #4]
+ 8003b6a:	9901      	ldr	r1, [sp, #4]
+ 8003b6c:	6999      	ldr	r1, [r3, #24]
+ 8003b6e:	6094      	str	r4, [r2, #8]
+ 8003b70:	f041 0104 	orr.w	r1, r1, #4
+ 8003b74:	6199      	str	r1, [r3, #24]
+ 8003b76:	6999      	ldr	r1, [r3, #24]
+ 8003b78:	60d4      	str	r4, [r2, #12]
+ 8003b7a:	f001 0104 	and.w	r1, r1, #4
+ 8003b7e:	9102      	str	r1, [sp, #8]
+ 8003b80:	9902      	ldr	r1, [sp, #8]
+ 8003b82:	6999      	ldr	r1, [r3, #24]
+ 8003b84:	6154      	str	r4, [r2, #20]
+ 8003b86:	f041 0108 	orr.w	r1, r1, #8
+ 8003b8a:	6199      	str	r1, [r3, #24]
+ 8003b8c:	699b      	ldr	r3, [r3, #24]
+ 8003b8e:	e9c2 7600 	strd	r7, r6, [r2]
+ 8003b92:	f003 0308 	and.w	r3, r3, #8
+ 8003b96:	9303      	str	r3, [sp, #12]
+ 8003b98:	6115      	str	r5, [r2, #16]
+ 8003b9a:	9b03      	ldr	r3, [sp, #12]
+ 8003b9c:	e9c2 4406 	strd	r4, r4, [r2, #24]
+ 8003ba0:	6214      	str	r4, [r2, #32]
+ 8003ba2:	f04f 35ff 	mov.w	r5, #4294967295	; 0xffffffff
+ 8003ba6:	f7fc fc83 	bl	80004b0 
+ 8003baa:	f44f 7280 	mov.w	r2, #256	; 0x100
+ 8003bae:	4b28      	ldr	r3, [pc, #160]	; (8003c50 )
+ 8003bb0:	4928      	ldr	r1, [pc, #160]	; (8003c54 )
+ 8003bb2:	4618      	mov	r0, r3
+ 8003bb4:	e9c3 1500 	strd	r1, r5, [r3]
+ 8003bb8:	609a      	str	r2, [r3, #8]
+ 8003bba:	f44f 7582 	mov.w	r5, #260	; 0x104
+ 8003bbe:	f7fd fd4f 	bl	8001660 
+ 8003bc2:	f44f 7100 	mov.w	r1, #512	; 0x200
+ 8003bc6:	220a      	movs	r2, #10
+ 8003bc8:	4b23      	ldr	r3, [pc, #140]	; (8003c58 )
+ 8003bca:	4e24      	ldr	r6, [pc, #144]	; (8003c5c )
+ 8003bcc:	4618      	mov	r0, r3
+ 8003bce:	e9c3 6500 	strd	r6, r5, [r3]
+ 8003bd2:	6199      	str	r1, [r3, #24]
+ 8003bd4:	62da      	str	r2, [r3, #44]	; 0x2c
+ 8003bd6:	e9c3 4402 	strd	r4, r4, [r3, #8]
+ 8003bda:	e9c3 4404 	strd	r4, r4, [r3, #16]
+ 8003bde:	e9c3 4407 	strd	r4, r4, [r3, #28]
+ 8003be2:	e9c3 4409 	strd	r4, r4, [r3, #36]	; 0x24
+ 8003be6:	f7fd fdb9 	bl	800175c 
+ 8003bea:	f44f 31e1 	mov.w	r1, #115200	; 0x1c200
+ 8003bee:	220c      	movs	r2, #12
+ 8003bf0:	4b1b      	ldr	r3, [pc, #108]	; (8003c60 )
+ 8003bf2:	4d1c      	ldr	r5, [pc, #112]	; (8003c64 )
+ 8003bf4:	4618      	mov	r0, r3
+ 8003bf6:	e9c3 5100 	strd	r5, r1, [r3]
+ 8003bfa:	4d1b      	ldr	r5, [pc, #108]	; (8003c68 )
+ 8003bfc:	ae04      	add	r6, sp, #16
+ 8003bfe:	e9c3 4402 	strd	r4, r4, [r3, #8]
+ 8003c02:	611c      	str	r4, [r3, #16]
+ 8003c04:	e9c3 4406 	strd	r4, r4, [r3, #24]
+ 8003c08:	615a      	str	r2, [r3, #20]
+ 8003c0a:	f7fd fde7 	bl	80017dc 
+ 8003c0e:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 8003c10:	c60f      	stmia	r6!, {r0, r1, r2, r3}
+ 8003c12:	f855 3b04 	ldr.w	r3, [r5], #4
+ 8003c16:	4621      	mov	r1, r4
+ 8003c18:	a804      	add	r0, sp, #16
+ 8003c1a:	6033      	str	r3, [r6, #0]
+ 8003c1c:	f7ff f84a 	bl	8002cb4 
+ 8003c20:	4b12      	ldr	r3, [pc, #72]	; (8003c6c )
+ 8003c22:	ae09      	add	r6, sp, #36	; 0x24
+ 8003c24:	6018      	str	r0, [r3, #0]
+ 8003c26:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 8003c28:	c60f      	stmia	r6!, {r0, r1, r2, r3}
+ 8003c2a:	682b      	ldr	r3, [r5, #0]
+ 8003c2c:	4621      	mov	r1, r4
+ 8003c2e:	a809      	add	r0, sp, #36	; 0x24
+ 8003c30:	6033      	str	r3, [r6, #0]
+ 8003c32:	f7ff f83f 	bl	8002cb4 
+ 8003c36:	4b0e      	ldr	r3, [pc, #56]	; (8003c70 )
+ 8003c38:	6018      	str	r0, [r3, #0]
+ 8003c3a:	f7ff f835 	bl	8002ca8 
+ 8003c3e:	e7fe      	b.n	8003c3e 
+ 8003c40:	40021000 	.word	0x40021000
+ 8003c44:	000186a0 	.word	0x000186a0
+ 8003c48:	2000116c 	.word	0x2000116c
+ 8003c4c:	40005400 	.word	0x40005400
+ 8003c50:	200011c4 	.word	0x200011c4
+ 8003c54:	40002800 	.word	0x40002800
+ 8003c58:	20001114 	.word	0x20001114
+ 8003c5c:	40003800 	.word	0x40003800
+ 8003c60:	200011d8 	.word	0x200011d8
+ 8003c64:	40004400 	.word	0x40004400
+ 8003c68:	0800445c 	.word	0x0800445c
+ 8003c6c:	20001110 	.word	0x20001110
+ 8003c70:	200011c0 	.word	0x200011c0
+
+08003c74 :
+ 8003c74:	4770      	bx	lr
+ 8003c76:	bf00      	nop
+
+08003c78 :
+ 8003c78:	4b11      	ldr	r3, [pc, #68]	; (8003cc0 )
+ 8003c7a:	b510      	push	{r4, lr}
+ 8003c7c:	6998      	ldr	r0, [r3, #24]
+ 8003c7e:	b082      	sub	sp, #8
+ 8003c80:	f040 0001 	orr.w	r0, r0, #1
+ 8003c84:	6198      	str	r0, [r3, #24]
+ 8003c86:	699c      	ldr	r4, [r3, #24]
+ 8003c88:	2200      	movs	r2, #0
+ 8003c8a:	f004 0401 	and.w	r4, r4, #1
+ 8003c8e:	9400      	str	r4, [sp, #0]
+ 8003c90:	9c00      	ldr	r4, [sp, #0]
+ 8003c92:	69dc      	ldr	r4, [r3, #28]
+ 8003c94:	210f      	movs	r1, #15
+ 8003c96:	f044 5480 	orr.w	r4, r4, #268435456	; 0x10000000
+ 8003c9a:	61dc      	str	r4, [r3, #28]
+ 8003c9c:	69db      	ldr	r3, [r3, #28]
+ 8003c9e:	f06f 0001 	mvn.w	r0, #1
+ 8003ca2:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
+ 8003ca6:	9301      	str	r3, [sp, #4]
+ 8003ca8:	9b01      	ldr	r3, [sp, #4]
+ 8003caa:	f7fc faab 	bl	8000204 
+ 8003cae:	4a05      	ldr	r2, [pc, #20]	; (8003cc4 )
+ 8003cb0:	6853      	ldr	r3, [r2, #4]
+ 8003cb2:	f023 63e0 	bic.w	r3, r3, #117440512	; 0x7000000
+ 8003cb6:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
+ 8003cba:	6053      	str	r3, [r2, #4]
+ 8003cbc:	b002      	add	sp, #8
+ 8003cbe:	bd10      	pop	{r4, pc}
+ 8003cc0:	40021000 	.word	0x40021000
+ 8003cc4:	40010000 	.word	0x40010000
+
+08003cc8 :
+ 8003cc8:	2300      	movs	r3, #0
+ 8003cca:	b530      	push	{r4, r5, lr}
+ 8003ccc:	6801      	ldr	r1, [r0, #0]
+ 8003cce:	4a14      	ldr	r2, [pc, #80]	; (8003d20 )
+ 8003cd0:	b087      	sub	sp, #28
+ 8003cd2:	4291      	cmp	r1, r2
+ 8003cd4:	e9cd 3302 	strd	r3, r3, [sp, #8]
+ 8003cd8:	e9cd 3304 	strd	r3, r3, [sp, #16]
+ 8003cdc:	d001      	beq.n	8003ce2 
+ 8003cde:	b007      	add	sp, #28
+ 8003ce0:	bd30      	pop	{r4, r5, pc}
+ 8003ce2:	20c0      	movs	r0, #192	; 0xc0
+ 8003ce4:	2203      	movs	r2, #3
+ 8003ce6:	2512      	movs	r5, #18
+ 8003ce8:	4c0e      	ldr	r4, [pc, #56]	; (8003d24 )
+ 8003cea:	a902      	add	r1, sp, #8
+ 8003cec:	69a3      	ldr	r3, [r4, #24]
+ 8003cee:	f043 0308 	orr.w	r3, r3, #8
+ 8003cf2:	61a3      	str	r3, [r4, #24]
+ 8003cf4:	69a3      	ldr	r3, [r4, #24]
+ 8003cf6:	9002      	str	r0, [sp, #8]
+ 8003cf8:	f003 0308 	and.w	r3, r3, #8
+ 8003cfc:	9300      	str	r3, [sp, #0]
+ 8003cfe:	480a      	ldr	r0, [pc, #40]	; (8003d28 )
+ 8003d00:	9b00      	ldr	r3, [sp, #0]
+ 8003d02:	9503      	str	r5, [sp, #12]
+ 8003d04:	9205      	str	r2, [sp, #20]
+ 8003d06:	f7fc fad9 	bl	80002bc 
+ 8003d0a:	69e3      	ldr	r3, [r4, #28]
+ 8003d0c:	f443 1300 	orr.w	r3, r3, #2097152	; 0x200000
+ 8003d10:	61e3      	str	r3, [r4, #28]
+ 8003d12:	69e3      	ldr	r3, [r4, #28]
+ 8003d14:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
+ 8003d18:	9301      	str	r3, [sp, #4]
+ 8003d1a:	9b01      	ldr	r3, [sp, #4]
+ 8003d1c:	b007      	add	sp, #28
+ 8003d1e:	bd30      	pop	{r4, r5, pc}
+ 8003d20:	40005400 	.word	0x40005400
+ 8003d24:	40021000 	.word	0x40021000
+ 8003d28:	40010c00 	.word	0x40010c00
+
+08003d2c :
+ 8003d2c:	6802      	ldr	r2, [r0, #0]
+ 8003d2e:	4b0c      	ldr	r3, [pc, #48]	; (8003d60 )
+ 8003d30:	429a      	cmp	r2, r3
+ 8003d32:	d000      	beq.n	8003d36 
+ 8003d34:	4770      	bx	lr
+ 8003d36:	b500      	push	{lr}
+ 8003d38:	b083      	sub	sp, #12
+ 8003d3a:	f7fd f8ad 	bl	8000e98 
+ 8003d3e:	2001      	movs	r0, #1
+ 8003d40:	4b08      	ldr	r3, [pc, #32]	; (8003d64 )
+ 8003d42:	4909      	ldr	r1, [pc, #36]	; (8003d68 )
+ 8003d44:	69da      	ldr	r2, [r3, #28]
+ 8003d46:	f042 6200 	orr.w	r2, r2, #134217728	; 0x8000000
+ 8003d4a:	61da      	str	r2, [r3, #28]
+ 8003d4c:	69db      	ldr	r3, [r3, #28]
+ 8003d4e:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
+ 8003d52:	9301      	str	r3, [sp, #4]
+ 8003d54:	9b01      	ldr	r3, [sp, #4]
+ 8003d56:	6008      	str	r0, [r1, #0]
+ 8003d58:	b003      	add	sp, #12
+ 8003d5a:	f85d fb04 	ldr.w	pc, [sp], #4
+ 8003d5e:	bf00      	nop
+ 8003d60:	40002800 	.word	0x40002800
+ 8003d64:	40021000 	.word	0x40021000
+ 8003d68:	4242043c 	.word	0x4242043c
+
+08003d6c :
+ 8003d6c:	b570      	push	{r4, r5, r6, lr}
+ 8003d6e:	2400      	movs	r4, #0
+ 8003d70:	6802      	ldr	r2, [r0, #0]
+ 8003d72:	4b1a      	ldr	r3, [pc, #104]	; (8003ddc )
+ 8003d74:	b086      	sub	sp, #24
+ 8003d76:	429a      	cmp	r2, r3
+ 8003d78:	e9cd 4402 	strd	r4, r4, [sp, #8]
+ 8003d7c:	e9cd 4404 	strd	r4, r4, [sp, #16]
+ 8003d80:	d001      	beq.n	8003d86 
+ 8003d82:	b006      	add	sp, #24
+ 8003d84:	bd70      	pop	{r4, r5, r6, pc}
+ 8003d86:	f44f 4120 	mov.w	r1, #40960	; 0xa000
+ 8003d8a:	2602      	movs	r6, #2
+ 8003d8c:	2503      	movs	r5, #3
+ 8003d8e:	f503 33ec 	add.w	r3, r3, #120832	; 0x1d800
+ 8003d92:	69da      	ldr	r2, [r3, #28]
+ 8003d94:	4812      	ldr	r0, [pc, #72]	; (8003de0 )
+ 8003d96:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
+ 8003d9a:	61da      	str	r2, [r3, #28]
+ 8003d9c:	69da      	ldr	r2, [r3, #28]
+ 8003d9e:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
+ 8003da2:	9200      	str	r2, [sp, #0]
+ 8003da4:	9a00      	ldr	r2, [sp, #0]
+ 8003da6:	699a      	ldr	r2, [r3, #24]
+ 8003da8:	f042 0208 	orr.w	r2, r2, #8
+ 8003dac:	619a      	str	r2, [r3, #24]
+ 8003dae:	699b      	ldr	r3, [r3, #24]
+ 8003db0:	9102      	str	r1, [sp, #8]
+ 8003db2:	f003 0308 	and.w	r3, r3, #8
+ 8003db6:	9301      	str	r3, [sp, #4]
+ 8003db8:	a902      	add	r1, sp, #8
+ 8003dba:	9b01      	ldr	r3, [sp, #4]
+ 8003dbc:	9603      	str	r6, [sp, #12]
+ 8003dbe:	9505      	str	r5, [sp, #20]
+ 8003dc0:	f7fc fa7c 	bl	80002bc 
+ 8003dc4:	f44f 4380 	mov.w	r3, #16384	; 0x4000
+ 8003dc8:	a902      	add	r1, sp, #8
+ 8003dca:	4805      	ldr	r0, [pc, #20]	; (8003de0 )
+ 8003dcc:	e9cd 4403 	strd	r4, r4, [sp, #12]
+ 8003dd0:	9302      	str	r3, [sp, #8]
+ 8003dd2:	f7fc fa73 	bl	80002bc 
+ 8003dd6:	b006      	add	sp, #24
+ 8003dd8:	bd70      	pop	{r4, r5, r6, pc}
+ 8003dda:	bf00      	nop
+ 8003ddc:	40003800 	.word	0x40003800
+ 8003de0:	40010c00 	.word	0x40010c00
+
+08003de4 :
+ 8003de4:	b570      	push	{r4, r5, r6, lr}
+ 8003de6:	2400      	movs	r4, #0
+ 8003de8:	6802      	ldr	r2, [r0, #0]
+ 8003dea:	4b18      	ldr	r3, [pc, #96]	; (8003e4c )
+ 8003dec:	b086      	sub	sp, #24
+ 8003dee:	429a      	cmp	r2, r3
+ 8003df0:	e9cd 4402 	strd	r4, r4, [sp, #8]
+ 8003df4:	e9cd 4404 	strd	r4, r4, [sp, #16]
+ 8003df8:	d001      	beq.n	8003dfe 
+ 8003dfa:	b006      	add	sp, #24
+ 8003dfc:	bd70      	pop	{r4, r5, r6, pc}
+ 8003dfe:	2104      	movs	r1, #4
+ 8003e00:	2602      	movs	r6, #2
+ 8003e02:	2503      	movs	r5, #3
+ 8003e04:	f503 33e6 	add.w	r3, r3, #117760	; 0x1cc00
+ 8003e08:	69da      	ldr	r2, [r3, #28]
+ 8003e0a:	4811      	ldr	r0, [pc, #68]	; (8003e50 )
+ 8003e0c:	f442 3200 	orr.w	r2, r2, #131072	; 0x20000
+ 8003e10:	61da      	str	r2, [r3, #28]
+ 8003e12:	69da      	ldr	r2, [r3, #28]
+ 8003e14:	f402 3200 	and.w	r2, r2, #131072	; 0x20000
+ 8003e18:	9200      	str	r2, [sp, #0]
+ 8003e1a:	9a00      	ldr	r2, [sp, #0]
+ 8003e1c:	699a      	ldr	r2, [r3, #24]
+ 8003e1e:	430a      	orrs	r2, r1
+ 8003e20:	619a      	str	r2, [r3, #24]
+ 8003e22:	699b      	ldr	r3, [r3, #24]
+ 8003e24:	9102      	str	r1, [sp, #8]
+ 8003e26:	400b      	ands	r3, r1
+ 8003e28:	9301      	str	r3, [sp, #4]
+ 8003e2a:	a902      	add	r1, sp, #8
+ 8003e2c:	9b01      	ldr	r3, [sp, #4]
+ 8003e2e:	9603      	str	r6, [sp, #12]
+ 8003e30:	9505      	str	r5, [sp, #20]
+ 8003e32:	f7fc fa43 	bl	80002bc 
+ 8003e36:	2308      	movs	r3, #8
+ 8003e38:	4805      	ldr	r0, [pc, #20]	; (8003e50 )
+ 8003e3a:	eb0d 0103 	add.w	r1, sp, r3
+ 8003e3e:	e9cd 4403 	strd	r4, r4, [sp, #12]
+ 8003e42:	9302      	str	r3, [sp, #8]
+ 8003e44:	f7fc fa3a 	bl	80002bc 
+ 8003e48:	b006      	add	sp, #24
+ 8003e4a:	bd70      	pop	{r4, r5, r6, pc}
+ 8003e4c:	40004400 	.word	0x40004400
+ 8003e50:	40010800 	.word	0x40010800
+
+08003e54 :
+ 8003e54:	4770      	bx	lr
+ 8003e56:	bf00      	nop
+
+08003e58 :
+ 8003e58:	e7fe      	b.n	8003e58 
+ 8003e5a:	bf00      	nop
+
+08003e5c :
+ 8003e5c:	e7fe      	b.n	8003e5c 
+ 8003e5e:	bf00      	nop
+
+08003e60 :
+ 8003e60:	e7fe      	b.n	8003e60 
+ 8003e62:	bf00      	nop
+
+08003e64 :
+ 8003e64:	e7fe      	b.n	8003e64 
+ 8003e66:	bf00      	nop
+
+08003e68 :
+ 8003e68:	4770      	bx	lr
+ 8003e6a:	bf00      	nop
+
+08003e6c :
+ 8003e6c:	b508      	push	{r3, lr}
+ 8003e6e:	f7fc f9a5 	bl	80001bc 
+ 8003e72:	f7ff fbd1 	bl	8003618 
+ 8003e76:	2801      	cmp	r0, #1
+ 8003e78:	d003      	beq.n	8003e82 
+ 8003e7a:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
+ 8003e7e:	f7ff bc89 	b.w	8003794 
+ 8003e82:	bd08      	pop	{r3, pc}
+
+08003e84 :
+ 8003e84:	4801      	ldr	r0, [pc, #4]	; (8003e8c )
+ 8003e86:	f7fc bc61 	b.w	800074c 
+ 8003e8a:	bf00      	nop
+ 8003e8c:	20001cac 	.word	0x20001cac
+
+08003e90 :
+ 8003e90:	b430      	push	{r4, r5}
+ 8003e92:	f44f 051f 	mov.w	r5, #10420224	; 0x9f0000
+ 8003e96:	f04f 6400 	mov.w	r4, #134217728	; 0x8000000
+ 8003e9a:	4b0e      	ldr	r3, [pc, #56]	; (8003ed4 )
+ 8003e9c:	4a0e      	ldr	r2, [pc, #56]	; (8003ed8 )
+ 8003e9e:	6819      	ldr	r1, [r3, #0]
+ 8003ea0:	480e      	ldr	r0, [pc, #56]	; (8003edc )
+ 8003ea2:	f041 0101 	orr.w	r1, r1, #1
+ 8003ea6:	6019      	str	r1, [r3, #0]
+ 8003ea8:	6859      	ldr	r1, [r3, #4]
+ 8003eaa:	400a      	ands	r2, r1
+ 8003eac:	605a      	str	r2, [r3, #4]
+ 8003eae:	681a      	ldr	r2, [r3, #0]
+ 8003eb0:	f022 7284 	bic.w	r2, r2, #17301504	; 0x1080000
+ 8003eb4:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
+ 8003eb8:	601a      	str	r2, [r3, #0]
+ 8003eba:	681a      	ldr	r2, [r3, #0]
+ 8003ebc:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
+ 8003ec0:	601a      	str	r2, [r3, #0]
+ 8003ec2:	685a      	ldr	r2, [r3, #4]
+ 8003ec4:	f422 02fe 	bic.w	r2, r2, #8323072	; 0x7f0000
+ 8003ec8:	605a      	str	r2, [r3, #4]
+ 8003eca:	609d      	str	r5, [r3, #8]
+ 8003ecc:	6084      	str	r4, [r0, #8]
+ 8003ece:	bc30      	pop	{r4, r5}
+ 8003ed0:	4770      	bx	lr
+ 8003ed2:	bf00      	nop
+ 8003ed4:	40021000 	.word	0x40021000
+ 8003ed8:	f8ff0000 	.word	0xf8ff0000
+ 8003edc:	e000ed00 	.word	0xe000ed00
+
+08003ee0 :
+ 8003ee0:	b508      	push	{r3, lr}
+ 8003ee2:	2200      	movs	r2, #0
+ 8003ee4:	4910      	ldr	r1, [pc, #64]	; (8003f28 )
+ 8003ee6:	4811      	ldr	r0, [pc, #68]	; (8003f2c )
+ 8003ee8:	f7fe fabe 	bl	8002468 
+ 8003eec:	b9c0      	cbnz	r0, 8003f20 
+ 8003eee:	4910      	ldr	r1, [pc, #64]	; (8003f30 )
+ 8003ef0:	480e      	ldr	r0, [pc, #56]	; (8003f2c )
+ 8003ef2:	f7fe facf 	bl	8002494 
+ 8003ef6:	b980      	cbnz	r0, 8003f1a 
+ 8003ef8:	490e      	ldr	r1, [pc, #56]	; (8003f34 )
+ 8003efa:	480c      	ldr	r0, [pc, #48]	; (8003f2c )
+ 8003efc:	f7fe fa86 	bl	800240c 
+ 8003f00:	b940      	cbnz	r0, 8003f14 
+ 8003f02:	480a      	ldr	r0, [pc, #40]	; (8003f2c )
+ 8003f04:	f7fe face 	bl	80024a4 
+ 8003f08:	b900      	cbnz	r0, 8003f0c 
+ 8003f0a:	bd08      	pop	{r3, pc}
+ 8003f0c:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
+ 8003f10:	f7ff beb0 	b.w	8003c74 
+ 8003f14:	f7ff feae 	bl	8003c74 
+ 8003f18:	e7f3      	b.n	8003f02 
+ 8003f1a:	f7ff feab 	bl	8003c74 
+ 8003f1e:	e7eb      	b.n	8003ef8 
+ 8003f20:	f7ff fea8 	bl	8003c74 
+ 8003f24:	e7e3      	b.n	8003eee 
+ 8003f26:	bf00      	nop
+ 8003f28:	20000130 	.word	0x20000130
+ 8003f2c:	20001218 	.word	0x20001218
+ 8003f30:	20000008 	.word	0x20000008
+ 8003f34:	20000120 	.word	0x20000120
+
+08003f38 :
+ 8003f38:	2000      	movs	r0, #0
+ 8003f3a:	4770      	bx	lr
+
+08003f3c :
+ 8003f3c:	2000      	movs	r0, #0
+ 8003f3e:	4770      	bx	lr
+
+08003f40 :
+ 8003f40:	b510      	push	{r4, lr}
+ 8003f42:	4c05      	ldr	r4, [pc, #20]	; (8003f58 )
+ 8003f44:	4601      	mov	r1, r0
+ 8003f46:	4620      	mov	r0, r4
+ 8003f48:	f7fe fa70 	bl	800242c 
+ 8003f4c:	4620      	mov	r0, r4
+ 8003f4e:	f7fe fa73 	bl	8002438 
+ 8003f52:	2000      	movs	r0, #0
+ 8003f54:	bd10      	pop	{r4, pc}
+ 8003f56:	bf00      	nop
+ 8003f58:	20001218 	.word	0x20001218
+
+08003f5c :
+ 8003f5c:	b510      	push	{r4, lr}
+ 8003f5e:	4c06      	ldr	r4, [pc, #24]	; (8003f78 )
+ 8003f60:	2200      	movs	r2, #0
+ 8003f62:	4620      	mov	r0, r4
+ 8003f64:	4905      	ldr	r1, [pc, #20]	; (8003f7c )
+ 8003f66:	f7fe fa59 	bl	800241c 
+ 8003f6a:	4620      	mov	r0, r4
+ 8003f6c:	4904      	ldr	r1, [pc, #16]	; (8003f80 )
+ 8003f6e:	f7fe fa5d 	bl	800242c 
+ 8003f72:	2000      	movs	r0, #0
+ 8003f74:	bd10      	pop	{r4, pc}
+ 8003f76:	bf00      	nop
+ 8003f78:	20001218 	.word	0x20001218
+ 8003f7c:	200018c4 	.word	0x200018c4
+ 8003f80:	200014dc 	.word	0x200014dc
+
+08003f84 :
+ 8003f84:	6802      	ldr	r2, [r0, #0]
+ 8003f86:	4b0e      	ldr	r3, [pc, #56]	; (8003fc0 )
+ 8003f88:	429a      	cmp	r2, r3
+ 8003f8a:	d000      	beq.n	8003f8e 
+ 8003f8c:	4770      	bx	lr
+ 8003f8e:	f503 33da 	add.w	r3, r3, #111616	; 0x1b400
+ 8003f92:	69d8      	ldr	r0, [r3, #28]
+ 8003f94:	b500      	push	{lr}
+ 8003f96:	f440 0000 	orr.w	r0, r0, #8388608	; 0x800000
+ 8003f9a:	61d8      	str	r0, [r3, #28]
+ 8003f9c:	69db      	ldr	r3, [r3, #28]
+ 8003f9e:	b083      	sub	sp, #12
+ 8003fa0:	f403 0300 	and.w	r3, r3, #8388608	; 0x800000
+ 8003fa4:	9301      	str	r3, [sp, #4]
+ 8003fa6:	2200      	movs	r2, #0
+ 8003fa8:	2105      	movs	r1, #5
+ 8003faa:	2014      	movs	r0, #20
+ 8003fac:	9b01      	ldr	r3, [sp, #4]
+ 8003fae:	f7fc f929 	bl	8000204 
+ 8003fb2:	2014      	movs	r0, #20
+ 8003fb4:	b003      	add	sp, #12
+ 8003fb6:	f85d eb04 	ldr.w	lr, [sp], #4
+ 8003fba:	f7fc b959 	b.w	8000270 
+ 8003fbe:	bf00      	nop
+ 8003fc0:	40005c00 	.word	0x40005c00
+
+08003fc4 :
+ 8003fc4:	f500 710c 	add.w	r1, r0, #560	; 0x230
+ 8003fc8:	f8d0 0268 	ldr.w	r0, [r0, #616]	; 0x268
+ 8003fcc:	f7fe ba82 	b.w	80024d4 
+
+08003fd0 :
+ 8003fd0:	eb00 1341 	add.w	r3, r0, r1, lsl #5
+ 8003fd4:	f8d3 213c 	ldr.w	r2, [r3, #316]	; 0x13c
+ 8003fd8:	f8d0 0268 	ldr.w	r0, [r0, #616]	; 0x268
+ 8003fdc:	f7fe baaa 	b.w	8002534 
+
+08003fe0 :
+ 8003fe0:	eb00 1341 	add.w	r3, r0, r1, lsl #5
+ 8003fe4:	6bda      	ldr	r2, [r3, #60]	; 0x3c
+ 8003fe6:	f8d0 0268 	ldr.w	r0, [r0, #616]	; 0x268
+ 8003fea:	f7fe bae3 	b.w	80025b4 
+ 8003fee:	bf00      	nop
+
+08003ff0 :
+ 8003ff0:	f8d0 0268 	ldr.w	r0, [r0, #616]	; 0x268
+ 8003ff4:	f7fe bb7e 	b.w	80026f4 
+
+08003ff8 :
+ 8003ff8:	6883      	ldr	r3, [r0, #8]
+ 8003ffa:	b510      	push	{r4, lr}
+ 8003ffc:	2b02      	cmp	r3, #2
+ 8003ffe:	4604      	mov	r4, r0
+ 8004000:	d001      	beq.n	8004006 
+ 8004002:	f7ff fe37 	bl	8003c74 
+ 8004006:	f8d4 0268 	ldr.w	r0, [r4, #616]	; 0x268
+ 800400a:	2101      	movs	r1, #1
+ 800400c:	f7fe fb5a 	bl	80026c4 
+ 8004010:	f8d4 0268 	ldr.w	r0, [r4, #616]	; 0x268
+ 8004014:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
+ 8004018:	f7fe bb2c 	b.w	8002674 
+
+0800401c :
+ 800401c:	b510      	push	{r4, lr}
+ 800401e:	4604      	mov	r4, r0
+ 8004020:	f8d0 0268 	ldr.w	r0, [r0, #616]	; 0x268
+ 8004024:	f7fe fb52 	bl	80026cc 
+ 8004028:	69a3      	ldr	r3, [r4, #24]
+ 800402a:	b123      	cbz	r3, 8004036 
+ 800402c:	4a02      	ldr	r2, [pc, #8]	; (8004038 )
+ 800402e:	6913      	ldr	r3, [r2, #16]
+ 8004030:	f043 0306 	orr.w	r3, r3, #6
+ 8004034:	6113      	str	r3, [r2, #16]
+ 8004036:	bd10      	pop	{r4, pc}
+ 8004038:	e000ed00 	.word	0xe000ed00
+
+0800403c :
+ 800403c:	f8d0 0268 	ldr.w	r0, [r0, #616]	; 0x268
+ 8004040:	f7fe bb4e 	b.w	80026e0 
+
+08004044 :
+ 8004044:	b538      	push	{r3, r4, r5, lr}
+ 8004046:	4604      	mov	r4, r0
+ 8004048:	2200      	movs	r2, #0
+ 800404a:	2508      	movs	r5, #8
+ 800404c:	2102      	movs	r1, #2
+ 800404e:	4b1c      	ldr	r3, [pc, #112]	; (80040c0 )
+ 8004050:	481c      	ldr	r0, [pc, #112]	; (80040c4 )
+ 8004052:	f8c4 32c0 	str.w	r3, [r4, #704]	; 0x2c0
+ 8004056:	6018      	str	r0, [r3, #0]
+ 8004058:	4618      	mov	r0, r3
+ 800405a:	f8c3 4268 	str.w	r4, [r3, #616]	; 0x268
+ 800405e:	e9c3 5101 	strd	r5, r1, [r3, #4]
+ 8004062:	e9c3 2206 	strd	r2, r2, [r3, #24]
+ 8004066:	621a      	str	r2, [r3, #32]
+ 8004068:	f7fc fada 	bl	8000620 
+ 800406c:	b108      	cbz	r0, 8004072 
+ 800406e:	f7ff fe01 	bl	8003c74 
+ 8004072:	2200      	movs	r2, #0
+ 8004074:	2318      	movs	r3, #24
+ 8004076:	4611      	mov	r1, r2
+ 8004078:	f8d4 02c0 	ldr.w	r0, [r4, #704]	; 0x2c0
+ 800407c:	f7fc fef0 	bl	8000e60 
+ 8004080:	2358      	movs	r3, #88	; 0x58
+ 8004082:	2200      	movs	r2, #0
+ 8004084:	2180      	movs	r1, #128	; 0x80
+ 8004086:	f8d4 02c0 	ldr.w	r0, [r4, #704]	; 0x2c0
+ 800408a:	f7fc fee9 	bl	8000e60 
+ 800408e:	23c0      	movs	r3, #192	; 0xc0
+ 8004090:	2200      	movs	r2, #0
+ 8004092:	2181      	movs	r1, #129	; 0x81
+ 8004094:	f8d4 02c0 	ldr.w	r0, [r4, #704]	; 0x2c0
+ 8004098:	f7fc fee2 	bl	8000e60 
+ 800409c:	f44f 7388 	mov.w	r3, #272	; 0x110
+ 80040a0:	2200      	movs	r2, #0
+ 80040a2:	2101      	movs	r1, #1
+ 80040a4:	f8d4 02c0 	ldr.w	r0, [r4, #704]	; 0x2c0
+ 80040a8:	f7fc feda 	bl	8000e60 
+ 80040ac:	f8d4 02c0 	ldr.w	r0, [r4, #704]	; 0x2c0
+ 80040b0:	f44f 7380 	mov.w	r3, #256	; 0x100
+ 80040b4:	2200      	movs	r2, #0
+ 80040b6:	2182      	movs	r1, #130	; 0x82
+ 80040b8:	f7fc fed2 	bl	8000e60 
+ 80040bc:	2000      	movs	r0, #0
+ 80040be:	bd38      	pop	{r3, r4, r5, pc}
+ 80040c0:	20001cac 	.word	0x20001cac
+ 80040c4:	40005c00 	.word	0x40005c00
+
+080040c8 :
+ 80040c8:	b508      	push	{r3, lr}
+ 80040ca:	f8d0 02c0 	ldr.w	r0, [r0, #704]	; 0x2c0
+ 80040ce:	f7fc fb25 	bl	800071c 
+ 80040d2:	2803      	cmp	r0, #3
+ 80040d4:	bf96      	itet	ls
+ 80040d6:	4b02      	ldrls	r3, [pc, #8]	; (80040e0 )
+ 80040d8:	2002      	movhi	r0, #2
+ 80040da:	5c18      	ldrbls	r0, [r3, r0]
+ 80040dc:	bd08      	pop	{r3, pc}
+ 80040de:	bf00      	nop
+ 80040e0:	080044b4 	.word	0x080044b4
+
+080040e4 :
+ 80040e4:	b510      	push	{r4, lr}
+ 80040e6:	461c      	mov	r4, r3
+ 80040e8:	f8d0 02c0 	ldr.w	r0, [r0, #704]	; 0x2c0
+ 80040ec:	4613      	mov	r3, r2
+ 80040ee:	4622      	mov	r2, r4
+ 80040f0:	f7fc fdae 	bl	8000c50 
+ 80040f4:	2803      	cmp	r0, #3
+ 80040f6:	bf96      	itet	ls
+ 80040f8:	4b01      	ldrls	r3, [pc, #4]	; (8004100 )
+ 80040fa:	2002      	movhi	r0, #2
+ 80040fc:	5c18      	ldrbls	r0, [r3, r0]
+ 80040fe:	bd10      	pop	{r4, pc}
+ 8004100:	080044b4 	.word	0x080044b4
+
+08004104 :
+ 8004104:	b508      	push	{r3, lr}
+ 8004106:	f8d0 02c0 	ldr.w	r0, [r0, #704]	; 0x2c0
+ 800410a:	f7fc fdd3 	bl	8000cb4 
+ 800410e:	2803      	cmp	r0, #3
+ 8004110:	bf96      	itet	ls
+ 8004112:	4b02      	ldrls	r3, [pc, #8]	; (800411c )
+ 8004114:	2002      	movhi	r0, #2
+ 8004116:	5c18      	ldrbls	r0, [r3, r0]
+ 8004118:	bd08      	pop	{r3, pc}
+ 800411a:	bf00      	nop
+ 800411c:	080044b4 	.word	0x080044b4
+
+08004120 :
+ 8004120:	b508      	push	{r3, lr}
+ 8004122:	f8d0 02c0 	ldr.w	r0, [r0, #704]	; 0x2c0
+ 8004126:	f7fc fe27 	bl	8000d78 
+ 800412a:	2803      	cmp	r0, #3
+ 800412c:	bf96      	itet	ls
+ 800412e:	4b02      	ldrls	r3, [pc, #8]	; (8004138 )
+ 8004130:	2002      	movhi	r0, #2
+ 8004132:	5c18      	ldrbls	r0, [r3, r0]
+ 8004134:	bd08      	pop	{r3, pc}
+ 8004136:	bf00      	nop
+ 8004138:	080044b4 	.word	0x080044b4
+
+0800413c :
+ 800413c:	b508      	push	{r3, lr}
+ 800413e:	f8d0 02c0 	ldr.w	r0, [r0, #704]	; 0x2c0
+ 8004142:	f7fc fe55 	bl	8000df0 
+ 8004146:	2803      	cmp	r0, #3
+ 8004148:	bf96      	itet	ls
+ 800414a:	4b02      	ldrls	r3, [pc, #8]	; (8004154 )
+ 800414c:	2002      	movhi	r0, #2
+ 800414e:	5c18      	ldrbls	r0, [r3, r0]
+ 8004150:	bd08      	pop	{r3, pc}
+ 8004152:	bf00      	nop
+ 8004154:	080044b4 	.word	0x080044b4
+
+08004158 :
+ 8004158:	060a      	lsls	r2, r1, #24
+ 800415a:	f8d0 32c0 	ldr.w	r3, [r0, #704]	; 0x2c0
+ 800415e:	d404      	bmi.n	800416a 
+ 8004160:	eb03 1341 	add.w	r3, r3, r1, lsl #5
+ 8004164:	f893 012a 	ldrb.w	r0, [r3, #298]	; 0x12a
+ 8004168:	4770      	bx	lr
+ 800416a:	f001 017f 	and.w	r1, r1, #127	; 0x7f
+ 800416e:	eb03 1341 	add.w	r3, r3, r1, lsl #5
+ 8004172:	f893 002a 	ldrb.w	r0, [r3, #42]	; 0x2a
+ 8004176:	4770      	bx	lr
+
+08004178 :
+ 8004178:	b508      	push	{r3, lr}
+ 800417a:	f8d0 02c0 	ldr.w	r0, [r0, #704]	; 0x2c0
+ 800417e:	f7fc fd53 	bl	8000c28 
+ 8004182:	2803      	cmp	r0, #3
+ 8004184:	bf96      	itet	ls
+ 8004186:	4b02      	ldrls	r3, [pc, #8]	; (8004190 )
+ 8004188:	2002      	movhi	r0, #2
+ 800418a:	5c18      	ldrbls	r0, [r3, r0]
+ 800418c:	bd08      	pop	{r3, pc}
+ 800418e:	bf00      	nop
+ 8004190:	080044b4 	.word	0x080044b4
+
+08004194 :
+ 8004194:	b508      	push	{r3, lr}
+ 8004196:	f8d0 02c0 	ldr.w	r0, [r0, #704]	; 0x2c0
+ 800419a:	f7fc fdd7 	bl	8000d4c 
+ 800419e:	2803      	cmp	r0, #3
+ 80041a0:	bf96      	itet	ls
+ 80041a2:	4b02      	ldrls	r3, [pc, #8]	; (80041ac )
+ 80041a4:	2002      	movhi	r0, #2
+ 80041a6:	5c18      	ldrbls	r0, [r3, r0]
+ 80041a8:	bd08      	pop	{r3, pc}
+ 80041aa:	bf00      	nop
+ 80041ac:	080044b4 	.word	0x080044b4
+
+080041b0 :
+ 80041b0:	b508      	push	{r3, lr}
+ 80041b2:	f8d0 02c0 	ldr.w	r0, [r0, #704]	; 0x2c0
+ 80041b6:	f7fc fda9 	bl	8000d0c 
+ 80041ba:	2803      	cmp	r0, #3
+ 80041bc:	bf96      	itet	ls
+ 80041be:	4b02      	ldrls	r3, [pc, #8]	; (80041c8 )
+ 80041c0:	2002      	movhi	r0, #2
+ 80041c2:	5c18      	ldrbls	r0, [r3, r0]
+ 80041c4:	bd08      	pop	{r3, pc}
+ 80041c6:	bf00      	nop
+ 80041c8:	080044b4 	.word	0x080044b4
+
+080041cc :
+ 80041cc:	f8d0 02c0 	ldr.w	r0, [r0, #704]	; 0x2c0
+ 80041d0:	f7fc bdb4 	b.w	8000d3c 
+
+080041d4 :
+ 80041d4:	4800      	ldr	r0, [pc, #0]	; (80041d8 )
+ 80041d6:	4770      	bx	lr
+ 80041d8:	20000eec 	.word	0x20000eec
+
+080041dc :
+ 80041dc:	4770      	bx	lr
+ 80041de:	bf00      	nop
+
+080041e0 :
+ 80041e0:	4770      	bx	lr
+ 80041e2:	bf00      	nop
+
+080041e4 :
+ 80041e4:	2312      	movs	r3, #18
+ 80041e6:	4801      	ldr	r0, [pc, #4]	; (80041ec )
+ 80041e8:	800b      	strh	r3, [r1, #0]
+ 80041ea:	4770      	bx	lr
+ 80041ec:	2000014c 	.word	0x2000014c
+
+080041f0 :
+ 80041f0:	2304      	movs	r3, #4
+ 80041f2:	4801      	ldr	r0, [pc, #4]	; (80041f8 )
+ 80041f4:	800b      	strh	r3, [r1, #0]
+ 80041f6:	4770      	bx	lr
+ 80041f8:	20000160 	.word	0x20000160
+
+080041fc :
+ 80041fc:	b510      	push	{r4, lr}
+ 80041fe:	4c04      	ldr	r4, [pc, #16]	; (8004210 )
+ 8004200:	460a      	mov	r2, r1
+ 8004202:	4804      	ldr	r0, [pc, #16]	; (8004214 )
+ 8004204:	4621      	mov	r1, r4
+ 8004206:	f7fe fce3 	bl	8002bd0 
+ 800420a:	4620      	mov	r0, r4
+ 800420c:	bd10      	pop	{r4, pc}
+ 800420e:	bf00      	nop
+ 8004210:	20001f18 	.word	0x20001f18
+ 8004214:	080044d4 	.word	0x080044d4
+
+08004218 :
+ 8004218:	b510      	push	{r4, lr}
+ 800421a:	4c04      	ldr	r4, [pc, #16]	; (800422c )
+ 800421c:	460a      	mov	r2, r1
+ 800421e:	4804      	ldr	r0, [pc, #16]	; (8004230 )
+ 8004220:	4621      	mov	r1, r4
+ 8004222:	f7fe fcd5 	bl	8002bd0 
+ 8004226:	4620      	mov	r0, r4
+ 8004228:	bd10      	pop	{r4, pc}
+ 800422a:	bf00      	nop
+ 800422c:	20001f18 	.word	0x20001f18
+ 8004230:	080044e8 	.word	0x080044e8
+
+08004234 :
+ 8004234:	b510      	push	{r4, lr}
+ 8004236:	4c04      	ldr	r4, [pc, #16]	; (8004248 )
+ 8004238:	460a      	mov	r2, r1
+ 800423a:	4804      	ldr	r0, [pc, #16]	; (800424c )
+ 800423c:	4621      	mov	r1, r4
+ 800423e:	f7fe fcc7 	bl	8002bd0 
+ 8004242:	4620      	mov	r0, r4
+ 8004244:	bd10      	pop	{r4, pc}
+ 8004246:	bf00      	nop
+ 8004248:	20001f18 	.word	0x20001f18
+ 800424c:	080044b8 	.word	0x080044b8
+
+08004250 :
+ 8004250:	b510      	push	{r4, lr}
+ 8004252:	4c04      	ldr	r4, [pc, #16]	; (8004264 )
+ 8004254:	460a      	mov	r2, r1
+ 8004256:	4804      	ldr	r0, [pc, #16]	; (8004268 )
+ 8004258:	4621      	mov	r1, r4
+ 800425a:	f7fe fcb9 	bl	8002bd0 
+ 800425e:	4620      	mov	r0, r4
+ 8004260:	bd10      	pop	{r4, pc}
+ 8004262:	bf00      	nop
+ 8004264:	20001f18 	.word	0x20001f18
+ 8004268:	080044c4 	.word	0x080044c4
+
+0800426c :
+ 800426c:	201a      	movs	r0, #26
+ 800426e:	4a44      	ldr	r2, [pc, #272]	; (8004380 )
+ 8004270:	4b44      	ldr	r3, [pc, #272]	; (8004384 )
+ 8004272:	6812      	ldr	r2, [r2, #0]
+ 8004274:	681b      	ldr	r3, [r3, #0]
+ 8004276:	8008      	strh	r0, [r1, #0]
+ 8004278:	18d2      	adds	r2, r2, r3
+ 800427a:	d101      	bne.n	8004280 
+ 800427c:	4842      	ldr	r0, [pc, #264]	; (8004388 )
+ 800427e:	4770      	bx	lr
+ 8004280:	b410      	push	{r4}
+ 8004282:	2400      	movs	r4, #0
+ 8004284:	0f13      	lsrs	r3, r2, #28
+ 8004286:	b2d8      	uxtb	r0, r3
+ 8004288:	2b09      	cmp	r3, #9
+ 800428a:	4940      	ldr	r1, [pc, #256]	; (800438c )
+ 800428c:	4b3e      	ldr	r3, [pc, #248]	; (8004388 )
+ 800428e:	bf94      	ite	ls
+ 8004290:	3030      	addls	r0, #48	; 0x30
+ 8004292:	3037      	addhi	r0, #55	; 0x37
+ 8004294:	6809      	ldr	r1, [r1, #0]
+ 8004296:	7098      	strb	r0, [r3, #2]
+ 8004298:	f3c2 6003 	ubfx	r0, r2, #24, #4
+ 800429c:	2809      	cmp	r0, #9
+ 800429e:	70dc      	strb	r4, [r3, #3]
+ 80042a0:	b2c4      	uxtb	r4, r0
+ 80042a2:	bf94      	ite	ls
+ 80042a4:	3430      	addls	r4, #48	; 0x30
+ 80042a6:	3437      	addhi	r4, #55	; 0x37
+ 80042a8:	711c      	strb	r4, [r3, #4]
+ 80042aa:	2400      	movs	r4, #0
+ 80042ac:	f3c2 5003 	ubfx	r0, r2, #20, #4
+ 80042b0:	2809      	cmp	r0, #9
+ 80042b2:	715c      	strb	r4, [r3, #5]
+ 80042b4:	b2c4      	uxtb	r4, r0
+ 80042b6:	bf94      	ite	ls
+ 80042b8:	3430      	addls	r4, #48	; 0x30
+ 80042ba:	3437      	addhi	r4, #55	; 0x37
+ 80042bc:	719c      	strb	r4, [r3, #6]
+ 80042be:	2400      	movs	r4, #0
+ 80042c0:	f3c2 4003 	ubfx	r0, r2, #16, #4
+ 80042c4:	2809      	cmp	r0, #9
+ 80042c6:	71dc      	strb	r4, [r3, #7]
+ 80042c8:	b2c4      	uxtb	r4, r0
+ 80042ca:	bf94      	ite	ls
+ 80042cc:	3430      	addls	r4, #48	; 0x30
+ 80042ce:	3437      	addhi	r4, #55	; 0x37
+ 80042d0:	721c      	strb	r4, [r3, #8]
+ 80042d2:	2400      	movs	r4, #0
+ 80042d4:	f3c2 3003 	ubfx	r0, r2, #12, #4
+ 80042d8:	2809      	cmp	r0, #9
+ 80042da:	725c      	strb	r4, [r3, #9]
+ 80042dc:	b2c4      	uxtb	r4, r0
+ 80042de:	bf94      	ite	ls
+ 80042e0:	3430      	addls	r4, #48	; 0x30
+ 80042e2:	3437      	addhi	r4, #55	; 0x37
+ 80042e4:	729c      	strb	r4, [r3, #10]
+ 80042e6:	2400      	movs	r4, #0
+ 80042e8:	f3c2 2003 	ubfx	r0, r2, #8, #4
+ 80042ec:	2809      	cmp	r0, #9
+ 80042ee:	72dc      	strb	r4, [r3, #11]
+ 80042f0:	b2c4      	uxtb	r4, r0
+ 80042f2:	bf94      	ite	ls
+ 80042f4:	3430      	addls	r4, #48	; 0x30
+ 80042f6:	3437      	addhi	r4, #55	; 0x37
+ 80042f8:	731c      	strb	r4, [r3, #12]
+ 80042fa:	2400      	movs	r4, #0
+ 80042fc:	f3c2 1003 	ubfx	r0, r2, #4, #4
+ 8004300:	2809      	cmp	r0, #9
+ 8004302:	f002 020f 	and.w	r2, r2, #15
+ 8004306:	735c      	strb	r4, [r3, #13]
+ 8004308:	b2c4      	uxtb	r4, r0
+ 800430a:	bf98      	it	ls
+ 800430c:	3430      	addls	r4, #48	; 0x30
+ 800430e:	b2d0      	uxtb	r0, r2
+ 8004310:	bf88      	it	hi
+ 8004312:	3437      	addhi	r4, #55	; 0x37
+ 8004314:	2a09      	cmp	r2, #9
+ 8004316:	bf94      	ite	ls
+ 8004318:	3030      	addls	r0, #48	; 0x30
+ 800431a:	3037      	addhi	r0, #55	; 0x37
+ 800431c:	7418      	strb	r0, [r3, #16]
+ 800431e:	2000      	movs	r0, #0
+ 8004320:	0f0a      	lsrs	r2, r1, #28
+ 8004322:	2a09      	cmp	r2, #9
+ 8004324:	7458      	strb	r0, [r3, #17]
+ 8004326:	b2d0      	uxtb	r0, r2
+ 8004328:	bf94      	ite	ls
+ 800432a:	3030      	addls	r0, #48	; 0x30
+ 800432c:	3037      	addhi	r0, #55	; 0x37
+ 800432e:	7498      	strb	r0, [r3, #18]
+ 8004330:	2000      	movs	r0, #0
+ 8004332:	f3c1 6203 	ubfx	r2, r1, #24, #4
+ 8004336:	2a09      	cmp	r2, #9
+ 8004338:	74d8      	strb	r0, [r3, #19]
+ 800433a:	b2d0      	uxtb	r0, r2
+ 800433c:	bf94      	ite	ls
+ 800433e:	3030      	addls	r0, #48	; 0x30
+ 8004340:	3037      	addhi	r0, #55	; 0x37
+ 8004342:	7518      	strb	r0, [r3, #20]
+ 8004344:	2000      	movs	r0, #0
+ 8004346:	f3c1 5203 	ubfx	r2, r1, #20, #4
+ 800434a:	2a09      	cmp	r2, #9
+ 800434c:	7558      	strb	r0, [r3, #21]
+ 800434e:	f3c1 4103 	ubfx	r1, r1, #16, #4
+ 8004352:	b2d0      	uxtb	r0, r2
+ 8004354:	bf98      	it	ls
+ 8004356:	3030      	addls	r0, #48	; 0x30
+ 8004358:	b2ca      	uxtb	r2, r1
+ 800435a:	bf88      	it	hi
+ 800435c:	3037      	addhi	r0, #55	; 0x37
+ 800435e:	2909      	cmp	r1, #9
+ 8004360:	bf94      	ite	ls
+ 8004362:	3230      	addls	r2, #48	; 0x30
+ 8004364:	3237      	addhi	r2, #55	; 0x37
+ 8004366:	739c      	strb	r4, [r3, #14]
+ 8004368:	7598      	strb	r0, [r3, #22]
+ 800436a:	2400      	movs	r4, #0
+ 800436c:	2000      	movs	r0, #0
+ 800436e:	761a      	strb	r2, [r3, #24]
+ 8004370:	2200      	movs	r2, #0
+ 8004372:	75d8      	strb	r0, [r3, #23]
+ 8004374:	73dc      	strb	r4, [r3, #15]
+ 8004376:	765a      	strb	r2, [r3, #25]
+ 8004378:	4803      	ldr	r0, [pc, #12]	; (8004388 )
+ 800437a:	bc10      	pop	{r4}
+ 800437c:	4770      	bx	lr
+ 800437e:	bf00      	nop
+ 8004380:	1ffff7e8 	.word	0x1ffff7e8
+ 8004384:	1ffff7f0 	.word	0x1ffff7f0
+ 8004388:	20000164 	.word	0x20000164
+ 800438c:	1ffff7ec 	.word	0x1ffff7ec
+
+08004390 :
+ 8004390:	2100      	movs	r1, #0
+ 8004392:	e003      	b.n	800439c 
+
+08004394 :
+ 8004394:	4b0b      	ldr	r3, [pc, #44]	; (80043c4 )
+ 8004396:	585b      	ldr	r3, [r3, r1]
+ 8004398:	5043      	str	r3, [r0, r1]
+ 800439a:	3104      	adds	r1, #4
+
+0800439c :
+ 800439c:	480a      	ldr	r0, [pc, #40]	; (80043c8 )
+ 800439e:	4b0b      	ldr	r3, [pc, #44]	; (80043cc )
+ 80043a0:	1842      	adds	r2, r0, r1
+ 80043a2:	429a      	cmp	r2, r3
+ 80043a4:	d3f6      	bcc.n	8004394 
+ 80043a6:	4a0a      	ldr	r2, [pc, #40]	; (80043d0 )
+ 80043a8:	e002      	b.n	80043b0 
+
+080043aa :
+ 80043aa:	2300      	movs	r3, #0
+ 80043ac:	f842 3b04 	str.w	r3, [r2], #4
+
+080043b0 :
+ 80043b0:	4b08      	ldr	r3, [pc, #32]	; (80043d4 )
+ 80043b2:	429a      	cmp	r2, r3
+ 80043b4:	d3f9      	bcc.n	80043aa 
+ 80043b6:	f7ff fd6b 	bl	8003e90 
+ 80043ba:	f000 f80f 	bl	80043dc <__libc_init_array>
+ 80043be:	f7ff fbb5 	bl	8003b2c 

+ 80043c2:	4770      	bx	lr
+ 80043c4:	08004508 	.word	0x08004508
+ 80043c8:	20000000 	.word	0x20000000
+ 80043cc:	20000180 	.word	0x20000180
+ 80043d0:	20000180 	.word	0x20000180
+ 80043d4:	20002118 	.word	0x20002118
+
+080043d8 :
+ 80043d8:	e7fe      	b.n	80043d8 
+	...
+
+080043dc <__libc_init_array>:
+ 80043dc:	b570      	push	{r4, r5, r6, lr}
+ 80043de:	2500      	movs	r5, #0
+ 80043e0:	4e0c      	ldr	r6, [pc, #48]	; (8004414 <__libc_init_array+0x38>)
+ 80043e2:	4c0d      	ldr	r4, [pc, #52]	; (8004418 <__libc_init_array+0x3c>)
+ 80043e4:	1ba4      	subs	r4, r4, r6
+ 80043e6:	10a4      	asrs	r4, r4, #2
+ 80043e8:	42a5      	cmp	r5, r4
+ 80043ea:	d109      	bne.n	8004400 <__libc_init_array+0x24>
+ 80043ec:	f000 f81a 	bl	8004424 <_init>
+ 80043f0:	2500      	movs	r5, #0
+ 80043f2:	4e0a      	ldr	r6, [pc, #40]	; (800441c <__libc_init_array+0x40>)
+ 80043f4:	4c0a      	ldr	r4, [pc, #40]	; (8004420 <__libc_init_array+0x44>)
+ 80043f6:	1ba4      	subs	r4, r4, r6
+ 80043f8:	10a4      	asrs	r4, r4, #2
+ 80043fa:	42a5      	cmp	r5, r4
+ 80043fc:	d105      	bne.n	800440a <__libc_init_array+0x2e>
+ 80043fe:	bd70      	pop	{r4, r5, r6, pc}
+ 8004400:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
+ 8004404:	4798      	blx	r3
+ 8004406:	3501      	adds	r5, #1
+ 8004408:	e7ee      	b.n	80043e8 <__libc_init_array+0xc>
+ 800440a:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
+ 800440e:	4798      	blx	r3
+ 8004410:	3501      	adds	r5, #1
+ 8004412:	e7f2      	b.n	80043fa <__libc_init_array+0x1e>
+ 8004414:	08004500 	.word	0x08004500
+ 8004418:	08004500 	.word	0x08004500
+ 800441c:	08004500 	.word	0x08004500
+ 8004420:	08004504 	.word	0x08004504
+
+08004424 <_init>:
+ 8004424:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8004426:	bf00      	nop
+ 8004428:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 800442a:	bc08      	pop	{r3}
+ 800442c:	469e      	mov	lr, r3
+ 800442e:	4770      	bx	lr
+
+08004430 <_fini>:
+ 8004430:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8004432:	bf00      	nop
+ 8004434:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 8004436:	bc08      	pop	{r3}
+ 8004438:	469e      	mov	lr, r3
+ 800443a:	4770      	bx	lr
diff --git a/Release/Src/subdir.mk b/Release/Src/subdir.mk
new file mode 100644
index 0000000..54238f1
--- /dev/null
+++ b/Release/Src/subdir.mk
@@ -0,0 +1,69 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Src/freertos.c \
+../Src/main.c \
+../Src/stm32f1xx_hal_msp.c \
+../Src/stm32f1xx_it.c \
+../Src/syscalls.c \
+../Src/sysmem.c \
+../Src/system_stm32f1xx.c \
+../Src/usb_device.c \
+../Src/usbd_cdc_if.c \
+../Src/usbd_conf.c \
+../Src/usbd_desc.c 
+
+OBJS += \
+./Src/freertos.o \
+./Src/main.o \
+./Src/stm32f1xx_hal_msp.o \
+./Src/stm32f1xx_it.o \
+./Src/syscalls.o \
+./Src/sysmem.o \
+./Src/system_stm32f1xx.o \
+./Src/usb_device.o \
+./Src/usbd_cdc_if.o \
+./Src/usbd_conf.o \
+./Src/usbd_desc.o 
+
+C_DEPS += \
+./Src/freertos.d \
+./Src/main.d \
+./Src/stm32f1xx_hal_msp.d \
+./Src/stm32f1xx_it.d \
+./Src/syscalls.d \
+./Src/sysmem.d \
+./Src/system_stm32f1xx.d \
+./Src/usb_device.d \
+./Src/usbd_cdc_if.d \
+./Src/usbd_conf.d \
+./Src/usbd_desc.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Src/freertos.o: ../Src/freertos.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/freertos.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/main.o: ../Src/main.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/main.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/stm32f1xx_hal_msp.o: ../Src/stm32f1xx_hal_msp.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/stm32f1xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/stm32f1xx_it.o: ../Src/stm32f1xx_it.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/stm32f1xx_it.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/syscalls.o: ../Src/syscalls.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/syscalls.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/sysmem.o: ../Src/sysmem.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/sysmem.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/system_stm32f1xx.o: ../Src/system_stm32f1xx.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/system_stm32f1xx.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/usb_device.o: ../Src/usb_device.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/usb_device.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/usbd_cdc_if.o: ../Src/usbd_cdc_if.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/usbd_cdc_if.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/usbd_conf.o: ../Src/usbd_conf.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/usbd_conf.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Src/usbd_desc.o: ../Src/usbd_desc.c
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F103xB -c -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Inc -I../Drivers/CMSIS/Device/ST/STM32F1xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -I../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy -I../Drivers/STM32F1xx_HAL_Driver/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/usbd_desc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/Release/Startup/subdir.mk b/Release/Startup/subdir.mk
new file mode 100644
index 0000000..81bf109
--- /dev/null
+++ b/Release/Startup/subdir.mk
@@ -0,0 +1,16 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+S_SRCS += \
+../Startup/startup_stm32f103c8tx.s 
+
+OBJS += \
+./Startup/startup_stm32f103c8tx.o 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Startup/%.o: ../Startup/%.s
+	arm-none-eabi-gcc -mcpu=cortex-m3 -c -I../ -x assembler-with-cpp --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<"
+
diff --git a/Release/makefile b/Release/makefile
new file mode 100644
index 0000000..12d759e
--- /dev/null
+++ b/Release/makefile
@@ -0,0 +1,71 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Startup/subdir.mk
+-include Src/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk
+-include Middlewares/Third_Party/FreeRTOS/Source/subdir.mk
+-include Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk
+-include Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk
+-include Drivers/STM32F1xx_HAL_Driver/Src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables 
+EXECUTABLES += \
+STM32Display.elf \
+
+SIZE_OUTPUT += \
+default.size.stdout \
+
+OBJDUMP_LIST += \
+STM32Display.list \
+
+
+# All Target
+all: STM32Display.elf secondary-outputs
+
+# Tool invocations
+STM32Display.elf: $(OBJS) $(USER_OBJS) /home/vladimir/Desktop/STM32Display/STM32F103C8TX_FLASH.ld
+	arm-none-eabi-gcc -o "STM32Display.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m3 -T"/home/vladimir/Desktop/STM32Display/STM32F103C8TX_FLASH.ld" --specs=nosys.specs -Wl,-Map="STM32Display.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+default.size.stdout: $(EXECUTABLES)
+	arm-none-eabi-size  $(EXECUTABLES)
+	@echo 'Finished building: $@'
+	@echo ' '
+
+STM32Display.list: $(EXECUTABLES)
+	arm-none-eabi-objdump -h -S $(EXECUTABLES) > "STM32Display.list"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) *
+	-@echo ' '
+
+secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST)
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
diff --git a/Release/objects.list b/Release/objects.list
new file mode 100644
index 0000000..dfa0f48
--- /dev/null
+++ b/Release/objects.list
@@ -0,0 +1,47 @@
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o"
+"Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.o"
+"Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o"
+"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o"
+"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o"
+"Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o"
+"Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o"
+"Middlewares/Third_Party/FreeRTOS/Source/croutine.o"
+"Middlewares/Third_Party/FreeRTOS/Source/event_groups.o"
+"Middlewares/Third_Party/FreeRTOS/Source/list.o"
+"Middlewares/Third_Party/FreeRTOS/Source/queue.o"
+"Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o"
+"Middlewares/Third_Party/FreeRTOS/Source/tasks.o"
+"Middlewares/Third_Party/FreeRTOS/Source/timers.o"
+"Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.o"
+"Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o"
+"Src/freertos.o"
+"Src/main.o"
+"Src/stm32f1xx_hal_msp.o"
+"Src/stm32f1xx_it.o"
+"Src/syscalls.o"
+"Src/sysmem.o"
+"Src/system_stm32f1xx.o"
+"Src/usb_device.o"
+"Src/usbd_cdc_if.o"
+"Src/usbd_conf.o"
+"Src/usbd_desc.o"
+"Startup/startup_stm32f103c8tx.o"
diff --git a/Release/objects.mk b/Release/objects.mk
new file mode 100644
index 0000000..742c2da
--- /dev/null
+++ b/Release/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Release/sources.mk b/Release/sources.mk
new file mode 100644
index 0000000..4060185
--- /dev/null
+++ b/Release/sources.mk
@@ -0,0 +1,28 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS := 
+OBJ_SRCS := 
+S_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+O_SRCS := 
+SIZE_OUTPUT := 
+OBJDUMP_LIST := 
+EXECUTABLES := 
+OBJS := 
+C_DEPS := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Drivers/STM32F1xx_HAL_Driver/Src \
+Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src \
+Middlewares/ST/STM32_USB_Device_Library/Core/Src \
+Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS \
+Middlewares/Third_Party/FreeRTOS/Source \
+Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3 \
+Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang \
+Src \
+Startup \
+
diff --git a/STM32Display.elf.cfg b/STM32Display.elf.cfg
new file mode 100644
index 0000000..2e2e78f
--- /dev/null
+++ b/STM32Display.elf.cfg
@@ -0,0 +1,31 @@
+# This is an genericBoard board with a single STM32F103C8Tx chip
+#
+# Generated by STM32CubeIDE
+# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
+
+source [find interface/stlink.cfg] 
+
+set WORKAREASIZE 0x8000
+
+transport select "hla_swd"
+
+set CHIPNAME STM32F103C8Tx
+set BOARDNAME genericBoard
+
+# Enable debug when in low power modes
+set ENABLE_LOW_POWER 1
+
+# Stop Watchdog counters when halt
+set STOP_WATCHDOG 1
+
+# STlink Debug clock frequency
+set CLOCK_FREQ 8000
+
+# use hardware reset, connect under reset
+# connect_assert_srst needed if low power mode application running (WFI...)
+reset_config srst_only srst_nogate connect_assert_srst
+set CONNECT_UNDER_RESET 1
+
+# BCTM CPU variables
+
+source [find target/stm32f1x.cfg]
diff --git a/STM32Display.elf.launch b/STM32Display.elf.launch
new file mode 100644
index 0000000..7bad383
--- /dev/null
+++ b/STM32Display.elf.launch
@@ -0,0 +1,87 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/STM32Display.ioc b/STM32Display.ioc
new file mode 100644
index 0000000..22b1b44
--- /dev/null
+++ b/STM32Display.ioc
@@ -0,0 +1,200 @@
+#MicroXplorer Configuration settings - do not modify
+FREERTOS.FootprintOK=true
+FREERTOS.IPParameters=Tasks01,FootprintOK
+FREERTOS.Tasks01=defaultTask,0,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;myTask02,0,128,StartTask02,Default,NULL,Dynamic,NULL,NULL
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32F1
+Mcu.IP0=FREERTOS
+Mcu.IP1=I2C1
+Mcu.IP10=USB_DEVICE
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=RTC
+Mcu.IP5=SPI2
+Mcu.IP6=SYS
+Mcu.IP7=TIM2
+Mcu.IP8=USART2
+Mcu.IP9=USB
+Mcu.IPNb=11
+Mcu.Name=STM32F103C(8-B)Tx
+Mcu.Package=LQFP48
+Mcu.Pin0=PC14-OSC32_IN
+Mcu.Pin1=PC15-OSC32_OUT
+Mcu.Pin10=PA6
+Mcu.Pin11=PA7
+Mcu.Pin12=PB13
+Mcu.Pin13=PB14
+Mcu.Pin14=PB15
+Mcu.Pin15=PA11
+Mcu.Pin16=PA12
+Mcu.Pin17=PA13
+Mcu.Pin18=PA14
+Mcu.Pin19=PB6
+Mcu.Pin2=PD0-OSC_IN
+Mcu.Pin20=PB7
+Mcu.Pin21=VP_FREERTOS_VS_CMSIS_V1
+Mcu.Pin22=VP_RTC_VS_RTC_Activate
+Mcu.Pin23=VP_RTC_VS_RTC_Calendar
+Mcu.Pin24=VP_SYS_VS_Systick
+Mcu.Pin25=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS
+Mcu.Pin3=PD1-OSC_OUT
+Mcu.Pin4=PA0-WKUP
+Mcu.Pin5=PA1
+Mcu.Pin6=PA2
+Mcu.Pin7=PA3
+Mcu.Pin8=PA4
+Mcu.Pin9=PA5
+Mcu.PinsNb=26
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F103C8Tx
+MxCube.Version=5.3.0
+MxDb.Version=DB.5.0.30
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:false\:true
+NVIC.USB_LP_CAN1_RX0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA0-WKUP.GPIOParameters=GPIO_PuPd
+PA0-WKUP.GPIO_PuPd=GPIO_PULLUP
+PA0-WKUP.Signal=S_TIM2_CH1_ETR
+PA1.GPIOParameters=GPIO_PuPd
+PA1.GPIO_PuPd=GPIO_PULLUP
+PA1.Signal=S_TIM2_CH2
+PA11.Mode=Device
+PA11.Signal=USB_DM
+PA12.Mode=Device
+PA12.Signal=USB_DP
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
+PA2.Mode=Asynchronous
+PA2.Signal=USART2_TX
+PA3.Mode=Asynchronous
+PA3.Signal=USART2_RX
+PA4.Locked=true
+PA4.Signal=GPIO_Input
+PA5.Locked=true
+PA5.Signal=GPIO_Output
+PA6.Locked=true
+PA6.Signal=GPIO_Output
+PA7.Locked=true
+PA7.Signal=GPIO_Output
+PB13.Mode=Full_Duplex_Master
+PB13.Signal=SPI2_SCK
+PB14.Mode=Full_Duplex_Master
+PB14.Signal=SPI2_MISO
+PB15.Mode=Full_Duplex_Master
+PB15.Signal=SPI2_MOSI
+PB6.Mode=I2C
+PB6.Signal=I2C1_SCL
+PB7.Mode=I2C
+PB7.Signal=I2C1_SDA
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
+PC14-OSC32_IN.Signal=RCC_OSC32_IN
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
+PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
+PCC.Checker=false
+PCC.Line=STM32F103
+PCC.MCU=STM32F103C(8-B)Tx
+PCC.PartNumber=STM32F103C8Tx
+PCC.Seq0=0
+PCC.Series=STM32F1
+PCC.Temperature=25
+PCC.Vdd=3.3
+PD0-OSC_IN.Mode=HSE-External-Oscillator
+PD0-OSC_IN.Signal=RCC_OSC_IN
+PD1-OSC_OUT.Mode=HSE-External-Oscillator
+PD1-OSC_OUT.Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F103C8Tx
+ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=STM32CubeIDE
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=STM32Display.ioc
+ProjectManager.ProjectName=STM32Display
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_I2C1_Init-I2C1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-true,7-MX_TIM2_Init-TIM2-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true
+RCC.ADCFreqValue=36000000
+RCC.AHBFreq_Value=72000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV2
+RCC.APB1Freq_Value=36000000
+RCC.APB1TimFreq_Value=72000000
+RCC.APB2Freq_Value=72000000
+RCC.APB2TimFreq_Value=72000000
+RCC.FCLKCortexFreq_Value=72000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=72000000
+RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,USBPrescaler,VCOOutput2Freq_Value
+RCC.MCOFreq_Value=72000000
+RCC.PLLCLKFreq_Value=72000000
+RCC.PLLMCOFreq_Value=36000000
+RCC.PLLMUL=RCC_PLL_MUL9
+RCC.SYSCLKFreq_VALUE=72000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.TimSysFreq_Value=72000000
+RCC.USBFreq_Value=48000000
+RCC.USBPrescaler=RCC_USBCLKSOURCE_PLL_DIV1_5
+RCC.VCOOutput2Freq_Value=8000000
+RTC.Format=RTC_FORMAT_BIN
+RTC.Hours=14
+RTC.IPParameters=Hours,Minutes,Format
+RTC.Minutes=54
+SH.S_TIM2_CH1_ETR.0=TIM2_CH1,Encoder_Interface
+SH.S_TIM2_CH1_ETR.ConfNb=1
+SH.S_TIM2_CH2.0=TIM2_CH2,Encoder_Interface
+SH.S_TIM2_CH2.ConfNb=1
+SPI2.CalculateBaudRate=18.0 MBits/s
+SPI2.Direction=SPI_DIRECTION_2LINES
+SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
+SPI2.Mode=SPI_MODE_MASTER
+SPI2.VirtualType=VM_MASTER
+TIM2.ClockDivision=TIM_CLOCKDIVISION_DIV1
+TIM2.EncoderMode=TIM_ENCODERMODE_TI12
+TIM2.IPParameters=Period,EncoderMode,ClockDivision
+TIM2.Period=65535
+USART2.IPParameters=VirtualMode
+USART2.VirtualMode=VM_ASYNC
+USB_DEVICE.CLASS_NAME_FS=CDC
+USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS
+USB_DEVICE.VirtualMode=Cdc
+USB_DEVICE.VirtualModeFS=Cdc_FS
+VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
+VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
+VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar
+VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS
+VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS
+board=custom
+isbadioc=false
diff --git a/STM32F103C8TX_FLASH.ld b/STM32F103C8TX_FLASH.ld
new file mode 100644
index 0000000..bbdc5d4
--- /dev/null
+++ b/STM32F103C8TX_FLASH.ld
@@ -0,0 +1,200 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32F103C8Tx Device from STM32F1 series
+**                      64Kbytes FLASH
+**                      20Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** 
© COPYRIGHT(c) 2019 STMicroelectronics

+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20005000;	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+    RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 20K
+    FLASH	(rx)	: ORIGIN = 0x8000000,	LENGTH = 64K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { 
+  	. = ALIGN(4);
+  	*(.ARM.extab* .gnu.linkonce.armextab.*)
+  	. = ALIGN(4);
+  } >FLASH
+  
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+  
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+  
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM AT> FLASH
+  
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/Src/freertos.c b/Src/freertos.c
new file mode 100644
index 0000000..387c7dd
--- /dev/null
+++ b/Src/freertos.c
@@ -0,0 +1,61 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : freertos.c
+  * Description        : Code for freertos applications
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "FreeRTOS.h"
+#include "task.h"
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */     
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN FunctionPrototypes */
+   
+/* USER CODE END FunctionPrototypes */
+
+/* Private application code --------------------------------------------------*/
+/* USER CODE BEGIN Application */
+     
+/* USER CODE END Application */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/main.c b/Src/main.c
new file mode 100644
index 0000000..514f55d
--- /dev/null
+++ b/Src/main.c
@@ -0,0 +1,635 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file           : main.c
+ * @brief          : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * 
© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.

+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ *                             www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+#include "usb_device.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include 
+#include 
+#include 
+#include "ili9341.h"
+#include "ili9341_touch.h"
+#include "fonts.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+I2C_HandleTypeDef hi2c1;
+
+RTC_HandleTypeDef hrtc;
+
+SPI_HandleTypeDef hspi2;
+
+TIM_HandleTypeDef htim2;
+
+UART_HandleTypeDef huart2;
+
+osThreadId defaultTaskHandle;
+osThreadId myTask02Handle;
+/* USER CODE BEGIN PV */
+RTC_TimeTypeDef sTime = {0};
+RTC_DateTypeDef DateToUpdate = {0};
+char time_str[64] = {0,};
+int32_t radius = 79, x_center = 210, y_center = 130;
+int32_t encoder = 0, encoder_prev = 0;
+int32_t capture = 0, capture_prev = 0;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_I2C1_Init(void);
+static void MX_SPI2_Init(void);
+static void MX_USART2_UART_Init(void);
+static void MX_TIM2_Init(void);
+static void MX_RTC_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_I2C1_Init();
+  MX_SPI2_Init();
+  MX_USART2_UART_Init();
+  MX_TIM2_Init();
+  MX_RTC_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* USER CODE BEGIN RTOS_MUTEX */
+	/* add mutexes, ... */
+  /* USER CODE END RTOS_MUTEX */
+
+  /* USER CODE BEGIN RTOS_SEMAPHORES */
+	/* add semaphores, ... */
+  /* USER CODE END RTOS_SEMAPHORES */
+
+  /* USER CODE BEGIN RTOS_TIMERS */
+	/* start timers, add new ones, ... */
+  /* USER CODE END RTOS_TIMERS */
+
+  /* USER CODE BEGIN RTOS_QUEUES */
+	/* add queues, ... */
+  /* USER CODE END RTOS_QUEUES */
+
+  /* Create the thread(s) */
+  /* definition and creation of defaultTask */
+  osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+  defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+  /* definition and creation of myTask02 */
+  osThreadDef(myTask02, StartTask02, osPriorityNormal, 0, 128);
+  myTask02Handle = osThreadCreate(osThread(myTask02), NULL);
+
+  /* USER CODE BEGIN RTOS_THREADS */
+	/* add threads, ... */
+  /* USER CODE END RTOS_THREADS */
+
+  /* Start scheduler */
+  osKernelStart();
+  
+  /* We should never get here as control is now taken by the scheduler */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+	while (1) {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+	}
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USB;
+  PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief I2C1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C1_Init(void)
+{
+
+  /* USER CODE BEGIN I2C1_Init 0 */
+
+  /* USER CODE END I2C1_Init 0 */
+
+  /* USER CODE BEGIN I2C1_Init 1 */
+
+  /* USER CODE END I2C1_Init 1 */
+  hi2c1.Instance = I2C1;
+  hi2c1.Init.ClockSpeed = 100000;
+  hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
+  hi2c1.Init.OwnAddress1 = 0;
+  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c1.Init.OwnAddress2 = 0;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN I2C1_Init 2 */
+
+  /* USER CODE END I2C1_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  RTC_TimeTypeDef sTime = {0};
+  RTC_DateTypeDef DateToUpdate = {0};
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /** Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
+  hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN Check_RTC_BKUP */
+    
+  /* USER CODE END Check_RTC_BKUP */
+
+  /** Initialize RTC and set the Time and Date 
+  */
+  sTime.Hours = 14;
+  sTime.Minutes = 54;
+  sTime.Seconds = 0;
+
+  if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  DateToUpdate.WeekDay = RTC_WEEKDAY_MONDAY;
+  DateToUpdate.Month = RTC_MONTH_JANUARY;
+  DateToUpdate.Date = 1;
+  DateToUpdate.Year = 0;
+
+  if (HAL_RTC_SetDate(&hrtc, &DateToUpdate, RTC_FORMAT_BIN) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+
+  /* USER CODE END RTC_Init 2 */
+
+}
+
+/**
+  * @brief SPI2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI2_Init(void)
+{
+
+  /* USER CODE BEGIN SPI2_Init 0 */
+
+  /* USER CODE END SPI2_Init 0 */
+
+  /* USER CODE BEGIN SPI2_Init 1 */
+
+  /* USER CODE END SPI2_Init 1 */
+  /* SPI2 parameter configuration*/
+  hspi2.Instance = SPI2;
+  hspi2.Init.Mode = SPI_MODE_MASTER;
+  hspi2.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
+  hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi2.Init.NSS = SPI_NSS_SOFT;
+  hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+  hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi2.Init.CRCPolynomial = 10;
+  if (HAL_SPI_Init(&hspi2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI2_Init 2 */
+
+  /* USER CODE END SPI2_Init 2 */
+
+}
+
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_Encoder_InitTypeDef sConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 0;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 65535;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
+  sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
+  sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
+  sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
+  sConfig.IC1Filter = 0;
+  sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
+  sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
+  sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
+  sConfig.IC2Filter = 0;
+  if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+/**
+  * @brief USART2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART2_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART2_Init 0 */
+
+  /* USER CODE END USART2_Init 0 */
+
+  /* USER CODE BEGIN USART2_Init 1 */
+
+  /* USER CODE END USART2_Init 1 */
+  huart2.Instance = USART2;
+  huart2.Init.BaudRate = 115200;
+  huart2.Init.WordLength = UART_WORDLENGTH_8B;
+  huart2.Init.StopBits = UART_STOPBITS_1;
+  huart2.Init.Parity = UART_PARITY_NONE;
+  huart2.Init.Mode = UART_MODE_TX_RX;
+  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
+  if (HAL_UART_Init(&huart2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART2_Init 2 */
+
+  /* USER CODE END USART2_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin : PA4 */
+  GPIO_InitStruct.Pin = GPIO_PIN_4;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PA5 PA6 PA7 */
+  GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+void initDisplay() {
+	ILI9341_Unselect();
+	ILI9341_TouchUnselect();
+	ILI9341_Init();
+}
+
+void UART_Printf(const char* fmt, ...) {
+	char buff[256];
+	va_list args;
+	va_start(args, fmt);
+	vsnprintf(buff, sizeof(buff), fmt, args);
+	HAL_UART_Transmit(&huart2, (uint8_t*) buff, strlen(buff),
+	HAL_MAX_DELAY);
+	va_end(args);
+}
+
+void drawLineCircle (int32_t centreX, int32_t centreY, int32_t diameter, uint16_t color)
+{
+	int32_t dxOuter, dyOuter, dxi, dyi;
+	for (float i = 0; i <360; i = i + 22.5) {
+	  dxOuter = diameter * cos((i-90)*M_PI/180.0);
+	  dyOuter = diameter * sin((i-90)*M_PI/180.0);
+	  dxi = dxOuter * 0.98;
+	  dyi = dyOuter * 0.98;
+	  ILI9341_writeLine(dxi+centreX,dyi+centreY,dxOuter+centreX,dyOuter+centreY,color);
+}
+}
+
+void drawStatic (void)
+{
+	ILI9341_FillScreen(ILI9341_BLACK);
+	ILI9341_WriteString(0, 0, "ANTENNA ROTATOR", Font_11x18, ILI9341_RED, ILI9341_BLACK);
+	ILI9341_WriteString(30, 18, "CONTROLLER", Font_11x18, ILI9341_RED, ILI9341_BLACK);
+	ILI9341_WriteString(5, 80, "Cur pos:", Font_11x18, ILI9341_RED, ILI9341_BLACK);
+	ILI9341_WriteString(55, 100, "O", Font_7x10, ILI9341_RED, ILI9341_BLACK);
+	ILI9341_WriteString(5, 126, "Set pos:", Font_11x18, ILI9341_RED, ILI9341_BLACK);
+	ILI9341_WriteString(55, 145, "O", Font_7x10, ILI9341_RED, ILI9341_BLACK);
+	ILI9341_WriteString(x_center+radius+7, y_center-5, "90", Font_7x10, ILI9341_GREEN, ILI9341_BLACK);
+	ILI9341_WriteString(x_center-radius-28, y_center-5, "270", Font_7x10, ILI9341_GREEN, ILI9341_BLACK);
+	ILI9341_WriteString(x_center-10, y_center+radius+7, "180", Font_7x10, ILI9341_GREEN, ILI9341_BLACK);
+	ILI9341_WriteString(x_center-3, y_center-radius-17, "0", Font_7x10, ILI9341_GREEN, ILI9341_BLACK);
+}
+
+void drawDirection (int32_t angle, int32_t x, int32_t y, uint16_t color) {
+	if((angle < 22.5)  || (angle > 337.5 )) ILI9341_WriteString(x,y,"North     ",Font_16x26,color, ILI9341_BLACK);
+	if((angle > 22.5)  && (angle < 67.5 )) ILI9341_WriteString(x,y,"North-East",Font_16x26,color, ILI9341_BLACK);
+	if((angle > 67.5)  && (angle < 112.5 )) ILI9341_WriteString(x,y,"East      ",Font_16x26,color, ILI9341_BLACK);
+	if((angle > 112.5) && (angle < 157.5 )) ILI9341_WriteString(x,y,"South-East",Font_16x26,color, ILI9341_BLACK);
+	if((angle > 157.5) && (angle < 202.5 )) ILI9341_WriteString(x,y,"South     ",Font_16x26,color, ILI9341_BLACK);
+	if((angle > 202.5) && (angle < 247.5 )) ILI9341_WriteString(x,y,"South-West",Font_16x26,color, ILI9341_BLACK);
+	if((angle > 247.5) && (angle < 292.5 )) ILI9341_WriteString(x,y,"West      ",Font_16x26,color, ILI9341_BLACK);
+	if((angle > 292.5) && (angle < 337.5 )) ILI9341_WriteString(x,y,"North-West",Font_16x26,color, ILI9341_BLACK);
+}
+
+void GetTime (void)
+{
+	HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN);
+	snprintf(time_str, 63, "%02d:%02d:%02d", sTime.Hours, sTime.Minutes, sTime.Seconds);
+}
+
+void GetEncoder (void)
+{
+	capture = TIM2->CNT / 4;
+	if (capture > 8000) { capture -= 65535 / 4; }
+	if (capture != capture_prev) {
+	encoder_prev = encoder;	}
+	else { encoder_prev = 10000; }
+	encoder += capture - capture_prev;
+	encoder = (encoder + 360) % 360;
+	if (encoder == 0) {	TIM2->CNT = 0; }
+	if (encoder > 360) {TIM2->CNT = 0; }
+	capture_prev = capture;
+}
+
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief  Function implementing the defaultTask thread.
+ * @param  argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+  /* init code for USB_DEVICE */
+  MX_USB_DEVICE_Init();
+
+  /* USER CODE BEGIN 5 */
+	/* Infinite loop */
+	for (;;) {
+		osDelay(1);
+	}
+  /* USER CODE END 5 */ 
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+ * @brief Function implementing the myTask02 thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+  /* USER CODE BEGIN StartTask02 */
+	char buf[25];
+
+	initDisplay();
+	hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+	HAL_TIM_Encoder_Start(&htim2, TIM_CHANNEL_ALL);
+	drawStatic();
+
+	/* Infinite loop */
+	for (;;) {
+        GetTime();
+		GetEncoder();
+
+		if (HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_4) == 0) {
+
+		}
+
+		sprintf(buf, "%03ld", encoder);
+		drawDirection(encoder,0,210, ILI9341_CYAN);
+		ILI9341_WriteString(5, 100, buf, Font_16x26, ILI9341_RED, ILI9341_BLACK);
+		ILI9341_WriteString(5, 145, buf, Font_16x26, ILI9341_RED, ILI9341_BLACK);
+		ILI9341_WriteString(229, 0, time_str, Font_11x18, ILI9341_GREEN, ILI9341_BLACK);
+		ILI9341_DrawArrow(x_center, y_center, x_center+radius*cos((encoder/180.0*M_PI)-(90/180.0*M_PI)), y_center+radius*sin((encoder/180.0*M_PI)-(90/180.0 * M_PI)), 0.23, ILI9341_RED);
+		ILI9341_drawCircle(x_center, y_center, radius, ILI9341_RED);
+		drawLineCircle(x_center,y_center,radius,ILI9341_YELLOW);
+		if (encoder_prev != 10000) {
+			ILI9341_DrawArrow(x_center, y_center, x_center+radius*cos((encoder_prev/180.0*M_PI)-(90/180.0*M_PI)), y_center+radius*sin((encoder_prev/180.0*M_PI)-(90/180.0 * M_PI)), 0.23, ILI9341_BLACK);
+			ILI9341_DrawArrow(x_center, y_center, x_center+radius*cos((encoder/180.0*M_PI)-(90/180.0*M_PI)), y_center+radius*sin((encoder/180.0*M_PI)-(90/180.0 * M_PI)), 0.23, ILI9341_RED);
+		}
+		osDelay(1);
+
+	}
+  /* USER CODE END StartTask02 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+	/* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f1xx_hal_msp.c b/Src/stm32f1xx_hal_msp.c
new file mode 100644
index 0000000..addc34e
--- /dev/null
+++ b/Src/stm32f1xx_hal_msp.c
@@ -0,0 +1,401 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32f1xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_AFIO_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+
+  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 
+  */
+  __HAL_AFIO_REMAP_SWJ_NOJTAG();
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief I2C MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspInit 0 */
+
+  /* USER CODE END I2C1_MspInit 0 */
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C1 GPIO Configuration    
+    PB6     ------> I2C1_SCL
+    PB7     ------> I2C1_SDA 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_I2C1_CLK_ENABLE();
+  /* USER CODE BEGIN I2C1_MspInit 1 */
+
+  /* USER CODE END I2C1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief I2C MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+{
+  if(hi2c->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspDeInit 0 */
+
+  /* USER CODE END I2C1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C1_CLK_DISABLE();
+  
+    /**I2C1 GPIO Configuration    
+    PB6     ------> I2C1_SCL
+    PB7     ------> I2C1_SDA 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+  /* USER CODE BEGIN I2C1_MspDeInit 1 */
+
+  /* USER CODE END I2C1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+
+  /* USER CODE END RTC_MspInit 0 */
+    HAL_PWR_EnableBkUpAccess();
+    /* Enable BKP CLK enable for backup registers */
+    __HAL_RCC_BKP_CLK_ENABLE();
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hspi->Instance==SPI2)
+  {
+  /* USER CODE BEGIN SPI2_MspInit 0 */
+
+  /* USER CODE END SPI2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**SPI2 GPIO Configuration    
+    PB13     ------> SPI2_SCK
+    PB14     ------> SPI2_MISO
+    PB15     ------> SPI2_MOSI 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_14;
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI2_MspInit 1 */
+
+  /* USER CODE END SPI2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI2)
+  {
+  /* USER CODE BEGIN SPI2_MspDeInit 0 */
+
+  /* USER CODE END SPI2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI2_CLK_DISABLE();
+  
+    /**SPI2 GPIO Configuration    
+    PB13     ------> SPI2_SCK
+    PB14     ------> SPI2_MISO
+    PB15     ------> SPI2_MOSI 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
+
+  /* USER CODE BEGIN SPI2_MspDeInit 1 */
+
+  /* USER CODE END SPI2_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Encoder MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_encoder: TIM_Encoder handle pointer
+* @retval None
+*/
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim_encoder->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM2 GPIO Configuration    
+    PA0-WKUP     ------> TIM2_CH1
+    PA1     ------> TIM2_CH2 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_Encoder MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_encoder: TIM_Encoder handle pointer
+* @retval None
+*/
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder)
+{
+  if(htim_encoder->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  
+    /**TIM2 GPIO Configuration    
+    PA0-WKUP     ------> TIM2_CH1
+    PA1     ------> TIM2_CH2 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1);
+
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART2)
+  {
+  /* USER CODE BEGIN USART2_MspInit 0 */
+
+  /* USER CODE END USART2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USART2 GPIO Configuration    
+    PA2     ------> USART2_TX
+    PA3     ------> USART2_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART2_MspInit 1 */
+
+  /* USER CODE END USART2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART2)
+  {
+  /* USER CODE BEGIN USART2_MspDeInit 0 */
+
+  /* USER CODE END USART2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART2_CLK_DISABLE();
+  
+    /**USART2 GPIO Configuration    
+    PA2     ------> USART2_TX
+    PA3     ------> USART2_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3);
+
+  /* USER CODE BEGIN USART2_MspDeInit 1 */
+
+  /* USER CODE END USART2_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f1xx_it.c b/Src/stm32f1xx_it.c
new file mode 100644
index 0000000..491d1bb
--- /dev/null
+++ b/Src/stm32f1xx_it.c
@@ -0,0 +1,201 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f1xx_it.h"
+#include "FreeRTOS.h"
+#include "task.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern PCD_HandleTypeDef hpcd_USB_FS;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M3 Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+#if (INCLUDE_xTaskGetSchedulerState == 1 )
+  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
+  {
+#endif /* INCLUDE_xTaskGetSchedulerState */
+  xPortSysTickHandler();
+#if (INCLUDE_xTaskGetSchedulerState == 1 )
+  }
+#endif /* INCLUDE_xTaskGetSchedulerState */
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F1xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f1xx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles USB low priority or CAN RX0 interrupts.
+  */
+void USB_LP_CAN1_RX0_IRQHandler(void)
+{
+  /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */
+
+  /* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */
+  HAL_PCD_IRQHandler(&hpcd_USB_FS);
+  /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */
+
+  /* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/syscalls.c b/Src/syscalls.c
new file mode 100644
index 0000000..c3de5d6
--- /dev/null
+++ b/Src/syscalls.c
@@ -0,0 +1,184 @@
+/**
+*****************************************************************************
+**
+**  File        : syscalls.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
© COPYRIGHT(c) 2018 STMicroelectronics

+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Src/sysmem.c b/Src/sysmem.c
new file mode 100644
index 0000000..847daf4
--- /dev/null
+++ b/Src/sysmem.c
@@ -0,0 +1,83 @@
+/**
+*****************************************************************************
+**
+**  File        : sysmem.c
+**
+**  Author	    : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : STM32CubeIDE Minimal System Memory calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : STM32CubeIDE MCU
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+**
+** 
© COPYRIGHT(c) 2018 STMicroelectronics

+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include 
+#include 
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+
diff --git a/Src/system_stm32f1xx.c b/Src/system_stm32f1xx.c
new file mode 100644
index 0000000..be2da1b
--- /dev/null
+++ b/Src/system_stm32f1xx.c
@@ -0,0 +1,430 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f1xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f1xx_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+  *    the product used), refer to "HSE_VALUE". 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM  */ 
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Variables
+  * @{
+  */
+
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= 0x00000001U;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+  RCC->CFGR &= 0xF8FF0000U;
+#else
+  RCC->CFGR &= 0xF0FF0000U;
+#endif /* STM32F105xC */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= 0xFEF6FFFFU;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= 0xFF80FFFFU;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEBFFFFFFU;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+#endif /* STM32F105xC */
+    
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+  uint32_t prediv1factor = 0U;
+#endif /* STM32F100xB or STM32F100xE */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00U:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04U:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08U:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#if !defined(STM32F105xC) && !defined(STM32F107xC)      
+      pllmull = ( pllmull >> 18U) + 2U;
+      
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+      }
+      else
+      {
+ #if defined(STM32F100xB) || defined(STM32F100xE)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18U;
+      
+      if (pllmull != 0x0DU)
+      {
+         pllmull += 2U;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13U / 2U; 
+      }
+            
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+        
+        if (prediv1source == 0U)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F105xC */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
+  *         This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+  __IO uint32_t tmpreg;
+  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+    required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114U;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+  RCC->APB2ENR = 0x000001E0U;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
+
+  (void)(tmpreg);
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BBU;  
+  GPIOD->CRH = 0xBBBBBBBBU;
+
+  GPIOE->CRL = 0xB44444BBU;  
+  GPIOE->CRH = 0xBBBBBBBBU;
+
+  GPIOF->CRL = 0x44BBBBBBU;  
+  GPIOF->CRH = 0xBBBB4444U;
+
+  GPIOG->CRL = 0x44BBBBBBU;  
+  GPIOG->CRH = 0x444B4B44U;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4U] = 0x00001091U;
+  FSMC_Bank1->BTCR[5U] = 0x00110212U;
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/usb_device.c b/Src/usb_device.c
new file mode 100644
index 0000000..e6c367b
--- /dev/null
+++ b/Src/usb_device.c
@@ -0,0 +1,102 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usb_device.c
+  * @version        : v2.0_Cube
+  * @brief          : This file implements the USB Device
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "usb_device.h"
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_cdc.h"
+#include "usbd_cdc_if.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+
+/* USER CODE END PFP */
+
+/* USB Device Core handle declaration. */
+USBD_HandleTypeDef hUsbDeviceFS;
+
+/*
+ * -- Insert your variables declaration here --
+ */
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*
+ * -- Insert your external function declaration here --
+ */
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+  * Init USB device Library, add supported class and start the library
+  * @retval None
+  */
+void MX_USB_DEVICE_Init(void)
+{
+  /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
+  
+  /* USER CODE END USB_DEVICE_Init_PreTreatment */
+  
+  /* Init Device Library, add supported class and start the library. */
+  if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
+  {
+    Error_Handler();
+  }
+  if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)
+  {
+    Error_Handler();
+  }
+  if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK)
+  {
+    Error_Handler();
+  }
+  if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
+  
+  /* USER CODE END USB_DEVICE_Init_PostTreatment */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/usbd_cdc_if.c b/Src/usbd_cdc_if.c
new file mode 100644
index 0000000..58ddc62
--- /dev/null
+++ b/Src/usbd_cdc_if.c
@@ -0,0 +1,309 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_cdc_if.c
+  * @version        : v2.0_Cube
+  * @brief          : Usb device for Virtual Com Port.
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_cdc_if.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @brief Usb device library.
+  * @{
+  */
+
+/** @addtogroup USBD_CDC_IF
+  * @{
+  */
+
+/** @defgroup USBD_CDC_IF_Private_TypesDefinitions USBD_CDC_IF_Private_TypesDefinitions
+  * @brief Private types.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_TYPES */
+
+/* USER CODE END PRIVATE_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CDC_IF_Private_Defines USBD_CDC_IF_Private_Defines
+  * @brief Private defines.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_DEFINES */
+/* Define size for the receive and transmit buffer over CDC */
+/* It's up to user to redefine and/or remove those define */
+#define APP_RX_DATA_SIZE  1000
+#define APP_TX_DATA_SIZE  1000
+/* USER CODE END PRIVATE_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CDC_IF_Private_Macros USBD_CDC_IF_Private_Macros
+  * @brief Private macros.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_MACRO */
+
+/* USER CODE END PRIVATE_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CDC_IF_Private_Variables USBD_CDC_IF_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+/* Create buffer for reception and transmission           */
+/* It's up to user to redefine and/or remove those define */
+/** Received data over USB are stored in this buffer      */
+uint8_t UserRxBufferFS[APP_RX_DATA_SIZE];
+
+/** Data to send over USB CDC are stored in this buffer   */
+uint8_t UserTxBufferFS[APP_TX_DATA_SIZE];
+
+/* USER CODE BEGIN PRIVATE_VARIABLES */
+
+/* USER CODE END PRIVATE_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+extern USBD_HandleTypeDef hUsbDeviceFS;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CDC_IF_Private_FunctionPrototypes USBD_CDC_IF_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+
+static int8_t CDC_Init_FS(void);
+static int8_t CDC_DeInit_FS(void);
+static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length);
+static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len);
+
+/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
+
+/* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */
+
+/**
+  * @}
+  */
+
+USBD_CDC_ItfTypeDef USBD_Interface_fops_FS =
+{
+  CDC_Init_FS,
+  CDC_DeInit_FS,
+  CDC_Control_FS,
+  CDC_Receive_FS
+};
+
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @brief  Initializes the CDC media low layer over the FS USB IP
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t CDC_Init_FS(void)
+{
+  /* USER CODE BEGIN 3 */
+  /* Set Application Buffers */
+  USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
+  USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS);
+  return (USBD_OK);
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief  DeInitializes the CDC media low layer
+  * @retval USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t CDC_DeInit_FS(void)
+{
+  /* USER CODE BEGIN 4 */
+  return (USBD_OK);
+  /* USER CODE END 4 */
+}
+
+/**
+  * @brief  Manage the CDC class requests
+  * @param  cmd: Command code
+  * @param  pbuf: Buffer containing command data (request parameters)
+  * @param  length: Number of data to be sent (in bytes)
+  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
+{
+  /* USER CODE BEGIN 5 */
+  switch(cmd)
+  {
+    case CDC_SEND_ENCAPSULATED_COMMAND:
+
+    break;
+
+    case CDC_GET_ENCAPSULATED_RESPONSE:
+
+    break;
+
+    case CDC_SET_COMM_FEATURE:
+
+    break;
+
+    case CDC_GET_COMM_FEATURE:
+
+    break;
+
+    case CDC_CLEAR_COMM_FEATURE:
+
+    break;
+
+  /*******************************************************************************/
+  /* Line Coding Structure                                                       */
+  /*-----------------------------------------------------------------------------*/
+  /* Offset | Field       | Size | Value  | Description                          */
+  /* 0      | dwDTERate   |   4  | Number |Data terminal rate, in bits per second*/
+  /* 4      | bCharFormat |   1  | Number | Stop bits                            */
+  /*                                        0 - 1 Stop bit                       */
+  /*                                        1 - 1.5 Stop bits                    */
+  /*                                        2 - 2 Stop bits                      */
+  /* 5      | bParityType |  1   | Number | Parity                               */
+  /*                                        0 - None                             */
+  /*                                        1 - Odd                              */
+  /*                                        2 - Even                             */
+  /*                                        3 - Mark                             */
+  /*                                        4 - Space                            */
+  /* 6      | bDataBits  |   1   | Number Data bits (5, 6, 7, 8 or 16).          */
+  /*******************************************************************************/
+    case CDC_SET_LINE_CODING:
+
+    break;
+
+    case CDC_GET_LINE_CODING:
+
+    break;
+
+    case CDC_SET_CONTROL_LINE_STATE:
+
+    break;
+
+    case CDC_SEND_BREAK:
+
+    break;
+
+  default:
+    break;
+  }
+
+  return (USBD_OK);
+  /* USER CODE END 5 */
+}
+
+/**
+  * @brief  Data received over USB OUT endpoint are sent over CDC interface
+  *         through this function.
+  *
+  *         @note
+  *         This function will block any OUT packet reception on USB endpoint
+  *         untill exiting this function. If you exit this function before transfer
+  *         is complete on CDC interface (ie. using DMA controller) it will result
+  *         in receiving more data while previous ones are still not sent.
+  *
+  * @param  Buf: Buffer of data to be received
+  * @param  Len: Number of data received (in bytes)
+  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
+  */
+static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
+{
+  /* USER CODE BEGIN 6 */
+  USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
+  USBD_CDC_ReceivePacket(&hUsbDeviceFS);
+  return (USBD_OK);
+  /* USER CODE END 6 */
+}
+
+/**
+  * @brief  CDC_Transmit_FS
+  *         Data to send over USB IN endpoint are sent over CDC interface
+  *         through this function.
+  *         @note
+  *
+  *
+  * @param  Buf: Buffer of data to be sent
+  * @param  Len: Number of data to be sent (in bytes)
+  * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
+  */
+uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
+{
+  uint8_t result = USBD_OK;
+  /* USER CODE BEGIN 7 */
+  USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
+  if (hcdc->TxState != 0){
+    return USBD_BUSY;
+  }
+  USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
+  result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
+  /* USER CODE END 7 */
+  return result;
+}
+
+/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */
+
+/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/usbd_conf.c b/Src/usbd_conf.c
new file mode 100644
index 0000000..49e5c34
--- /dev/null
+++ b/Src/usbd_conf.c
@@ -0,0 +1,663 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_conf.c
+  * @version        : v2.0_Cube
+  * @brief          : This file implements the board support package for the USB device library
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */  
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+#include "stm32f1xx_hal.h"
+#include "usbd_def.h"
+#include "usbd_core.h"
+#include "usbd_cdc.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+PCD_HandleTypeDef hpcd_USB_FS;
+void Error_Handler(void);
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+
+/* USER CODE END PFP */
+
+/* Private functions ---------------------------------------------------------*/
+static USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status);
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
+else
+void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/*******************************************************************************
+                       LL Driver Callbacks (PCD -> USB Device Library)
+*******************************************************************************/
+/* MSP Init */
+
+void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
+{
+  if(pcdHandle->Instance==USB)
+  {
+  /* USER CODE BEGIN USB_MspInit 0 */
+
+  /* USER CODE END USB_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USB_CLK_ENABLE();
+
+    /* Peripheral interrupt init */
+    HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
+  /* USER CODE BEGIN USB_MspInit 1 */
+
+  /* USER CODE END USB_MspInit 1 */
+  }
+}
+
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
+{
+  if(pcdHandle->Instance==USB)
+  {
+  /* USER CODE BEGIN USB_MspDeInit 0 */
+
+  /* USER CODE END USB_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USB_CLK_DISABLE();
+
+    /* Peripheral interrupt Deinit*/
+    HAL_NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
+
+  /* USER CODE BEGIN USB_MspDeInit 1 */
+
+  /* USER CODE END USB_MspDeInit 1 */
+  }
+}
+
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
+}
+
+/**
+  * @brief  Data Out stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
+}
+
+/**
+  * @brief  Data In stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  Reset callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{ 
+  USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
+
+  if ( hpcd->Init.speed != PCD_SPEED_FULL)
+  {
+    Error_Handler();
+  }
+    /* Set Speed. */
+  USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
+
+  /* Reset Device. */
+  USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  Suspend callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* Inform USB library that core enters in suspend Mode. */
+  USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
+  /* Enter in STOP mode. */
+  /* USER CODE BEGIN 2 */
+  if (hpcd->Init.low_power_enable)
+  {
+    /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
+    SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+  }
+  /* USER CODE END 2 */
+}
+
+/**
+  * @brief  Resume callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN 3 */
+
+  /* USER CODE END 3 */
+  USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  ISOOUTIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+}
+
+/**
+  * @brief  ISOINIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+}
+
+/**
+  * @brief  Connect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  Disconnect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/*******************************************************************************
+                       LL Driver Interface (USB Device Library --> PCD)
+*******************************************************************************/
+
+/**
+  * @brief  Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
+{
+  /* Init USB Ip. */
+  /* Link the driver to the stack. */
+  hpcd_USB_FS.pData = pdev;
+  pdev->pData = &hpcd_USB_FS;
+
+  hpcd_USB_FS.Instance = USB;
+  hpcd_USB_FS.Init.dev_endpoints = 8;
+  hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
+  hpcd_USB_FS.Init.low_power_enable = DISABLE;
+  hpcd_USB_FS.Init.lpm_enable = DISABLE;
+  hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
+  if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  /* Register USB PCD CallBacks */
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback);
+
+  HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_FS, PCD_DataOutStageCallback);
+  HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
+  HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
+  HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  /* USER CODE BEGIN EndPoint_Configuration */
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
+  /* USER CODE END EndPoint_Configuration */
+  /* USER CODE BEGIN EndPoint_Configuration_CDC */
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
+  HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
+  /* USER CODE END EndPoint_Configuration_CDC */
+  return USBD_OK;
+}
+
+/**
+  * @brief  De-Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_DeInit(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status; 
+}
+
+/**
+  * @brief  Starts the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+ 
+  hal_status = HAL_PCD_Start(pdev->pData);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Stops the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_Stop(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Opens an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  ep_type: Endpoint type
+  * @param  ep_mps: Endpoint max packet size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;
+}
+
+/**
+  * @brief  Closes an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
+      
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status;  
+}
+
+/**
+  * @brief  Flushes an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
+      
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;  
+}
+
+/**
+  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;  
+}
+
+/**
+  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);  
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns Stall condition.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Stall (1: Yes, 0: No)
+  */
+uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
+  
+  if((ep_addr & 0x80) == 0x80)
+  {
+    return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 
+  }
+  else
+  {
+    return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 
+  }
+}
+
+/**
+  * @brief  Assigns a USB address to the device.
+  * @param  pdev: Device handle
+  * @param  dev_addr: Device address
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;  
+}
+
+/**
+  * @brief  Transmits data over an endpoint.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be sent
+  * @param  size: Data size    
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;    
+}
+
+/**
+  * @brief  Prepares an endpoint for reception.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be received
+  * @param  size: Data size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
+     
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  	
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns the last transfered packet size.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Recived Data Size
+  */
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
+}
+
+/**
+  * @brief  Delays routine for the USB device library.
+  * @param  Delay: Delay in ms
+  * @retval None
+  */
+void USBD_LL_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**
+  * @brief  Static single allocation.
+  * @param  size: Size of allocated memory
+  * @retval None
+  */
+void *USBD_static_malloc(uint32_t size)
+{
+  static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
+  return mem;
+}
+
+/**
+  * @brief  Dummy memory free
+  * @param  p: Pointer to allocated  memory address
+  * @retval None
+  */
+void USBD_static_free(void *p)
+{
+
+}
+
+/**
+  * @brief Software Device Connection
+  * @param hpcd: PCD handle
+  * @param state: Connection state (0: disconnected / 1: connected)
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
+#else
+void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN 6 */
+  if (state == 1)
+  {
+    /* Configure Low connection state. */
+
+  }
+  else
+  {
+    /* Configure High connection state. */
+
+  }
+  /* USER CODE END 6 */
+}
+
+/**
+  * @brief  Retuns the USB status depending on the HAL status:
+  * @param  hal_status: HAL status
+  * @retval USB status
+  */
+USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
+{
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  switch (hal_status)
+  {
+    case HAL_OK :
+      usb_status = USBD_OK;
+    break;
+    case HAL_ERROR :
+      usb_status = USBD_FAIL;
+    break;
+    case HAL_BUSY :
+      usb_status = USBD_BUSY;
+    break;
+    case HAL_TIMEOUT :
+      usb_status = USBD_FAIL;
+    break;
+    default :
+      usb_status = USBD_FAIL;
+    break;
+  }
+  return usb_status;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/usbd_desc.c b/Src/usbd_desc.c
new file mode 100644
index 0000000..40b8438
--- /dev/null
+++ b/Src/usbd_desc.c
@@ -0,0 +1,399 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_desc.c
+  * @version        : v2.0_Cube
+  * @brief          : This file implements the USB device descriptors.
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_conf.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @addtogroup USBD_DESC
+  * @{
+  */
+
+/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions
+  * @brief Private types.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_TYPES */
+
+/* USER CODE END PRIVATE_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines
+  * @brief Private defines.
+  * @{
+  */
+
+#define USBD_VID     1155
+#define USBD_LANGID_STRING     1033
+#define USBD_MANUFACTURER_STRING     "STMicroelectronics"
+#define USBD_PID_FS     22336
+#define USBD_PRODUCT_STRING_FS     "STM32 Virtual ComPort"
+#define USBD_CONFIGURATION_STRING_FS     "CDC Config"
+#define USBD_INTERFACE_STRING_FS     "CDC Interface"
+
+/* USER CODE BEGIN PRIVATE_DEFINES */
+
+/* USER CODE END PRIVATE_DEFINES */
+
+/**
+  * @}
+  */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros
+  * @brief Private macros.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_MACRO */
+
+/* USER CODE END PRIVATE_MACRO */
+
+/**
+  * @}
+  */
+  
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+  
+static void Get_SerialNum(void);
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
+  
+/**
+  * @}
+  */  
+  
+
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration for FS.
+  * @{
+  */
+
+uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+
+#ifdef USBD_SUPPORT_USER_STRING_DESC
+uint8_t * USBD_FS_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length);
+#endif /* USBD_SUPPORT_USER_STRING_DESC */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+USBD_DescriptorsTypeDef FS_Desc =
+{
+  USBD_FS_DeviceDescriptor
+, USBD_FS_LangIDStrDescriptor
+, USBD_FS_ManufacturerStrDescriptor
+, USBD_FS_ProductStrDescriptor
+, USBD_FS_SerialStrDescriptor
+, USBD_FS_ConfigStrDescriptor
+, USBD_FS_InterfaceStrDescriptor
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/** USB standard device descriptor. */
+__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
+{
+  0x12,                       /*bLength */
+  USB_DESC_TYPE_DEVICE,       /*bDescriptorType*/
+  0x00,                       /*bcdUSB */
+  0x02,
+  0x02,                       /*bDeviceClass*/
+  0x02,                       /*bDeviceSubClass*/
+  0x00,                       /*bDeviceProtocol*/
+  USB_MAX_EP0_SIZE,           /*bMaxPacketSize*/
+  LOBYTE(USBD_VID),           /*idVendor*/
+  HIBYTE(USBD_VID),           /*idVendor*/
+  LOBYTE(USBD_PID_FS),        /*idProduct*/
+  HIBYTE(USBD_PID_FS),        /*idProduct*/
+  0x00,                       /*bcdDevice rel. 2.00*/
+  0x02,
+  USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/
+  USBD_IDX_PRODUCT_STR,       /*Index of product string*/
+  USBD_IDX_SERIAL_STR,        /*Index of serial number string*/
+  USBD_MAX_NUM_CONFIGURATION  /*bNumConfigurations*/
+};
+
+/* USB_DeviceDescriptor */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+
+/** USB lang indentifier descriptor. */
+__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
+{
+     USB_LEN_LANGID_STR_DESC,
+     USB_DESC_TYPE_STRING,
+     LOBYTE(USBD_LANGID_STRING),
+     HIBYTE(USBD_LANGID_STRING)
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/* Internal string descriptor. */
+__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
+
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+  #pragma data_alignment=4   
+#endif
+__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
+  USB_SIZ_STRING_SERIAL,
+  USB_DESC_TYPE_STRING,
+};
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions
+  * @brief Private functions.
+  * @{
+  */
+
+/**
+  * @brief  Return the device descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_FS_DeviceDesc);
+  return USBD_FS_DeviceDesc;
+}
+
+/**
+  * @brief  Return the LangID string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_LangIDDesc);
+  return USBD_LangIDDesc;
+}
+
+/**
+  * @brief  Return the product string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the manufacturer string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the serial number string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = USB_SIZ_STRING_SERIAL;
+
+  /* Update the serial number string descriptor with the data from the unique
+   * ID */
+  Get_SerialNum();
+  /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
+  
+  /* USER CODE END USBD_FS_SerialStrDescriptor */
+  return (uint8_t *) USBD_StringSerial;
+}
+
+/**
+  * @brief  Return the configuration string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == USBD_SPEED_HIGH)
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the interface string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Create the serial number string descriptor 
+  * @param  None 
+  * @retval None
+  */
+static void Get_SerialNum(void)
+{
+  uint32_t deviceserial0, deviceserial1, deviceserial2;
+
+  deviceserial0 = *(uint32_t *) DEVICE_ID1;
+  deviceserial1 = *(uint32_t *) DEVICE_ID2;
+  deviceserial2 = *(uint32_t *) DEVICE_ID3;
+
+  deviceserial0 += deviceserial2;
+
+  if (deviceserial0 != 0)
+  {
+    IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
+    IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
+  }
+}
+
+/**
+  * @brief  Convert Hex 32Bits value into char 
+  * @param  value: value to convert
+  * @param  pbuf: pointer to the buffer 
+  * @param  len: buffer length
+  * @retval None
+  */
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
+{
+  uint8_t idx = 0;
+
+  for (idx = 0; idx < len; idx++)
+  {
+    if (((value >> 28)) < 0xA)
+    {
+      pbuf[2 * idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2 * idx] = (value >> 28) + 'A' - 10;
+    }
+
+    value = value << 4;
+
+    pbuf[2 * idx + 1] = 0;
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Startup/startup_stm32f103c8tx.s b/Startup/startup_stm32f103c8tx.s
new file mode 100644
index 0000000..48cf447
--- /dev/null
+++ b/Startup/startup_stm32f103c8tx.s
@@ -0,0 +1,362 @@
+/**
+  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
+  * @file      startup_stm32f103xb.s
+  * @author    MCD Application Team
+  * @brief     STM32F103xB Devices vector table for Atollic toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system   
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_IRQHandler
+  .word RTC_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_2_IRQHandler
+  .word USB_HP_CAN1_TX_IRQHandler
+  .word USB_LP_CAN1_RX0_IRQHandler
+  .word CAN1_RX1_IRQHandler
+  .word CAN1_SCE_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word TIM1_BRK_IRQHandler
+  .word TIM1_UP_IRQHandler
+  .word TIM1_TRG_COM_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word USBWakeUp_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM          /* @0x108. This is for boot in RAM mode for
+                            STM32F10x Medium Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_2_IRQHandler
+  .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+  .weak USB_HP_CAN1_TX_IRQHandler
+  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+  .weak USB_LP_CAN1_RX0_IRQHandler
+  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+  .weak CAN1_RX1_IRQHandler
+  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+  .weak CAN1_SCE_IRQHandler
+  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+  .weak EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak TIM1_UP_IRQHandler
+  .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+  .weak TIM1_TRG_COM_IRQHandler
+  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+  .weak TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak USBWakeUp_IRQHandler
+  .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+