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workaround for gige timing bug, make sure all rx freq's are sent on init

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n1gp
2015-08-23 10:39:07 -04:00
parent 98ddf64367
commit 3d5c8479ff
1 changed files with 12 additions and 2 deletions
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Source/src/DataEngine/cusdr_dataEngine.cpp
+12 -2
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@@ -57,6 +57,9 @@
- implements the audio processor thread. - implements the audio processor thread.
- implements the interface to the Chirp WSPR decoding functionality. - implements the interface to the Chirp WSPR decoding functionality.
*/ */
static int firstTimeRxInit;
DataEngine::DataEngine(QObject *parent) DataEngine::DataEngine(QObject *parent)
: QObject(parent) : QObject(parent)
, set(Settings::instance()) , set(Settings::instance())
@@ -522,6 +525,7 @@ bool DataEngine::getFirmwareVersions() {
// init receivers // init receivers
int rcvrs = set->getNumberOfReceivers(); int rcvrs = set->getNumberOfReceivers();
firstTimeRxInit = rcvrs;
QString str = "Initializing %1 receiver(s)...please wait"; QString str = "Initializing %1 receiver(s)...please wait";
set->setSystemMessage(str.arg(set->getNumberOfReceivers()), rcvrs * 500); set->setSystemMessage(str.arg(set->getNumberOfReceivers()), rcvrs * 500);
@@ -982,7 +986,7 @@ bool DataEngine::start() {
SleeperThread::msleep(100); SleeperThread::msleep(100);
// pre-conditioning // pre-conditioning
for (int i = 0; i < io.receivers; i++) for (int i = 0; i < io.receivers; i++)
m_dataIO->sendInitFramesToNetworkDevice(i); m_dataIO->sendInitFramesToNetworkDevice(i);
if (m_serverMode == QSDR::SDRMode && set->getWidebandData()) if (m_serverMode == QSDR::SDRMode && set->getWidebandData())
@@ -3204,7 +3208,7 @@ void DataProcessor::processOutputBuffer(const CPX &buffer) {
void DataProcessor::encodeCCBytes() { void DataProcessor::encodeCCBytes() {
de->io.output_buffer[0] = SYNC; de->io.output_buffer[0] = SYNC;
de->io.output_buffer[1] = SYNC; de->io.output_buffer[1] = SYNC;
de->io.output_buffer[2] = SYNC; de->io.output_buffer[2] = SYNC;
@@ -3373,6 +3377,12 @@ void DataProcessor::encodeCCBytes() {
// C0 = 0 0 1 0 0 1 0 x C1, C2, C3, C4 NCO Frequency in Hz for Receiver _8 // Was 0 0 0 1 0 0 1 x // C0 = 0 0 1 0 0 1 0 x C1, C2, C3, C4 NCO Frequency in Hz for Receiver _8 // Was 0 0 0 1 0 0 1 x
// C0 = 0 0 1 1 0 1 0 x C1, C2, C3, C4 NCO Frequency in Hz for Receiver _16 // C0 = 0 0 1 1 0 1 0 x C1, C2, C3, C4 NCO Frequency in Hz for Receiver _16
// RRK, workaround for gige timing bug, make sure all rx freq's are sent on init.
if (firstTimeRxInit) {
firstTimeRxInit -= 1;
de->io.rx_freq_change = firstTimeRxInit;
}
if (de->io.rx_freq_change >= 0) { if (de->io.rx_freq_change >= 0) {
de->io.output_buffer[3] = (de->io.rx_freq_change < 7) ? (de->io.rx_freq_change + 2) << 1 de->io.output_buffer[3] = (de->io.rx_freq_change < 7) ? (de->io.rx_freq_change + 2) << 1